1292407Sbr/*- 2292407Sbr * Copyright (c) 2014 Andrew Turner 3292407Sbr * Copyright (c) 2015 Ruslan Bukin <br@bsdpad.com> 4292407Sbr * All rights reserved. 5292407Sbr * 6292407Sbr * Portions of this software were developed by SRI International and the 7292407Sbr * University of Cambridge Computer Laboratory under DARPA/AFRL contract 8292407Sbr * FA8750-10-C-0237 ("CTSRD"), as part of the DARPA CRASH research programme. 9292407Sbr * 10292407Sbr * Portions of this software were developed by the University of Cambridge 11292407Sbr * Computer Laboratory as part of the CTSRD Project, with support from the 12292407Sbr * UK Higher Education Innovation Fund (HEIF). 13292407Sbr * 14292407Sbr * Redistribution and use in source and binary forms, with or without 15292407Sbr * modification, are permitted provided that the following conditions 16292407Sbr * are met: 17292407Sbr * 1. Redistributions of source code must retain the above copyright 18292407Sbr * notice, this list of conditions and the following disclaimer. 19292407Sbr * 2. Redistributions in binary form must reproduce the above copyright 20292407Sbr * notice, this list of conditions and the following disclaimer in the 21292407Sbr * documentation and/or other materials provided with the distribution. 22292407Sbr * 23292407Sbr * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 24292407Sbr * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25292407Sbr * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26292407Sbr * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 27292407Sbr * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 28292407Sbr * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 29292407Sbr * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30292407Sbr * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31292407Sbr * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32292407Sbr * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33292407Sbr * SUCH DAMAGE. 34292407Sbr * 35292407Sbr * $FreeBSD$ 36292407Sbr */ 37292407Sbr 38292407Sbr#ifndef _MACHINE_PTE_H_ 39292407Sbr#define _MACHINE_PTE_H_ 40292407Sbr 41292407Sbr#ifndef LOCORE 42292407Sbrtypedef uint64_t pd_entry_t; /* page directory entry */ 43292407Sbrtypedef uint64_t pt_entry_t; /* page table entry */ 44296094Sbrtypedef uint64_t pn_t; /* page number */ 45292407Sbr#endif 46292407Sbr 47292407Sbr/* Level 0 table, 512GiB per entry */ 48292407Sbr#define L0_SHIFT 39 49292407Sbr 50292407Sbr/* Level 1 table, 1GiB per entry */ 51292407Sbr#define L1_SHIFT 30 52292407Sbr#define L1_SIZE (1 << L1_SHIFT) 53292407Sbr#define L1_OFFSET (L1_SIZE - 1) 54292407Sbr 55292407Sbr/* Level 2 table, 2MiB per entry */ 56292407Sbr#define L2_SHIFT 21 57292407Sbr#define L2_SIZE (1 << L2_SHIFT) 58292407Sbr#define L2_OFFSET (L2_SIZE - 1) 59292407Sbr 60292407Sbr/* Level 3 table, 4KiB per entry */ 61292407Sbr#define L3_SHIFT 12 62292407Sbr#define L3_SIZE (1 << L3_SHIFT) 63292407Sbr#define L3_OFFSET (L3_SIZE - 1) 64292407Sbr 65292407Sbr#define Ln_ENTRIES (1 << 9) 66292407Sbr#define Ln_ADDR_MASK (Ln_ENTRIES - 1) 67292407Sbr 68292407Sbr/* Bits 9:7 are reserved for software */ 69292407Sbr#define PTE_SW_MANAGED (1 << 8) 70292407Sbr#define PTE_SW_WIRED (1 << 7) 71292407Sbr#define PTE_DIRTY (1 << 6) /* Virtual page is written */ 72292407Sbr#define PTE_REF (1 << 5) /* Virtual page is referenced */ 73292407Sbr#define PTE_VALID (1 << 0) /* Virtual page is valid */ 74292407Sbr#define PTE_TYPE_S 1 75292407Sbr#define PTE_TYPE_M (0xf << PTE_TYPE_S) 76292407Sbr#define PTE_TYPE_PTR 0 77292407Sbr#define PTE_TYPE_PTR_G 1 78292407Sbr#define PTE_TYPE_SROURX 2 /* Supervisor read-only, user read-execute page. */ 79292407Sbr#define PTE_TYPE_SRWURWX 3 /* Supervisor read-write, user read-write-execute page. */ 80292407Sbr#define PTE_TYPE_SURO 4 /* Supervisor and user read-only page. */ 81292407Sbr#define PTE_TYPE_SURW 5 /* Supervisor and user read-write page. */ 82292407Sbr#define PTE_TYPE_SURX 6 /* Supervisor and user read-execute page. */ 83292407Sbr#define PTE_TYPE_SURWX 7 /* Supervisor and User Read Write Execute */ 84292407Sbr#define PTE_TYPE_SRO 8 /* Supervisor read-only page. */ 85292407Sbr#define PTE_TYPE_SRW 9 /* Supervisor read-write page. */ 86292407Sbr#define PTE_TYPE_SRX 10 /* Supervisor read-execute page. */ 87292407Sbr#define PTE_TYPE_SRWX 11 /* Supervisor read-write-execute page. */ 88292407Sbr#define PTE_TYPE_SRO_G 12 /* Supervisor read-only page--global mapping. */ 89292407Sbr#define PTE_TYPE_SRW_G 13 /* Supervisor read-write page--global mapping. */ 90292407Sbr#define PTE_TYPE_SRX_G 14 /* Supervisor read-execute page--global mapping. */ 91292407Sbr#define PTE_TYPE_SRWX_G 15 /* Supervisor Read Write Execute Global */ 92292407Sbr 93292407Sbr#define PTE_PPN0_S 10 94292407Sbr#define PTE_PPN1_S 19 95292407Sbr#define PTE_PPN2_S 28 96292407Sbr#define PTE_PPN3_S 37 97292407Sbr#define PTE_SIZE 8 98292407Sbr 99292407Sbr#endif /* !_MACHINE_PTE_H_ */ 100292407Sbr 101292407Sbr/* End of pte.h */ 102