if_glc.c revision 257324
1/*- 2 * Copyright (C) 2010 Nathan Whitehorn 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 17 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 18 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 19 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 20 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 21 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 22 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 23 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 24 * 25 * $FreeBSD: head/sys/powerpc/ps3/if_glc.c 257324 2013-10-29 11:17:49Z glebius $ 26 */ 27 28#include <sys/param.h> 29#include <sys/systm.h> 30#include <sys/sockio.h> 31#include <sys/endian.h> 32#include <sys/lock.h> 33#include <sys/mbuf.h> 34#include <sys/module.h> 35#include <sys/malloc.h> 36#include <sys/mutex.h> 37#include <sys/kernel.h> 38#include <sys/socket.h> 39 40#include <vm/vm.h> 41#include <vm/pmap.h> 42 43#include <net/bpf.h> 44#include <net/if.h> 45#include <net/if_var.h> 46#include <net/ethernet.h> 47#include <net/if_media.h> 48#include <net/if_types.h> 49#include <net/if_dl.h> 50 51#include <machine/pio.h> 52#include <machine/bus.h> 53#include <machine/platform.h> 54#include <machine/pmap.h> 55#include <machine/resource.h> 56#include <sys/bus.h> 57#include <sys/rman.h> 58 59#include "ps3bus.h" 60#include "ps3-hvcall.h" 61#include "if_glcreg.h" 62 63static int glc_probe(device_t); 64static int glc_attach(device_t); 65static void glc_init(void *xsc); 66static void glc_start(struct ifnet *ifp); 67static int glc_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data); 68static void glc_set_multicast(struct glc_softc *sc); 69static int glc_add_rxbuf(struct glc_softc *sc, int idx); 70static int glc_add_rxbuf_dma(struct glc_softc *sc, int idx); 71static int glc_encap(struct glc_softc *sc, struct mbuf **m_head, 72 bus_addr_t *pktdesc); 73static int glc_intr_filter(void *xsc); 74static void glc_intr(void *xsc); 75static void glc_tick(void *xsc); 76static void glc_media_status(struct ifnet *ifp, struct ifmediareq *ifmr); 77static int glc_media_change(struct ifnet *ifp); 78 79static MALLOC_DEFINE(M_GLC, "gelic", "PS3 GELIC ethernet"); 80 81static device_method_t glc_methods[] = { 82 /* Device interface */ 83 DEVMETHOD(device_probe, glc_probe), 84 DEVMETHOD(device_attach, glc_attach), 85 86 { 0, 0 } 87}; 88 89static driver_t glc_driver = { 90 "glc", 91 glc_methods, 92 sizeof(struct glc_softc) 93}; 94 95static devclass_t glc_devclass; 96 97DRIVER_MODULE(glc, ps3bus, glc_driver, glc_devclass, 0, 0); 98 99static int 100glc_probe(device_t dev) 101{ 102 103 if (ps3bus_get_bustype(dev) != PS3_BUSTYPE_SYSBUS || 104 ps3bus_get_devtype(dev) != PS3_DEVTYPE_GELIC) 105 return (ENXIO); 106 107 device_set_desc(dev, "Playstation 3 GELIC Network Controller"); 108 return (BUS_PROBE_SPECIFIC); 109} 110 111static void 112glc_getphys(void *xaddr, bus_dma_segment_t *segs, int nsegs, int error) 113{ 114 if (error != 0) 115 return; 116 117 *(bus_addr_t *)xaddr = segs[0].ds_addr; 118} 119 120static int 121glc_attach(device_t dev) 122{ 123 struct glc_softc *sc; 124 struct glc_txsoft *txs; 125 uint64_t mac64, val, junk; 126 int i, err; 127 128 sc = device_get_softc(dev); 129 130 sc->sc_bus = ps3bus_get_bus(dev); 131 sc->sc_dev = ps3bus_get_device(dev); 132 sc->sc_self = dev; 133 134 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 135 MTX_DEF); 136 callout_init_mtx(&sc->sc_tick_ch, &sc->sc_mtx, 0); 137 sc->next_txdma_slot = 0; 138 sc->bsy_txdma_slots = 0; 139 sc->sc_next_rxdma_slot = 0; 140 sc->first_used_txdma_slot = -1; 141 142 /* 143 * Shut down existing tasks. 144 */ 145 146 lv1_net_stop_tx_dma(sc->sc_bus, sc->sc_dev, 0); 147 lv1_net_stop_rx_dma(sc->sc_bus, sc->sc_dev, 0); 148 149 sc->sc_ifp = if_alloc(IFT_ETHER); 150 sc->sc_ifp->if_softc = sc; 151 152 /* 153 * Get MAC address and VLAN id 154 */ 155 156 lv1_net_control(sc->sc_bus, sc->sc_dev, GELIC_GET_MAC_ADDRESS, 157 0, 0, 0, &mac64, &junk); 158 memcpy(sc->sc_enaddr, &((uint8_t *)&mac64)[2], sizeof(sc->sc_enaddr)); 159 sc->sc_tx_vlan = sc->sc_rx_vlan = -1; 160 err = lv1_net_control(sc->sc_bus, sc->sc_dev, GELIC_GET_VLAN_ID, 161 GELIC_VLAN_TX_ETHERNET, 0, 0, &val, &junk); 162 if (err == 0) 163 sc->sc_tx_vlan = val; 164 err = lv1_net_control(sc->sc_bus, sc->sc_dev, GELIC_GET_VLAN_ID, 165 GELIC_VLAN_RX_ETHERNET, 0, 0, &val, &junk); 166 if (err == 0) 167 sc->sc_rx_vlan = val; 168 169 /* 170 * Set up interrupt handler 171 */ 172 sc->sc_irqid = 0; 173 sc->sc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->sc_irqid, 174 RF_ACTIVE); 175 if (sc->sc_irq == NULL) { 176 device_printf(dev, "Could not allocate IRQ!\n"); 177 mtx_destroy(&sc->sc_mtx); 178 return (ENXIO); 179 } 180 181 bus_setup_intr(dev, sc->sc_irq, 182 INTR_TYPE_NET | INTR_MPSAFE | INTR_ENTROPY, 183 glc_intr_filter, glc_intr, sc, &sc->sc_irqctx); 184 sc->sc_hwirq_status = (uint64_t *)contigmalloc(8, M_GLC, M_ZERO, 0, 185 BUS_SPACE_MAXADDR_32BIT, 8, PAGE_SIZE); 186 lv1_net_set_interrupt_status_indicator(sc->sc_bus, sc->sc_dev, 187 vtophys(sc->sc_hwirq_status), 0); 188 lv1_net_set_interrupt_mask(sc->sc_bus, sc->sc_dev, 189 GELIC_INT_RXDONE | GELIC_INT_RXFRAME | GELIC_INT_PHY | 190 GELIC_INT_TX_CHAIN_END, 0); 191 192 /* 193 * Set up DMA. 194 */ 195 196 err = bus_dma_tag_create(bus_get_dma_tag(dev), 32, 0, 197 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 198 129*sizeof(struct glc_dmadesc), 1, 128*sizeof(struct glc_dmadesc), 199 0, NULL,NULL, &sc->sc_dmadesc_tag); 200 201 err = bus_dmamem_alloc(sc->sc_dmadesc_tag, (void **)&sc->sc_txdmadesc, 202 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 203 &sc->sc_txdmadesc_map); 204 err = bus_dmamap_load(sc->sc_dmadesc_tag, sc->sc_txdmadesc_map, 205 sc->sc_txdmadesc, 128*sizeof(struct glc_dmadesc), glc_getphys, 206 &sc->sc_txdmadesc_phys, 0); 207 err = bus_dmamem_alloc(sc->sc_dmadesc_tag, (void **)&sc->sc_rxdmadesc, 208 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 209 &sc->sc_rxdmadesc_map); 210 err = bus_dmamap_load(sc->sc_dmadesc_tag, sc->sc_rxdmadesc_map, 211 sc->sc_rxdmadesc, 128*sizeof(struct glc_dmadesc), glc_getphys, 212 &sc->sc_rxdmadesc_phys, 0); 213 214 err = bus_dma_tag_create(bus_get_dma_tag(dev), 128, 0, 215 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 216 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0, NULL,NULL, 217 &sc->sc_rxdma_tag); 218 err = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0, 219 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 220 BUS_SPACE_MAXSIZE_32BIT, 16, BUS_SPACE_MAXSIZE_32BIT, 0, NULL,NULL, 221 &sc->sc_txdma_tag); 222 223 /* init transmit descriptors */ 224 STAILQ_INIT(&sc->sc_txfreeq); 225 STAILQ_INIT(&sc->sc_txdirtyq); 226 227 /* create TX DMA maps */ 228 err = ENOMEM; 229 for (i = 0; i < GLC_MAX_TX_PACKETS; i++) { 230 txs = &sc->sc_txsoft[i]; 231 txs->txs_mbuf = NULL; 232 err = bus_dmamap_create(sc->sc_txdma_tag, 0, &txs->txs_dmamap); 233 if (err) { 234 device_printf(dev, 235 "unable to create TX DMA map %d, error = %d\n", 236 i, err); 237 } 238 STAILQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 239 } 240 241 /* Create the receive buffer DMA maps. */ 242 for (i = 0; i < GLC_MAX_RX_PACKETS; i++) { 243 err = bus_dmamap_create(sc->sc_rxdma_tag, 0, 244 &sc->sc_rxsoft[i].rxs_dmamap); 245 if (err) { 246 device_printf(dev, 247 "unable to create RX DMA map %d, error = %d\n", 248 i, err); 249 } 250 sc->sc_rxsoft[i].rxs_mbuf = NULL; 251 } 252 253 /* 254 * Attach to network stack 255 */ 256 257 if_initname(sc->sc_ifp, device_get_name(dev), device_get_unit(dev)); 258 sc->sc_ifp->if_mtu = ETHERMTU; 259 sc->sc_ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 260 sc->sc_ifp->if_hwassist = CSUM_TCP | CSUM_UDP; 261 sc->sc_ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_RXCSUM; 262 sc->sc_ifp->if_capenable = IFCAP_HWCSUM | IFCAP_RXCSUM; 263 sc->sc_ifp->if_start = glc_start; 264 sc->sc_ifp->if_ioctl = glc_ioctl; 265 sc->sc_ifp->if_init = glc_init; 266 267 ifmedia_init(&sc->sc_media, IFM_IMASK, glc_media_change, 268 glc_media_status); 269 ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_10_T, 0, NULL); 270 ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_10_T | IFM_FDX, 0, NULL); 271 ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_100_TX, 0, NULL); 272 ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_100_TX | IFM_FDX, 0, NULL); 273 ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL); 274 ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_AUTO, 0, NULL); 275 ifmedia_set(&sc->sc_media, IFM_ETHER | IFM_AUTO); 276 277 IFQ_SET_MAXLEN(&sc->sc_ifp->if_snd, GLC_MAX_TX_PACKETS); 278 sc->sc_ifp->if_snd.ifq_drv_maxlen = GLC_MAX_TX_PACKETS; 279 IFQ_SET_READY(&sc->sc_ifp->if_snd); 280 281 ether_ifattach(sc->sc_ifp, sc->sc_enaddr); 282 sc->sc_ifp->if_hwassist = 0; 283 284 return (0); 285 286 mtx_destroy(&sc->sc_mtx); 287 if_free(sc->sc_ifp); 288 return (ENXIO); 289} 290 291static void 292glc_init_locked(struct glc_softc *sc) 293{ 294 int i, error; 295 struct glc_rxsoft *rxs; 296 struct glc_txsoft *txs; 297 298 mtx_assert(&sc->sc_mtx, MA_OWNED); 299 300 lv1_net_stop_tx_dma(sc->sc_bus, sc->sc_dev, 0); 301 lv1_net_stop_rx_dma(sc->sc_bus, sc->sc_dev, 0); 302 303 glc_set_multicast(sc); 304 305 for (i = 0; i < GLC_MAX_RX_PACKETS; i++) { 306 rxs = &sc->sc_rxsoft[i]; 307 rxs->rxs_desc_slot = i; 308 309 if (rxs->rxs_mbuf == NULL) { 310 glc_add_rxbuf(sc, i); 311 312 if (rxs->rxs_mbuf == NULL) { 313 rxs->rxs_desc_slot = -1; 314 break; 315 } 316 } 317 318 glc_add_rxbuf_dma(sc, i); 319 bus_dmamap_sync(sc->sc_dmadesc_tag, sc->sc_rxdmadesc_map, 320 BUS_DMASYNC_PREREAD); 321 } 322 323 /* Clear TX dirty queue */ 324 while ((txs = STAILQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 325 STAILQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 326 bus_dmamap_unload(sc->sc_txdma_tag, txs->txs_dmamap); 327 328 if (txs->txs_mbuf != NULL) { 329 m_freem(txs->txs_mbuf); 330 txs->txs_mbuf = NULL; 331 } 332 333 STAILQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 334 } 335 sc->first_used_txdma_slot = -1; 336 sc->bsy_txdma_slots = 0; 337 338 error = lv1_net_start_rx_dma(sc->sc_bus, sc->sc_dev, 339 sc->sc_rxsoft[0].rxs_desc, 0); 340 if (error != 0) 341 device_printf(sc->sc_self, 342 "lv1_net_start_rx_dma error: %d\n", error); 343 344 sc->sc_ifp->if_drv_flags |= IFF_DRV_RUNNING; 345 sc->sc_ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 346 sc->sc_ifpflags = sc->sc_ifp->if_flags; 347 348 sc->sc_wdog_timer = 0; 349 callout_reset(&sc->sc_tick_ch, hz, glc_tick, sc); 350} 351 352static void 353glc_stop(void *xsc) 354{ 355 struct glc_softc *sc = xsc; 356 357 mtx_assert(&sc->sc_mtx, MA_OWNED); 358 359 lv1_net_stop_tx_dma(sc->sc_bus, sc->sc_dev, 0); 360 lv1_net_stop_rx_dma(sc->sc_bus, sc->sc_dev, 0); 361} 362 363static void 364glc_init(void *xsc) 365{ 366 struct glc_softc *sc = xsc; 367 368 mtx_lock(&sc->sc_mtx); 369 glc_init_locked(sc); 370 mtx_unlock(&sc->sc_mtx); 371} 372 373static void 374glc_tick(void *xsc) 375{ 376 struct glc_softc *sc = xsc; 377 378 mtx_assert(&sc->sc_mtx, MA_OWNED); 379 380 /* 381 * XXX: Sometimes the RX queue gets stuck. Poke it periodically until 382 * we figure out why. This will fail harmlessly if the RX queue is 383 * already running. 384 */ 385 lv1_net_start_rx_dma(sc->sc_bus, sc->sc_dev, 386 sc->sc_rxsoft[sc->sc_next_rxdma_slot].rxs_desc, 0); 387 388 if (sc->sc_wdog_timer == 0 || --sc->sc_wdog_timer != 0) { 389 callout_reset(&sc->sc_tick_ch, hz, glc_tick, sc); 390 return; 391 } 392 393 /* Problems */ 394 device_printf(sc->sc_self, "device timeout\n"); 395 396 glc_init_locked(sc); 397} 398 399static void 400glc_start_locked(struct ifnet *ifp) 401{ 402 struct glc_softc *sc = ifp->if_softc; 403 bus_addr_t first, pktdesc; 404 int kickstart = 0; 405 int error; 406 struct mbuf *mb_head; 407 408 mtx_assert(&sc->sc_mtx, MA_OWNED); 409 first = 0; 410 411 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 412 IFF_DRV_RUNNING) 413 return; 414 415 if (STAILQ_EMPTY(&sc->sc_txdirtyq)) 416 kickstart = 1; 417 418 while (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) { 419 IFQ_DRV_DEQUEUE(&ifp->if_snd, mb_head); 420 421 if (mb_head == NULL) 422 break; 423 424 /* Check if the ring buffer is full */ 425 if (sc->bsy_txdma_slots > 125) { 426 /* Put the packet back and stop */ 427 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 428 IFQ_DRV_PREPEND(&ifp->if_snd, mb_head); 429 break; 430 } 431 432 BPF_MTAP(ifp, mb_head); 433 434 if (sc->sc_tx_vlan >= 0) 435 mb_head = ether_vlanencap(mb_head, sc->sc_tx_vlan); 436 437 if (glc_encap(sc, &mb_head, &pktdesc)) { 438 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 439 break; 440 } 441 442 if (first == 0) 443 first = pktdesc; 444 } 445 446 if (kickstart && first != 0) { 447 error = lv1_net_start_tx_dma(sc->sc_bus, sc->sc_dev, first, 0); 448 if (error != 0) 449 device_printf(sc->sc_self, 450 "lv1_net_start_tx_dma error: %d\n", error); 451 sc->sc_wdog_timer = 5; 452 } 453} 454 455static void 456glc_start(struct ifnet *ifp) 457{ 458 struct glc_softc *sc = ifp->if_softc; 459 460 mtx_lock(&sc->sc_mtx); 461 glc_start_locked(ifp); 462 mtx_unlock(&sc->sc_mtx); 463} 464 465static int 466glc_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 467{ 468 struct glc_softc *sc = ifp->if_softc; 469 struct ifreq *ifr = (struct ifreq *)data; 470 int err = 0; 471 472 switch (cmd) { 473 case SIOCSIFFLAGS: 474 mtx_lock(&sc->sc_mtx); 475 if ((ifp->if_flags & IFF_UP) != 0) { 476 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 && 477 ((ifp->if_flags ^ sc->sc_ifpflags) & 478 (IFF_ALLMULTI | IFF_PROMISC)) != 0) 479 glc_set_multicast(sc); 480 else 481 glc_init_locked(sc); 482 } 483 else if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 484 glc_stop(sc); 485 sc->sc_ifpflags = ifp->if_flags; 486 mtx_unlock(&sc->sc_mtx); 487 break; 488 case SIOCADDMULTI: 489 case SIOCDELMULTI: 490 mtx_lock(&sc->sc_mtx); 491 glc_set_multicast(sc); 492 mtx_unlock(&sc->sc_mtx); 493 break; 494 case SIOCGIFMEDIA: 495 case SIOCSIFMEDIA: 496 err = ifmedia_ioctl(ifp, ifr, &sc->sc_media, cmd); 497 break; 498 default: 499 err = ether_ioctl(ifp, cmd, data); 500 break; 501 } 502 503 return (err); 504} 505 506static void 507glc_set_multicast(struct glc_softc *sc) 508{ 509 struct ifnet *ifp = sc->sc_ifp; 510 struct ifmultiaddr *inm; 511 uint64_t addr; 512 int naddrs; 513 514 /* Clear multicast filter */ 515 lv1_net_remove_multicast_address(sc->sc_bus, sc->sc_dev, 0, 1); 516 517 /* Add broadcast */ 518 lv1_net_add_multicast_address(sc->sc_bus, sc->sc_dev, 519 0xffffffffffffL, 0); 520 521 if ((ifp->if_flags & IFF_ALLMULTI) != 0) { 522 lv1_net_add_multicast_address(sc->sc_bus, sc->sc_dev, 0, 1); 523 } else { 524 if_maddr_rlock(ifp); 525 naddrs = 1; /* Include broadcast */ 526 TAILQ_FOREACH(inm, &ifp->if_multiaddrs, ifma_link) { 527 if (inm->ifma_addr->sa_family != AF_LINK) 528 continue; 529 addr = 0; 530 memcpy(&((uint8_t *)(&addr))[2], 531 LLADDR((struct sockaddr_dl *)inm->ifma_addr), 532 ETHER_ADDR_LEN); 533 534 lv1_net_add_multicast_address(sc->sc_bus, sc->sc_dev, 535 addr, 0); 536 537 /* 538 * Filter can only hold 32 addresses, so fall back to 539 * the IFF_ALLMULTI case if we have too many. 540 */ 541 if (++naddrs >= 32) { 542 lv1_net_add_multicast_address(sc->sc_bus, 543 sc->sc_dev, 0, 1); 544 break; 545 } 546 } 547 if_maddr_runlock(ifp); 548 } 549} 550 551static int 552glc_add_rxbuf(struct glc_softc *sc, int idx) 553{ 554 struct glc_rxsoft *rxs = &sc->sc_rxsoft[idx]; 555 struct mbuf *m; 556 bus_dma_segment_t segs[1]; 557 int error, nsegs; 558 559 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 560 if (m == NULL) 561 return (ENOBUFS); 562 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size; 563 564 if (rxs->rxs_mbuf != NULL) { 565 bus_dmamap_sync(sc->sc_rxdma_tag, rxs->rxs_dmamap, 566 BUS_DMASYNC_POSTREAD); 567 bus_dmamap_unload(sc->sc_rxdma_tag, rxs->rxs_dmamap); 568 } 569 570 error = bus_dmamap_load_mbuf_sg(sc->sc_rxdma_tag, rxs->rxs_dmamap, m, 571 segs, &nsegs, BUS_DMA_NOWAIT); 572 if (error != 0) { 573 device_printf(sc->sc_self, 574 "cannot load RS DMA map %d, error = %d\n", idx, error); 575 m_freem(m); 576 return (error); 577 } 578 /* If nsegs is wrong then the stack is corrupt. */ 579 KASSERT(nsegs == 1, 580 ("%s: too many DMA segments (%d)", __func__, nsegs)); 581 rxs->rxs_mbuf = m; 582 rxs->segment = segs[0]; 583 584 bus_dmamap_sync(sc->sc_rxdma_tag, rxs->rxs_dmamap, BUS_DMASYNC_PREREAD); 585 586 return (0); 587} 588 589static int 590glc_add_rxbuf_dma(struct glc_softc *sc, int idx) 591{ 592 struct glc_rxsoft *rxs = &sc->sc_rxsoft[idx]; 593 594 bzero(&sc->sc_rxdmadesc[idx], sizeof(sc->sc_rxdmadesc[idx])); 595 sc->sc_rxdmadesc[idx].paddr = rxs->segment.ds_addr; 596 sc->sc_rxdmadesc[idx].len = rxs->segment.ds_len; 597 sc->sc_rxdmadesc[idx].next = sc->sc_rxdmadesc_phys + 598 ((idx + 1) % GLC_MAX_RX_PACKETS)*sizeof(sc->sc_rxdmadesc[idx]); 599 sc->sc_rxdmadesc[idx].cmd_stat = GELIC_DESCR_OWNED; 600 601 rxs->rxs_desc_slot = idx; 602 rxs->rxs_desc = sc->sc_rxdmadesc_phys + idx*sizeof(struct glc_dmadesc); 603 604 return (0); 605} 606 607static int 608glc_encap(struct glc_softc *sc, struct mbuf **m_head, bus_addr_t *pktdesc) 609{ 610 bus_dma_segment_t segs[16]; 611 struct glc_txsoft *txs; 612 struct mbuf *m; 613 bus_addr_t firstslotphys; 614 int i, idx, nsegs, nsegs_max; 615 int err = 0; 616 617 /* Max number of segments is the number of free DMA slots */ 618 nsegs_max = 128 - sc->bsy_txdma_slots; 619 620 if (nsegs_max > 16 || sc->first_used_txdma_slot < 0) 621 nsegs_max = 16; 622 623 /* Get a work queue entry. */ 624 if ((txs = STAILQ_FIRST(&sc->sc_txfreeq)) == NULL) { 625 /* Ran out of descriptors. */ 626 return (ENOBUFS); 627 } 628 629 nsegs = 0; 630 for (m = *m_head; m != NULL; m = m->m_next) 631 nsegs++; 632 633 if (nsegs > nsegs_max) { 634 m = m_collapse(*m_head, M_NOWAIT, nsegs_max); 635 if (m == NULL) { 636 m_freem(*m_head); 637 *m_head = NULL; 638 return (ENOBUFS); 639 } 640 *m_head = m; 641 } 642 643 err = bus_dmamap_load_mbuf_sg(sc->sc_txdma_tag, txs->txs_dmamap, 644 *m_head, segs, &nsegs, BUS_DMA_NOWAIT); 645 if (err != 0) { 646 m_freem(*m_head); 647 *m_head = NULL; 648 return (err); 649 } 650 651 KASSERT(nsegs <= 128 - sc->bsy_txdma_slots, 652 ("GLC: Mapped too many (%d) DMA segments with %d available", 653 nsegs, 128 - sc->bsy_txdma_slots)); 654 655 if (nsegs == 0) { 656 m_freem(*m_head); 657 *m_head = NULL; 658 return (EIO); 659 } 660 661 txs->txs_ndescs = nsegs; 662 txs->txs_firstdesc = sc->next_txdma_slot; 663 664 idx = txs->txs_firstdesc; 665 firstslotphys = sc->sc_txdmadesc_phys + 666 txs->txs_firstdesc*sizeof(struct glc_dmadesc); 667 668 for (i = 0; i < nsegs; i++) { 669 bzero(&sc->sc_txdmadesc[idx], sizeof(sc->sc_txdmadesc[idx])); 670 sc->sc_txdmadesc[idx].paddr = segs[i].ds_addr; 671 sc->sc_txdmadesc[idx].len = segs[i].ds_len; 672 sc->sc_txdmadesc[idx].next = sc->sc_txdmadesc_phys + 673 ((idx + 1) % GLC_MAX_TX_PACKETS)*sizeof(struct glc_dmadesc); 674 sc->sc_txdmadesc[idx].cmd_stat |= GELIC_CMDSTAT_NOIPSEC; 675 676 if (i+1 == nsegs) { 677 txs->txs_lastdesc = idx; 678 sc->sc_txdmadesc[idx].next = 0; 679 sc->sc_txdmadesc[idx].cmd_stat |= GELIC_CMDSTAT_LAST; 680 } 681 682 if ((*m_head)->m_pkthdr.csum_flags & CSUM_TCP) 683 sc->sc_txdmadesc[idx].cmd_stat |= GELIC_CMDSTAT_CSUM_TCP; 684 if ((*m_head)->m_pkthdr.csum_flags & CSUM_UDP) 685 sc->sc_txdmadesc[idx].cmd_stat |= GELIC_CMDSTAT_CSUM_UDP; 686 sc->sc_txdmadesc[idx].cmd_stat |= GELIC_DESCR_OWNED; 687 688 idx = (idx + 1) % GLC_MAX_TX_PACKETS; 689 } 690 sc->next_txdma_slot = idx; 691 sc->bsy_txdma_slots += nsegs; 692 if (txs->txs_firstdesc != 0) 693 idx = txs->txs_firstdesc - 1; 694 else 695 idx = GLC_MAX_TX_PACKETS - 1; 696 697 if (sc->first_used_txdma_slot < 0) 698 sc->first_used_txdma_slot = txs->txs_firstdesc; 699 700 bus_dmamap_sync(sc->sc_txdma_tag, txs->txs_dmamap, 701 BUS_DMASYNC_PREWRITE); 702 sc->sc_txdmadesc[idx].next = firstslotphys; 703 704 STAILQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 705 STAILQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 706 txs->txs_mbuf = *m_head; 707 *pktdesc = firstslotphys; 708 709 return (0); 710} 711 712static void 713glc_rxintr(struct glc_softc *sc) 714{ 715 int i, restart_rxdma, error; 716 struct mbuf *m; 717 struct ifnet *ifp = sc->sc_ifp; 718 719 bus_dmamap_sync(sc->sc_dmadesc_tag, sc->sc_rxdmadesc_map, 720 BUS_DMASYNC_POSTREAD); 721 722 restart_rxdma = 0; 723 while ((sc->sc_rxdmadesc[sc->sc_next_rxdma_slot].cmd_stat & 724 GELIC_DESCR_OWNED) == 0) { 725 i = sc->sc_next_rxdma_slot; 726 sc->sc_next_rxdma_slot++; 727 if (sc->sc_next_rxdma_slot >= GLC_MAX_RX_PACKETS) 728 sc->sc_next_rxdma_slot = 0; 729 730 if (sc->sc_rxdmadesc[i].cmd_stat & GELIC_CMDSTAT_CHAIN_END) 731 restart_rxdma = 1; 732 733 if (sc->sc_rxdmadesc[i].rxerror & GELIC_RXERRORS) { 734 ifp->if_ierrors++; 735 goto requeue; 736 } 737 738 m = sc->sc_rxsoft[i].rxs_mbuf; 739 if (sc->sc_rxdmadesc[i].data_stat & GELIC_RX_IPCSUM) { 740 m->m_pkthdr.csum_flags |= 741 CSUM_IP_CHECKED | CSUM_IP_VALID; 742 } 743 if (sc->sc_rxdmadesc[i].data_stat & GELIC_RX_TCPUDPCSUM) { 744 m->m_pkthdr.csum_flags |= 745 CSUM_DATA_VALID | CSUM_PSEUDO_HDR; 746 m->m_pkthdr.csum_data = 0xffff; 747 } 748 749 if (glc_add_rxbuf(sc, i)) { 750 ifp->if_ierrors++; 751 goto requeue; 752 } 753 754 ifp->if_ipackets++; 755 m->m_pkthdr.rcvif = ifp; 756 m->m_len = sc->sc_rxdmadesc[i].valid_size; 757 m->m_pkthdr.len = m->m_len; 758 759 /* 760 * Remove VLAN tag. Even on early firmwares that do not allow 761 * multiple VLANs, the VLAN tag is still in place here. 762 */ 763 m_adj(m, 2); 764 765 mtx_unlock(&sc->sc_mtx); 766 (*ifp->if_input)(ifp, m); 767 mtx_lock(&sc->sc_mtx); 768 769 requeue: 770 glc_add_rxbuf_dma(sc, i); 771 } 772 773 bus_dmamap_sync(sc->sc_dmadesc_tag, sc->sc_rxdmadesc_map, 774 BUS_DMASYNC_PREWRITE); 775 776 if (restart_rxdma) { 777 error = lv1_net_start_rx_dma(sc->sc_bus, sc->sc_dev, 778 sc->sc_rxsoft[sc->sc_next_rxdma_slot].rxs_desc, 0); 779 if (error != 0) 780 device_printf(sc->sc_self, 781 "lv1_net_start_rx_dma error: %d\n", error); 782 } 783} 784 785static void 786glc_txintr(struct glc_softc *sc) 787{ 788 struct ifnet *ifp = sc->sc_ifp; 789 struct glc_txsoft *txs; 790 int progress = 0, kickstart = 0, error; 791 792 bus_dmamap_sync(sc->sc_dmadesc_tag, sc->sc_txdmadesc_map, 793 BUS_DMASYNC_POSTREAD); 794 795 while ((txs = STAILQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 796 if (sc->sc_txdmadesc[txs->txs_lastdesc].cmd_stat 797 & GELIC_DESCR_OWNED) 798 break; 799 800 STAILQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 801 bus_dmamap_unload(sc->sc_txdma_tag, txs->txs_dmamap); 802 sc->bsy_txdma_slots -= txs->txs_ndescs; 803 804 if (txs->txs_mbuf != NULL) { 805 m_freem(txs->txs_mbuf); 806 txs->txs_mbuf = NULL; 807 } 808 809 if ((sc->sc_txdmadesc[txs->txs_lastdesc].cmd_stat & 0xf0000000) 810 != 0) { 811 lv1_net_stop_tx_dma(sc->sc_bus, sc->sc_dev, 0); 812 kickstart = 1; 813 ifp->if_oerrors++; 814 } 815 816 if (sc->sc_txdmadesc[txs->txs_lastdesc].cmd_stat & 817 GELIC_CMDSTAT_CHAIN_END) 818 kickstart = 1; 819 820 STAILQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 821 ifp->if_opackets++; 822 progress = 1; 823 } 824 825 if (txs != NULL) 826 sc->first_used_txdma_slot = txs->txs_firstdesc; 827 else 828 sc->first_used_txdma_slot = -1; 829 830 if (kickstart || txs != NULL) { 831 /* Speculatively (or necessarily) start the TX queue again */ 832 error = lv1_net_start_tx_dma(sc->sc_bus, sc->sc_dev, 833 sc->sc_txdmadesc_phys + 834 txs->txs_firstdesc*sizeof(struct glc_dmadesc), 0); 835 if (error != 0) 836 device_printf(sc->sc_self, 837 "lv1_net_start_tx_dma error: %d\n", error); 838 } 839 840 if (progress) { 841 /* 842 * We freed some descriptors, so reset IFF_DRV_OACTIVE 843 * and restart. 844 */ 845 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 846 sc->sc_wdog_timer = STAILQ_EMPTY(&sc->sc_txdirtyq) ? 0 : 5; 847 848 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) && 849 !IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 850 glc_start_locked(ifp); 851 } 852} 853 854static int 855glc_intr_filter(void *xsc) 856{ 857 struct glc_softc *sc = xsc; 858 859 powerpc_sync(); 860 atomic_set_64(&sc->sc_interrupt_status, *sc->sc_hwirq_status); 861 return (FILTER_SCHEDULE_THREAD); 862} 863 864static void 865glc_intr(void *xsc) 866{ 867 struct glc_softc *sc = xsc; 868 uint64_t status, linkstat, junk; 869 870 mtx_lock(&sc->sc_mtx); 871 872 status = atomic_readandclear_64(&sc->sc_interrupt_status); 873 874 if (status == 0) { 875 mtx_unlock(&sc->sc_mtx); 876 return; 877 } 878 879 if (status & (GELIC_INT_RXDONE | GELIC_INT_RXFRAME)) 880 glc_rxintr(sc); 881 882 if (status & (GELIC_INT_TXDONE | GELIC_INT_TX_CHAIN_END)) 883 glc_txintr(sc); 884 885 if (status & GELIC_INT_PHY) { 886 lv1_net_control(sc->sc_bus, sc->sc_dev, GELIC_GET_LINK_STATUS, 887 GELIC_VLAN_TX_ETHERNET, 0, 0, &linkstat, &junk); 888 889 linkstat = (linkstat & GELIC_LINK_UP) ? 890 LINK_STATE_UP : LINK_STATE_DOWN; 891 if (linkstat != sc->sc_ifp->if_link_state) 892 if_link_state_change(sc->sc_ifp, linkstat); 893 } 894 895 mtx_unlock(&sc->sc_mtx); 896} 897 898static void 899glc_media_status(struct ifnet *ifp, struct ifmediareq *ifmr) 900{ 901 struct glc_softc *sc = ifp->if_softc; 902 uint64_t status, junk; 903 904 ifmr->ifm_status = IFM_AVALID; 905 ifmr->ifm_active = IFM_ETHER; 906 907 lv1_net_control(sc->sc_bus, sc->sc_dev, GELIC_GET_LINK_STATUS, 908 GELIC_VLAN_TX_ETHERNET, 0, 0, &status, &junk); 909 910 if (status & GELIC_LINK_UP) 911 ifmr->ifm_status |= IFM_ACTIVE; 912 913 if (status & GELIC_SPEED_10) 914 ifmr->ifm_active |= IFM_10_T; 915 else if (status & GELIC_SPEED_100) 916 ifmr->ifm_active |= IFM_100_TX; 917 else if (status & GELIC_SPEED_1000) 918 ifmr->ifm_active |= IFM_1000_T; 919 920 if (status & GELIC_FULL_DUPLEX) 921 ifmr->ifm_active |= IFM_FDX; 922 else 923 ifmr->ifm_active |= IFM_HDX; 924} 925 926static int 927glc_media_change(struct ifnet *ifp) 928{ 929 struct glc_softc *sc = ifp->if_softc; 930 uint64_t mode, junk; 931 int result; 932 933 if (IFM_TYPE(sc->sc_media.ifm_media) != IFM_ETHER) 934 return (EINVAL); 935 936 switch (IFM_SUBTYPE(sc->sc_media.ifm_media)) { 937 case IFM_AUTO: 938 mode = GELIC_AUTO_NEG; 939 break; 940 case IFM_10_T: 941 mode = GELIC_SPEED_10; 942 break; 943 case IFM_100_TX: 944 mode = GELIC_SPEED_100; 945 break; 946 case IFM_1000_T: 947 mode = GELIC_SPEED_1000 | GELIC_FULL_DUPLEX; 948 break; 949 default: 950 return (EINVAL); 951 } 952 953 if (IFM_OPTIONS(sc->sc_media.ifm_media) & IFM_FDX) 954 mode |= GELIC_FULL_DUPLEX; 955 956 result = lv1_net_control(sc->sc_bus, sc->sc_dev, GELIC_SET_LINK_MODE, 957 GELIC_VLAN_TX_ETHERNET, mode, 0, &junk, &junk); 958 959 return (result ? EIO : 0); 960} 961 962