dbdma.c revision 183411 
1/*-
2 * Copyright (c) 2008 Nathan Whitehorn
3 * All rights reserved
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 *    notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 *    notice, this list of conditions and the following disclaimer in the
12 *    documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27#include <sys/cdefs.h>
28__FBSDID("$FreeBSD: head/sys/powerpc/powermac/dbdma.c 183411 2008-09-27 15:41:16Z nwhitehorn $");
29
30#include <sys/param.h>
31#include <sys/systm.h>
32#include <sys/kernel.h>
33#include <sys/malloc.h>
34#include <sys/module.h>
35#include <sys/endian.h>
36#include <sys/bus.h>
37#include <machine/bus.h>
38#include <machine/dbdma.h>
39#include <sys/rman.h>
40
41#include "dbdmavar.h"
42
43MALLOC_DEFINE(M_DBDMA, "dbdma", "DBDMA Command List");
44
45static uint32_t dbdma_read_reg(dbdma_channel_t *, u_int);
46static void dbdma_write_reg(dbdma_channel_t *, u_int, uint32_t);
47static void dbdma_phys_callback(void *, bus_dma_segment_t *, int, int);
48
49static void
50dbdma_phys_callback(void *chan, bus_dma_segment_t *segs, int nsegs, int error)
51{
52	dbdma_channel_t *channel = (dbdma_channel_t *)(chan);
53
54	channel->sc_slots_pa = segs[0].ds_addr;
55	dbdma_write_reg(channel, CHAN_CMDPTR, channel->sc_slots_pa);
56}
57
58int
59dbdma_allocate_channel(struct resource *dbdma_regs, u_int offset,
60    bus_dma_tag_t parent_dma, int slots, dbdma_channel_t **chan)
61{
62	int error = 0;
63	dbdma_channel_t *channel;
64
65	channel = *chan = malloc(sizeof(struct dbdma_channel), M_DBDMA,
66	    M_WAITOK | M_ZERO);
67
68	channel->sc_regs = dbdma_regs;
69	channel->sc_off = offset;
70	dbdma_stop(channel);
71
72	channel->sc_slots_pa = 0;
73
74	error = bus_dma_tag_create(parent_dma, 16, 0, BUS_SPACE_MAXADDR_32BIT,
75	    BUS_SPACE_MAXADDR, NULL, NULL, PAGE_SIZE, 1, PAGE_SIZE, 0, NULL,
76	    NULL, &(channel->sc_dmatag));
77
78	error = bus_dmamem_alloc(channel->sc_dmatag,
79	    (void **)&channel->sc_slots, BUS_DMA_WAITOK | BUS_DMA_ZERO,
80	    &channel->sc_dmamap);
81
82	error = bus_dmamap_load(channel->sc_dmatag, channel->sc_dmamap,
83	    channel->sc_slots, PAGE_SIZE, dbdma_phys_callback, channel, 0);
84
85	dbdma_write_reg(channel, CHAN_CMDPTR_HI, 0);
86
87	channel->sc_nslots = slots;
88
89	return (error);
90}
91
92int
93dbdma_resize_channel(dbdma_channel_t *chan, int newslots)
94{
95
96	if (newslots > (PAGE_SIZE / 16))
97		return (-1);
98
99	chan->sc_nslots = newslots;
100	return (0);
101}
102
103int
104dbdma_free_channel(dbdma_channel_t *chan)
105{
106
107	dbdma_stop(chan);
108
109	bus_dmamem_free(chan->sc_dmatag, chan->sc_slots, chan->sc_dmamap);
110	bus_dma_tag_destroy(chan->sc_dmatag);
111
112	free(chan, M_DBDMA);
113
114	return (0);
115}
116
117uint16_t
118dbdma_get_cmd_status(dbdma_channel_t *chan, int slot)
119{
120
121	bus_dmamap_sync(chan->sc_dmatag, chan->sc_dmamap, BUS_DMASYNC_POSTREAD);
122
123	/*
124	 * I really did mean to swap resCount and xferStatus here, to
125	 * account for the quad-word little endian fields.
126	 */
127	return (le16toh(chan->sc_slots[slot].resCount));
128}
129
130void
131dbdma_clear_cmd_status(dbdma_channel_t *chan, int slot)
132{
133	/* See endian note above */
134	chan->sc_slots[slot].resCount = 0;
135}
136
137uint16_t
138dbdma_get_residuals(dbdma_channel_t *chan, int slot)
139{
140
141	bus_dmamap_sync(chan->sc_dmatag, chan->sc_dmamap, BUS_DMASYNC_POSTREAD);
142
143	return (le16toh(chan->sc_slots[slot].xferStatus));
144}
145
146void
147dbdma_reset(dbdma_channel_t *chan)
148{
149
150	dbdma_stop(chan);
151	dbdma_set_current_cmd(chan, 0);
152	dbdma_run(chan);
153}
154
155void
156dbdma_run(dbdma_channel_t *chan)
157{
158	uint32_t control_reg;
159
160	control_reg = DBDMA_STATUS_RUN | DBDMA_STATUS_PAUSE |
161	    DBDMA_STATUS_WAKE | DBDMA_STATUS_DEAD;
162	control_reg <<= 16;
163	control_reg |= DBDMA_STATUS_RUN;
164	dbdma_write_reg(chan, CHAN_CONTROL_REG, control_reg);
165}
166
167void
168dbdma_pause(dbdma_channel_t *chan)
169{
170	uint32_t control_reg;
171
172	control_reg = DBDMA_STATUS_PAUSE;
173	control_reg <<= 16;
174	control_reg |= DBDMA_STATUS_PAUSE;
175	dbdma_write_reg(chan, CHAN_CONTROL_REG, control_reg);
176}
177
178void
179dbdma_wake(dbdma_channel_t *chan)
180{
181	uint32_t control_reg;
182
183	control_reg = DBDMA_STATUS_WAKE | DBDMA_STATUS_PAUSE |
184	    DBDMA_STATUS_RUN | DBDMA_STATUS_DEAD;
185	control_reg <<= 16;
186	control_reg |= DBDMA_STATUS_WAKE | DBDMA_STATUS_RUN;
187	dbdma_write_reg(chan, CHAN_CONTROL_REG, control_reg);
188}
189
190void
191dbdma_stop(dbdma_channel_t *chan)
192{
193	uint32_t control_reg;
194
195	control_reg = DBDMA_STATUS_RUN;
196	control_reg <<= 16;
197	dbdma_write_reg(chan, CHAN_CONTROL_REG, control_reg);
198
199	while (dbdma_read_reg(chan, CHAN_STATUS_REG) & DBDMA_STATUS_ACTIVE)
200		DELAY(5);
201}
202
203void
204dbdma_set_current_cmd(dbdma_channel_t *chan, int slot)
205{
206	uint32_t cmd;
207
208	cmd = chan->sc_slots_pa + slot * 16;
209	dbdma_write_reg(chan, CHAN_CMDPTR, cmd);
210}
211
212uint16_t
213dbdma_get_chan_status(dbdma_channel_t *chan)
214{
215	uint32_t status_reg;
216
217	status_reg = dbdma_read_reg(chan, CHAN_STATUS_REG);
218	return (status_reg & 0x0000ffff);
219}
220
221uint8_t
222dbdma_get_device_status(dbdma_channel_t *chan)
223{
224	return (dbdma_get_chan_status(chan) & 0x00ff);
225}
226
227void
228dbdma_set_device_status(dbdma_channel_t *chan, uint8_t mask, uint8_t value)
229{
230	uint32_t control_reg;
231
232	control_reg = mask;
233	control_reg <<= 16;
234	control_reg |= value;
235
236	dbdma_write_reg(chan, CHAN_CONTROL_REG, control_reg);
237}
238
239void
240dbdma_set_interrupt_selector(dbdma_channel_t *chan, uint8_t mask, uint8_t val)
241{
242	uint32_t intr_select;
243
244	intr_select = mask;
245	intr_select <<= 16;
246	intr_select |= val;
247	dbdma_write_reg(chan, CHAN_INTR_SELECT, intr_select);
248}
249
250void
251dbdma_set_branch_selector(dbdma_channel_t *chan, uint8_t mask, uint8_t val)
252{
253	uint32_t br_select;
254
255	br_select = mask;
256	br_select <<= 16;
257	br_select |= val;
258	dbdma_write_reg(chan, CHAN_BRANCH_SELECT, br_select);
259}
260
261void
262dbdma_set_wait_selector(dbdma_channel_t *chan, uint8_t mask, uint8_t val)
263{
264	uint32_t wait_select;
265
266	wait_select = mask;
267	wait_select <<= 16;
268	wait_select |= val;
269	dbdma_write_reg(chan, CHAN_WAIT_SELECT, wait_select);
270}
271
272void
273dbdma_insert_command(dbdma_channel_t *chan, int slot, int command, int stream,
274    bus_addr_t data, size_t count, uint8_t interrupt, uint8_t branch,
275    uint8_t wait, uint32_t branch_slot)
276{
277	struct dbdma_command cmd;
278	uint32_t *flip;
279
280	cmd.cmd = command;
281	cmd.key = stream;
282	cmd.intr = interrupt;
283	cmd.branch = branch;
284	cmd.wait = wait;
285
286	cmd.reqCount = count;
287	cmd.address = (uint32_t)(data);
288	if (command != DBDMA_STORE_QUAD && command != DBDMA_LOAD_QUAD)
289		cmd.cmdDep = chan->sc_slots_pa + branch_slot * 16;
290	else
291		cmd.cmdDep = branch_slot;
292
293	cmd.resCount = 0;
294	cmd.xferStatus = 0;
295
296	/*
297	 * Move quadwords to little-endian. God only knows why
298	 * Apple thought this was a good idea.
299	 */
300	flip = (uint32_t *)(&cmd);
301	flip[0] = htole32(flip[0]);
302	flip[1] = htole32(flip[1]);
303	flip[2] = htole32(flip[2]);
304
305	chan->sc_slots[slot] = cmd;
306}
307
308void
309dbdma_insert_stop(dbdma_channel_t *chan, int slot)
310{
311
312	dbdma_insert_command(chan, slot, DBDMA_STOP, 0, 0, 0, DBDMA_NEVER,
313	    DBDMA_NEVER, DBDMA_NEVER, 0);
314}
315
316void
317dbdma_insert_nop(dbdma_channel_t *chan, int slot)
318{
319
320	dbdma_insert_command(chan, slot, DBDMA_NOP, 0, 0, 0, DBDMA_NEVER,
321	    DBDMA_NEVER, DBDMA_NEVER, 0);
322}
323
324void
325dbdma_insert_branch(dbdma_channel_t *chan, int slot, int to_slot)
326{
327
328	dbdma_insert_command(chan, slot, DBDMA_NOP, 0, 0, 0, DBDMA_NEVER,
329	    DBDMA_ALWAYS, DBDMA_NEVER, to_slot);
330}
331
332void
333dbdma_sync_commands(dbdma_channel_t *chan, bus_dmasync_op_t op)
334{
335
336	bus_dmamap_sync(chan->sc_dmatag, chan->sc_dmamap, op);
337}
338
339static uint32_t
340dbdma_read_reg(dbdma_channel_t *chan, u_int offset)
341{
342
343	return (bus_read_4(chan->sc_regs, chan->sc_off + offset));
344}
345
346static void
347dbdma_write_reg(dbdma_channel_t *chan, u_int offset, uint32_t val)
348{
349
350	bus_write_4(chan->sc_regs, chan->sc_off + offset, val);
351}
352