dbdma.c revision 179644
1/*-
2 * Copyright (c) 2008 Nathan Whitehorn
3 * All rights reserved
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 *    notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 *    notice, this list of conditions and the following disclaimer in the
12 *    documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27#include <sys/cdefs.h>
28__FBSDID("$FreeBSD: head/sys/powerpc/powermac/dbdma.c 179644 2008-06-07 21:56:48Z marcel $");
29
30#include <sys/param.h>
31#include <sys/systm.h>
32#include <sys/kernel.h>
33#include <sys/malloc.h>
34#include <sys/module.h>
35#include <sys/endian.h>
36#include <sys/bus.h>
37#include <machine/bus.h>
38#include <machine/dbdma.h>
39#include <sys/rman.h>
40
41#include "dbdmavar.h"
42
43MALLOC_DEFINE(M_DBDMA, "dbdma", "DBDMA Command List");
44
45static uint32_t dbdma_read_reg(dbdma_channel_t *, u_int);
46static void dbdma_write_reg(dbdma_channel_t *, u_int, uint32_t);
47static void dbdma_phys_callback(void *, bus_dma_segment_t *, int, int);
48
49static void
50dbdma_phys_callback(void *chan, bus_dma_segment_t *segs, int nsegs, int error)
51{
52	dbdma_channel_t *channel = (dbdma_channel_t *)(chan);
53
54	channel->sc_slots_pa = segs[0].ds_addr;
55	dbdma_write_reg(channel, CHAN_CMDPTR, channel->sc_slots_pa);
56}
57
58int
59dbdma_allocate_channel(struct resource *dbdma_regs, bus_dma_tag_t parent_dma,
60    int slots, dbdma_channel_t **chan)
61{
62	int error = 0;
63	dbdma_channel_t *channel;
64
65	channel = *chan = malloc(sizeof(struct dbdma_channel), M_DBDMA,
66	    M_WAITOK | M_ZERO);
67
68	channel->sc_bt = rman_get_bustag(dbdma_regs);
69	channel->sc_bh = rman_get_bushandle(dbdma_regs);
70	dbdma_stop(channel);
71
72	channel->sc_slots_pa = 0;
73
74	error = bus_dma_tag_create(parent_dma, 16, 0, BUS_SPACE_MAXADDR_32BIT,
75	    BUS_SPACE_MAXADDR, NULL, NULL, PAGE_SIZE, 1, PAGE_SIZE, 0, NULL,
76	    NULL, &(channel->sc_dmatag));
77
78	error = bus_dmamem_alloc(channel->sc_dmatag,
79	    (void **)&channel->sc_slots, BUS_DMA_WAITOK | BUS_DMA_ZERO,
80	    &channel->sc_dmamap);
81
82	error = bus_dmamap_load(channel->sc_dmatag, channel->sc_dmamap,
83	    channel->sc_slots, PAGE_SIZE, dbdma_phys_callback, channel, 0);
84
85	channel->sc_nslots = slots;
86
87	return (error);
88}
89
90int
91dbdma_resize_channel(dbdma_channel_t *chan, int newslots)
92{
93
94	if (newslots > (PAGE_SIZE / 16))
95		return (-1);
96
97	chan->sc_nslots = newslots;
98	return (0);
99}
100
101int
102dbdma_free_channel(dbdma_channel_t *chan)
103{
104
105	dbdma_stop(chan);
106
107	bus_dmamem_free(chan->sc_dmatag, chan->sc_slots, chan->sc_dmamap);
108	bus_dma_tag_destroy(chan->sc_dmatag);
109
110	free(chan, M_DBDMA);
111
112	return (0);
113}
114
115uint16_t
116dbdma_get_cmd_status(dbdma_channel_t *chan, int slot)
117{
118
119	bus_dmamap_sync(chan->sc_dmatag, chan->sc_dmamap, BUS_DMASYNC_POSTREAD);
120
121	/*
122	 * I really did mean to swap resCount and xferStatus here, to
123	 * account for the quad-word little endian fields.
124	 */
125	return (le16toh(chan->sc_slots[slot].resCount));
126}
127
128uint16_t
129dbdma_get_residuals(dbdma_channel_t *chan, int slot)
130{
131
132	bus_dmamap_sync(chan->sc_dmatag, chan->sc_dmamap, BUS_DMASYNC_POSTREAD);
133
134	return (le16toh(chan->sc_slots[slot].xferStatus));
135}
136
137void
138dbdma_reset(dbdma_channel_t *chan)
139{
140
141	dbdma_stop(chan);
142	dbdma_set_current_cmd(chan, 0);
143	dbdma_run(chan);
144}
145
146void
147dbdma_run(dbdma_channel_t *chan)
148{
149	uint32_t control_reg;
150
151	control_reg = DBDMA_STATUS_RUN | DBDMA_STATUS_PAUSE |
152	    DBDMA_STATUS_WAKE | DBDMA_STATUS_DEAD;
153	control_reg <<= 16;
154	control_reg |= DBDMA_STATUS_RUN;
155	dbdma_write_reg(chan, CHAN_CONTROL_REG, control_reg);
156}
157
158void
159dbdma_pause(dbdma_channel_t *chan)
160{
161	uint32_t control_reg;
162
163	control_reg = DBDMA_STATUS_PAUSE;
164	control_reg <<= 16;
165	control_reg |= DBDMA_STATUS_PAUSE;
166	dbdma_write_reg(chan, CHAN_CONTROL_REG, control_reg);
167}
168
169void
170dbdma_wake(dbdma_channel_t *chan)
171{
172	uint32_t control_reg;
173
174	control_reg = DBDMA_STATUS_WAKE | DBDMA_STATUS_PAUSE |
175	    DBDMA_STATUS_RUN | DBDMA_STATUS_DEAD;
176	control_reg <<= 16;
177	control_reg |= DBDMA_STATUS_WAKE | DBDMA_STATUS_RUN;
178	dbdma_write_reg(chan, CHAN_CONTROL_REG, control_reg);
179}
180
181void
182dbdma_stop(dbdma_channel_t *chan)
183{
184	uint32_t control_reg;
185
186	control_reg = DBDMA_STATUS_RUN;
187	control_reg <<= 16;
188	dbdma_write_reg(chan, CHAN_CONTROL_REG, control_reg);
189
190	while (dbdma_read_reg(chan, CHAN_STATUS_REG) & DBDMA_STATUS_ACTIVE)
191		DELAY(5);
192}
193
194void
195dbdma_set_current_cmd(dbdma_channel_t *chan, int slot)
196{
197	uint32_t cmd;
198
199	cmd = chan->sc_slots_pa + slot * 16;
200	dbdma_write_reg(chan, CHAN_CMDPTR, cmd);
201}
202
203uint16_t
204dbdma_get_chan_status(dbdma_channel_t *chan)
205{
206	uint32_t status_reg;
207
208	status_reg = dbdma_read_reg(chan, CHAN_STATUS_REG);
209	return (status_reg & 0x0000ffff);
210}
211
212uint8_t
213dbdma_get_chan_device_status(dbdma_channel_t *chan)
214{
215
216	return (dbdma_get_chan_status(chan) & 0x00ff);
217}
218
219void
220dbdma_set_interrupt_selector(dbdma_channel_t *chan, uint8_t mask, uint8_t val)
221{
222	uint32_t intr_select;
223
224	intr_select = mask;
225	intr_select <<= 16;
226	intr_select |= val;
227	dbdma_write_reg(chan, CHAN_INTR_SELECT, intr_select);
228}
229
230void
231dbdma_set_branch_selector(dbdma_channel_t *chan, uint8_t mask, uint8_t val)
232{
233	uint32_t br_select;
234
235	br_select = mask;
236	br_select <<= 16;
237	br_select |= val;
238	dbdma_write_reg(chan, CHAN_BRANCH_SELECT, br_select);
239}
240
241void
242dbdma_set_wait_selector(dbdma_channel_t *chan, uint8_t mask, uint8_t val)
243{
244	uint32_t wait_select;
245
246	wait_select = mask;
247	wait_select <<= 16;
248	wait_select |= val;
249	dbdma_write_reg(chan, CHAN_WAIT_SELECT, wait_select);
250}
251
252void
253dbdma_insert_command(dbdma_channel_t *chan, int slot, int command, int stream,
254    bus_addr_t data, size_t count, uint8_t interrupt, uint8_t branch,
255    uint8_t wait, uint32_t branch_slot)
256{
257	struct dbdma_command cmd;
258	uint32_t *flip;
259
260	cmd.cmd = command;
261	cmd.key = stream;
262	cmd.intr = interrupt;
263	cmd.branch = branch;
264	cmd.wait = wait;
265
266	cmd.reqCount = count;
267	cmd.address = (uint32_t)(data);
268	if (command != DBDMA_STORE_QUAD && command != DBDMA_LOAD_QUAD)
269		cmd.cmdDep = chan->sc_slots_pa + branch_slot * 16;
270	else
271		cmd.cmdDep = branch_slot;
272
273	cmd.resCount = 0;
274	cmd.xferStatus = 0;
275
276	/*
277	 * Move quadwords to little-endian. God only knows why
278	 * Apple thought this was a good idea.
279	 */
280	flip = (uint32_t *)(&cmd);
281	flip[0] = htole32(flip[0]);
282	flip[1] = htole32(flip[1]);
283	flip[2] = htole32(flip[2]);
284
285	chan->sc_slots[slot] = cmd;
286}
287
288void
289dbdma_insert_stop(dbdma_channel_t *chan, int slot)
290{
291
292	dbdma_insert_command(chan, slot, DBDMA_STOP, 0, 0, 0, DBDMA_NEVER,
293	    DBDMA_NEVER, DBDMA_NEVER, 0);
294}
295
296void
297dbdma_insert_nop(dbdma_channel_t *chan, int slot)
298{
299
300	dbdma_insert_command(chan, slot, DBDMA_NOP, 0, 0, 0, DBDMA_NEVER,
301	    DBDMA_NEVER, DBDMA_NEVER, 0);
302}
303
304void
305dbdma_insert_branch(dbdma_channel_t *chan, int slot, int to_slot)
306{
307
308	dbdma_insert_command(chan, slot, DBDMA_NOP, 0, 0, 0, DBDMA_NEVER,
309	    DBDMA_ALWAYS, DBDMA_NEVER, to_slot);
310}
311
312void
313dbdma_sync_commands(dbdma_channel_t *chan, bus_dmasync_op_t op)
314{
315
316	bus_dmamap_sync(chan->sc_dmatag, chan->sc_dmamap, op);
317}
318
319static uint32_t
320dbdma_read_reg(dbdma_channel_t *chan, u_int offset)
321{
322
323	return (bus_space_read_4(chan->sc_bt, chan->sc_bh, offset));
324}
325
326static void
327dbdma_write_reg(dbdma_channel_t *chan, u_int offset, uint32_t val)
328{
329
330	bus_space_write_4(chan->sc_bt, chan->sc_bh, offset, val);
331}
332