1184250Smarcel/*- 2184250Smarcel * Copyright (c) 2006-2008, Juniper Networks, Inc. 3184250Smarcel * All rights reserved. 4184250Smarcel * 5184250Smarcel * Redistribution and use in source and binary forms, with or without 6184250Smarcel * modification, are permitted provided that the following conditions 7184250Smarcel * are met: 8184250Smarcel * 9184250Smarcel * 1. Redistributions of source code must retain the above copyright 10184250Smarcel * notice, this list of conditions and the following disclaimer. 11184250Smarcel * 2. Redistributions in binary form must reproduce the above copyright 12184250Smarcel * notice, this list of conditions and the following disclaimer in the 13184250Smarcel * documentation and/or other materials provided with the distribution. 14184250Smarcel * 15184250Smarcel * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16184250Smarcel * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17184250Smarcel * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18184250Smarcel * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19184250Smarcel * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20184250Smarcel * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21184250Smarcel * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22184250Smarcel * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23184250Smarcel * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24184250Smarcel * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25184250Smarcel * 26184250Smarcel * $FreeBSD$ 27184250Smarcel */ 28184250Smarcel 29184250Smarcel#ifndef _MACHINE_LBC_H_ 30184250Smarcel#define _MACHINE_LBC_H_ 31184250Smarcel 32186288Sraj/* Maximum number of devices on Local Bus */ 33186288Sraj#define LBC_DEV_MAX 8 34186288Sraj 35186288Sraj/* Local access registers */ 36235937Smarcel#define LBC85XX_BR(n) (0x0 + (8 * n)) /* Base register 0-7 */ 37235937Smarcel#define LBC85XX_OR(n) (0x4 + (8 * n)) /* Options register 0-7 */ 38235937Smarcel#define LBC85XX_MAR 0x068 /* UPM address register */ 39235937Smarcel#define LBC85XX_MAMR 0x070 /* UPMA mode register */ 40235937Smarcel#define LBC85XX_MBMR 0x074 /* UPMB mode register */ 41235937Smarcel#define LBC85XX_MCMR 0x078 /* UPMC mode register */ 42235937Smarcel#define LBC85XX_MRTPR 0x084 /* Memory refresh timer prescaler */ 43235937Smarcel#define LBC85XX_MDR 0x088 /* UPM data register */ 44235937Smarcel#define LBC85XX_LSOR 0x090 /* Special operation initiation */ 45235937Smarcel#define LBC85XX_LURT 0x0a0 /* UPM refresh timer */ 46235937Smarcel#define LBC85XX_LSRT 0x0a4 /* SDRAM refresh timer */ 47235937Smarcel#define LBC85XX_LTESR 0x0b0 /* Transfer error status register */ 48235937Smarcel#define LBC85XX_LTEDR 0x0b4 /* Transfer error disable register */ 49235937Smarcel#define LBC85XX_LTEIR 0x0b8 /* Transfer error interrupt register */ 50235937Smarcel#define LBC85XX_LTEATR 0x0bc /* Transfer error attributes register */ 51235937Smarcel#define LBC85XX_LTEAR 0x0c0 /* Transfer error address register */ 52235937Smarcel#define LBC85XX_LTECCR 0x0c4 /* Transfer error ECC register */ 53235937Smarcel#define LBC85XX_LBCR 0x0d0 /* Configuration register */ 54235937Smarcel#define LBC85XX_LCRR 0x0d4 /* Clock ratio register */ 55235937Smarcel#define LBC85XX_FMR 0x0e0 /* Flash mode register */ 56235937Smarcel#define LBC85XX_FIR 0x0e4 /* Flash instruction register */ 57235937Smarcel#define LBC85XX_FCR 0x0e8 /* Flash command register */ 58235937Smarcel#define LBC85XX_FBAR 0x0ec /* Flash block address register */ 59235937Smarcel#define LBC85XX_FPAR 0x0f0 /* Flash page address register */ 60235937Smarcel#define LBC85XX_FBCR 0x0f4 /* Flash byte count register */ 61235937Smarcel#define LBC85XX_FECC0 0x100 /* Flash ECC block 0 register */ 62235937Smarcel#define LBC85XX_FECC1 0x104 /* Flash ECC block 0 register */ 63235937Smarcel#define LBC85XX_FECC2 0x108 /* Flash ECC block 0 register */ 64235937Smarcel#define LBC85XX_FECC3 0x10c /* Flash ECC block 0 register */ 65186288Sraj 66186288Sraj/* LBC machine select */ 67186288Sraj#define LBCRES_MSEL_GPCM 0 68186288Sraj#define LBCRES_MSEL_FCM 1 69186288Sraj#define LBCRES_MSEL_UPMA 8 70186288Sraj#define LBCRES_MSEL_UPMB 9 71186288Sraj#define LBCRES_MSEL_UPMC 10 72186288Sraj 73186288Sraj/* LBC data error checking modes */ 74186288Sraj#define LBCRES_DECC_DISABLED 0 75186288Sraj#define LBCRES_DECC_NORMAL 1 76186288Sraj#define LBCRES_DECC_RMW 2 77186288Sraj 78186288Sraj/* LBC atomic operation modes */ 79186288Sraj#define LBCRES_ATOM_DISABLED 0 80186288Sraj#define LBCRES_ATOM_RAWA 1 81186288Sraj#define LBCRES_ATOM_WARA 2 82186288Sraj 83235937Smarcelstruct lbc_memrange { 84235937Smarcel vm_paddr_t addr; 85235937Smarcel vm_size_t size; 86235937Smarcel vm_offset_t kva; 87235937Smarcel}; 88235937Smarcel 89209908Srajstruct lbc_bank { 90235937Smarcel vm_paddr_t addr; /* physical addr of the bank */ 91235937Smarcel vm_size_t size; /* bank size */ 92235937Smarcel vm_offset_t kva; /* VA of the bank */ 93209908Sraj 94209908Sraj /* 95209908Sraj * XXX the following bank attributes do not have properties specified 96209908Sraj * in the LBC DTS bindings yet (11.2009), so they are mainly a 97209908Sraj * placeholder for future extensions. 98209908Sraj */ 99209908Sraj int width; /* data bus width */ 100209908Sraj uint8_t msel; /* machine select */ 101209908Sraj uint8_t atom; /* atomic op mode */ 102209908Sraj uint8_t wp; /* write protect */ 103209908Sraj uint8_t decc; /* data error checking */ 104186288Sraj}; 105186288Sraj 106209908Srajstruct lbc_softc { 107209908Sraj device_t sc_dev; 108238045Smarcel 109238045Smarcel struct resource *sc_mres; 110209908Sraj bus_space_handle_t sc_bsh; 111209908Sraj bus_space_tag_t sc_bst; 112238045Smarcel int sc_mrid; 113186288Sraj 114238045Smarcel int sc_irid; 115238045Smarcel struct resource *sc_ires; 116238045Smarcel void *sc_icookie; 117238045Smarcel 118209908Sraj struct rman sc_rman; 119209908Sraj 120209908Sraj int sc_addr_cells; 121209908Sraj int sc_size_cells; 122209908Sraj 123235937Smarcel struct lbc_memrange sc_range[LBC_DEV_MAX]; 124209908Sraj struct lbc_bank sc_banks[LBC_DEV_MAX]; 125238045Smarcel 126238045Smarcel uint32_t sc_ltesr; 127209908Sraj}; 128209908Sraj 129209908Srajstruct lbc_devinfo { 130209908Sraj struct ofw_bus_devinfo di_ofw; 131209908Sraj struct resource_list di_res; 132209908Sraj int di_bank; 133209908Sraj}; 134209908Sraj 135235937Smarceluint32_t lbc_read_reg(device_t child, u_int off); 136235937Smarcelvoid lbc_write_reg(device_t child, u_int off, uint32_t val); 137235937Smarcel 138184250Smarcel#endif /* _MACHINE_LBC_H_ */ 139