1139825Simp/*- 299654Sbenno * Copyright (C) 2002 Benno Rice. 399654Sbenno * All rights reserved. 499654Sbenno * 599654Sbenno * Redistribution and use in source and binary forms, with or without 699654Sbenno * modification, are permitted provided that the following conditions 799654Sbenno * are met: 899654Sbenno * 1. Redistributions of source code must retain the above copyright 999654Sbenno * notice, this list of conditions and the following disclaimer. 1099654Sbenno * 2. Redistributions in binary form must reproduce the above copyright 1199654Sbenno * notice, this list of conditions and the following disclaimer in the 1299654Sbenno * documentation and/or other materials provided with the distribution. 1399654Sbenno * 1499654Sbenno * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR 1599654Sbenno * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 1699654Sbenno * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 1799654Sbenno * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 1899654Sbenno * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 1999654Sbenno * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 2099654Sbenno * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 2199654Sbenno * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 2299654Sbenno * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 2399654Sbenno * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2499654Sbenno * 2599654Sbenno * $FreeBSD$ 2699654Sbenno */ 2799654Sbenno 2899654Sbenno#ifndef _POWERPC_OPENPICVAR_H_ 2999654Sbenno#define _POWERPC_OPENPICVAR_H_ 3099654Sbenno 31124469Sgrehan#define OPENPIC_DEVSTR "OpenPIC Interrupt Controller" 32124469Sgrehan 33124469Sgrehan#define OPENPIC_IRQMAX 256 /* h/w allows more */ 34124469Sgrehan 35259676Sjhibbits/* Names match the macros in openpicreg.h. */ 36259676Sjhibbitsstruct openpic_timer { 37259676Sjhibbits uint32_t tcnt; 38259676Sjhibbits uint32_t tbase; 39259676Sjhibbits uint32_t tvec; 40259676Sjhibbits uint32_t tdst; 41259676Sjhibbits}; 42259676Sjhibbits 4399654Sbennostruct openpic_softc { 44171805Smarcel device_t sc_dev; 45171805Smarcel struct resource *sc_memr; 46209298Snwhitehorn struct resource *sc_intr; 47171805Smarcel bus_space_tag_t sc_bt; 48171805Smarcel bus_space_handle_t sc_bh; 4999654Sbenno char *sc_version; 50171805Smarcel int sc_rid; 51209298Snwhitehorn int sc_irq; 52209298Snwhitehorn void *sc_icookie; 5399654Sbenno u_int sc_ncpu; 5499654Sbenno u_int sc_nirq; 55171805Smarcel int sc_psim; 56259676Sjhibbits 57259676Sjhibbits /* Saved states. */ 58259676Sjhibbits uint32_t sc_saved_config; 59259676Sjhibbits uint32_t sc_saved_ipis[4]; 60259676Sjhibbits uint32_t sc_saved_prios[4]; 61259676Sjhibbits struct openpic_timer sc_saved_timers[OPENPIC_TIMERS]; 62259676Sjhibbits uint32_t sc_saved_vectors[OPENPIC_SRC_VECTOR_COUNT]; 63259676Sjhibbits 6499654Sbenno}; 6599654Sbenno 66171805Smarcelextern devclass_t openpic_devclass; 67171805Smarcel 68124469Sgrehan/* 69124469Sgrehan * Bus-independent attach i/f 70124469Sgrehan */ 71218075Smarcelint openpic_common_attach(device_t, uint32_t); 72124469Sgrehan 73124469Sgrehan/* 74124469Sgrehan * PIC interface. 75124469Sgrehan */ 76222813Sattiliovoid openpic_bind(device_t dev, u_int irq, cpuset_t cpumask); 77176918Smarcelvoid openpic_config(device_t, u_int, enum intr_trigger, enum intr_polarity); 78171805Smarcelvoid openpic_dispatch(device_t, struct trapframe *); 79171805Smarcelvoid openpic_enable(device_t, u_int, u_int); 80171805Smarcelvoid openpic_eoi(device_t, u_int); 81176208Smarcelvoid openpic_ipi(device_t, u_int); 82171805Smarcelvoid openpic_mask(device_t, u_int); 83171805Smarcelvoid openpic_unmask(device_t, u_int); 84124469Sgrehan 85259676Sjhibbitsint openpic_suspend(device_t dev); 86259676Sjhibbitsint openpic_resume(device_t dev); 87259676Sjhibbits 8899654Sbenno#endif /* _POWERPC_OPENPICVAR_H_ */ 89