trap_subr64.S revision 242723
1/* $FreeBSD: head/sys/powerpc/aim/trap_subr64.S 242723 2012-11-07 23:45:09Z jhibbits $ */ 2/* $NetBSD: trap_subr.S,v 1.20 2002/04/22 23:20:08 kleink Exp $ */ 3 4/*- 5 * Copyright (C) 1995, 1996 Wolfgang Solfrank. 6 * Copyright (C) 1995, 1996 TooLs GmbH. 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by TooLs GmbH. 20 * 4. The name of TooLs GmbH may not be used to endorse or promote products 21 * derived from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 27 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 28 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 29 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 31 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 32 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35/* 36 * NOTICE: This is not a standalone file. to use it, #include it in 37 * your port's locore.S, like so: 38 * 39 * #include <powerpc/aim/trap_subr.S> 40 */ 41 42/* 43 * Save/restore segment registers 44 */ 45 46/* 47 * Restore SRs for a pmap 48 * 49 * Requires that r28-r31 be scratch, with r28 initialized to the SLB cache 50 */ 51 52/* 53 * User SRs are loaded through a pointer to the current pmap. 54 */ 55restore_usersrs: 56 GET_CPUINFO(%r28) 57 ld %r28,PC_USERSLB(%r28) 58 li %r29, 0 /* Set the counter to zero */ 59 60 slbia 61 slbmfee %r31,%r29 62 clrrdi %r31,%r31,28 63 slbie %r31 641: ld %r31, 0(%r28) /* Load SLB entry pointer */ 65 cmpli 0, %r31, 0 /* If NULL, stop */ 66 beqlr 67 68 ld %r30, 0(%r31) /* Load SLBV */ 69 ld %r31, 8(%r31) /* Load SLBE */ 70 or %r31, %r31, %r29 /* Set SLBE slot */ 71 slbmte %r30, %r31 /* Install SLB entry */ 72 73 addi %r28, %r28, 8 /* Advance pointer */ 74 addi %r29, %r29, 1 75 b 1b /* Repeat */ 76 77/* 78 * Kernel SRs are loaded directly from the PCPU fields 79 */ 80restore_kernsrs: 81 GET_CPUINFO(%r28) 82 addi %r28,%r28,PC_KERNSLB 83 li %r29, 0 /* Set the counter to zero */ 84 85 slbia 86 slbmfee %r31,%r29 87 clrrdi %r31,%r31,28 88 slbie %r31 891: cmpli 0, %r29, USER_SLB_SLOT /* Skip the user slot */ 90 beq- 2f 91 92 ld %r31, 8(%r28) /* Load SLBE */ 93 cmpli 0, %r31, 0 /* If SLBE is not valid, stop */ 94 beqlr 95 ld %r30, 0(%r28) /* Load SLBV */ 96 slbmte %r30, %r31 /* Install SLB entry */ 97 982: addi %r28, %r28, 16 /* Advance pointer */ 99 addi %r29, %r29, 1 100 cmpli 0, %r29, 64 /* Repeat if we are not at the end */ 101 blt 1b 102 blr 103 104/* 105 * FRAME_SETUP assumes: 106 * SPRG1 SP (1) 107 * SPRG3 trap type 108 * savearea r27-r31,DAR,DSISR (DAR & DSISR only for DSI traps) 109 * r28 LR 110 * r29 CR 111 * r30 scratch 112 * r31 scratch 113 * r1 kernel stack 114 * SRR0/1 as at start of trap 115 * 116 * NOTE: SPRG1 is never used while the MMU is on, making it safe to reuse 117 * in any real-mode fault handler, including those handling double faults. 118 */ 119#define FRAME_SETUP(savearea) \ 120/* Have to enable translation to allow access of kernel stack: */ \ 121 GET_CPUINFO(%r31); \ 122 mfsrr0 %r30; \ 123 std %r30,(savearea+CPUSAVE_SRR0)(%r31); /* save SRR0 */ \ 124 mfsrr1 %r30; \ 125 std %r30,(savearea+CPUSAVE_SRR1)(%r31); /* save SRR1 */ \ 126 mfsprg1 %r31; /* get saved SP (clears SPRG1) */ \ 127 mfmsr %r30; \ 128 ori %r30,%r30,(PSL_DR|PSL_IR|PSL_RI)@l; /* relocation on */ \ 129 mtmsr %r30; /* stack can now be accessed */ \ 130 isync; \ 131 stdu %r31,-(FRAMELEN+288)(%r1); /* save it in the callframe */ \ 132 std %r0, FRAME_0+48(%r1); /* save r0 in the trapframe */ \ 133 std %r31,FRAME_1+48(%r1); /* save SP " " */ \ 134 std %r2, FRAME_2+48(%r1); /* save r2 " " */ \ 135 std %r28,FRAME_LR+48(%r1); /* save LR " " */ \ 136 std %r29,FRAME_CR+48(%r1); /* save CR " " */ \ 137 GET_CPUINFO(%r2); \ 138 ld %r27,(savearea+CPUSAVE_R27)(%r2); /* get saved r27 */ \ 139 ld %r28,(savearea+CPUSAVE_R28)(%r2); /* get saved r28 */ \ 140 ld %r29,(savearea+CPUSAVE_R29)(%r2); /* get saved r29 */ \ 141 ld %r30,(savearea+CPUSAVE_R30)(%r2); /* get saved r30 */ \ 142 ld %r31,(savearea+CPUSAVE_R31)(%r2); /* get saved r31 */ \ 143 std %r3, FRAME_3+48(%r1); /* save r3-r31 */ \ 144 std %r4, FRAME_4+48(%r1); \ 145 std %r5, FRAME_5+48(%r1); \ 146 std %r6, FRAME_6+48(%r1); \ 147 std %r7, FRAME_7+48(%r1); \ 148 std %r8, FRAME_8+48(%r1); \ 149 std %r9, FRAME_9+48(%r1); \ 150 std %r10, FRAME_10+48(%r1); \ 151 std %r11, FRAME_11+48(%r1); \ 152 std %r12, FRAME_12+48(%r1); \ 153 std %r13, FRAME_13+48(%r1); \ 154 std %r14, FRAME_14+48(%r1); \ 155 std %r15, FRAME_15+48(%r1); \ 156 std %r16, FRAME_16+48(%r1); \ 157 std %r17, FRAME_17+48(%r1); \ 158 std %r18, FRAME_18+48(%r1); \ 159 std %r19, FRAME_19+48(%r1); \ 160 std %r20, FRAME_20+48(%r1); \ 161 std %r21, FRAME_21+48(%r1); \ 162 std %r22, FRAME_22+48(%r1); \ 163 std %r23, FRAME_23+48(%r1); \ 164 std %r24, FRAME_24+48(%r1); \ 165 std %r25, FRAME_25+48(%r1); \ 166 std %r26, FRAME_26+48(%r1); \ 167 std %r27, FRAME_27+48(%r1); \ 168 std %r28, FRAME_28+48(%r1); \ 169 std %r29, FRAME_29+48(%r1); \ 170 std %r30, FRAME_30+48(%r1); \ 171 std %r31, FRAME_31+48(%r1); \ 172 ld %r28,(savearea+CPUSAVE_AIM_DAR)(%r2); /* saved DAR */ \ 173 ld %r29,(savearea+CPUSAVE_AIM_DSISR)(%r2);/* saved DSISR */\ 174 ld %r30,(savearea+CPUSAVE_SRR0)(%r2); /* saved SRR0 */ \ 175 ld %r31,(savearea+CPUSAVE_SRR1)(%r2); /* saved SRR1 */ \ 176 mfxer %r3; \ 177 mfctr %r4; \ 178 mfsprg3 %r5; \ 179 std %r3, FRAME_XER+48(1); /* save xer/ctr/exc */ \ 180 std %r4, FRAME_CTR+48(1); \ 181 std %r5, FRAME_EXC+48(1); \ 182 std %r28,FRAME_AIM_DAR+48(1); \ 183 std %r29,FRAME_AIM_DSISR+48(1); /* save dsisr/srr0/srr1 */ \ 184 std %r30,FRAME_SRR0+48(1); \ 185 std %r31,FRAME_SRR1+48(1); \ 186 ld %r13,PC_CURTHREAD(%r2) /* set kernel curthread */ 187 188#define FRAME_LEAVE(savearea) \ 189/* Disable exceptions: */ \ 190 mfmsr %r2; \ 191 andi. %r2,%r2,~PSL_EE@l; \ 192 mtmsr %r2; \ 193 isync; \ 194/* Now restore regs: */ \ 195 ld %r2,FRAME_SRR0+48(%r1); \ 196 ld %r3,FRAME_SRR1+48(%r1); \ 197 ld %r4,FRAME_CTR+48(%r1); \ 198 ld %r5,FRAME_XER+48(%r1); \ 199 ld %r6,FRAME_LR+48(%r1); \ 200 GET_CPUINFO(%r7); \ 201 std %r2,(savearea+CPUSAVE_SRR0)(%r7); /* save SRR0 */ \ 202 std %r3,(savearea+CPUSAVE_SRR1)(%r7); /* save SRR1 */ \ 203 ld %r7,FRAME_CR+48(%r1); \ 204 mtctr %r4; \ 205 mtxer %r5; \ 206 mtlr %r6; \ 207 mtsprg2 %r7; /* save cr */ \ 208 ld %r31,FRAME_31+48(%r1); /* restore r0-31 */ \ 209 ld %r30,FRAME_30+48(%r1); \ 210 ld %r29,FRAME_29+48(%r1); \ 211 ld %r28,FRAME_28+48(%r1); \ 212 ld %r27,FRAME_27+48(%r1); \ 213 ld %r26,FRAME_26+48(%r1); \ 214 ld %r25,FRAME_25+48(%r1); \ 215 ld %r24,FRAME_24+48(%r1); \ 216 ld %r23,FRAME_23+48(%r1); \ 217 ld %r22,FRAME_22+48(%r1); \ 218 ld %r21,FRAME_21+48(%r1); \ 219 ld %r20,FRAME_20+48(%r1); \ 220 ld %r19,FRAME_19+48(%r1); \ 221 ld %r18,FRAME_18+48(%r1); \ 222 ld %r17,FRAME_17+48(%r1); \ 223 ld %r16,FRAME_16+48(%r1); \ 224 ld %r15,FRAME_15+48(%r1); \ 225 ld %r14,FRAME_14+48(%r1); \ 226 ld %r13,FRAME_13+48(%r1); \ 227 ld %r12,FRAME_12+48(%r1); \ 228 ld %r11,FRAME_11+48(%r1); \ 229 ld %r10,FRAME_10+48(%r1); \ 230 ld %r9, FRAME_9+48(%r1); \ 231 ld %r8, FRAME_8+48(%r1); \ 232 ld %r7, FRAME_7+48(%r1); \ 233 ld %r6, FRAME_6+48(%r1); \ 234 ld %r5, FRAME_5+48(%r1); \ 235 ld %r4, FRAME_4+48(%r1); \ 236 ld %r3, FRAME_3+48(%r1); \ 237 ld %r2, FRAME_2+48(%r1); \ 238 ld %r0, FRAME_0+48(%r1); \ 239 ld %r1, FRAME_1+48(%r1); \ 240/* Can't touch %r1 from here on */ \ 241 mtsprg3 %r3; /* save r3 */ \ 242/* Disable translation, machine check and recoverability: */ \ 243 mfmsr %r3; \ 244 andi. %r3,%r3,~(PSL_DR|PSL_IR|PSL_ME|PSL_RI)@l; \ 245 mtmsr %r3; \ 246 isync; \ 247/* Decide whether we return to user mode: */ \ 248 GET_CPUINFO(%r3); \ 249 ld %r3,(savearea+CPUSAVE_SRR1)(%r3); \ 250 mtcr %r3; \ 251 bf 17,1f; /* branch if PSL_PR is false */ \ 252/* Restore user SRs */ \ 253 GET_CPUINFO(%r3); \ 254 std %r27,(savearea+CPUSAVE_R27)(%r3); \ 255 std %r28,(savearea+CPUSAVE_R28)(%r3); \ 256 std %r29,(savearea+CPUSAVE_R29)(%r3); \ 257 std %r30,(savearea+CPUSAVE_R30)(%r3); \ 258 std %r31,(savearea+CPUSAVE_R31)(%r3); \ 259 mflr %r27; /* preserve LR */ \ 260 bl restore_usersrs; /* uses r28-r31 */ \ 261 mtlr %r27; \ 262 ld %r31,(savearea+CPUSAVE_R31)(%r3); \ 263 ld %r30,(savearea+CPUSAVE_R30)(%r3); \ 264 ld %r29,(savearea+CPUSAVE_R29)(%r3); \ 265 ld %r28,(savearea+CPUSAVE_R28)(%r3); \ 266 ld %r27,(savearea+CPUSAVE_R27)(%r3); \ 2671: mfsprg2 %r3; /* restore cr */ \ 268 mtcr %r3; \ 269 GET_CPUINFO(%r3); \ 270 ld %r3,(savearea+CPUSAVE_SRR0)(%r3); /* restore srr0 */ \ 271 mtsrr0 %r3; \ 272 GET_CPUINFO(%r3); \ 273 ld %r3,(savearea+CPUSAVE_SRR1)(%r3); /* restore srr1 */ \ 274 mtsrr1 %r3; \ 275 mfsprg3 %r3 /* restore r3 */ 276 277#ifdef KDTRACE_HOOKS 278 .data 279 .globl dtrace_invop_jump_addr 280 .align 8 281 .type dtrace_invop_jump_addr, @object 282 .size dtrace_invop_jump_addr, 8 283dtrace_invop_jump_addr: 284 .word 0 285 .word 0 286 .globl dtrace_invop_calltrap_addr 287 .align 8 288 .type dtrace_invop_calltrap_addr, @object 289 .size dtrace_invop_calltrap_addr, 8 290dtrace_invop_calltrap_addr: 291 .word 0 292 .word 0 293 294 .text 295#endif 296 297#ifdef SMP 298/* 299 * Processor reset exception handler. These are typically 300 * the first instructions the processor executes after a 301 * software reset. We do this in two bits so that we are 302 * not still hanging around in the trap handling region 303 * once the MMU is turned on. 304 */ 305 .globl CNAME(rstcode), CNAME(rstsize) 306CNAME(rstcode): 307 /* Explicitly set MSR[SF] */ 308 mfmsr %r9 309 li %r8,1 310 insrdi %r9,%r8,1,0 311 mtmsrd %r9 312 isync 313 314 ba cpu_reset 315CNAME(rstsize) = . - CNAME(rstcode) 316 317cpu_reset: 318 lis %r1,(tmpstk+TMPSTKSZ-48)@ha /* get new SP */ 319 addi %r1,%r1,(tmpstk+TMPSTKSZ-48)@l 320 321 lis %r3,tocbase@ha 322 ld %r2,tocbase@l(%r3) 323 lis %r3,1@l 324 bl CNAME(cpudep_ap_early_bootstrap) /* Set PCPU */ 325 nop 326 lis %r3,1@l 327 bl CNAME(pmap_cpu_bootstrap) /* Turn on virtual memory */ 328 nop 329 bl CNAME(cpudep_ap_bootstrap) /* Set up PCPU and stack */ 330 nop 331 mr %r1,%r3 /* Use new stack */ 332 bl CNAME(machdep_ap_bootstrap) /* And away! */ 333 nop 334 335 /* Should not be reached */ 3369: 337 b 9b 338#endif 339 340/* 341 * This code gets copied to all the trap vectors 342 * (except ISI/DSI, ALI, and the interrupts) 343 */ 344 345 .globl CNAME(trapcode),CNAME(trapsize) 346CNAME(trapcode): 347 mtsprg1 %r1 /* save SP */ 348 mflr %r1 /* Save the old LR in r1 */ 349 mtsprg2 %r1 /* And then in SPRG2 */ 350 li %r1, 0xA0 /* How to get the vector from LR */ 351 bla generictrap /* LR & SPRG3 is exception # */ 352CNAME(trapsize) = .-CNAME(trapcode) 353 354/* 355 * For SLB misses: do special things for the kernel 356 * 357 * Note: SPRG1 is always safe to overwrite any time the MMU is on, which is 358 * the only time this can be called. 359 */ 360 .globl CNAME(slbtrap),CNAME(slbtrapsize) 361CNAME(slbtrap): 362 mtsprg1 %r1 /* save SP */ 363 GET_CPUINFO(%r1) 364 std %r2,(PC_SLBSAVE+16)(%r1) 365 mfcr %r2 /* save CR */ 366 std %r2,(PC_SLBSAVE+104)(%r1) 367 mfsrr1 %r2 /* test kernel mode */ 368 mtcr %r2 369 bf 17,1f /* branch if PSL_PR is false */ 370 /* User mode */ 371 ld %r2,(PC_SLBSAVE+104)(%r1) /* Restore CR */ 372 mtcr %r2 373 ld %r2,(PC_SLBSAVE+16)(%r1) /* Restore R2 */ 374 mflr %r1 /* Save the old LR in r1 */ 375 mtsprg2 %r1 /* And then in SPRG2 */ 376 li %r1, 0x80 /* How to get the vector from LR */ 377 bla generictrap /* LR & SPRG3 is exception # */ 3781: mflr %r2 /* Save the old LR in r2 */ 379 bla kern_slbtrap 380CNAME(slbtrapsize) = .-CNAME(slbtrap) 381 382kern_slbtrap: 383 std %r2,(PC_SLBSAVE+136)(%r1) /* old LR */ 384 std %r3,(PC_SLBSAVE+24)(%r1) /* save R3 */ 385 386 /* Check if this needs to be handled as a regular trap (userseg miss) */ 387 mflr %r2 388 andi. %r2,%r2,0xff80 389 cmpwi %r2,0x380 390 bne 1f 391 mfdar %r2 392 b 2f 3931: mfsrr0 %r2 3942: /* r2 now contains the fault address */ 395 lis %r3,SEGMENT_MASK@highesta 396 ori %r3,%r3,SEGMENT_MASK@highera 397 sldi %r3,%r3,32 398 oris %r3,%r3,SEGMENT_MASK@ha 399 ori %r3,%r3,SEGMENT_MASK@l 400 and %r2,%r2,%r3 /* R2 = segment base address */ 401 lis %r3,USER_ADDR@highesta 402 ori %r3,%r3,USER_ADDR@highera 403 sldi %r3,%r3,32 404 oris %r3,%r3,USER_ADDR@ha 405 ori %r3,%r3,USER_ADDR@l 406 cmpd %r2,%r3 /* Compare fault base to USER_ADDR */ 407 bne 3f 408 409 /* User seg miss, handle as a regular trap */ 410 ld %r2,(PC_SLBSAVE+104)(%r1) /* Restore CR */ 411 mtcr %r2 412 ld %r2,(PC_SLBSAVE+16)(%r1) /* Restore R2,R3 */ 413 ld %r3,(PC_SLBSAVE+24)(%r1) 414 ld %r1,(PC_SLBSAVE+136)(%r1) /* Save the old LR in r1 */ 415 mtsprg2 %r1 /* And then in SPRG2 */ 416 li %r1, 0x80 /* How to get the vector from LR */ 417 b generictrap /* Retain old LR using b */ 418 4193: /* Real kernel SLB miss */ 420 std %r0,(PC_SLBSAVE+0)(%r1) /* free all volatile regs */ 421 mfsprg1 %r2 /* Old R1 */ 422 std %r2,(PC_SLBSAVE+8)(%r1) 423 /* R2,R3 already saved */ 424 std %r4,(PC_SLBSAVE+32)(%r1) 425 std %r5,(PC_SLBSAVE+40)(%r1) 426 std %r6,(PC_SLBSAVE+48)(%r1) 427 std %r7,(PC_SLBSAVE+56)(%r1) 428 std %r8,(PC_SLBSAVE+64)(%r1) 429 std %r9,(PC_SLBSAVE+72)(%r1) 430 std %r10,(PC_SLBSAVE+80)(%r1) 431 std %r11,(PC_SLBSAVE+88)(%r1) 432 std %r12,(PC_SLBSAVE+96)(%r1) 433 /* CR already saved */ 434 mfxer %r2 /* save XER */ 435 std %r2,(PC_SLBSAVE+112)(%r1) 436 mflr %r2 /* save LR (SP already saved) */ 437 std %r2,(PC_SLBSAVE+120)(%r1) 438 mfctr %r2 /* save CTR */ 439 std %r2,(PC_SLBSAVE+128)(%r1) 440 441 /* Call handler */ 442 addi %r1,%r1,PC_SLBSTACK-48+1024 443 li %r2,~15 444 and %r1,%r1,%r2 445 lis %r3,tocbase@ha 446 ld %r2,tocbase@l(%r3) 447 mflr %r3 448 andi. %r3,%r3,0xff80 449 mfdar %r4 450 mfsrr0 %r5 451 bl handle_kernel_slb_spill 452 nop 453 454 /* Save r28-31, restore r4-r12 */ 455 GET_CPUINFO(%r1) 456 ld %r4,(PC_SLBSAVE+32)(%r1) 457 ld %r5,(PC_SLBSAVE+40)(%r1) 458 ld %r6,(PC_SLBSAVE+48)(%r1) 459 ld %r7,(PC_SLBSAVE+56)(%r1) 460 ld %r8,(PC_SLBSAVE+64)(%r1) 461 ld %r9,(PC_SLBSAVE+72)(%r1) 462 ld %r10,(PC_SLBSAVE+80)(%r1) 463 ld %r11,(PC_SLBSAVE+88)(%r1) 464 ld %r12,(PC_SLBSAVE+96)(%r1) 465 std %r28,(PC_SLBSAVE+64)(%r1) 466 std %r29,(PC_SLBSAVE+72)(%r1) 467 std %r30,(PC_SLBSAVE+80)(%r1) 468 std %r31,(PC_SLBSAVE+88)(%r1) 469 470 /* Restore kernel mapping */ 471 bl restore_kernsrs 472 473 /* Restore remaining registers */ 474 ld %r28,(PC_SLBSAVE+64)(%r1) 475 ld %r29,(PC_SLBSAVE+72)(%r1) 476 ld %r30,(PC_SLBSAVE+80)(%r1) 477 ld %r31,(PC_SLBSAVE+88)(%r1) 478 479 ld %r2,(PC_SLBSAVE+104)(%r1) 480 mtcr %r2 481 ld %r2,(PC_SLBSAVE+112)(%r1) 482 mtxer %r2 483 ld %r2,(PC_SLBSAVE+120)(%r1) 484 mtlr %r2 485 ld %r2,(PC_SLBSAVE+128)(%r1) 486 mtctr %r2 487 ld %r2,(PC_SLBSAVE+136)(%r1) 488 mtlr %r2 489 490 /* Restore r0-r3 */ 491 ld %r0,(PC_SLBSAVE+0)(%r1) 492 ld %r2,(PC_SLBSAVE+16)(%r1) 493 ld %r3,(PC_SLBSAVE+24)(%r1) 494 mfsprg1 %r1 495 496 /* Back to whatever we were doing */ 497 rfid 498 499/* 500 * For ALI: has to save DSISR and DAR 501 */ 502 .globl CNAME(alitrap),CNAME(alisize) 503CNAME(alitrap): 504 mtsprg1 %r1 /* save SP */ 505 GET_CPUINFO(%r1) 506 std %r27,(PC_TEMPSAVE+CPUSAVE_R27)(%r1) /* free r27-r31 */ 507 std %r28,(PC_TEMPSAVE+CPUSAVE_R28)(%r1) 508 std %r29,(PC_TEMPSAVE+CPUSAVE_R29)(%r1) 509 std %r30,(PC_TEMPSAVE+CPUSAVE_R30)(%r1) 510 std %r31,(PC_TEMPSAVE+CPUSAVE_R31)(%r1) 511 mfdar %r30 512 mfdsisr %r31 513 std %r30,(PC_TEMPSAVE+CPUSAVE_AIM_DAR)(%r1) 514 std %r31,(PC_TEMPSAVE+CPUSAVE_AIM_DSISR)(%r1) 515 mfsprg1 %r1 /* restore SP, in case of branch */ 516 mflr %r28 /* save LR */ 517 mfcr %r29 /* save CR */ 518 519 /* Put our exception vector in SPRG3 */ 520 li %r31, EXC_ALI 521 mtsprg3 %r31 522 523 /* Test whether we already had PR set */ 524 mfsrr1 %r31 525 mtcr %r31 526 bla s_trap 527CNAME(alisize) = .-CNAME(alitrap) 528 529/* 530 * Similar to the above for DSI 531 * Has to handle BAT spills 532 * and standard pagetable spills 533 */ 534 .globl CNAME(dsitrap),CNAME(dsisize) 535CNAME(dsitrap): 536 mtsprg1 %r1 /* save SP */ 537 GET_CPUINFO(%r1) 538 std %r27,(PC_DISISAVE+CPUSAVE_R27)(%r1) /* free r27-r31 */ 539 std %r28,(PC_DISISAVE+CPUSAVE_R28)(%r1) 540 std %r29,(PC_DISISAVE+CPUSAVE_R29)(%r1) 541 std %r30,(PC_DISISAVE+CPUSAVE_R30)(%r1) 542 std %r31,(PC_DISISAVE+CPUSAVE_R31)(%r1) 543 mfsprg1 %r1 /* restore SP */ 544 mfcr %r29 /* save CR */ 545 mfxer %r30 /* save XER */ 546 mtsprg2 %r30 /* in SPRG2 */ 547 mfsrr1 %r31 /* test kernel mode */ 548 mtcr %r31 549 mflr %r28 /* save LR (SP already saved) */ 550 bla disitrap 551CNAME(dsisize) = .-CNAME(dsitrap) 552 553/* 554 * Preamble code for DSI/ISI traps 555 */ 556disitrap: 557 /* Write the trap vector to SPRG3 by computing LR & 0xff00 */ 558 mflr %r1 559 andi. %r1,%r1,0xff00 560 mtsprg3 %r1 561 562 GET_CPUINFO(%r1) 563 ld %r31,(PC_DISISAVE+CPUSAVE_R27)(%r1) 564 std %r31,(PC_TEMPSAVE+CPUSAVE_R27)(%r1) 565 ld %r30,(PC_DISISAVE+CPUSAVE_R28)(%r1) 566 std %r30,(PC_TEMPSAVE+CPUSAVE_R28)(%r1) 567 ld %r31,(PC_DISISAVE+CPUSAVE_R29)(%r1) 568 std %r31,(PC_TEMPSAVE+CPUSAVE_R29)(%r1) 569 ld %r30,(PC_DISISAVE+CPUSAVE_R30)(%r1) 570 std %r30,(PC_TEMPSAVE+CPUSAVE_R30)(%r1) 571 ld %r31,(PC_DISISAVE+CPUSAVE_R31)(%r1) 572 std %r31,(PC_TEMPSAVE+CPUSAVE_R31)(%r1) 573 mfdar %r30 574 mfdsisr %r31 575 std %r30,(PC_TEMPSAVE+CPUSAVE_AIM_DAR)(%r1) 576 std %r31,(PC_TEMPSAVE+CPUSAVE_AIM_DSISR)(%r1) 577 578#ifdef KDB 579 /* Try and detect a kernel stack overflow */ 580 mfsrr1 %r31 581 mtcr %r31 582 bt 17,realtrap /* branch is user mode */ 583 mfsprg1 %r31 /* get old SP */ 584 sub. %r30,%r31,%r30 /* SP - DAR */ 585 bge 1f 586 neg %r30,%r30 /* modulo value */ 5871: cmpldi %cr0,%r30,4096 /* is DAR within a page of SP? */ 588 bge %cr0,realtrap /* no, too far away. */ 589 590 /* Now convert this DSI into a DDB trap. */ 591 GET_CPUINFO(%r1) 592 ld %r30,(PC_TEMPSAVE+CPUSAVE_AIM_DAR)(%r1) /* get DAR */ 593 std %r30,(PC_DBSAVE +CPUSAVE_AIM_DAR)(%r1) /* save DAR */ 594 ld %r30,(PC_TEMPSAVE+CPUSAVE_AIM_DSISR)(%r1) /* get DSISR */ 595 std %r30,(PC_DBSAVE +CPUSAVE_AIM_DSISR)(%r1) /* save DSISR */ 596 ld %r31,(PC_DISISAVE+CPUSAVE_R27)(%r1) /* get r27 */ 597 std %r31,(PC_DBSAVE +CPUSAVE_R27)(%r1) /* save r27 */ 598 ld %r30,(PC_DISISAVE+CPUSAVE_R28)(%r1) /* get r28 */ 599 std %r30,(PC_DBSAVE +CPUSAVE_R28)(%r1) /* save r28 */ 600 ld %r31,(PC_DISISAVE+CPUSAVE_R29)(%r1) /* get r29 */ 601 std %r31,(PC_DBSAVE +CPUSAVE_R29)(%r1) /* save r29 */ 602 ld %r30,(PC_DISISAVE+CPUSAVE_R30)(%r1) /* get r30 */ 603 std %r30,(PC_DBSAVE +CPUSAVE_R30)(%r1) /* save r30 */ 604 ld %r31,(PC_DISISAVE+CPUSAVE_R31)(%r1) /* get r31 */ 605 std %r31,(PC_DBSAVE +CPUSAVE_R31)(%r1) /* save r31 */ 606 b dbtrap 607#endif 608 609 /* XXX need stack probe here */ 610realtrap: 611/* Test whether we already had PR set */ 612 mfsrr1 %r1 613 mtcr %r1 614 mfsprg1 %r1 /* restore SP (might have been 615 overwritten) */ 616 bf 17,k_trap /* branch if PSL_PR is false */ 617 GET_CPUINFO(%r1) 618 ld %r1,PC_CURPCB(%r1) 619 mr %r27,%r28 /* Save LR, r29 */ 620 mtsprg2 %r29 621 bl restore_kernsrs /* enable kernel mapping */ 622 mfsprg2 %r29 623 mr %r28,%r27 624 ba s_trap 625 626/* 627 * generictrap does some standard setup for trap handling to minimize 628 * the code that need be installed in the actual vectors. It expects 629 * the following conditions. 630 * 631 * R1 - Trap vector = LR & (0xff00 | R1) 632 * SPRG1 - Original R1 contents 633 * SPRG2 - Original LR 634 */ 635 636generictrap: 637 /* Save R1 for computing the exception vector */ 638 mtsprg3 %r1 639 640 /* Save interesting registers */ 641 GET_CPUINFO(%r1) 642 std %r27,(PC_TEMPSAVE+CPUSAVE_R27)(%r1) /* free r27-r31 */ 643 std %r28,(PC_TEMPSAVE+CPUSAVE_R28)(%r1) 644 std %r29,(PC_TEMPSAVE+CPUSAVE_R29)(%r1) 645 std %r30,(PC_TEMPSAVE+CPUSAVE_R30)(%r1) 646 std %r31,(PC_TEMPSAVE+CPUSAVE_R31)(%r1) 647 mfdar %r30 648 std %r30,(PC_TEMPSAVE+CPUSAVE_AIM_DAR)(%r1) 649 mfsprg1 %r1 /* restore SP, in case of branch */ 650 mfsprg2 %r28 /* save LR */ 651 mfcr %r29 /* save CR */ 652 653 /* Compute the exception vector from the link register */ 654 mfsprg3 %r31 655 ori %r31,%r31,0xff00 656 mflr %r30 657 and %r30,%r30,%r31 658 mtsprg3 %r30 659 660 /* Test whether we already had PR set */ 661 mfsrr1 %r31 662 mtcr %r31 663 664s_trap: 665 bf 17,k_trap /* branch if PSL_PR is false */ 666 GET_CPUINFO(%r1) 667u_trap: 668 ld %r1,PC_CURPCB(%r1) 669 mr %r27,%r28 /* Save LR, r29 */ 670 mtsprg2 %r29 671 bl restore_kernsrs /* enable kernel mapping */ 672 mfsprg2 %r29 673 mr %r28,%r27 674 675/* 676 * Now the common trap catching code. 677 */ 678k_trap: 679 FRAME_SETUP(PC_TEMPSAVE) 680/* Call C interrupt dispatcher: */ 681trapagain: 682 lis %r3,tocbase@ha 683 ld %r2,tocbase@l(%r3) 684 addi %r3,%r1,48 685 bl CNAME(powerpc_interrupt) 686 nop 687 688 .globl CNAME(trapexit) /* backtrace code sentinel */ 689CNAME(trapexit): 690/* Disable interrupts: */ 691 mfmsr %r3 692 andi. %r3,%r3,~PSL_EE@l 693 mtmsr %r3 694 isync 695/* Test AST pending: */ 696 ld %r5,FRAME_SRR1+48(%r1) 697 mtcr %r5 698 bf 17,1f /* branch if PSL_PR is false */ 699 700 GET_CPUINFO(%r3) /* get per-CPU pointer */ 701 lwz %r4, TD_FLAGS(%r13) /* get thread flags value */ 702 lis %r5, (TDF_ASTPENDING|TDF_NEEDRESCHED)@h 703 ori %r5,%r5, (TDF_ASTPENDING|TDF_NEEDRESCHED)@l 704 and. %r4,%r4,%r5 705 beq 1f 706 mfmsr %r3 /* re-enable interrupts */ 707 ori %r3,%r3,PSL_EE@l 708 mtmsr %r3 709 isync 710 lis %r3,tocbase@ha 711 ld %r2,tocbase@l(%r3) 712 addi %r3,%r1,48 713 bl CNAME(ast) 714 nop 715 .globl CNAME(asttrapexit) /* backtrace code sentinel #2 */ 716CNAME(asttrapexit): 717 b trapexit /* test ast ret value ? */ 7181: 719 FRAME_LEAVE(PC_TEMPSAVE) 720 rfid 721 722#if defined(KDB) 723/* 724 * Deliberate entry to dbtrap 725 */ 726ASENTRY_NOPROF(breakpoint) 727 mtsprg1 %r1 728 mfmsr %r3 729 mtsrr1 %r3 730 andi. %r3,%r3,~(PSL_EE|PSL_ME)@l 731 mtmsr %r3 /* disable interrupts */ 732 isync 733 GET_CPUINFO(%r3) 734 std %r27,(PC_DBSAVE+CPUSAVE_R27)(%r3) 735 std %r28,(PC_DBSAVE+CPUSAVE_R28)(%r3) 736 std %r29,(PC_DBSAVE+CPUSAVE_R29)(%r3) 737 std %r30,(PC_DBSAVE+CPUSAVE_R30)(%r3) 738 std %r31,(PC_DBSAVE+CPUSAVE_R31)(%r3) 739 mflr %r28 740 li %r29,EXC_BPT 741 mtlr %r29 742 mfcr %r29 743 mtsrr0 %r28 744 745/* 746 * Now the kdb trap catching code. 747 */ 748dbtrap: 749 /* Write the trap vector to SPRG3 by computing LR & 0xff00 */ 750 mflr %r1 751 andi. %r1,%r1,0xff00 752 mtsprg3 %r1 753 754 lis %r1,(tmpstk+TMPSTKSZ-48)@ha /* get new SP */ 755 addi %r1,%r1,(tmpstk+TMPSTKSZ-48)@l 756 757 FRAME_SETUP(PC_DBSAVE) 758/* Call C trap code: */ 759 lis %r3,tocbase@ha 760 ld %r2,tocbase@l(%r3) 761 addi %r3,%r1,48 762 bl CNAME(db_trap_glue) 763 nop 764 or. %r3,%r3,%r3 765 bne dbleave 766/* This wasn't for KDB, so switch to real trap: */ 767 ld %r3,FRAME_EXC+48(%r1) /* save exception */ 768 GET_CPUINFO(%r4) 769 std %r3,(PC_DBSAVE+CPUSAVE_R31)(%r4) 770 FRAME_LEAVE(PC_DBSAVE) 771 mtsprg1 %r1 /* prepare for entrance to realtrap */ 772 GET_CPUINFO(%r1) 773 std %r27,(PC_TEMPSAVE+CPUSAVE_R27)(%r1) 774 std %r28,(PC_TEMPSAVE+CPUSAVE_R28)(%r1) 775 std %r29,(PC_TEMPSAVE+CPUSAVE_R29)(%r1) 776 std %r30,(PC_TEMPSAVE+CPUSAVE_R30)(%r1) 777 std %r31,(PC_TEMPSAVE+CPUSAVE_R31)(%r1) 778 mflr %r28 779 mfcr %r29 780 ld %r31,(PC_DBSAVE+CPUSAVE_R31)(%r1) 781 mtsprg3 %r31 /* SPRG3 was clobbered by FRAME_LEAVE */ 782 mfsprg1 %r1 783 b realtrap 784dbleave: 785 FRAME_LEAVE(PC_DBSAVE) 786 rfid 787 788/* 789 * In case of KDB we want a separate trap catcher for it 790 */ 791 .globl CNAME(dblow),CNAME(dbsize) 792CNAME(dblow): 793 mtsprg1 %r1 /* save SP */ 794 mtsprg2 %r29 /* save r29 */ 795 mfcr %r29 /* save CR in r29 */ 796 mfsrr1 %r1 797 mtcr %r1 798 bf 17,1f /* branch if privileged */ 799 800 /* Unprivileged case */ 801 mtcr %r29 /* put the condition register back */ 802 mfsprg2 %r29 /* ... and r29 */ 803 mflr %r1 /* save LR */ 804 mtsprg2 %r1 /* And then in SPRG2 */ 805 li %r1, 0 /* How to get the vector from LR */ 806 807 bla generictrap /* and we look like a generic trap */ 8081: 809 /* Privileged, so drop to KDB */ 810 GET_CPUINFO(%r1) 811 std %r27,(PC_DBSAVE+CPUSAVE_R27)(%r1) /* free r27 */ 812 std %r28,(PC_DBSAVE+CPUSAVE_R28)(%r1) /* free r28 */ 813 mfsprg2 %r28 /* r29 holds cr... */ 814 std %r28,(PC_DBSAVE+CPUSAVE_R29)(%r1) /* free r29 */ 815 std %r30,(PC_DBSAVE+CPUSAVE_R30)(%r1) /* free r30 */ 816 std %r31,(PC_DBSAVE+CPUSAVE_R31)(%r1) /* free r31 */ 817 mflr %r28 /* save LR */ 818 bla dbtrap 819CNAME(dbsize) = .-CNAME(dblow) 820#endif /* KDB */ 821