trap_subr64.S revision 191039
195719Sbenno/* $FreeBSD: head/sys/powerpc/aim/trap_subr.S 191039 2009-04-14 04:15:56Z nwhitehorn $ */ 295719Sbenno/* $NetBSD: trap_subr.S,v 1.20 2002/04/22 23:20:08 kleink Exp $ */ 395719Sbenno 4139825Simp/*- 595719Sbenno * Copyright (C) 1995, 1996 Wolfgang Solfrank. 695719Sbenno * Copyright (C) 1995, 1996 TooLs GmbH. 795719Sbenno * All rights reserved. 895719Sbenno * 995719Sbenno * Redistribution and use in source and binary forms, with or without 1095719Sbenno * modification, are permitted provided that the following conditions 1195719Sbenno * are met: 1295719Sbenno * 1. Redistributions of source code must retain the above copyright 1395719Sbenno * notice, this list of conditions and the following disclaimer. 1495719Sbenno * 2. Redistributions in binary form must reproduce the above copyright 1595719Sbenno * notice, this list of conditions and the following disclaimer in the 1695719Sbenno * documentation and/or other materials provided with the distribution. 1795719Sbenno * 3. All advertising materials mentioning features or use of this software 1895719Sbenno * must display the following acknowledgement: 1995719Sbenno * This product includes software developed by TooLs GmbH. 2095719Sbenno * 4. The name of TooLs GmbH may not be used to endorse or promote products 2195719Sbenno * derived from this software without specific prior written permission. 2295719Sbenno * 2395719Sbenno * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 2495719Sbenno * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 2595719Sbenno * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 2695719Sbenno * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2795719Sbenno * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 2895719Sbenno * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 2995719Sbenno * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 3095719Sbenno * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 3195719Sbenno * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 3295719Sbenno * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3395719Sbenno */ 3495719Sbenno 3595719Sbenno/* 3695719Sbenno * NOTICE: This is not a standalone file. to use it, #include it in 3795719Sbenno * your port's locore.S, like so: 3895719Sbenno * 39174599Smarcel * #include <powerpc/aim/trap_subr.S> 4095719Sbenno */ 4195719Sbenno 4295719Sbenno/* 43125441Sgrehan * Save/restore segment registers 4495719Sbenno */ 45125441Sgrehan#define RESTORE_SRS(pmap,sr) mtsr 0,sr; \ 46125441Sgrehan lwz sr,1*4(pmap); mtsr 1,sr; \ 47125441Sgrehan lwz sr,2*4(pmap); mtsr 2,sr; \ 48125441Sgrehan lwz sr,3*4(pmap); mtsr 3,sr; \ 49125441Sgrehan lwz sr,4*4(pmap); mtsr 4,sr; \ 50125441Sgrehan lwz sr,5*4(pmap); mtsr 5,sr; \ 51125441Sgrehan lwz sr,6*4(pmap); mtsr 6,sr; \ 52125441Sgrehan lwz sr,7*4(pmap); mtsr 7,sr; \ 53125441Sgrehan lwz sr,8*4(pmap); mtsr 8,sr; \ 54125441Sgrehan lwz sr,9*4(pmap); mtsr 9,sr; \ 55125441Sgrehan lwz sr,10*4(pmap); mtsr 10,sr; \ 56125441Sgrehan lwz sr,11*4(pmap); mtsr 11,sr; \ 57125441Sgrehan lwz sr,12*4(pmap); mtsr 12,sr; \ 58125441Sgrehan lwz sr,13*4(pmap); mtsr 13,sr; \ 59125441Sgrehan lwz sr,14*4(pmap); mtsr 14,sr; \ 60125441Sgrehan lwz sr,15*4(pmap); mtsr 15,sr; isync; 6195719Sbenno 6295719Sbenno/* 63125441Sgrehan * User SRs are loaded through a pointer to the current pmap. 6495719Sbenno */ 65125441Sgrehan#define RESTORE_USER_SRS(pmap,sr) \ 66125441Sgrehan GET_CPUINFO(pmap); \ 67125441Sgrehan lwz pmap,PC_CURPMAP(pmap); \ 68125441Sgrehan lwzu sr,PM_SR(pmap); \ 69125441Sgrehan RESTORE_SRS(pmap,sr) 7095719Sbenno 7195719Sbenno/* 72125441Sgrehan * Kernel SRs are loaded directly from kernel_pmap_ 7395719Sbenno */ 74125441Sgrehan#define RESTORE_KERN_SRS(pmap,sr) \ 75125441Sgrehan lis pmap,CNAME(kernel_pmap_store)@ha; \ 76125441Sgrehan lwzu sr,CNAME(kernel_pmap_store)+PM_SR@l(pmap); \ 77125441Sgrehan RESTORE_SRS(pmap,sr) 7895719Sbenno 79125441Sgrehan/* 80125441Sgrehan * FRAME_SETUP assumes: 81125441Sgrehan * SPRG1 SP (1) 82188860Snwhitehorn * SPRG3 trap type 83125441Sgrehan * savearea r28-r31,DAR,DSISR (DAR & DSISR only for DSI traps) 84125441Sgrehan * r28 LR 85125441Sgrehan * r29 CR 86125441Sgrehan * r30 scratch 87125441Sgrehan * r31 scratch 88125441Sgrehan * r1 kernel stack 89125441Sgrehan * SRR0/1 as at start of trap 90125441Sgrehan */ 91125441Sgrehan#define FRAME_SETUP(savearea) \ 92125441Sgrehan/* Have to enable translation to allow access of kernel stack: */ \ 93125441Sgrehan GET_CPUINFO(%r31); \ 94125441Sgrehan mfsrr0 %r30; \ 95125441Sgrehan stw %r30,(savearea+CPUSAVE_SRR0)(%r31); /* save SRR0 */ \ 96125441Sgrehan mfsrr1 %r30; \ 97125441Sgrehan stw %r30,(savearea+CPUSAVE_SRR1)(%r31); /* save SRR1 */ \ 98125441Sgrehan mfmsr %r30; \ 99125441Sgrehan ori %r30,%r30,(PSL_DR|PSL_IR|PSL_RI)@l; /* relocation on */ \ 100125441Sgrehan mtmsr %r30; /* stack can now be accessed */ \ 101125441Sgrehan isync; \ 102125441Sgrehan mfsprg1 %r31; /* get saved SP */ \ 103125441Sgrehan stwu %r31,-FRAMELEN(%r1); /* save it in the callframe */ \ 104125441Sgrehan stw %r0, FRAME_0+8(%r1); /* save r0 in the trapframe */ \ 105125441Sgrehan stw %r31,FRAME_1+8(%r1); /* save SP " " */ \ 106125441Sgrehan stw %r2, FRAME_2+8(%r1); /* save r2 " " */ \ 107125441Sgrehan stw %r28,FRAME_LR+8(%r1); /* save LR " " */ \ 108125441Sgrehan stw %r29,FRAME_CR+8(%r1); /* save CR " " */ \ 109125441Sgrehan GET_CPUINFO(%r2); \ 110125441Sgrehan lwz %r28,(savearea+CPUSAVE_R28)(%r2); /* get saved r28 */ \ 111125441Sgrehan lwz %r29,(savearea+CPUSAVE_R29)(%r2); /* get saved r29 */ \ 112125441Sgrehan lwz %r30,(savearea+CPUSAVE_R30)(%r2); /* get saved r30 */ \ 113125441Sgrehan lwz %r31,(savearea+CPUSAVE_R31)(%r2); /* get saved r31 */ \ 114125441Sgrehan stw %r3, FRAME_3+8(%r1); /* save r3-r31 */ \ 115125441Sgrehan stw %r4, FRAME_4+8(%r1); \ 116125441Sgrehan stw %r5, FRAME_5+8(%r1); \ 117125441Sgrehan stw %r6, FRAME_6+8(%r1); \ 118125441Sgrehan stw %r7, FRAME_7+8(%r1); \ 119125441Sgrehan stw %r8, FRAME_8+8(%r1); \ 120125441Sgrehan stw %r9, FRAME_9+8(%r1); \ 121125441Sgrehan stw %r10, FRAME_10+8(%r1); \ 122125441Sgrehan stw %r11, FRAME_11+8(%r1); \ 123125441Sgrehan stw %r12, FRAME_12+8(%r1); \ 124125441Sgrehan stw %r13, FRAME_13+8(%r1); \ 125125441Sgrehan stw %r14, FRAME_14+8(%r1); \ 126125441Sgrehan stw %r15, FRAME_15+8(%r1); \ 127125441Sgrehan stw %r16, FRAME_16+8(%r1); \ 128125441Sgrehan stw %r17, FRAME_17+8(%r1); \ 129125441Sgrehan stw %r18, FRAME_18+8(%r1); \ 130125441Sgrehan stw %r19, FRAME_19+8(%r1); \ 131125441Sgrehan stw %r20, FRAME_20+8(%r1); \ 132125441Sgrehan stw %r21, FRAME_21+8(%r1); \ 133125441Sgrehan stw %r22, FRAME_22+8(%r1); \ 134125441Sgrehan stw %r23, FRAME_23+8(%r1); \ 135125441Sgrehan stw %r24, FRAME_24+8(%r1); \ 136125441Sgrehan stw %r25, FRAME_25+8(%r1); \ 137125441Sgrehan stw %r26, FRAME_26+8(%r1); \ 138125441Sgrehan stw %r27, FRAME_27+8(%r1); \ 139125441Sgrehan stw %r28, FRAME_28+8(%r1); \ 140125441Sgrehan stw %r29, FRAME_29+8(%r1); \ 141125441Sgrehan stw %r30, FRAME_30+8(%r1); \ 142125441Sgrehan stw %r31, FRAME_31+8(%r1); \ 143176742Sraj lwz %r28,(savearea+CPUSAVE_AIM_DAR)(%r2); /* saved DAR */ \ 144176742Sraj lwz %r29,(savearea+CPUSAVE_AIM_DSISR)(%r2);/* saved DSISR */\ 145125441Sgrehan lwz %r30,(savearea+CPUSAVE_SRR0)(%r2); /* saved SRR0 */ \ 146125441Sgrehan lwz %r31,(savearea+CPUSAVE_SRR1)(%r2); /* saved SRR1 */ \ 147125441Sgrehan mfxer %r3; \ 148125441Sgrehan mfctr %r4; \ 149188860Snwhitehorn mfsprg3 %r5; \ 150125441Sgrehan stw %r3, FRAME_XER+8(1); /* save xer/ctr/exc */ \ 151125441Sgrehan stw %r4, FRAME_CTR+8(1); \ 152125441Sgrehan stw %r5, FRAME_EXC+8(1); \ 153176742Sraj stw %r28,FRAME_AIM_DAR+8(1); \ 154176742Sraj stw %r29,FRAME_AIM_DSISR+8(1); /* save dsisr/srr0/srr1 */ \ 155125441Sgrehan stw %r30,FRAME_SRR0+8(1); \ 156125441Sgrehan stw %r31,FRAME_SRR1+8(1) 15795719Sbenno 158125441Sgrehan#define FRAME_LEAVE(savearea) \ 159125441Sgrehan/* Now restore regs: */ \ 160125441Sgrehan lwz %r2,FRAME_SRR0+8(%r1); \ 161125441Sgrehan lwz %r3,FRAME_SRR1+8(%r1); \ 162125441Sgrehan lwz %r4,FRAME_CTR+8(%r1); \ 163125441Sgrehan lwz %r5,FRAME_XER+8(%r1); \ 164125441Sgrehan lwz %r6,FRAME_LR+8(%r1); \ 165125441Sgrehan GET_CPUINFO(%r7); \ 166125441Sgrehan stw %r2,(savearea+CPUSAVE_SRR0)(%r7); /* save SRR0 */ \ 167125441Sgrehan stw %r3,(savearea+CPUSAVE_SRR1)(%r7); /* save SRR1 */ \ 168125441Sgrehan lwz %r7,FRAME_CR+8(%r1); \ 169125441Sgrehan mtctr %r4; \ 170125441Sgrehan mtxer %r5; \ 171125441Sgrehan mtlr %r6; \ 172125441Sgrehan mtsprg1 %r7; /* save cr */ \ 173125441Sgrehan lwz %r31,FRAME_31+8(%r1); /* restore r0-31 */ \ 174125441Sgrehan lwz %r30,FRAME_30+8(%r1); \ 175125441Sgrehan lwz %r29,FRAME_29+8(%r1); \ 176125441Sgrehan lwz %r28,FRAME_28+8(%r1); \ 177125441Sgrehan lwz %r27,FRAME_27+8(%r1); \ 178125441Sgrehan lwz %r26,FRAME_26+8(%r1); \ 179125441Sgrehan lwz %r25,FRAME_25+8(%r1); \ 180125441Sgrehan lwz %r24,FRAME_24+8(%r1); \ 181125441Sgrehan lwz %r23,FRAME_23+8(%r1); \ 182125441Sgrehan lwz %r22,FRAME_22+8(%r1); \ 183125441Sgrehan lwz %r21,FRAME_21+8(%r1); \ 184125441Sgrehan lwz %r20,FRAME_20+8(%r1); \ 185125441Sgrehan lwz %r19,FRAME_19+8(%r1); \ 186125441Sgrehan lwz %r18,FRAME_18+8(%r1); \ 187125441Sgrehan lwz %r17,FRAME_17+8(%r1); \ 188125441Sgrehan lwz %r16,FRAME_16+8(%r1); \ 189125441Sgrehan lwz %r15,FRAME_15+8(%r1); \ 190125441Sgrehan lwz %r14,FRAME_14+8(%r1); \ 191125441Sgrehan lwz %r13,FRAME_13+8(%r1); \ 192125441Sgrehan lwz %r12,FRAME_12+8(%r1); \ 193125441Sgrehan lwz %r11,FRAME_11+8(%r1); \ 194125441Sgrehan lwz %r10,FRAME_10+8(%r1); \ 195125441Sgrehan lwz %r9, FRAME_9+8(%r1); \ 196125441Sgrehan lwz %r8, FRAME_8+8(%r1); \ 197125441Sgrehan lwz %r7, FRAME_7+8(%r1); \ 198125441Sgrehan lwz %r6, FRAME_6+8(%r1); \ 199125441Sgrehan lwz %r5, FRAME_5+8(%r1); \ 200125441Sgrehan lwz %r4, FRAME_4+8(%r1); \ 201125441Sgrehan lwz %r3, FRAME_3+8(%r1); \ 202125441Sgrehan lwz %r2, FRAME_2+8(%r1); \ 203125441Sgrehan lwz %r0, FRAME_0+8(%r1); \ 204125441Sgrehan lwz %r1, FRAME_1+8(%r1); \ 205125441Sgrehan/* Can't touch %r1 from here on */ \ 206125441Sgrehan mtsprg2 %r2; /* save r2 & r3 */ \ 207125441Sgrehan mtsprg3 %r3; \ 208125441Sgrehan/* Disable translation, machine check and recoverability: */ \ 209125441Sgrehan mfmsr %r2; \ 210125441Sgrehan andi. %r2,%r2,~(PSL_DR|PSL_IR|PSL_EE|PSL_ME|PSL_RI)@l; \ 211125441Sgrehan mtmsr %r2; \ 212125441Sgrehan isync; \ 213125441Sgrehan/* Decide whether we return to user mode: */ \ 214125441Sgrehan GET_CPUINFO(%r2); \ 215125441Sgrehan lwz %r3,(savearea+CPUSAVE_SRR1)(%r2); \ 216125441Sgrehan mtcr %r3; \ 217125441Sgrehan bf 17,1f; /* branch if PSL_PR is false */ \ 218125441Sgrehan/* Restore user SRs */ \ 219125441Sgrehan RESTORE_USER_SRS(%r2,%r3); \ 220125441Sgrehan1: mfsprg1 %r2; /* restore cr */ \ 221125441Sgrehan mtcr %r2; \ 222125441Sgrehan GET_CPUINFO(%r2); \ 223125441Sgrehan lwz %r3,(savearea+CPUSAVE_SRR0)(%r2); /* restore srr0 */ \ 224125441Sgrehan mtsrr0 %r3; \ 225125441Sgrehan lwz %r3,(savearea+CPUSAVE_SRR1)(%r2); /* restore srr1 */ \ 226190681Snwhitehorn \ 227190681Snwhitehorn /* Make sure HV bit of MSR propagated to SRR1 */ \ 228190681Snwhitehorn mfmsr %r2; \ 229190681Snwhitehorn or %r3,%r2,%r3; \ 230190681Snwhitehorn \ 231125441Sgrehan mtsrr1 %r3; \ 232125441Sgrehan mfsprg2 %r2; /* restore r2 & r3 */ \ 233125441Sgrehan mfsprg3 %r3 23495719Sbenno 235190681Snwhitehorn/* 236190681Snwhitehorn * The next two routines are 64-bit glue code. The first is used to test if 237190681Snwhitehorn * we are on a 64-bit system. By copying it to the illegal instruction 238190681Snwhitehorn * handler, we can test for 64-bit mode by trying to execute a 64-bit 239190681Snwhitehorn * instruction and seeing what happens. The second gets copied in front 240190681Snwhitehorn * of all the other handlers to restore 32-bit bridge mode when traps 241190681Snwhitehorn * are taken. 242190681Snwhitehorn */ 243190681Snwhitehorn 244190681Snwhitehorn/* 64-bit test code. Sets SPRG2 to 0 if an illegal instruction is executed */ 245190681Snwhitehorn 246190681Snwhitehorn .globl CNAME(testppc64),CNAME(testppc64size) 247190681SnwhitehornCNAME(testppc64): 248190681Snwhitehorn mtsprg1 %r31 249190681Snwhitehorn mfsrr0 %r31 250190681Snwhitehorn addi %r31, %r31, 4 251190681Snwhitehorn mtsrr0 %r31 252190681Snwhitehorn 253190681Snwhitehorn li %r31, 0 254190681Snwhitehorn mtsprg2 %r31 255190681Snwhitehorn mfsprg1 %r31 256190681Snwhitehorn 257190681Snwhitehorn rfi 258190681SnwhitehornCNAME(testppc64size) = .-CNAME(testppc64) 259190681Snwhitehorn 260190681Snwhitehorn 261190681Snwhitehorn/* 64-bit bridge mode restore snippet. Gets copied in front of everything else 262190681Snwhitehorn * on 64-bit systems. */ 263190681Snwhitehorn 264190681Snwhitehorn .globl CNAME(restorebridge),CNAME(restorebridgesize) 265190681SnwhitehornCNAME(restorebridge): 266190681Snwhitehorn mtsprg1 %r31 267190681Snwhitehorn mfmsr %r31 268190681Snwhitehorn clrldi %r31,%r31,1 269190681Snwhitehorn mtmsrd %r31 270190681Snwhitehorn mfsprg1 %r31 271190681Snwhitehorn isync 272190681SnwhitehornCNAME(restorebridgesize) = .-CNAME(restorebridge) 273190681Snwhitehorn 274178628Smarcel#ifdef SMP 27595719Sbenno/* 276178628Smarcel * Processor reset exception handler. These are typically 277178628Smarcel * the first instructions the processor executes after a 278178628Smarcel * software reset. 279132571Sgrehan */ 280178628Smarcel .globl CNAME(rstcode), CNAME(rstsize) 281178628SmarcelCNAME(rstcode): 282178628Smarcel bl 1f 283178628Smarcel 284183060Smarcel .space 124 285178628Smarcel 286178628Smarcel1: 287183060Smarcel mflr %r1 288183060Smarcel addi %r1,%r1,(124-16)@l 289178628Smarcel 290183060Smarcel lis %r3,1@l 291178628Smarcel bla CNAME(pmap_cpu_bootstrap) 292178628Smarcel bla CNAME(cpudep_ap_bootstrap) 293178628Smarcel mr %r1,%r3 294178628Smarcel bla CNAME(machdep_ap_bootstrap) 295178628Smarcel 296178628Smarcel /* Should not be reached */ 297178628Smarcel9: 298178628Smarcel b 9b 299178628SmarcelCNAME(rstsize) = . - CNAME(rstcode) 300132571Sgrehan#endif 301132571Sgrehan 302132571Sgrehan/* 30395719Sbenno * This code gets copied to all the trap vectors 304125441Sgrehan * (except ISI/DSI, ALI, and the interrupts) 30595719Sbenno */ 306178628Smarcel 30796773Sbenno .globl CNAME(trapcode),CNAME(trapsize) 30896773SbennoCNAME(trapcode): 309125441Sgrehan mtsprg1 %r1 /* save SP */ 310188860Snwhitehorn mflr %r1 /* Save the old LR in r1 */ 311188860Snwhitehorn mtsprg2 %r1 /* And then in SPRG2 */ 312188860Snwhitehorn li %r1, 0x20 /* How to get the vector from LR */ 313188860Snwhitehorn bla generictrap /* LR & SPRG3 is exception # */ 31496773SbennoCNAME(trapsize) = .-CNAME(trapcode) 31595719Sbenno 31695719Sbenno/* 317190681Snwhitehorn * 64-bit version of trapcode. Identical, except it calls generictrap64. 318190681Snwhitehorn */ 319190681Snwhitehorn .globl CNAME(trapcode64) 320190681SnwhitehornCNAME(trapcode64): 321190681Snwhitehorn mtsprg1 %r1 /* save SP */ 322190681Snwhitehorn mflr %r1 /* Save the old LR in r1 */ 323190681Snwhitehorn mtsprg2 %r1 /* And then in SPRG2 */ 324190681Snwhitehorn li %r1, 0x20 /* How to get the vector from LR */ 325190681Snwhitehorn bla generictrap64 /* LR & SPRG3 is exception # */ 326190681Snwhitehorn 327190681Snwhitehorn/* 32895719Sbenno * For ALI: has to save DSISR and DAR 32995719Sbenno */ 33096773Sbenno .globl CNAME(alitrap),CNAME(alisize) 33196773SbennoCNAME(alitrap): 332125441Sgrehan mtsprg1 %r1 /* save SP */ 333125441Sgrehan GET_CPUINFO(%r1) 334125441Sgrehan stw %r28,(PC_TEMPSAVE+CPUSAVE_R28)(%r1) /* free r28-r31 */ 335125441Sgrehan stw %r29,(PC_TEMPSAVE+CPUSAVE_R29)(%r1) 336125441Sgrehan stw %r30,(PC_TEMPSAVE+CPUSAVE_R30)(%r1) 337125441Sgrehan stw %r31,(PC_TEMPSAVE+CPUSAVE_R31)(%r1) 338125441Sgrehan mfdar %r30 339125441Sgrehan mfdsisr %r31 340176742Sraj stw %r30,(PC_TEMPSAVE+CPUSAVE_AIM_DAR)(%r1) 341176742Sraj stw %r31,(PC_TEMPSAVE+CPUSAVE_AIM_DSISR)(%r1) 342125441Sgrehan mfsprg1 %r1 /* restore SP, in case of branch */ 343125441Sgrehan mflr %r28 /* save LR */ 344125441Sgrehan mfcr %r29 /* save CR */ 345188860Snwhitehorn 346188951Snwhitehorn /* Put our exception vector in SPRG3 */ 347188860Snwhitehorn li %r31, EXC_ALI 348188860Snwhitehorn mtsprg3 %r31 349188860Snwhitehorn 350188860Snwhitehorn /* Test whether we already had PR set */ 351125441Sgrehan mfsrr1 %r31 352125441Sgrehan mtcr %r31 353188860Snwhitehorn bla s_trap 35496773SbennoCNAME(alisize) = .-CNAME(alitrap) 35595719Sbenno 35695719Sbenno/* 35795719Sbenno * Similar to the above for DSI 35895719Sbenno * Has to handle BAT spills 35995719Sbenno * and standard pagetable spills 36095719Sbenno */ 36196773Sbenno .globl CNAME(dsitrap),CNAME(dsisize) 36296773SbennoCNAME(dsitrap): 363125441Sgrehan mtsprg1 %r1 /* save SP */ 364125441Sgrehan GET_CPUINFO(%r1) 365125441Sgrehan stw %r28,(PC_DISISAVE+CPUSAVE_R28)(%r1) /* free r28-r31 */ 366125441Sgrehan stw %r29,(PC_DISISAVE+CPUSAVE_R29)(%r1) 367125441Sgrehan stw %r30,(PC_DISISAVE+CPUSAVE_R30)(%r1) 368125441Sgrehan stw %r31,(PC_DISISAVE+CPUSAVE_R31)(%r1) 369125441Sgrehan mfsprg1 %r1 /* restore SP */ 370125441Sgrehan mfcr %r29 /* save CR */ 371125441Sgrehan mfxer %r30 /* save XER */ 372125441Sgrehan mtsprg2 %r30 /* in SPRG2 */ 373125441Sgrehan mfsrr1 %r31 /* test kernel mode */ 374125441Sgrehan mtcr %r31 375125441Sgrehan bt 17,1f /* branch if PSL_PR is set */ 376125441Sgrehan mfdar %r31 /* get fault address */ 377125441Sgrehan rlwinm %r31,%r31,7,25,28 /* get segment * 8 */ 37895719Sbenno 37995719Sbenno /* get batu */ 380125441Sgrehan addis %r31,%r31,CNAME(battable)@ha 381125441Sgrehan lwz %r30,CNAME(battable)@l(31) 382125441Sgrehan mtcr %r30 383125441Sgrehan bf 30,1f /* branch if supervisor valid is 38495719Sbenno false */ 38595719Sbenno /* get batl */ 386125441Sgrehan lwz %r31,CNAME(battable)+4@l(31) 38795719Sbenno/* We randomly use the highest two bat registers here */ 388125441Sgrehan mftb %r28 389125441Sgrehan andi. %r28,%r28,1 39095719Sbenno bne 2f 391125441Sgrehan mtdbatu 2,%r30 392125441Sgrehan mtdbatl 2,%r31 39395719Sbenno b 3f 39495719Sbenno2: 395125441Sgrehan mtdbatu 3,%r30 396125441Sgrehan mtdbatl 3,%r31 39795719Sbenno3: 398125441Sgrehan mfsprg2 %r30 /* restore XER */ 399125441Sgrehan mtxer %r30 400125441Sgrehan mtcr %r29 /* restore CR */ 401125441Sgrehan mtsprg1 %r1 402125441Sgrehan GET_CPUINFO(%r1) 403125441Sgrehan lwz %r28,(PC_DISISAVE+CPUSAVE_R28)(%r1) /* restore r28-r31 */ 404125441Sgrehan lwz %r29,(PC_DISISAVE+CPUSAVE_R29)(%r1) 405125441Sgrehan lwz %r30,(PC_DISISAVE+CPUSAVE_R30)(%r1) 406125441Sgrehan lwz %r31,(PC_DISISAVE+CPUSAVE_R31)(%r1) 407125441Sgrehan mfsprg1 %r1 40895719Sbenno rfi /* return to trapped code */ 40995719Sbenno1: 410125441Sgrehan mflr %r28 /* save LR (SP already saved) */ 411125441Sgrehan bla disitrap 41296773SbennoCNAME(dsisize) = .-CNAME(dsitrap) 41395719Sbenno 41495719Sbenno/* 41595719Sbenno * Preamble code for DSI/ISI traps 41695719Sbenno */ 41795719Sbennodisitrap: 418188951Snwhitehorn /* Write the trap vector to SPRG3 by computing LR & 0xff00 */ 419188860Snwhitehorn mflr %r1 420188860Snwhitehorn andi. %r1,%r1,0xff00 421188860Snwhitehorn mtsprg3 %r1 422188860Snwhitehorn 423125441Sgrehan GET_CPUINFO(%r1) 424125441Sgrehan lwz %r30,(PC_DISISAVE+CPUSAVE_R28)(%r1) 425125441Sgrehan stw %r30,(PC_TEMPSAVE+CPUSAVE_R28)(%r1) 426125441Sgrehan lwz %r31,(PC_DISISAVE+CPUSAVE_R29)(%r1) 427125441Sgrehan stw %r31,(PC_TEMPSAVE+CPUSAVE_R29)(%r1) 428125441Sgrehan lwz %r30,(PC_DISISAVE+CPUSAVE_R30)(%r1) 429125441Sgrehan stw %r30,(PC_TEMPSAVE+CPUSAVE_R30)(%r1) 430125441Sgrehan lwz %r31,(PC_DISISAVE+CPUSAVE_R31)(%r1) 431125441Sgrehan stw %r31,(PC_TEMPSAVE+CPUSAVE_R31)(%r1) 432125441Sgrehan mfdar %r30 433125441Sgrehan mfdsisr %r31 434176742Sraj stw %r30,(PC_TEMPSAVE+CPUSAVE_AIM_DAR)(%r1) 435176742Sraj stw %r31,(PC_TEMPSAVE+CPUSAVE_AIM_DSISR)(%r1) 436125441Sgrehan 437132571Sgrehan#ifdef KDB 438132571Sgrehan /* Try and detect a kernel stack overflow */ 439132571Sgrehan mfsrr1 %r31 440132571Sgrehan mtcr %r31 441132571Sgrehan bt 17,realtrap /* branch is user mode */ 442132571Sgrehan mfsprg1 %r31 /* get old SP */ 443132571Sgrehan sub. %r30,%r31,%r30 /* SP - DAR */ 444132571Sgrehan bge 1f 445132571Sgrehan neg %r30,%r30 /* modulo value */ 446132571Sgrehan1: cmplwi %cr0,%r30,4096 /* is DAR within a page of SP? */ 447132571Sgrehan bge %cr0,realtrap /* no, too far away. */ 448132571Sgrehan 449132571Sgrehan /* Now convert this DSI into a DDB trap. */ 450132571Sgrehan GET_CPUINFO(%r1) 451176742Sraj lwz %r30,(PC_TEMPSAVE+CPUSAVE_AIM_DAR)(%r1) /* get DAR */ 452176742Sraj stw %r30,(PC_DBSAVE +CPUSAVE_AIM_DAR)(%r1) /* save DAR */ 453176742Sraj lwz %r30,(PC_TEMPSAVE+CPUSAVE_AIM_DSISR)(%r1) /* get DSISR */ 454176742Sraj lwz %r30,(PC_DBSAVE +CPUSAVE_AIM_DSISR)(%r1) /* save DSISR */ 455132571Sgrehan lwz %r30,(PC_DISISAVE+CPUSAVE_R28)(%r1) /* get r28 */ 456132571Sgrehan stw %r30,(PC_DBSAVE +CPUSAVE_R28)(%r1) /* save r28 */ 457132571Sgrehan lwz %r31,(PC_DISISAVE+CPUSAVE_R29)(%r1) /* get r29 */ 458132571Sgrehan stw %r31,(PC_DBSAVE +CPUSAVE_R29)(%r1) /* save r29 */ 459132571Sgrehan lwz %r30,(PC_DISISAVE+CPUSAVE_R30)(%r1) /* get r30 */ 460132571Sgrehan stw %r30,(PC_DBSAVE +CPUSAVE_R30)(%r1) /* save r30 */ 461132571Sgrehan lwz %r31,(PC_DISISAVE+CPUSAVE_R31)(%r1) /* get r31 */ 462132571Sgrehan stw %r31,(PC_DBSAVE +CPUSAVE_R31)(%r1) /* save r31 */ 463191039Snwhitehorn b dbtrap 464132571Sgrehan#endif 465132571Sgrehan 466125441Sgrehan /* XXX need stack probe here */ 46795719Sbennorealtrap: 46895719Sbenno/* Test whether we already had PR set */ 469125441Sgrehan mfsrr1 %r1 470125441Sgrehan mtcr %r1 471125441Sgrehan mfsprg1 %r1 /* restore SP (might have been 47295719Sbenno overwritten) */ 473188860Snwhitehorn bf 17,k_trap /* branch if PSL_PR is false */ 474188860Snwhitehorn GET_CPUINFO(%r1) 475188860Snwhitehorn lwz %r1,PC_CURPCB(%r1) 476188860Snwhitehorn RESTORE_KERN_SRS(%r30,%r31) /* enable kernel mapping */ 477188860Snwhitehorn ba s_trap 478188860Snwhitehorn 479188860Snwhitehorn/* 480188860Snwhitehorn * generictrap does some standard setup for trap handling to minimize 481188860Snwhitehorn * the code that need be installed in the actual vectors. It expects 482188860Snwhitehorn * the following conditions. 483188860Snwhitehorn * 484188860Snwhitehorn * R1 - Trap vector = LR & (0xff00 | R1) 485188860Snwhitehorn * SPRG1 - Original R1 contents 486188860Snwhitehorn * SPRG2 - Original LR 487188860Snwhitehorn */ 488188860Snwhitehorn 489190681Snwhitehorngenerictrap64: 490190681Snwhitehorn mtsprg3 %r31 491190681Snwhitehorn mfmsr %r31 492190681Snwhitehorn clrldi %r31,%r31,1 493190681Snwhitehorn mtmsrd %r31 494190681Snwhitehorn mfsprg3 %r31 495190681Snwhitehorn isync 496190681Snwhitehorn 497188860Snwhitehorngenerictrap: 498188860Snwhitehorn /* Save R1 for computing the exception vector */ 499188860Snwhitehorn mtsprg3 %r1 500188860Snwhitehorn 501188860Snwhitehorn /* Save interesting registers */ 502188860Snwhitehorn GET_CPUINFO(%r1) 503188860Snwhitehorn stw %r28,(PC_TEMPSAVE+CPUSAVE_R28)(%r1) /* free r28-r31 */ 504188860Snwhitehorn stw %r29,(PC_TEMPSAVE+CPUSAVE_R29)(%r1) 505188860Snwhitehorn stw %r30,(PC_TEMPSAVE+CPUSAVE_R30)(%r1) 506188860Snwhitehorn stw %r31,(PC_TEMPSAVE+CPUSAVE_R31)(%r1) 507188860Snwhitehorn mfsprg1 %r1 /* restore SP, in case of branch */ 508188860Snwhitehorn mfsprg2 %r28 /* save LR */ 509188860Snwhitehorn mfcr %r29 /* save CR */ 510188860Snwhitehorn 511188860Snwhitehorn /* Compute the exception vector from the link register */ 512188860Snwhitehorn mfsprg3 %r31 513188860Snwhitehorn ori %r31,%r31,0xff00 514188860Snwhitehorn mflr %r30 515188860Snwhitehorn and %r30,%r30,%r31 516188860Snwhitehorn mtsprg3 %r30 517188860Snwhitehorn 518188860Snwhitehorn /* Test whether we already had PR set */ 519188860Snwhitehorn mfsrr1 %r31 520188860Snwhitehorn mtcr %r31 521188860Snwhitehorn 522125441Sgrehans_trap: 523125441Sgrehan bf 17,k_trap /* branch if PSL_PR is false */ 524125441Sgrehan GET_CPUINFO(%r1) 525125441Sgrehanu_trap: 526125441Sgrehan lwz %r1,PC_CURPCB(%r1) 527125441Sgrehan RESTORE_KERN_SRS(%r30,%r31) /* enable kernel mapping */ 52895719Sbenno 52995719Sbenno/* 53095719Sbenno * Now the common trap catching code. 53195719Sbenno */ 532125441Sgrehank_trap: 533125441Sgrehan FRAME_SETUP(PC_TEMPSAVE) 53499032Sbenno/* Call C interrupt dispatcher: */ 53595719Sbennotrapagain: 536125441Sgrehan addi %r3,%r1,8 53799032Sbenno bl CNAME(powerpc_interrupt) 538132075Sgrehan .globl CNAME(trapexit) /* backtrace code sentinel */ 53996773SbennoCNAME(trapexit): 54099032Sbenno 54195719Sbenno/* Disable interrupts: */ 542125441Sgrehan mfmsr %r3 543125441Sgrehan andi. %r3,%r3,~PSL_EE@l 544125441Sgrehan mtmsr %r3 54595719Sbenno/* Test AST pending: */ 546125441Sgrehan lwz %r5,FRAME_SRR1+8(%r1) 547125441Sgrehan mtcr %r5 548125441Sgrehan bf 17,1f /* branch if PSL_PR is false */ 54999032Sbenno 550125441Sgrehan GET_CPUINFO(%r3) /* get per-CPU pointer */ 551125441Sgrehan lwz %r4, PC_CURTHREAD(%r3) /* deref to get curthread */ 552125441Sgrehan lwz %r4, TD_FLAGS(%r4) /* get thread flags value */ 553125441Sgrehan lis %r5, (TDF_ASTPENDING|TDF_NEEDRESCHED)@h 554125441Sgrehan ori %r5,%r5, (TDF_ASTPENDING|TDF_NEEDRESCHED)@l 555125441Sgrehan and. %r4,%r4,%r5 55695719Sbenno beq 1f 557125441Sgrehan mfmsr %r3 /* re-enable interrupts */ 558125441Sgrehan ori %r3,%r3,PSL_EE@l 559125441Sgrehan mtmsr %r3 56099032Sbenno isync 561125441Sgrehan addi %r3,%r1,8 562103608Sgrehan bl CNAME(ast) 563153685Sgrehan .globl CNAME(asttrapexit) /* backtrace code sentinel #2 */ 564153685SgrehanCNAME(asttrapexit): 56599032Sbenno b trapexit /* test ast ret value ? */ 56695719Sbenno1: 567125441Sgrehan FRAME_LEAVE(PC_TEMPSAVE) 568190681Snwhitehorn 569190681Snwhitehorn .globl CNAME(rfi_patch1) /* replace rfi with rfid on ppc64 */ 570190681SnwhitehornCNAME(rfi_patch1): 57195719Sbenno rfi 57295719Sbenno 573190681Snwhitehorn .globl CNAME(rfid_patch) 574190681SnwhitehornCNAME(rfid_patch): 575190681Snwhitehorn rfid 576190681Snwhitehorn 577132075Sgrehan#if defined(KDB) 57895719Sbenno/* 579132075Sgrehan * Deliberate entry to dbtrap 58095719Sbenno */ 581178628Smarcel .globl CNAME(breakpoint) 582178628SmarcelCNAME(breakpoint): 583125441Sgrehan mtsprg1 %r1 584125441Sgrehan mfmsr %r3 585125441Sgrehan mtsrr1 %r3 586125441Sgrehan andi. %r3,%r3,~(PSL_EE|PSL_ME)@l 587125441Sgrehan mtmsr %r3 /* disable interrupts */ 58895719Sbenno isync 589125441Sgrehan GET_CPUINFO(%r3) 590132075Sgrehan stw %r28,(PC_DBSAVE+CPUSAVE_R28)(%r3) 591132075Sgrehan stw %r29,(PC_DBSAVE+CPUSAVE_R29)(%r3) 592132075Sgrehan stw %r30,(PC_DBSAVE+CPUSAVE_R30)(%r3) 593132075Sgrehan stw %r31,(PC_DBSAVE+CPUSAVE_R31)(%r3) 594125441Sgrehan mflr %r28 595125441Sgrehan li %r29,EXC_BPT 596125441Sgrehan mtlr %r29 597125441Sgrehan mfcr %r29 598125441Sgrehan mtsrr0 %r28 59995719Sbenno 60095719Sbenno/* 601132075Sgrehan * Now the kdb trap catching code. 60295719Sbenno */ 603132075Sgrehandbtrap: 604188951Snwhitehorn /* Write the trap vector to SPRG3 by computing LR & 0xff00 */ 605188860Snwhitehorn mflr %r1 606188860Snwhitehorn andi. %r1,%r1,0xff00 607188860Snwhitehorn mtsprg3 %r1 608188860Snwhitehorn 609188860Snwhitehorn lis %r1,(tmpstk+TMPSTKSZ-16)@ha /* get new SP */ 610188860Snwhitehorn addi %r1,%r1,(tmpstk+TMPSTKSZ-16)@l 611188860Snwhitehorn 612132075Sgrehan FRAME_SETUP(PC_DBSAVE) 61395719Sbenno/* Call C trap code: */ 614125441Sgrehan addi %r3,%r1,8 615132075Sgrehan bl CNAME(db_trap_glue) 616125441Sgrehan or. %r3,%r3,%r3 617132075Sgrehan bne dbleave 618132075Sgrehan/* This wasn't for KDB, so switch to real trap: */ 619125441Sgrehan lwz %r3,FRAME_EXC+8(%r1) /* save exception */ 620125441Sgrehan GET_CPUINFO(%r4) 621132075Sgrehan stw %r3,(PC_DBSAVE+CPUSAVE_R31)(%r4) 622132075Sgrehan FRAME_LEAVE(PC_DBSAVE) 623125441Sgrehan mtsprg1 %r1 /* prepare for entrance to realtrap */ 624125441Sgrehan GET_CPUINFO(%r1) 625125441Sgrehan stw %r28,(PC_TEMPSAVE+CPUSAVE_R28)(%r1) 626125441Sgrehan stw %r29,(PC_TEMPSAVE+CPUSAVE_R29)(%r1) 627125441Sgrehan stw %r30,(PC_TEMPSAVE+CPUSAVE_R30)(%r1) 628125441Sgrehan stw %r31,(PC_TEMPSAVE+CPUSAVE_R31)(%r1) 629125441Sgrehan mflr %r28 630125441Sgrehan mfcr %r29 631132075Sgrehan lwz %r31,(PC_DBSAVE+CPUSAVE_R31)(%r1) 632190946Snwhitehorn mtsprg3 %r31 /* SPRG3 was clobbered by FRAME_LEAVE */ 633125441Sgrehan mfsprg1 %r1 63495719Sbenno b realtrap 635132075Sgrehandbleave: 636132075Sgrehan FRAME_LEAVE(PC_DBSAVE) 637190681Snwhitehorn .globl CNAME(rfi_patch2) /* replace rfi with rfid on ppc64 */ 638190681SnwhitehornCNAME(rfi_patch2): 63995719Sbenno rfi 64095719Sbenno 64195719Sbenno/* 642132075Sgrehan * In case of KDB we want a separate trap catcher for it 64395719Sbenno */ 644132075Sgrehan .globl CNAME(dblow),CNAME(dbsize) 645132075SgrehanCNAME(dblow): 646125441Sgrehan mtsprg1 %r1 /* save SP */ 647125441Sgrehan mtsprg2 %r29 /* save r29 */ 648125441Sgrehan mfcr %r29 /* save CR in r29 */ 649125441Sgrehan mfsrr1 %r1 650125441Sgrehan mtcr %r1 651125441Sgrehan bf 17,1f /* branch if privileged */ 652188860Snwhitehorn 653188860Snwhitehorn /* Unprivileged case */ 654188860Snwhitehorn mtcr %r29 /* put the condition register back */ 655188860Snwhitehorn mfsprg2 %r29 /* ... and r29 */ 656188860Snwhitehorn mflr %r1 /* save LR */ 657188860Snwhitehorn mtsprg2 %r1 /* And then in SPRG2 */ 658188860Snwhitehorn li %r1, 0 /* How to get the vector from LR */ 659188860Snwhitehorn 660188860Snwhitehorn bla generictrap /* and we look like a generic trap */ 661125441Sgrehan1: 662188860Snwhitehorn /* Privileged, so drop to KDB */ 663188860Snwhitehorn GET_CPUINFO(%r1) 664132075Sgrehan stw %r28,(PC_DBSAVE+CPUSAVE_R28)(%r1) /* free r28 */ 665125441Sgrehan mfsprg2 %r28 /* r29 holds cr... */ 666132075Sgrehan stw %r28,(PC_DBSAVE+CPUSAVE_R29)(%r1) /* free r29 */ 667132075Sgrehan stw %r30,(PC_DBSAVE+CPUSAVE_R30)(%r1) /* free r30 */ 668132075Sgrehan stw %r31,(PC_DBSAVE+CPUSAVE_R31)(%r1) /* free r31 */ 669125441Sgrehan mflr %r28 /* save LR */ 670132075Sgrehan bla dbtrap 671132075SgrehanCNAME(dbsize) = .-CNAME(dblow) 672132075Sgrehan#endif /* KDB */ 673