mmu_oea64.c revision 215159
1190681Snwhitehorn/*- 2190681Snwhitehorn * Copyright (c) 2001 The NetBSD Foundation, Inc. 3190681Snwhitehorn * All rights reserved. 4190681Snwhitehorn * 5190681Snwhitehorn * This code is derived from software contributed to The NetBSD Foundation 6190681Snwhitehorn * by Matt Thomas <matt@3am-software.com> of Allegro Networks, Inc. 7190681Snwhitehorn * 8190681Snwhitehorn * Redistribution and use in source and binary forms, with or without 9190681Snwhitehorn * modification, are permitted provided that the following conditions 10190681Snwhitehorn * are met: 11190681Snwhitehorn * 1. Redistributions of source code must retain the above copyright 12190681Snwhitehorn * notice, this list of conditions and the following disclaimer. 13190681Snwhitehorn * 2. Redistributions in binary form must reproduce the above copyright 14190681Snwhitehorn * notice, this list of conditions and the following disclaimer in the 15190681Snwhitehorn * documentation and/or other materials provided with the distribution. 16190681Snwhitehorn * 3. All advertising materials mentioning features or use of this software 17190681Snwhitehorn * must display the following acknowledgement: 18190681Snwhitehorn * This product includes software developed by the NetBSD 19190681Snwhitehorn * Foundation, Inc. and its contributors. 20190681Snwhitehorn * 4. Neither the name of The NetBSD Foundation nor the names of its 21190681Snwhitehorn * contributors may be used to endorse or promote products derived 22190681Snwhitehorn * from this software without specific prior written permission. 23190681Snwhitehorn * 24190681Snwhitehorn * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 25190681Snwhitehorn * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 26190681Snwhitehorn * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27190681Snwhitehorn * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 28190681Snwhitehorn * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29190681Snwhitehorn * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30190681Snwhitehorn * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31190681Snwhitehorn * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32190681Snwhitehorn * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33190681Snwhitehorn * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34190681Snwhitehorn * POSSIBILITY OF SUCH DAMAGE. 35190681Snwhitehorn */ 36190681Snwhitehorn/*- 37190681Snwhitehorn * Copyright (C) 1995, 1996 Wolfgang Solfrank. 38190681Snwhitehorn * Copyright (C) 1995, 1996 TooLs GmbH. 39190681Snwhitehorn * All rights reserved. 40190681Snwhitehorn * 41190681Snwhitehorn * Redistribution and use in source and binary forms, with or without 42190681Snwhitehorn * modification, are permitted provided that the following conditions 43190681Snwhitehorn * are met: 44190681Snwhitehorn * 1. Redistributions of source code must retain the above copyright 45190681Snwhitehorn * notice, this list of conditions and the following disclaimer. 46190681Snwhitehorn * 2. Redistributions in binary form must reproduce the above copyright 47190681Snwhitehorn * notice, this list of conditions and the following disclaimer in the 48190681Snwhitehorn * documentation and/or other materials provided with the distribution. 49190681Snwhitehorn * 3. All advertising materials mentioning features or use of this software 50190681Snwhitehorn * must display the following acknowledgement: 51190681Snwhitehorn * This product includes software developed by TooLs GmbH. 52190681Snwhitehorn * 4. The name of TooLs GmbH may not be used to endorse or promote products 53190681Snwhitehorn * derived from this software without specific prior written permission. 54190681Snwhitehorn * 55190681Snwhitehorn * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 56190681Snwhitehorn * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 57190681Snwhitehorn * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 58190681Snwhitehorn * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 59190681Snwhitehorn * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 60190681Snwhitehorn * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 61190681Snwhitehorn * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 62190681Snwhitehorn * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 63190681Snwhitehorn * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 64190681Snwhitehorn * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 65190681Snwhitehorn * 66190681Snwhitehorn * $NetBSD: pmap.c,v 1.28 2000/03/26 20:42:36 kleink Exp $ 67190681Snwhitehorn */ 68190681Snwhitehorn/*- 69190681Snwhitehorn * Copyright (C) 2001 Benno Rice. 70190681Snwhitehorn * All rights reserved. 71190681Snwhitehorn * 72190681Snwhitehorn * Redistribution and use in source and binary forms, with or without 73190681Snwhitehorn * modification, are permitted provided that the following conditions 74190681Snwhitehorn * are met: 75190681Snwhitehorn * 1. Redistributions of source code must retain the above copyright 76190681Snwhitehorn * notice, this list of conditions and the following disclaimer. 77190681Snwhitehorn * 2. Redistributions in binary form must reproduce the above copyright 78190681Snwhitehorn * notice, this list of conditions and the following disclaimer in the 79190681Snwhitehorn * documentation and/or other materials provided with the distribution. 80190681Snwhitehorn * 81190681Snwhitehorn * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR 82190681Snwhitehorn * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 83190681Snwhitehorn * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 84190681Snwhitehorn * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 85190681Snwhitehorn * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 86190681Snwhitehorn * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 87190681Snwhitehorn * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 88190681Snwhitehorn * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 89190681Snwhitehorn * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 90190681Snwhitehorn * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 91190681Snwhitehorn */ 92190681Snwhitehorn 93190681Snwhitehorn#include <sys/cdefs.h> 94190681Snwhitehorn__FBSDID("$FreeBSD: head/sys/powerpc/aim/mmu_oea64.c 215159 2010-11-12 04:18:19Z nwhitehorn $"); 95190681Snwhitehorn 96190681Snwhitehorn/* 97190681Snwhitehorn * Manages physical address maps. 98190681Snwhitehorn * 99190681Snwhitehorn * In addition to hardware address maps, this module is called upon to 100190681Snwhitehorn * provide software-use-only maps which may or may not be stored in the 101190681Snwhitehorn * same form as hardware maps. These pseudo-maps are used to store 102190681Snwhitehorn * intermediate results from copy operations to and from address spaces. 103190681Snwhitehorn * 104190681Snwhitehorn * Since the information managed by this module is also stored by the 105190681Snwhitehorn * logical address mapping module, this module may throw away valid virtual 106190681Snwhitehorn * to physical mappings at almost any time. However, invalidations of 107190681Snwhitehorn * mappings must be done as requested. 108190681Snwhitehorn * 109190681Snwhitehorn * In order to cope with hardware architectures which make virtual to 110190681Snwhitehorn * physical map invalidates expensive, this module may delay invalidate 111190681Snwhitehorn * reduced protection operations until such time as they are actually 112190681Snwhitehorn * necessary. This module is given full information as to which processors 113190681Snwhitehorn * are currently using which maps, and to when physical maps must be made 114190681Snwhitehorn * correct. 115190681Snwhitehorn */ 116190681Snwhitehorn 117190681Snwhitehorn#include "opt_kstack_pages.h" 118190681Snwhitehorn 119190681Snwhitehorn#include <sys/param.h> 120190681Snwhitehorn#include <sys/kernel.h> 121190681Snwhitehorn#include <sys/ktr.h> 122190681Snwhitehorn#include <sys/lock.h> 123190681Snwhitehorn#include <sys/msgbuf.h> 124190681Snwhitehorn#include <sys/mutex.h> 125190681Snwhitehorn#include <sys/proc.h> 126190681Snwhitehorn#include <sys/sysctl.h> 127190681Snwhitehorn#include <sys/systm.h> 128190681Snwhitehorn#include <sys/vmmeter.h> 129190681Snwhitehorn 130190681Snwhitehorn#include <sys/kdb.h> 131190681Snwhitehorn 132190681Snwhitehorn#include <dev/ofw/openfirm.h> 133190681Snwhitehorn 134190681Snwhitehorn#include <vm/vm.h> 135190681Snwhitehorn#include <vm/vm_param.h> 136190681Snwhitehorn#include <vm/vm_kern.h> 137190681Snwhitehorn#include <vm/vm_page.h> 138190681Snwhitehorn#include <vm/vm_map.h> 139190681Snwhitehorn#include <vm/vm_object.h> 140190681Snwhitehorn#include <vm/vm_extern.h> 141190681Snwhitehorn#include <vm/vm_pageout.h> 142190681Snwhitehorn#include <vm/vm_pager.h> 143190681Snwhitehorn#include <vm/uma.h> 144190681Snwhitehorn 145209975Snwhitehorn#include <machine/_inttypes.h> 146190681Snwhitehorn#include <machine/cpu.h> 147192067Snwhitehorn#include <machine/platform.h> 148190681Snwhitehorn#include <machine/frame.h> 149190681Snwhitehorn#include <machine/md_var.h> 150190681Snwhitehorn#include <machine/psl.h> 151190681Snwhitehorn#include <machine/bat.h> 152209975Snwhitehorn#include <machine/hid.h> 153190681Snwhitehorn#include <machine/pte.h> 154190681Snwhitehorn#include <machine/sr.h> 155190681Snwhitehorn#include <machine/trap.h> 156190681Snwhitehorn#include <machine/mmuvar.h> 157190681Snwhitehorn 158190681Snwhitehorn#include "mmu_if.h" 159190681Snwhitehorn 160190681Snwhitehorn#define MOEA_DEBUG 161190681Snwhitehorn 162190681Snwhitehorn#define TODO panic("%s: not implemented", __func__); 163209975Snwhitehornvoid moea64_release_vsid(uint64_t vsid); 164209975Snwhitehornuintptr_t moea64_get_unique_vsid(void); 165190681Snwhitehorn 166209975Snwhitehornstatic __inline register_t 167209975Snwhitehorncntlzd(volatile register_t a) { 168209975Snwhitehorn register_t b; 169209975Snwhitehorn __asm ("cntlzd %0, %1" : "=r"(b) : "r"(a)); 170190681Snwhitehorn return b; 171190681Snwhitehorn} 172190681Snwhitehorn 173204042Snwhitehorn#define PTESYNC() __asm __volatile("ptesync"); 174190681Snwhitehorn#define TLBSYNC() __asm __volatile("tlbsync; ptesync"); 175190681Snwhitehorn#define SYNC() __asm __volatile("sync"); 176190681Snwhitehorn#define EIEIO() __asm __volatile("eieio"); 177190681Snwhitehorn 178190681Snwhitehorn/* 179190681Snwhitehorn * The tlbie instruction must be executed in 64-bit mode 180190681Snwhitehorn * so we have to twiddle MSR[SF] around every invocation. 181190681Snwhitehorn * Just to add to the fun, exceptions must be off as well 182190681Snwhitehorn * so that we can't trap in 64-bit mode. What a pain. 183190681Snwhitehorn */ 184198378Snwhitehornstruct mtx tlbie_mutex; 185190681Snwhitehorn 186190681Snwhitehornstatic __inline void 187209975SnwhitehornTLBIE(uint64_t vpn) { 188209975Snwhitehorn#ifndef __powerpc64__ 189198378Snwhitehorn register_t vpn_hi, vpn_lo; 190190681Snwhitehorn register_t msr; 191190681Snwhitehorn register_t scratch; 192209975Snwhitehorn#endif 193190681Snwhitehorn 194209975Snwhitehorn vpn <<= ADDR_PIDX_SHFT; 195204042Snwhitehorn vpn &= ~(0xffffULL << 48); 196190681Snwhitehorn 197209975Snwhitehorn mtx_lock_spin(&tlbie_mutex); 198209975Snwhitehorn#ifdef __powerpc64__ 199209975Snwhitehorn __asm __volatile("\ 200209975Snwhitehorn ptesync; \ 201209975Snwhitehorn tlbie %0; \ 202209975Snwhitehorn eieio; \ 203209975Snwhitehorn tlbsync; \ 204209975Snwhitehorn ptesync;" 205209975Snwhitehorn :: "r"(vpn) : "memory"); 206209975Snwhitehorn#else 207190681Snwhitehorn vpn_hi = (uint32_t)(vpn >> 32); 208190681Snwhitehorn vpn_lo = (uint32_t)vpn; 209190681Snwhitehorn 210190681Snwhitehorn __asm __volatile("\ 211190681Snwhitehorn mfmsr %0; \ 212204042Snwhitehorn mr %1, %0; \ 213198378Snwhitehorn insrdi %1,%5,1,0; \ 214213407Snwhitehorn mtmsrd %1; isync; \ 215190681Snwhitehorn ptesync; \ 216190681Snwhitehorn \ 217190681Snwhitehorn sld %1,%2,%4; \ 218190681Snwhitehorn or %1,%1,%3; \ 219190681Snwhitehorn tlbie %1; \ 220190681Snwhitehorn \ 221213407Snwhitehorn mtmsrd %0; isync; \ 222190681Snwhitehorn eieio; \ 223190681Snwhitehorn tlbsync; \ 224190681Snwhitehorn ptesync;" 225204042Snwhitehorn : "=r"(msr), "=r"(scratch) : "r"(vpn_hi), "r"(vpn_lo), "r"(32), "r"(1) 226204042Snwhitehorn : "memory"); 227209975Snwhitehorn#endif 228198378Snwhitehorn mtx_unlock_spin(&tlbie_mutex); 229190681Snwhitehorn} 230190681Snwhitehorn 231190681Snwhitehorn#define DISABLE_TRANS(msr) msr = mfmsr(); mtmsr(msr & ~PSL_DR); isync() 232190681Snwhitehorn#define ENABLE_TRANS(msr) mtmsr(msr); isync() 233190681Snwhitehorn 234190681Snwhitehorn#define VSID_MAKE(sr, hash) ((sr) | (((hash) & 0xfffff) << 4)) 235190681Snwhitehorn#define VSID_TO_HASH(vsid) (((vsid) >> 4) & 0xfffff) 236204268Snwhitehorn#define VSID_HASH_MASK 0x0000007fffffffffULL 237190681Snwhitehorn 238204042Snwhitehorn#define PVO_PTEGIDX_MASK 0x007UL /* which PTEG slot */ 239204042Snwhitehorn#define PVO_PTEGIDX_VALID 0x008UL /* slot is valid */ 240204042Snwhitehorn#define PVO_WIRED 0x010UL /* PVO entry is wired */ 241204042Snwhitehorn#define PVO_MANAGED 0x020UL /* PVO entry is managed */ 242204042Snwhitehorn#define PVO_BOOTSTRAP 0x080UL /* PVO entry allocated during 243190681Snwhitehorn bootstrap */ 244204042Snwhitehorn#define PVO_FAKE 0x100UL /* fictitious phys page */ 245209975Snwhitehorn#define PVO_LARGE 0x200UL /* large page */ 246190681Snwhitehorn#define PVO_VADDR(pvo) ((pvo)->pvo_vaddr & ~ADDR_POFF) 247190681Snwhitehorn#define PVO_ISFAKE(pvo) ((pvo)->pvo_vaddr & PVO_FAKE) 248190681Snwhitehorn#define PVO_PTEGIDX_GET(pvo) ((pvo)->pvo_vaddr & PVO_PTEGIDX_MASK) 249190681Snwhitehorn#define PVO_PTEGIDX_ISSET(pvo) ((pvo)->pvo_vaddr & PVO_PTEGIDX_VALID) 250190681Snwhitehorn#define PVO_PTEGIDX_CLR(pvo) \ 251190681Snwhitehorn ((void)((pvo)->pvo_vaddr &= ~(PVO_PTEGIDX_VALID|PVO_PTEGIDX_MASK))) 252190681Snwhitehorn#define PVO_PTEGIDX_SET(pvo, i) \ 253190681Snwhitehorn ((void)((pvo)->pvo_vaddr |= (i)|PVO_PTEGIDX_VALID)) 254209975Snwhitehorn#define PVO_VSID(pvo) ((pvo)->pvo_vpn >> 16) 255190681Snwhitehorn 256190681Snwhitehorn#define MOEA_PVO_CHECK(pvo) 257190681Snwhitehorn 258190681Snwhitehorn#define LOCK_TABLE() mtx_lock(&moea64_table_mutex) 259190681Snwhitehorn#define UNLOCK_TABLE() mtx_unlock(&moea64_table_mutex); 260190681Snwhitehorn#define ASSERT_TABLE_LOCK() mtx_assert(&moea64_table_mutex, MA_OWNED) 261190681Snwhitehorn 262190681Snwhitehornstruct ofw_map { 263209975Snwhitehorn cell_t om_va; 264209975Snwhitehorn cell_t om_len; 265209975Snwhitehorn cell_t om_pa_hi; 266209975Snwhitehorn cell_t om_pa_lo; 267209975Snwhitehorn cell_t om_mode; 268190681Snwhitehorn}; 269190681Snwhitehorn 270190681Snwhitehorn/* 271190681Snwhitehorn * Map of physical memory regions. 272190681Snwhitehorn */ 273190681Snwhitehornstatic struct mem_region *regions; 274190681Snwhitehornstatic struct mem_region *pregions; 275209975Snwhitehornstatic u_int phys_avail_count; 276209975Snwhitehornstatic int regions_sz, pregions_sz; 277190681Snwhitehorn 278190681Snwhitehornextern struct pmap ofw_pmap; 279190681Snwhitehorn 280190681Snwhitehornextern void bs_remap_earlyboot(void); 281190681Snwhitehorn 282190681Snwhitehorn 283190681Snwhitehorn/* 284190681Snwhitehorn * Lock for the pteg and pvo tables. 285190681Snwhitehorn */ 286190681Snwhitehornstruct mtx moea64_table_mutex; 287211967Snwhitehornstruct mtx moea64_slb_mutex; 288190681Snwhitehorn 289190681Snwhitehorn/* 290190681Snwhitehorn * PTEG data. 291190681Snwhitehorn */ 292190681Snwhitehornstatic struct lpteg *moea64_pteg_table; 293190681Snwhitehornu_int moea64_pteg_count; 294190681Snwhitehornu_int moea64_pteg_mask; 295190681Snwhitehorn 296190681Snwhitehorn/* 297190681Snwhitehorn * PVO data. 298190681Snwhitehorn */ 299190681Snwhitehornstruct pvo_head *moea64_pvo_table; /* pvo entries by pteg index */ 300213335Snwhitehornstruct pvo_head moea64_pvo_kunmanaged = /* list of unmanaged pages */ 301190681Snwhitehorn LIST_HEAD_INITIALIZER(moea64_pvo_kunmanaged); 302190681Snwhitehorn 303190681Snwhitehornuma_zone_t moea64_upvo_zone; /* zone for pvo entries for unmanaged pages */ 304190681Snwhitehornuma_zone_t moea64_mpvo_zone; /* zone for pvo entries for managed pages */ 305190681Snwhitehorn 306190681Snwhitehorn#define BPVO_POOL_SIZE 327680 307190681Snwhitehornstatic struct pvo_entry *moea64_bpvo_pool; 308190681Snwhitehornstatic int moea64_bpvo_pool_index = 0; 309190681Snwhitehorn 310190681Snwhitehorn#define VSID_NBPW (sizeof(u_int32_t) * 8) 311209975Snwhitehorn#ifdef __powerpc64__ 312209975Snwhitehorn#define NVSIDS (NPMAPS * 16) 313209975Snwhitehorn#define VSID_HASHMASK 0xffffffffUL 314209975Snwhitehorn#else 315209975Snwhitehorn#define NVSIDS NPMAPS 316209975Snwhitehorn#define VSID_HASHMASK 0xfffffUL 317209975Snwhitehorn#endif 318209975Snwhitehornstatic u_int moea64_vsid_bitmap[NVSIDS / VSID_NBPW]; 319190681Snwhitehorn 320190681Snwhitehornstatic boolean_t moea64_initialized = FALSE; 321190681Snwhitehorn 322190681Snwhitehorn/* 323190681Snwhitehorn * Statistics. 324190681Snwhitehorn */ 325190681Snwhitehornu_int moea64_pte_valid = 0; 326190681Snwhitehornu_int moea64_pte_overflow = 0; 327190681Snwhitehornu_int moea64_pvo_entries = 0; 328190681Snwhitehornu_int moea64_pvo_enter_calls = 0; 329190681Snwhitehornu_int moea64_pvo_remove_calls = 0; 330190681SnwhitehornSYSCTL_INT(_machdep, OID_AUTO, moea64_pte_valid, CTLFLAG_RD, 331190681Snwhitehorn &moea64_pte_valid, 0, ""); 332190681SnwhitehornSYSCTL_INT(_machdep, OID_AUTO, moea64_pte_overflow, CTLFLAG_RD, 333190681Snwhitehorn &moea64_pte_overflow, 0, ""); 334190681SnwhitehornSYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_entries, CTLFLAG_RD, 335190681Snwhitehorn &moea64_pvo_entries, 0, ""); 336190681SnwhitehornSYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_enter_calls, CTLFLAG_RD, 337190681Snwhitehorn &moea64_pvo_enter_calls, 0, ""); 338190681SnwhitehornSYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_remove_calls, CTLFLAG_RD, 339190681Snwhitehorn &moea64_pvo_remove_calls, 0, ""); 340190681Snwhitehorn 341190681Snwhitehornvm_offset_t moea64_scratchpage_va[2]; 342209975Snwhitehornuint64_t moea64_scratchpage_vpn[2]; 343190681Snwhitehornstruct lpte *moea64_scratchpage_pte[2]; 344190681Snwhitehornstruct mtx moea64_scratchpage_mtx; 345190681Snwhitehorn 346209975Snwhitehornuint64_t moea64_large_page_mask = 0; 347209975Snwhitehornint moea64_large_page_size = 0; 348209975Snwhitehornint moea64_large_page_shift = 0; 349209975Snwhitehorn 350190681Snwhitehorn/* 351190681Snwhitehorn * Allocate physical memory for use in moea64_bootstrap. 352190681Snwhitehorn */ 353190681Snwhitehornstatic vm_offset_t moea64_bootstrap_alloc(vm_size_t, u_int); 354190681Snwhitehorn 355190681Snwhitehorn/* 356190681Snwhitehorn * PTE calls. 357190681Snwhitehorn */ 358190681Snwhitehornstatic int moea64_pte_insert(u_int, struct lpte *); 359190681Snwhitehorn 360190681Snwhitehorn/* 361190681Snwhitehorn * PVO calls. 362190681Snwhitehorn */ 363190681Snwhitehornstatic int moea64_pvo_enter(pmap_t, uma_zone_t, struct pvo_head *, 364198378Snwhitehorn vm_offset_t, vm_offset_t, uint64_t, int); 365209975Snwhitehornstatic void moea64_pvo_remove(struct pvo_entry *); 366209975Snwhitehornstatic struct pvo_entry *moea64_pvo_find_va(pmap_t, vm_offset_t); 367209975Snwhitehornstatic struct lpte *moea64_pvo_to_pte(const struct pvo_entry *); 368190681Snwhitehorn 369190681Snwhitehorn/* 370190681Snwhitehorn * Utility routines. 371190681Snwhitehorn */ 372209975Snwhitehornstatic void moea64_bootstrap(mmu_t mmup, 373190681Snwhitehorn vm_offset_t kernelstart, vm_offset_t kernelend); 374209975Snwhitehornstatic void moea64_cpu_bootstrap(mmu_t, int ap); 375190681Snwhitehornstatic void moea64_enter_locked(pmap_t, vm_offset_t, vm_page_t, 376190681Snwhitehorn vm_prot_t, boolean_t); 377190681Snwhitehornstatic boolean_t moea64_query_bit(vm_page_t, u_int64_t); 378208990Salcstatic u_int moea64_clear_bit(vm_page_t, u_int64_t); 379190681Snwhitehornstatic void moea64_kremove(mmu_t, vm_offset_t); 380190681Snwhitehornstatic void moea64_syncicache(pmap_t pmap, vm_offset_t va, 381198341Smarcel vm_offset_t pa, vm_size_t sz); 382190681Snwhitehornstatic void tlbia(void); 383209975Snwhitehorn#ifdef __powerpc64__ 384209975Snwhitehornstatic void slbia(void); 385209975Snwhitehorn#endif 386190681Snwhitehorn 387190681Snwhitehorn/* 388190681Snwhitehorn * Kernel MMU interface 389190681Snwhitehorn */ 390190681Snwhitehornvoid moea64_change_wiring(mmu_t, pmap_t, vm_offset_t, boolean_t); 391190681Snwhitehornvoid moea64_clear_modify(mmu_t, vm_page_t); 392190681Snwhitehornvoid moea64_clear_reference(mmu_t, vm_page_t); 393190681Snwhitehornvoid moea64_copy_page(mmu_t, vm_page_t, vm_page_t); 394190681Snwhitehornvoid moea64_enter(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t, boolean_t); 395190681Snwhitehornvoid moea64_enter_object(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_page_t, 396190681Snwhitehorn vm_prot_t); 397190681Snwhitehornvoid moea64_enter_quick(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t); 398190681Snwhitehornvm_paddr_t moea64_extract(mmu_t, pmap_t, vm_offset_t); 399190681Snwhitehornvm_page_t moea64_extract_and_hold(mmu_t, pmap_t, vm_offset_t, vm_prot_t); 400190681Snwhitehornvoid moea64_init(mmu_t); 401190681Snwhitehornboolean_t moea64_is_modified(mmu_t, vm_page_t); 402214617Salcboolean_t moea64_is_prefaultable(mmu_t, pmap_t, vm_offset_t); 403207155Salcboolean_t moea64_is_referenced(mmu_t, vm_page_t); 404190681Snwhitehornboolean_t moea64_ts_referenced(mmu_t, vm_page_t); 405190681Snwhitehornvm_offset_t moea64_map(mmu_t, vm_offset_t *, vm_offset_t, vm_offset_t, int); 406190681Snwhitehornboolean_t moea64_page_exists_quick(mmu_t, pmap_t, vm_page_t); 407190681Snwhitehornint moea64_page_wired_mappings(mmu_t, vm_page_t); 408190681Snwhitehornvoid moea64_pinit(mmu_t, pmap_t); 409190681Snwhitehornvoid moea64_pinit0(mmu_t, pmap_t); 410190681Snwhitehornvoid moea64_protect(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_prot_t); 411190681Snwhitehornvoid moea64_qenter(mmu_t, vm_offset_t, vm_page_t *, int); 412190681Snwhitehornvoid moea64_qremove(mmu_t, vm_offset_t, int); 413190681Snwhitehornvoid moea64_release(mmu_t, pmap_t); 414190681Snwhitehornvoid moea64_remove(mmu_t, pmap_t, vm_offset_t, vm_offset_t); 415190681Snwhitehornvoid moea64_remove_all(mmu_t, vm_page_t); 416190681Snwhitehornvoid moea64_remove_write(mmu_t, vm_page_t); 417190681Snwhitehornvoid moea64_zero_page(mmu_t, vm_page_t); 418190681Snwhitehornvoid moea64_zero_page_area(mmu_t, vm_page_t, int, int); 419190681Snwhitehornvoid moea64_zero_page_idle(mmu_t, vm_page_t); 420190681Snwhitehornvoid moea64_activate(mmu_t, struct thread *); 421190681Snwhitehornvoid moea64_deactivate(mmu_t, struct thread *); 422190681Snwhitehornvoid *moea64_mapdev(mmu_t, vm_offset_t, vm_size_t); 423213307Snwhitehornvoid *moea64_mapdev_attr(mmu_t, vm_offset_t, vm_size_t, vm_memattr_t); 424190681Snwhitehornvoid moea64_unmapdev(mmu_t, vm_offset_t, vm_size_t); 425190681Snwhitehornvm_offset_t moea64_kextract(mmu_t, vm_offset_t); 426213307Snwhitehornvoid moea64_page_set_memattr(mmu_t, vm_page_t m, vm_memattr_t ma); 427213307Snwhitehornvoid moea64_kenter_attr(mmu_t, vm_offset_t, vm_offset_t, vm_memattr_t ma); 428190681Snwhitehornvoid moea64_kenter(mmu_t, vm_offset_t, vm_offset_t); 429190681Snwhitehornboolean_t moea64_dev_direct_mapped(mmu_t, vm_offset_t, vm_size_t); 430198341Smarcelstatic void moea64_sync_icache(mmu_t, pmap_t, vm_offset_t, vm_size_t); 431190681Snwhitehorn 432209975Snwhitehornstatic mmu_method_t moea64_methods[] = { 433190681Snwhitehorn MMUMETHOD(mmu_change_wiring, moea64_change_wiring), 434190681Snwhitehorn MMUMETHOD(mmu_clear_modify, moea64_clear_modify), 435190681Snwhitehorn MMUMETHOD(mmu_clear_reference, moea64_clear_reference), 436190681Snwhitehorn MMUMETHOD(mmu_copy_page, moea64_copy_page), 437190681Snwhitehorn MMUMETHOD(mmu_enter, moea64_enter), 438190681Snwhitehorn MMUMETHOD(mmu_enter_object, moea64_enter_object), 439190681Snwhitehorn MMUMETHOD(mmu_enter_quick, moea64_enter_quick), 440190681Snwhitehorn MMUMETHOD(mmu_extract, moea64_extract), 441190681Snwhitehorn MMUMETHOD(mmu_extract_and_hold, moea64_extract_and_hold), 442190681Snwhitehorn MMUMETHOD(mmu_init, moea64_init), 443190681Snwhitehorn MMUMETHOD(mmu_is_modified, moea64_is_modified), 444214617Salc MMUMETHOD(mmu_is_prefaultable, moea64_is_prefaultable), 445207155Salc MMUMETHOD(mmu_is_referenced, moea64_is_referenced), 446190681Snwhitehorn MMUMETHOD(mmu_ts_referenced, moea64_ts_referenced), 447190681Snwhitehorn MMUMETHOD(mmu_map, moea64_map), 448190681Snwhitehorn MMUMETHOD(mmu_page_exists_quick,moea64_page_exists_quick), 449190681Snwhitehorn MMUMETHOD(mmu_page_wired_mappings,moea64_page_wired_mappings), 450190681Snwhitehorn MMUMETHOD(mmu_pinit, moea64_pinit), 451190681Snwhitehorn MMUMETHOD(mmu_pinit0, moea64_pinit0), 452190681Snwhitehorn MMUMETHOD(mmu_protect, moea64_protect), 453190681Snwhitehorn MMUMETHOD(mmu_qenter, moea64_qenter), 454190681Snwhitehorn MMUMETHOD(mmu_qremove, moea64_qremove), 455190681Snwhitehorn MMUMETHOD(mmu_release, moea64_release), 456190681Snwhitehorn MMUMETHOD(mmu_remove, moea64_remove), 457190681Snwhitehorn MMUMETHOD(mmu_remove_all, moea64_remove_all), 458190681Snwhitehorn MMUMETHOD(mmu_remove_write, moea64_remove_write), 459198341Smarcel MMUMETHOD(mmu_sync_icache, moea64_sync_icache), 460190681Snwhitehorn MMUMETHOD(mmu_zero_page, moea64_zero_page), 461190681Snwhitehorn MMUMETHOD(mmu_zero_page_area, moea64_zero_page_area), 462190681Snwhitehorn MMUMETHOD(mmu_zero_page_idle, moea64_zero_page_idle), 463190681Snwhitehorn MMUMETHOD(mmu_activate, moea64_activate), 464190681Snwhitehorn MMUMETHOD(mmu_deactivate, moea64_deactivate), 465213307Snwhitehorn MMUMETHOD(mmu_page_set_memattr, moea64_page_set_memattr), 466190681Snwhitehorn 467190681Snwhitehorn /* Internal interfaces */ 468209975Snwhitehorn MMUMETHOD(mmu_bootstrap, moea64_bootstrap), 469209975Snwhitehorn MMUMETHOD(mmu_cpu_bootstrap, moea64_cpu_bootstrap), 470190681Snwhitehorn MMUMETHOD(mmu_mapdev, moea64_mapdev), 471213307Snwhitehorn MMUMETHOD(mmu_mapdev_attr, moea64_mapdev_attr), 472190681Snwhitehorn MMUMETHOD(mmu_unmapdev, moea64_unmapdev), 473190681Snwhitehorn MMUMETHOD(mmu_kextract, moea64_kextract), 474190681Snwhitehorn MMUMETHOD(mmu_kenter, moea64_kenter), 475213307Snwhitehorn MMUMETHOD(mmu_kenter_attr, moea64_kenter_attr), 476190681Snwhitehorn MMUMETHOD(mmu_dev_direct_mapped,moea64_dev_direct_mapped), 477190681Snwhitehorn 478190681Snwhitehorn { 0, 0 } 479190681Snwhitehorn}; 480190681Snwhitehorn 481212627SgrehanMMU_DEF(oea64_mmu, MMU_TYPE_G5, moea64_methods, 0); 482190681Snwhitehorn 483190681Snwhitehornstatic __inline u_int 484209975Snwhitehornva_to_pteg(uint64_t vsid, vm_offset_t addr, int large) 485190681Snwhitehorn{ 486204268Snwhitehorn uint64_t hash; 487209975Snwhitehorn int shift; 488190681Snwhitehorn 489209975Snwhitehorn shift = large ? moea64_large_page_shift : ADDR_PIDX_SHFT; 490204268Snwhitehorn hash = (vsid & VSID_HASH_MASK) ^ (((uint64_t)addr & ADDR_PIDX) >> 491209975Snwhitehorn shift); 492190681Snwhitehorn return (hash & moea64_pteg_mask); 493190681Snwhitehorn} 494190681Snwhitehorn 495190681Snwhitehornstatic __inline struct pvo_head * 496190681Snwhitehornvm_page_to_pvoh(vm_page_t m) 497190681Snwhitehorn{ 498190681Snwhitehorn 499190681Snwhitehorn return (&m->md.mdpg_pvoh); 500190681Snwhitehorn} 501190681Snwhitehorn 502190681Snwhitehornstatic __inline void 503190681Snwhitehornmoea64_attr_clear(vm_page_t m, u_int64_t ptebit) 504190681Snwhitehorn{ 505190681Snwhitehorn 506190681Snwhitehorn mtx_assert(&vm_page_queue_mtx, MA_OWNED); 507190681Snwhitehorn m->md.mdpg_attrs &= ~ptebit; 508190681Snwhitehorn} 509190681Snwhitehorn 510190681Snwhitehornstatic __inline u_int64_t 511190681Snwhitehornmoea64_attr_fetch(vm_page_t m) 512190681Snwhitehorn{ 513190681Snwhitehorn 514190681Snwhitehorn return (m->md.mdpg_attrs); 515190681Snwhitehorn} 516190681Snwhitehorn 517190681Snwhitehornstatic __inline void 518190681Snwhitehornmoea64_attr_save(vm_page_t m, u_int64_t ptebit) 519190681Snwhitehorn{ 520190681Snwhitehorn 521190681Snwhitehorn mtx_assert(&vm_page_queue_mtx, MA_OWNED); 522190681Snwhitehorn m->md.mdpg_attrs |= ptebit; 523190681Snwhitehorn} 524190681Snwhitehorn 525190681Snwhitehornstatic __inline void 526190681Snwhitehornmoea64_pte_create(struct lpte *pt, uint64_t vsid, vm_offset_t va, 527209975Snwhitehorn uint64_t pte_lo, int flags) 528190681Snwhitehorn{ 529209975Snwhitehorn 530190681Snwhitehorn ASSERT_TABLE_LOCK(); 531190681Snwhitehorn 532190681Snwhitehorn /* 533190681Snwhitehorn * Construct a PTE. Default to IMB initially. Valid bit only gets 534190681Snwhitehorn * set when the real pte is set in memory. 535190681Snwhitehorn * 536190681Snwhitehorn * Note: Don't set the valid bit for correct operation of tlb update. 537190681Snwhitehorn */ 538190681Snwhitehorn pt->pte_hi = (vsid << LPTE_VSID_SHIFT) | 539190681Snwhitehorn (((uint64_t)(va & ADDR_PIDX) >> ADDR_API_SHFT64) & LPTE_API); 540190681Snwhitehorn 541209975Snwhitehorn if (flags & PVO_LARGE) 542209975Snwhitehorn pt->pte_hi |= LPTE_BIG; 543209975Snwhitehorn 544190681Snwhitehorn pt->pte_lo = pte_lo; 545190681Snwhitehorn} 546190681Snwhitehorn 547190681Snwhitehornstatic __inline void 548190681Snwhitehornmoea64_pte_synch(struct lpte *pt, struct lpte *pvo_pt) 549190681Snwhitehorn{ 550190681Snwhitehorn 551190681Snwhitehorn ASSERT_TABLE_LOCK(); 552190681Snwhitehorn 553190681Snwhitehorn pvo_pt->pte_lo |= pt->pte_lo & (LPTE_REF | LPTE_CHG); 554190681Snwhitehorn} 555190681Snwhitehorn 556190681Snwhitehornstatic __inline void 557209975Snwhitehornmoea64_pte_clear(struct lpte *pt, uint64_t vpn, u_int64_t ptebit) 558190681Snwhitehorn{ 559190681Snwhitehorn ASSERT_TABLE_LOCK(); 560190681Snwhitehorn 561190681Snwhitehorn /* 562190681Snwhitehorn * As shown in Section 7.6.3.2.3 563190681Snwhitehorn */ 564190681Snwhitehorn pt->pte_lo &= ~ptebit; 565209975Snwhitehorn TLBIE(vpn); 566190681Snwhitehorn} 567190681Snwhitehorn 568190681Snwhitehornstatic __inline void 569190681Snwhitehornmoea64_pte_set(struct lpte *pt, struct lpte *pvo_pt) 570190681Snwhitehorn{ 571190681Snwhitehorn 572190681Snwhitehorn ASSERT_TABLE_LOCK(); 573190681Snwhitehorn pvo_pt->pte_hi |= LPTE_VALID; 574190681Snwhitehorn 575190681Snwhitehorn /* 576190681Snwhitehorn * Update the PTE as defined in section 7.6.3.1. 577190681Snwhitehorn * Note that the REF/CHG bits are from pvo_pt and thus should have 578190681Snwhitehorn * been saved so this routine can restore them (if desired). 579190681Snwhitehorn */ 580190681Snwhitehorn pt->pte_lo = pvo_pt->pte_lo; 581190681Snwhitehorn EIEIO(); 582190681Snwhitehorn pt->pte_hi = pvo_pt->pte_hi; 583204042Snwhitehorn PTESYNC(); 584190681Snwhitehorn moea64_pte_valid++; 585190681Snwhitehorn} 586190681Snwhitehorn 587190681Snwhitehornstatic __inline void 588209975Snwhitehornmoea64_pte_unset(struct lpte *pt, struct lpte *pvo_pt, uint64_t vpn) 589190681Snwhitehorn{ 590190681Snwhitehorn ASSERT_TABLE_LOCK(); 591190681Snwhitehorn pvo_pt->pte_hi &= ~LPTE_VALID; 592190681Snwhitehorn 593190681Snwhitehorn /* 594190681Snwhitehorn * Force the reg & chg bits back into the PTEs. 595190681Snwhitehorn */ 596190681Snwhitehorn SYNC(); 597190681Snwhitehorn 598190681Snwhitehorn /* 599190681Snwhitehorn * Invalidate the pte. 600190681Snwhitehorn */ 601190681Snwhitehorn pt->pte_hi &= ~LPTE_VALID; 602209975Snwhitehorn TLBIE(vpn); 603190681Snwhitehorn 604190681Snwhitehorn /* 605190681Snwhitehorn * Save the reg & chg bits. 606190681Snwhitehorn */ 607190681Snwhitehorn moea64_pte_synch(pt, pvo_pt); 608190681Snwhitehorn moea64_pte_valid--; 609190681Snwhitehorn} 610190681Snwhitehorn 611190681Snwhitehornstatic __inline void 612209975Snwhitehornmoea64_pte_change(struct lpte *pt, struct lpte *pvo_pt, uint64_t vpn) 613190681Snwhitehorn{ 614190681Snwhitehorn 615190681Snwhitehorn /* 616190681Snwhitehorn * Invalidate the PTE 617190681Snwhitehorn */ 618209975Snwhitehorn moea64_pte_unset(pt, pvo_pt, vpn); 619190681Snwhitehorn moea64_pte_set(pt, pvo_pt); 620190681Snwhitehorn} 621190681Snwhitehorn 622190681Snwhitehornstatic __inline uint64_t 623213307Snwhitehornmoea64_calc_wimg(vm_offset_t pa, vm_memattr_t ma) 624190681Snwhitehorn{ 625190681Snwhitehorn uint64_t pte_lo; 626190681Snwhitehorn int i; 627190681Snwhitehorn 628213307Snwhitehorn if (ma != VM_MEMATTR_DEFAULT) { 629213307Snwhitehorn switch (ma) { 630213307Snwhitehorn case VM_MEMATTR_UNCACHEABLE: 631213307Snwhitehorn return (LPTE_I | LPTE_G); 632213307Snwhitehorn case VM_MEMATTR_WRITE_COMBINING: 633213307Snwhitehorn case VM_MEMATTR_WRITE_BACK: 634213307Snwhitehorn case VM_MEMATTR_PREFETCHABLE: 635213307Snwhitehorn return (LPTE_I); 636213307Snwhitehorn case VM_MEMATTR_WRITE_THROUGH: 637213307Snwhitehorn return (LPTE_W | LPTE_M); 638213307Snwhitehorn } 639213307Snwhitehorn } 640213307Snwhitehorn 641190681Snwhitehorn /* 642190681Snwhitehorn * Assume the page is cache inhibited and access is guarded unless 643190681Snwhitehorn * it's in our available memory array. 644190681Snwhitehorn */ 645190681Snwhitehorn pte_lo = LPTE_I | LPTE_G; 646190681Snwhitehorn for (i = 0; i < pregions_sz; i++) { 647190681Snwhitehorn if ((pa >= pregions[i].mr_start) && 648190681Snwhitehorn (pa < (pregions[i].mr_start + pregions[i].mr_size))) { 649190681Snwhitehorn pte_lo &= ~(LPTE_I | LPTE_G); 650190681Snwhitehorn pte_lo |= LPTE_M; 651190681Snwhitehorn break; 652190681Snwhitehorn } 653190681Snwhitehorn } 654190681Snwhitehorn 655190681Snwhitehorn return pte_lo; 656190681Snwhitehorn} 657190681Snwhitehorn 658190681Snwhitehorn/* 659190681Snwhitehorn * Quick sort callout for comparing memory regions. 660190681Snwhitehorn */ 661190681Snwhitehornstatic int mr_cmp(const void *a, const void *b); 662190681Snwhitehornstatic int om_cmp(const void *a, const void *b); 663190681Snwhitehorn 664190681Snwhitehornstatic int 665190681Snwhitehornmr_cmp(const void *a, const void *b) 666190681Snwhitehorn{ 667190681Snwhitehorn const struct mem_region *regiona; 668190681Snwhitehorn const struct mem_region *regionb; 669190681Snwhitehorn 670190681Snwhitehorn regiona = a; 671190681Snwhitehorn regionb = b; 672190681Snwhitehorn if (regiona->mr_start < regionb->mr_start) 673190681Snwhitehorn return (-1); 674190681Snwhitehorn else if (regiona->mr_start > regionb->mr_start) 675190681Snwhitehorn return (1); 676190681Snwhitehorn else 677190681Snwhitehorn return (0); 678190681Snwhitehorn} 679190681Snwhitehorn 680190681Snwhitehornstatic int 681190681Snwhitehornom_cmp(const void *a, const void *b) 682190681Snwhitehorn{ 683190681Snwhitehorn const struct ofw_map *mapa; 684190681Snwhitehorn const struct ofw_map *mapb; 685190681Snwhitehorn 686190681Snwhitehorn mapa = a; 687190681Snwhitehorn mapb = b; 688190681Snwhitehorn if (mapa->om_pa_hi < mapb->om_pa_hi) 689190681Snwhitehorn return (-1); 690190681Snwhitehorn else if (mapa->om_pa_hi > mapb->om_pa_hi) 691190681Snwhitehorn return (1); 692190681Snwhitehorn else if (mapa->om_pa_lo < mapb->om_pa_lo) 693190681Snwhitehorn return (-1); 694190681Snwhitehorn else if (mapa->om_pa_lo > mapb->om_pa_lo) 695190681Snwhitehorn return (1); 696190681Snwhitehorn else 697190681Snwhitehorn return (0); 698190681Snwhitehorn} 699190681Snwhitehorn 700190681Snwhitehornstatic void 701209975Snwhitehornmoea64_cpu_bootstrap(mmu_t mmup, int ap) 702190681Snwhitehorn{ 703190681Snwhitehorn int i = 0; 704209975Snwhitehorn #ifdef __powerpc64__ 705209975Snwhitehorn struct slb *slb = PCPU_GET(slb); 706209975Snwhitehorn #endif 707190681Snwhitehorn 708190681Snwhitehorn /* 709190681Snwhitehorn * Initialize segment registers and MMU 710190681Snwhitehorn */ 711190681Snwhitehorn 712190681Snwhitehorn mtmsr(mfmsr() & ~PSL_DR & ~PSL_IR); isync(); 713209975Snwhitehorn 714209975Snwhitehorn /* 715209975Snwhitehorn * Install kernel SLB entries 716209975Snwhitehorn */ 717209975Snwhitehorn 718209975Snwhitehorn #ifdef __powerpc64__ 719209975Snwhitehorn slbia(); 720209975Snwhitehorn 721209975Snwhitehorn for (i = 0; i < 64; i++) { 722209975Snwhitehorn if (!(slb[i].slbe & SLBE_VALID)) 723209975Snwhitehorn continue; 724209975Snwhitehorn 725209975Snwhitehorn __asm __volatile ("slbmte %0, %1" :: 726209975Snwhitehorn "r"(slb[i].slbv), "r"(slb[i].slbe)); 727209975Snwhitehorn } 728209975Snwhitehorn #else 729209975Snwhitehorn for (i = 0; i < 16; i++) 730209975Snwhitehorn mtsrin(i << ADDR_SR_SHFT, kernel_pmap->pm_sr[i]); 731209975Snwhitehorn #endif 732209975Snwhitehorn 733209975Snwhitehorn /* 734209975Snwhitehorn * Install page table 735209975Snwhitehorn */ 736209975Snwhitehorn 737204042Snwhitehorn __asm __volatile ("ptesync; mtsdr1 %0; isync" 738209975Snwhitehorn :: "r"((uintptr_t)moea64_pteg_table 739209975Snwhitehorn | (64 - cntlzd(moea64_pteg_mask >> 11)))); 740190681Snwhitehorn tlbia(); 741190681Snwhitehorn} 742190681Snwhitehorn 743190681Snwhitehornstatic void 744199226Snwhitehornmoea64_add_ofw_mappings(mmu_t mmup, phandle_t mmu, size_t sz) 745199226Snwhitehorn{ 746199226Snwhitehorn struct ofw_map translations[sz/sizeof(struct ofw_map)]; 747199226Snwhitehorn register_t msr; 748199226Snwhitehorn vm_offset_t off; 749204128Snwhitehorn vm_paddr_t pa_base; 750199226Snwhitehorn int i, ofw_mappings; 751199226Snwhitehorn 752199226Snwhitehorn bzero(translations, sz); 753199226Snwhitehorn if (OF_getprop(mmu, "translations", translations, sz) == -1) 754199226Snwhitehorn panic("moea64_bootstrap: can't get ofw translations"); 755199226Snwhitehorn 756199226Snwhitehorn CTR0(KTR_PMAP, "moea64_add_ofw_mappings: translations"); 757199226Snwhitehorn sz /= sizeof(*translations); 758199226Snwhitehorn qsort(translations, sz, sizeof (*translations), om_cmp); 759199226Snwhitehorn 760199226Snwhitehorn for (i = 0, ofw_mappings = 0; i < sz; i++) { 761199226Snwhitehorn CTR3(KTR_PMAP, "translation: pa=%#x va=%#x len=%#x", 762199226Snwhitehorn (uint32_t)(translations[i].om_pa_lo), translations[i].om_va, 763199226Snwhitehorn translations[i].om_len); 764199226Snwhitehorn 765199226Snwhitehorn if (translations[i].om_pa_lo % PAGE_SIZE) 766199226Snwhitehorn panic("OFW translation not page-aligned!"); 767199226Snwhitehorn 768209975Snwhitehorn pa_base = translations[i].om_pa_lo; 769209975Snwhitehorn 770209975Snwhitehorn #ifdef __powerpc64__ 771209975Snwhitehorn pa_base += (vm_offset_t)translations[i].om_pa_hi << 32; 772209975Snwhitehorn #else 773199226Snwhitehorn if (translations[i].om_pa_hi) 774199226Snwhitehorn panic("OFW translations above 32-bit boundary!"); 775209975Snwhitehorn #endif 776199226Snwhitehorn 777199226Snwhitehorn /* Now enter the pages for this mapping */ 778199226Snwhitehorn 779199226Snwhitehorn DISABLE_TRANS(msr); 780199226Snwhitehorn for (off = 0; off < translations[i].om_len; off += PAGE_SIZE) { 781209975Snwhitehorn if (moea64_pvo_find_va(kernel_pmap, 782209975Snwhitehorn translations[i].om_va + off) != NULL) 783209975Snwhitehorn continue; 784209975Snwhitehorn 785204128Snwhitehorn moea64_kenter(mmup, translations[i].om_va + off, 786204128Snwhitehorn pa_base + off); 787199226Snwhitehorn 788199226Snwhitehorn ofw_mappings++; 789199226Snwhitehorn } 790199226Snwhitehorn ENABLE_TRANS(msr); 791199226Snwhitehorn } 792199226Snwhitehorn} 793199226Snwhitehorn 794209975Snwhitehorn#ifdef __powerpc64__ 795199226Snwhitehornstatic void 796209975Snwhitehornmoea64_probe_large_page(void) 797190681Snwhitehorn{ 798209975Snwhitehorn uint16_t pvr = mfpvr() >> 16; 799209975Snwhitehorn 800209975Snwhitehorn switch (pvr) { 801209975Snwhitehorn case IBM970: 802209975Snwhitehorn case IBM970FX: 803209975Snwhitehorn case IBM970MP: 804209975Snwhitehorn powerpc_sync(); isync(); 805209975Snwhitehorn mtspr(SPR_HID4, mfspr(SPR_HID4) & ~HID4_970_DISABLE_LG_PG); 806209975Snwhitehorn powerpc_sync(); isync(); 807209975Snwhitehorn 808209975Snwhitehorn /* FALLTHROUGH */ 809209975Snwhitehorn case IBMCELLBE: 810209975Snwhitehorn moea64_large_page_size = 0x1000000; /* 16 MB */ 811209975Snwhitehorn moea64_large_page_shift = 24; 812209975Snwhitehorn break; 813209975Snwhitehorn default: 814209975Snwhitehorn moea64_large_page_size = 0; 815209975Snwhitehorn } 816209975Snwhitehorn 817209975Snwhitehorn moea64_large_page_mask = moea64_large_page_size - 1; 818209975Snwhitehorn} 819209975Snwhitehorn 820209975Snwhitehornstatic void 821209975Snwhitehornmoea64_bootstrap_slb_prefault(vm_offset_t va, int large) 822209975Snwhitehorn{ 823209975Snwhitehorn struct slb *cache; 824209975Snwhitehorn struct slb entry; 825209975Snwhitehorn uint64_t esid, slbe; 826209975Snwhitehorn uint64_t i; 827209975Snwhitehorn 828209975Snwhitehorn cache = PCPU_GET(slb); 829209975Snwhitehorn esid = va >> ADDR_SR_SHFT; 830209975Snwhitehorn slbe = (esid << SLBE_ESID_SHIFT) | SLBE_VALID; 831209975Snwhitehorn 832209975Snwhitehorn for (i = 0; i < 64; i++) { 833209975Snwhitehorn if (cache[i].slbe == (slbe | i)) 834209975Snwhitehorn return; 835209975Snwhitehorn } 836209975Snwhitehorn 837209975Snwhitehorn entry.slbe = slbe; 838210704Snwhitehorn entry.slbv = KERNEL_VSID(esid) << SLBV_VSID_SHIFT; 839209975Snwhitehorn if (large) 840209975Snwhitehorn entry.slbv |= SLBV_L; 841209975Snwhitehorn 842212722Snwhitehorn slb_insert_kernel(entry.slbe, entry.slbv); 843209975Snwhitehorn} 844209975Snwhitehorn#endif 845209975Snwhitehorn 846209975Snwhitehornstatic void 847209975Snwhitehornmoea64_setup_direct_map(mmu_t mmup, vm_offset_t kernelstart, 848209975Snwhitehorn vm_offset_t kernelend) 849209975Snwhitehorn{ 850209975Snwhitehorn register_t msr; 851209975Snwhitehorn vm_paddr_t pa; 852209975Snwhitehorn vm_offset_t size, off; 853209975Snwhitehorn uint64_t pte_lo; 854209975Snwhitehorn int i; 855209975Snwhitehorn 856209975Snwhitehorn if (moea64_large_page_size == 0) 857209975Snwhitehorn hw_direct_map = 0; 858209975Snwhitehorn 859209975Snwhitehorn DISABLE_TRANS(msr); 860209975Snwhitehorn if (hw_direct_map) { 861209975Snwhitehorn PMAP_LOCK(kernel_pmap); 862209975Snwhitehorn for (i = 0; i < pregions_sz; i++) { 863209975Snwhitehorn for (pa = pregions[i].mr_start; pa < pregions[i].mr_start + 864209975Snwhitehorn pregions[i].mr_size; pa += moea64_large_page_size) { 865209975Snwhitehorn pte_lo = LPTE_M; 866209975Snwhitehorn 867209975Snwhitehorn /* 868209975Snwhitehorn * Set memory access as guarded if prefetch within 869209975Snwhitehorn * the page could exit the available physmem area. 870209975Snwhitehorn */ 871209975Snwhitehorn if (pa & moea64_large_page_mask) { 872209975Snwhitehorn pa &= moea64_large_page_mask; 873209975Snwhitehorn pte_lo |= LPTE_G; 874209975Snwhitehorn } 875209975Snwhitehorn if (pa + moea64_large_page_size > 876209975Snwhitehorn pregions[i].mr_start + pregions[i].mr_size) 877209975Snwhitehorn pte_lo |= LPTE_G; 878209975Snwhitehorn 879209975Snwhitehorn moea64_pvo_enter(kernel_pmap, moea64_upvo_zone, 880209975Snwhitehorn &moea64_pvo_kunmanaged, pa, pa, 881209975Snwhitehorn pte_lo, PVO_WIRED | PVO_LARGE | 882209975Snwhitehorn VM_PROT_EXECUTE); 883209975Snwhitehorn } 884209975Snwhitehorn } 885209975Snwhitehorn PMAP_UNLOCK(kernel_pmap); 886209975Snwhitehorn } else { 887209975Snwhitehorn size = moea64_pteg_count * sizeof(struct lpteg); 888209975Snwhitehorn off = (vm_offset_t)(moea64_pteg_table); 889209975Snwhitehorn for (pa = off; pa < off + size; pa += PAGE_SIZE) 890209975Snwhitehorn moea64_kenter(mmup, pa, pa); 891209975Snwhitehorn size = sizeof(struct pvo_head) * moea64_pteg_count; 892209975Snwhitehorn off = (vm_offset_t)(moea64_pvo_table); 893209975Snwhitehorn for (pa = off; pa < off + size; pa += PAGE_SIZE) 894209975Snwhitehorn moea64_kenter(mmup, pa, pa); 895209975Snwhitehorn size = BPVO_POOL_SIZE*sizeof(struct pvo_entry); 896209975Snwhitehorn off = (vm_offset_t)(moea64_bpvo_pool); 897209975Snwhitehorn for (pa = off; pa < off + size; pa += PAGE_SIZE) 898209975Snwhitehorn moea64_kenter(mmup, pa, pa); 899209975Snwhitehorn 900209975Snwhitehorn /* 901209975Snwhitehorn * Map certain important things, like ourselves. 902209975Snwhitehorn * 903209975Snwhitehorn * NOTE: We do not map the exception vector space. That code is 904209975Snwhitehorn * used only in real mode, and leaving it unmapped allows us to 905209975Snwhitehorn * catch NULL pointer deferences, instead of making NULL a valid 906209975Snwhitehorn * address. 907209975Snwhitehorn */ 908209975Snwhitehorn 909209975Snwhitehorn for (pa = kernelstart & ~PAGE_MASK; pa < kernelend; 910209975Snwhitehorn pa += PAGE_SIZE) 911209975Snwhitehorn moea64_kenter(mmup, pa, pa); 912209975Snwhitehorn } 913209975Snwhitehorn ENABLE_TRANS(msr); 914209975Snwhitehorn} 915209975Snwhitehorn 916209975Snwhitehornstatic void 917209975Snwhitehornmoea64_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend) 918209975Snwhitehorn{ 919190681Snwhitehorn ihandle_t mmui; 920190681Snwhitehorn phandle_t chosen; 921190681Snwhitehorn phandle_t mmu; 922199226Snwhitehorn size_t sz; 923190681Snwhitehorn int i, j; 924190681Snwhitehorn vm_size_t size, physsz, hwphyssz; 925209975Snwhitehorn vm_offset_t pa, va; 926199226Snwhitehorn register_t msr; 927194784Sjeff void *dpcpu; 928190681Snwhitehorn 929209975Snwhitehorn#ifndef __powerpc64__ 930190681Snwhitehorn /* We don't have a direct map since there is no BAT */ 931190681Snwhitehorn hw_direct_map = 0; 932190681Snwhitehorn 933190681Snwhitehorn /* Make sure battable is zero, since we have no BAT */ 934190681Snwhitehorn for (i = 0; i < 16; i++) { 935190681Snwhitehorn battable[i].batu = 0; 936190681Snwhitehorn battable[i].batl = 0; 937190681Snwhitehorn } 938209975Snwhitehorn#else 939209975Snwhitehorn moea64_probe_large_page(); 940190681Snwhitehorn 941209975Snwhitehorn /* Use a direct map if we have large page support */ 942209975Snwhitehorn if (moea64_large_page_size > 0) 943209975Snwhitehorn hw_direct_map = 1; 944209975Snwhitehorn else 945209975Snwhitehorn hw_direct_map = 0; 946209975Snwhitehorn#endif 947209975Snwhitehorn 948190681Snwhitehorn /* Get physical memory regions from firmware */ 949190681Snwhitehorn mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz); 950190681Snwhitehorn CTR0(KTR_PMAP, "moea64_bootstrap: physical memory"); 951190681Snwhitehorn 952190681Snwhitehorn qsort(pregions, pregions_sz, sizeof(*pregions), mr_cmp); 953190681Snwhitehorn if (sizeof(phys_avail)/sizeof(phys_avail[0]) < regions_sz) 954190681Snwhitehorn panic("moea64_bootstrap: phys_avail too small"); 955190681Snwhitehorn qsort(regions, regions_sz, sizeof(*regions), mr_cmp); 956190681Snwhitehorn phys_avail_count = 0; 957190681Snwhitehorn physsz = 0; 958190681Snwhitehorn hwphyssz = 0; 959190681Snwhitehorn TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz); 960190681Snwhitehorn for (i = 0, j = 0; i < regions_sz; i++, j += 2) { 961190681Snwhitehorn CTR3(KTR_PMAP, "region: %#x - %#x (%#x)", regions[i].mr_start, 962190681Snwhitehorn regions[i].mr_start + regions[i].mr_size, 963190681Snwhitehorn regions[i].mr_size); 964190681Snwhitehorn if (hwphyssz != 0 && 965190681Snwhitehorn (physsz + regions[i].mr_size) >= hwphyssz) { 966190681Snwhitehorn if (physsz < hwphyssz) { 967190681Snwhitehorn phys_avail[j] = regions[i].mr_start; 968190681Snwhitehorn phys_avail[j + 1] = regions[i].mr_start + 969190681Snwhitehorn hwphyssz - physsz; 970190681Snwhitehorn physsz = hwphyssz; 971190681Snwhitehorn phys_avail_count++; 972190681Snwhitehorn } 973190681Snwhitehorn break; 974190681Snwhitehorn } 975190681Snwhitehorn phys_avail[j] = regions[i].mr_start; 976190681Snwhitehorn phys_avail[j + 1] = regions[i].mr_start + regions[i].mr_size; 977190681Snwhitehorn phys_avail_count++; 978190681Snwhitehorn physsz += regions[i].mr_size; 979190681Snwhitehorn } 980209975Snwhitehorn 981209975Snwhitehorn /* Check for overlap with the kernel and exception vectors */ 982209975Snwhitehorn for (j = 0; j < 2*phys_avail_count; j+=2) { 983209975Snwhitehorn if (phys_avail[j] < EXC_LAST) 984209975Snwhitehorn phys_avail[j] += EXC_LAST; 985209975Snwhitehorn 986209975Snwhitehorn if (kernelstart >= phys_avail[j] && 987209975Snwhitehorn kernelstart < phys_avail[j+1]) { 988209975Snwhitehorn if (kernelend < phys_avail[j+1]) { 989209975Snwhitehorn phys_avail[2*phys_avail_count] = 990209975Snwhitehorn (kernelend & ~PAGE_MASK) + PAGE_SIZE; 991209975Snwhitehorn phys_avail[2*phys_avail_count + 1] = 992209975Snwhitehorn phys_avail[j+1]; 993209975Snwhitehorn phys_avail_count++; 994209975Snwhitehorn } 995209975Snwhitehorn 996209975Snwhitehorn phys_avail[j+1] = kernelstart & ~PAGE_MASK; 997209975Snwhitehorn } 998209975Snwhitehorn 999209975Snwhitehorn if (kernelend >= phys_avail[j] && 1000209975Snwhitehorn kernelend < phys_avail[j+1]) { 1001209975Snwhitehorn if (kernelstart > phys_avail[j]) { 1002209975Snwhitehorn phys_avail[2*phys_avail_count] = phys_avail[j]; 1003209975Snwhitehorn phys_avail[2*phys_avail_count + 1] = 1004209975Snwhitehorn kernelstart & ~PAGE_MASK; 1005209975Snwhitehorn phys_avail_count++; 1006209975Snwhitehorn } 1007209975Snwhitehorn 1008209975Snwhitehorn phys_avail[j] = (kernelend & ~PAGE_MASK) + PAGE_SIZE; 1009209975Snwhitehorn } 1010209975Snwhitehorn } 1011209975Snwhitehorn 1012190681Snwhitehorn physmem = btoc(physsz); 1013190681Snwhitehorn 1014190681Snwhitehorn /* 1015190681Snwhitehorn * Allocate PTEG table. 1016190681Snwhitehorn */ 1017190681Snwhitehorn#ifdef PTEGCOUNT 1018190681Snwhitehorn moea64_pteg_count = PTEGCOUNT; 1019190681Snwhitehorn#else 1020190681Snwhitehorn moea64_pteg_count = 0x1000; 1021190681Snwhitehorn 1022190681Snwhitehorn while (moea64_pteg_count < physmem) 1023190681Snwhitehorn moea64_pteg_count <<= 1; 1024209975Snwhitehorn 1025209975Snwhitehorn moea64_pteg_count >>= 1; 1026190681Snwhitehorn#endif /* PTEGCOUNT */ 1027190681Snwhitehorn 1028190681Snwhitehorn size = moea64_pteg_count * sizeof(struct lpteg); 1029190681Snwhitehorn CTR2(KTR_PMAP, "moea64_bootstrap: %d PTEGs, %d bytes", 1030190681Snwhitehorn moea64_pteg_count, size); 1031190681Snwhitehorn 1032190681Snwhitehorn /* 1033190681Snwhitehorn * We now need to allocate memory. This memory, to be allocated, 1034190681Snwhitehorn * has to reside in a page table. The page table we are about to 1035190681Snwhitehorn * allocate. We don't have BAT. So drop to data real mode for a minute 1036190681Snwhitehorn * as a measure of last resort. We do this a couple times. 1037190681Snwhitehorn */ 1038190681Snwhitehorn 1039190681Snwhitehorn moea64_pteg_table = (struct lpteg *)moea64_bootstrap_alloc(size, size); 1040190681Snwhitehorn DISABLE_TRANS(msr); 1041190681Snwhitehorn bzero((void *)moea64_pteg_table, moea64_pteg_count * sizeof(struct lpteg)); 1042190681Snwhitehorn ENABLE_TRANS(msr); 1043190681Snwhitehorn 1044190681Snwhitehorn moea64_pteg_mask = moea64_pteg_count - 1; 1045190681Snwhitehorn 1046190681Snwhitehorn CTR1(KTR_PMAP, "moea64_bootstrap: PTEG table at %p", moea64_pteg_table); 1047190681Snwhitehorn 1048190681Snwhitehorn /* 1049190681Snwhitehorn * Allocate pv/overflow lists. 1050190681Snwhitehorn */ 1051190681Snwhitehorn size = sizeof(struct pvo_head) * moea64_pteg_count; 1052190681Snwhitehorn 1053190681Snwhitehorn moea64_pvo_table = (struct pvo_head *)moea64_bootstrap_alloc(size, 1054190681Snwhitehorn PAGE_SIZE); 1055190681Snwhitehorn CTR1(KTR_PMAP, "moea64_bootstrap: PVO table at %p", moea64_pvo_table); 1056190681Snwhitehorn 1057190681Snwhitehorn DISABLE_TRANS(msr); 1058190681Snwhitehorn for (i = 0; i < moea64_pteg_count; i++) 1059190681Snwhitehorn LIST_INIT(&moea64_pvo_table[i]); 1060190681Snwhitehorn ENABLE_TRANS(msr); 1061190681Snwhitehorn 1062190681Snwhitehorn /* 1063190681Snwhitehorn * Initialize the lock that synchronizes access to the pteg and pvo 1064190681Snwhitehorn * tables. 1065190681Snwhitehorn */ 1066190681Snwhitehorn mtx_init(&moea64_table_mutex, "pmap table", NULL, MTX_DEF | 1067190681Snwhitehorn MTX_RECURSE); 1068211967Snwhitehorn mtx_init(&moea64_slb_mutex, "SLB table", NULL, MTX_DEF); 1069190681Snwhitehorn 1070190681Snwhitehorn /* 1071198378Snwhitehorn * Initialize the TLBIE lock. TLBIE can only be executed by one CPU. 1072198378Snwhitehorn */ 1073198378Snwhitehorn mtx_init(&tlbie_mutex, "tlbie mutex", NULL, MTX_SPIN); 1074198378Snwhitehorn 1075198378Snwhitehorn /* 1076190681Snwhitehorn * Initialise the unmanaged pvo pool. 1077190681Snwhitehorn */ 1078190681Snwhitehorn moea64_bpvo_pool = (struct pvo_entry *)moea64_bootstrap_alloc( 1079190681Snwhitehorn BPVO_POOL_SIZE*sizeof(struct pvo_entry), 0); 1080190681Snwhitehorn moea64_bpvo_pool_index = 0; 1081190681Snwhitehorn 1082190681Snwhitehorn /* 1083190681Snwhitehorn * Make sure kernel vsid is allocated as well as VSID 0. 1084190681Snwhitehorn */ 1085209975Snwhitehorn #ifndef __powerpc64__ 1086209975Snwhitehorn moea64_vsid_bitmap[(KERNEL_VSIDBITS & (NVSIDS - 1)) / VSID_NBPW] 1087190681Snwhitehorn |= 1 << (KERNEL_VSIDBITS % VSID_NBPW); 1088190681Snwhitehorn moea64_vsid_bitmap[0] |= 1; 1089209975Snwhitehorn #endif 1090190681Snwhitehorn 1091190681Snwhitehorn /* 1092190681Snwhitehorn * Initialize the kernel pmap (which is statically allocated). 1093190681Snwhitehorn */ 1094209975Snwhitehorn #ifdef __powerpc64__ 1095209975Snwhitehorn for (i = 0; i < 64; i++) { 1096209975Snwhitehorn pcpup->pc_slb[i].slbv = 0; 1097209975Snwhitehorn pcpup->pc_slb[i].slbe = 0; 1098209975Snwhitehorn } 1099209975Snwhitehorn #else 1100190681Snwhitehorn for (i = 0; i < 16; i++) 1101190681Snwhitehorn kernel_pmap->pm_sr[i] = EMPTY_SEGMENT + i; 1102209975Snwhitehorn #endif 1103190681Snwhitehorn 1104190681Snwhitehorn kernel_pmap->pmap_phys = kernel_pmap; 1105190681Snwhitehorn kernel_pmap->pm_active = ~0; 1106190681Snwhitehorn 1107190681Snwhitehorn PMAP_LOCK_INIT(kernel_pmap); 1108190681Snwhitehorn 1109190681Snwhitehorn /* 1110190681Snwhitehorn * Now map in all the other buffers we allocated earlier 1111190681Snwhitehorn */ 1112190681Snwhitehorn 1113209975Snwhitehorn moea64_setup_direct_map(mmup, kernelstart, kernelend); 1114190681Snwhitehorn 1115190681Snwhitehorn /* 1116209975Snwhitehorn * Set up the Open Firmware pmap and add its mappings if not in real 1117209975Snwhitehorn * mode. 1118190681Snwhitehorn */ 1119190681Snwhitehorn 1120215067Snwhitehorn chosen = OF_finddevice("/chosen"); 1121215067Snwhitehorn if (chosen != -1 && OF_getprop(chosen, "mmu", &mmui, 4) != -1) { 1122209975Snwhitehorn #ifndef __powerpc64__ 1123209975Snwhitehorn moea64_pinit(mmup, &ofw_pmap); 1124190681Snwhitehorn 1125204128Snwhitehorn for (i = 0; i < 16; i++) 1126204128Snwhitehorn ofw_pmap.pm_sr[i] = kernel_pmap->pm_sr[i]; 1127209975Snwhitehorn #endif 1128190681Snwhitehorn 1129215158Snwhitehorn mmu = OF_instance_to_package(mmui); 1130215158Snwhitehorn if (mmu == -1 || (sz = OF_getproplen(mmu, "translations")) == -1) 1131215158Snwhitehorn sz = 0; 1132199226Snwhitehorn if (sz > 6144 /* tmpstksz - 2 KB headroom */) 1133199226Snwhitehorn panic("moea64_bootstrap: too many ofw translations"); 1134190681Snwhitehorn 1135215158Snwhitehorn if (sz > 0) 1136215158Snwhitehorn moea64_add_ofw_mappings(mmup, mmu, sz); 1137190681Snwhitehorn } 1138190681Snwhitehorn 1139190681Snwhitehorn#ifdef SMP 1140190681Snwhitehorn TLBSYNC(); 1141190681Snwhitehorn#endif 1142190681Snwhitehorn 1143190681Snwhitehorn /* 1144190681Snwhitehorn * Calculate the last available physical address. 1145190681Snwhitehorn */ 1146190681Snwhitehorn for (i = 0; phys_avail[i + 2] != 0; i += 2) 1147190681Snwhitehorn ; 1148190681Snwhitehorn Maxmem = powerpc_btop(phys_avail[i + 1]); 1149190681Snwhitehorn 1150190681Snwhitehorn /* 1151190681Snwhitehorn * Initialize MMU and remap early physical mappings 1152190681Snwhitehorn */ 1153209975Snwhitehorn moea64_cpu_bootstrap(mmup,0); 1154190681Snwhitehorn mtmsr(mfmsr() | PSL_DR | PSL_IR); isync(); 1155190681Snwhitehorn pmap_bootstrapped++; 1156190681Snwhitehorn bs_remap_earlyboot(); 1157190681Snwhitehorn 1158190681Snwhitehorn /* 1159190681Snwhitehorn * Set the start and end of kva. 1160190681Snwhitehorn */ 1161190681Snwhitehorn virtual_avail = VM_MIN_KERNEL_ADDRESS; 1162204128Snwhitehorn virtual_end = VM_MAX_SAFE_KERNEL_ADDRESS; 1163190681Snwhitehorn 1164190681Snwhitehorn /* 1165209975Snwhitehorn * Map the entire KVA range into the SLB. We must not fault there. 1166209975Snwhitehorn */ 1167209975Snwhitehorn #ifdef __powerpc64__ 1168209975Snwhitehorn for (va = virtual_avail; va < virtual_end; va += SEGMENT_LENGTH) 1169209975Snwhitehorn moea64_bootstrap_slb_prefault(va, 0); 1170209975Snwhitehorn #endif 1171209975Snwhitehorn 1172209975Snwhitehorn /* 1173204128Snwhitehorn * Figure out how far we can extend virtual_end into segment 16 1174204128Snwhitehorn * without running into existing mappings. Segment 16 is guaranteed 1175204128Snwhitehorn * to contain neither RAM nor devices (at least on Apple hardware), 1176204128Snwhitehorn * but will generally contain some OFW mappings we should not 1177204128Snwhitehorn * step on. 1178190681Snwhitehorn */ 1179190681Snwhitehorn 1180209975Snwhitehorn #ifndef __powerpc64__ /* KVA is in high memory on PPC64 */ 1181204128Snwhitehorn PMAP_LOCK(kernel_pmap); 1182209975Snwhitehorn while (virtual_end < VM_MAX_KERNEL_ADDRESS && 1183209975Snwhitehorn moea64_pvo_find_va(kernel_pmap, virtual_end+1) == NULL) 1184204128Snwhitehorn virtual_end += PAGE_SIZE; 1185204128Snwhitehorn PMAP_UNLOCK(kernel_pmap); 1186209975Snwhitehorn #endif 1187190681Snwhitehorn 1188190681Snwhitehorn /* 1189204694Snwhitehorn * Allocate some things for page zeroing. We put this directly 1190204694Snwhitehorn * in the page table, marked with LPTE_LOCKED, to avoid any 1191204694Snwhitehorn * of the PVO book-keeping or other parts of the VM system 1192204694Snwhitehorn * from even knowing that this hack exists. 1193190681Snwhitehorn */ 1194190681Snwhitehorn 1195209975Snwhitehorn if (!hw_direct_map) { 1196209975Snwhitehorn mtx_init(&moea64_scratchpage_mtx, "pvo zero page", NULL, 1197209975Snwhitehorn MTX_DEF); 1198209975Snwhitehorn for (i = 0; i < 2; i++) { 1199209975Snwhitehorn struct lpte pt; 1200209975Snwhitehorn uint64_t vsid; 1201209975Snwhitehorn int pteidx, ptegidx; 1202204694Snwhitehorn 1203209975Snwhitehorn moea64_scratchpage_va[i] = (virtual_end+1) - PAGE_SIZE; 1204209975Snwhitehorn virtual_end -= PAGE_SIZE; 1205190681Snwhitehorn 1206209975Snwhitehorn LOCK_TABLE(); 1207209975Snwhitehorn 1208209975Snwhitehorn vsid = va_to_vsid(kernel_pmap, 1209209975Snwhitehorn moea64_scratchpage_va[i]); 1210209975Snwhitehorn moea64_pte_create(&pt, vsid, moea64_scratchpage_va[i], 1211209975Snwhitehorn LPTE_NOEXEC, 0); 1212209975Snwhitehorn pt.pte_hi |= LPTE_LOCKED; 1213190681Snwhitehorn 1214209975Snwhitehorn moea64_scratchpage_vpn[i] = (vsid << 16) | 1215209975Snwhitehorn ((moea64_scratchpage_va[i] & ADDR_PIDX) >> 1216209975Snwhitehorn ADDR_PIDX_SHFT); 1217209975Snwhitehorn ptegidx = va_to_pteg(vsid, moea64_scratchpage_va[i], 0); 1218209975Snwhitehorn pteidx = moea64_pte_insert(ptegidx, &pt); 1219209975Snwhitehorn if (pt.pte_hi & LPTE_HID) 1220209975Snwhitehorn ptegidx ^= moea64_pteg_mask; 1221204694Snwhitehorn 1222209975Snwhitehorn moea64_scratchpage_pte[i] = 1223209975Snwhitehorn &moea64_pteg_table[ptegidx].pt[pteidx]; 1224204694Snwhitehorn 1225209975Snwhitehorn UNLOCK_TABLE(); 1226209975Snwhitehorn } 1227190681Snwhitehorn } 1228190681Snwhitehorn 1229190681Snwhitehorn /* 1230190681Snwhitehorn * Allocate a kernel stack with a guard page for thread0 and map it 1231190681Snwhitehorn * into the kernel page map. 1232190681Snwhitehorn */ 1233190681Snwhitehorn pa = moea64_bootstrap_alloc(KSTACK_PAGES * PAGE_SIZE, PAGE_SIZE); 1234190681Snwhitehorn va = virtual_avail + KSTACK_GUARD_PAGES * PAGE_SIZE; 1235190681Snwhitehorn virtual_avail = va + KSTACK_PAGES * PAGE_SIZE; 1236190681Snwhitehorn CTR2(KTR_PMAP, "moea_bootstrap: kstack0 at %#x (%#x)", pa, va); 1237190681Snwhitehorn thread0.td_kstack = va; 1238190681Snwhitehorn thread0.td_kstack_pages = KSTACK_PAGES; 1239190681Snwhitehorn for (i = 0; i < KSTACK_PAGES; i++) { 1240201758Smbr moea64_kenter(mmup, va, pa); 1241190681Snwhitehorn pa += PAGE_SIZE; 1242190681Snwhitehorn va += PAGE_SIZE; 1243190681Snwhitehorn } 1244190681Snwhitehorn 1245190681Snwhitehorn /* 1246190681Snwhitehorn * Allocate virtual address space for the message buffer. 1247190681Snwhitehorn */ 1248190681Snwhitehorn pa = msgbuf_phys = moea64_bootstrap_alloc(MSGBUF_SIZE, PAGE_SIZE); 1249204297Snwhitehorn msgbufp = (struct msgbuf *)virtual_avail; 1250204297Snwhitehorn va = virtual_avail; 1251204297Snwhitehorn virtual_avail += round_page(MSGBUF_SIZE); 1252204297Snwhitehorn while (va < virtual_avail) { 1253204297Snwhitehorn moea64_kenter(mmup, va, pa); 1254190681Snwhitehorn pa += PAGE_SIZE; 1255204297Snwhitehorn va += PAGE_SIZE; 1256190681Snwhitehorn } 1257194784Sjeff 1258194784Sjeff /* 1259194784Sjeff * Allocate virtual address space for the dynamic percpu area. 1260194784Sjeff */ 1261194784Sjeff pa = moea64_bootstrap_alloc(DPCPU_SIZE, PAGE_SIZE); 1262204297Snwhitehorn dpcpu = (void *)virtual_avail; 1263209975Snwhitehorn va = virtual_avail; 1264204297Snwhitehorn virtual_avail += DPCPU_SIZE; 1265204297Snwhitehorn while (va < virtual_avail) { 1266204297Snwhitehorn moea64_kenter(mmup, va, pa); 1267194784Sjeff pa += PAGE_SIZE; 1268204297Snwhitehorn va += PAGE_SIZE; 1269194784Sjeff } 1270194784Sjeff dpcpu_init(dpcpu, 0); 1271190681Snwhitehorn} 1272190681Snwhitehorn 1273190681Snwhitehorn/* 1274209975Snwhitehorn * Activate a user pmap. The pmap must be activated before its address 1275190681Snwhitehorn * space can be accessed in any way. 1276190681Snwhitehorn */ 1277190681Snwhitehornvoid 1278190681Snwhitehornmoea64_activate(mmu_t mmu, struct thread *td) 1279190681Snwhitehorn{ 1280209975Snwhitehorn pmap_t pm; 1281190681Snwhitehorn 1282190681Snwhitehorn pm = &td->td_proc->p_vmspace->vm_pmap; 1283209975Snwhitehorn pm->pm_active |= PCPU_GET(cpumask); 1284190681Snwhitehorn 1285209975Snwhitehorn #ifdef __powerpc64__ 1286209975Snwhitehorn PCPU_SET(userslb, pm->pm_slb); 1287209975Snwhitehorn #else 1288209975Snwhitehorn PCPU_SET(curpmap, pm->pmap_phys); 1289209975Snwhitehorn #endif 1290190681Snwhitehorn} 1291190681Snwhitehorn 1292190681Snwhitehornvoid 1293190681Snwhitehornmoea64_deactivate(mmu_t mmu, struct thread *td) 1294190681Snwhitehorn{ 1295190681Snwhitehorn pmap_t pm; 1296190681Snwhitehorn 1297190681Snwhitehorn pm = &td->td_proc->p_vmspace->vm_pmap; 1298190681Snwhitehorn pm->pm_active &= ~(PCPU_GET(cpumask)); 1299209975Snwhitehorn #ifdef __powerpc64__ 1300209975Snwhitehorn PCPU_SET(userslb, NULL); 1301209975Snwhitehorn #else 1302190681Snwhitehorn PCPU_SET(curpmap, NULL); 1303209975Snwhitehorn #endif 1304190681Snwhitehorn} 1305190681Snwhitehorn 1306190681Snwhitehornvoid 1307190681Snwhitehornmoea64_change_wiring(mmu_t mmu, pmap_t pm, vm_offset_t va, boolean_t wired) 1308190681Snwhitehorn{ 1309190681Snwhitehorn struct pvo_entry *pvo; 1310209975Snwhitehorn struct lpte *pt; 1311209975Snwhitehorn uint64_t vsid; 1312209975Snwhitehorn int i, ptegidx; 1313190681Snwhitehorn 1314190681Snwhitehorn PMAP_LOCK(pm); 1315209975Snwhitehorn pvo = moea64_pvo_find_va(pm, va & ~ADDR_POFF); 1316190681Snwhitehorn 1317190681Snwhitehorn if (pvo != NULL) { 1318209975Snwhitehorn LOCK_TABLE(); 1319209975Snwhitehorn pt = moea64_pvo_to_pte(pvo); 1320209975Snwhitehorn 1321190681Snwhitehorn if (wired) { 1322190681Snwhitehorn if ((pvo->pvo_vaddr & PVO_WIRED) == 0) 1323190681Snwhitehorn pm->pm_stats.wired_count++; 1324190681Snwhitehorn pvo->pvo_vaddr |= PVO_WIRED; 1325209975Snwhitehorn pvo->pvo_pte.lpte.pte_hi |= LPTE_WIRED; 1326190681Snwhitehorn } else { 1327190681Snwhitehorn if ((pvo->pvo_vaddr & PVO_WIRED) != 0) 1328190681Snwhitehorn pm->pm_stats.wired_count--; 1329190681Snwhitehorn pvo->pvo_vaddr &= ~PVO_WIRED; 1330209975Snwhitehorn pvo->pvo_pte.lpte.pte_hi &= ~LPTE_WIRED; 1331190681Snwhitehorn } 1332209975Snwhitehorn 1333209975Snwhitehorn if (pt != NULL) { 1334209975Snwhitehorn /* Update wiring flag in page table. */ 1335209975Snwhitehorn moea64_pte_change(pt, &pvo->pvo_pte.lpte, 1336209975Snwhitehorn pvo->pvo_vpn); 1337209975Snwhitehorn } else if (wired) { 1338209975Snwhitehorn /* 1339209975Snwhitehorn * If we are wiring the page, and it wasn't in the 1340209975Snwhitehorn * page table before, add it. 1341209975Snwhitehorn */ 1342209975Snwhitehorn vsid = PVO_VSID(pvo); 1343209975Snwhitehorn ptegidx = va_to_pteg(vsid, PVO_VADDR(pvo), 1344209975Snwhitehorn pvo->pvo_vaddr & PVO_LARGE); 1345209975Snwhitehorn 1346209975Snwhitehorn i = moea64_pte_insert(ptegidx, &pvo->pvo_pte.lpte); 1347209975Snwhitehorn if (i >= 0) { 1348209975Snwhitehorn PVO_PTEGIDX_CLR(pvo); 1349209975Snwhitehorn PVO_PTEGIDX_SET(pvo, i); 1350209975Snwhitehorn } 1351209975Snwhitehorn } 1352209975Snwhitehorn 1353209975Snwhitehorn UNLOCK_TABLE(); 1354190681Snwhitehorn } 1355190681Snwhitehorn PMAP_UNLOCK(pm); 1356190681Snwhitehorn} 1357190681Snwhitehorn 1358190681Snwhitehorn/* 1359190681Snwhitehorn * This goes through and sets the physical address of our 1360190681Snwhitehorn * special scratch PTE to the PA we want to zero or copy. Because 1361190681Snwhitehorn * of locking issues (this can get called in pvo_enter() by 1362190681Snwhitehorn * the UMA allocator), we can't use most other utility functions here 1363190681Snwhitehorn */ 1364190681Snwhitehorn 1365190681Snwhitehornstatic __inline 1366190681Snwhitehornvoid moea64_set_scratchpage_pa(int which, vm_offset_t pa) { 1367204694Snwhitehorn 1368209975Snwhitehorn KASSERT(!hw_direct_map, ("Using OEA64 scratchpage with a direct map!")); 1369204268Snwhitehorn mtx_assert(&moea64_scratchpage_mtx, MA_OWNED); 1370204268Snwhitehorn 1371190681Snwhitehorn moea64_scratchpage_pte[which]->pte_hi &= ~LPTE_VALID; 1372209975Snwhitehorn TLBIE(moea64_scratchpage_vpn[which]); 1373190681Snwhitehorn 1374204694Snwhitehorn moea64_scratchpage_pte[which]->pte_lo &= 1375204694Snwhitehorn ~(LPTE_WIMG | LPTE_RPGN); 1376204694Snwhitehorn moea64_scratchpage_pte[which]->pte_lo |= 1377213307Snwhitehorn moea64_calc_wimg(pa, VM_MEMATTR_DEFAULT) | (uint64_t)pa; 1378190681Snwhitehorn EIEIO(); 1379190681Snwhitehorn 1380190681Snwhitehorn moea64_scratchpage_pte[which]->pte_hi |= LPTE_VALID; 1381204042Snwhitehorn PTESYNC(); isync(); 1382190681Snwhitehorn} 1383190681Snwhitehorn 1384190681Snwhitehornvoid 1385190681Snwhitehornmoea64_copy_page(mmu_t mmu, vm_page_t msrc, vm_page_t mdst) 1386190681Snwhitehorn{ 1387190681Snwhitehorn vm_offset_t dst; 1388190681Snwhitehorn vm_offset_t src; 1389190681Snwhitehorn 1390190681Snwhitehorn dst = VM_PAGE_TO_PHYS(mdst); 1391190681Snwhitehorn src = VM_PAGE_TO_PHYS(msrc); 1392190681Snwhitehorn 1393209975Snwhitehorn if (hw_direct_map) { 1394209975Snwhitehorn kcopy((void *)src, (void *)dst, PAGE_SIZE); 1395209975Snwhitehorn } else { 1396209975Snwhitehorn mtx_lock(&moea64_scratchpage_mtx); 1397190681Snwhitehorn 1398209975Snwhitehorn moea64_set_scratchpage_pa(0,src); 1399209975Snwhitehorn moea64_set_scratchpage_pa(1,dst); 1400190681Snwhitehorn 1401209975Snwhitehorn kcopy((void *)moea64_scratchpage_va[0], 1402209975Snwhitehorn (void *)moea64_scratchpage_va[1], PAGE_SIZE); 1403190681Snwhitehorn 1404209975Snwhitehorn mtx_unlock(&moea64_scratchpage_mtx); 1405209975Snwhitehorn } 1406190681Snwhitehorn} 1407190681Snwhitehorn 1408190681Snwhitehornvoid 1409190681Snwhitehornmoea64_zero_page_area(mmu_t mmu, vm_page_t m, int off, int size) 1410190681Snwhitehorn{ 1411190681Snwhitehorn vm_offset_t pa = VM_PAGE_TO_PHYS(m); 1412190681Snwhitehorn 1413190681Snwhitehorn if (!moea64_initialized) 1414209975Snwhitehorn panic("moea64_zero_page: can't zero pa %#" PRIxPTR, pa); 1415190681Snwhitehorn if (size + off > PAGE_SIZE) 1416190681Snwhitehorn panic("moea64_zero_page: size + off > PAGE_SIZE"); 1417190681Snwhitehorn 1418209975Snwhitehorn if (hw_direct_map) { 1419209975Snwhitehorn bzero((caddr_t)pa + off, size); 1420209975Snwhitehorn } else { 1421209975Snwhitehorn mtx_lock(&moea64_scratchpage_mtx); 1422209975Snwhitehorn moea64_set_scratchpage_pa(0,pa); 1423209975Snwhitehorn bzero((caddr_t)moea64_scratchpage_va[0] + off, size); 1424209975Snwhitehorn mtx_unlock(&moea64_scratchpage_mtx); 1425209975Snwhitehorn } 1426190681Snwhitehorn} 1427190681Snwhitehorn 1428204269Snwhitehorn/* 1429204269Snwhitehorn * Zero a page of physical memory by temporarily mapping it 1430204269Snwhitehorn */ 1431190681Snwhitehornvoid 1432204269Snwhitehornmoea64_zero_page(mmu_t mmu, vm_page_t m) 1433204269Snwhitehorn{ 1434204269Snwhitehorn vm_offset_t pa = VM_PAGE_TO_PHYS(m); 1435209975Snwhitehorn vm_offset_t va, off; 1436204269Snwhitehorn 1437204269Snwhitehorn if (!moea64_initialized) 1438209975Snwhitehorn panic("moea64_zero_page: can't zero pa %#zx", pa); 1439204269Snwhitehorn 1440209975Snwhitehorn if (!hw_direct_map) { 1441209975Snwhitehorn mtx_lock(&moea64_scratchpage_mtx); 1442204269Snwhitehorn 1443209975Snwhitehorn moea64_set_scratchpage_pa(0,pa); 1444209975Snwhitehorn va = moea64_scratchpage_va[0]; 1445209975Snwhitehorn } else { 1446209975Snwhitehorn va = pa; 1447209975Snwhitehorn } 1448209975Snwhitehorn 1449204269Snwhitehorn for (off = 0; off < PAGE_SIZE; off += cacheline_size) 1450209975Snwhitehorn __asm __volatile("dcbz 0,%0" :: "r"(va + off)); 1451209975Snwhitehorn 1452209975Snwhitehorn if (!hw_direct_map) 1453209975Snwhitehorn mtx_unlock(&moea64_scratchpage_mtx); 1454204269Snwhitehorn} 1455204269Snwhitehorn 1456204269Snwhitehornvoid 1457190681Snwhitehornmoea64_zero_page_idle(mmu_t mmu, vm_page_t m) 1458190681Snwhitehorn{ 1459190681Snwhitehorn 1460190681Snwhitehorn moea64_zero_page(mmu, m); 1461190681Snwhitehorn} 1462190681Snwhitehorn 1463190681Snwhitehorn/* 1464190681Snwhitehorn * Map the given physical page at the specified virtual address in the 1465190681Snwhitehorn * target pmap with the protection requested. If specified the page 1466190681Snwhitehorn * will be wired down. 1467190681Snwhitehorn */ 1468190681Snwhitehornvoid 1469190681Snwhitehornmoea64_enter(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, 1470190681Snwhitehorn vm_prot_t prot, boolean_t wired) 1471190681Snwhitehorn{ 1472190681Snwhitehorn 1473190681Snwhitehorn vm_page_lock_queues(); 1474190681Snwhitehorn PMAP_LOCK(pmap); 1475190681Snwhitehorn moea64_enter_locked(pmap, va, m, prot, wired); 1476190681Snwhitehorn vm_page_unlock_queues(); 1477190681Snwhitehorn PMAP_UNLOCK(pmap); 1478190681Snwhitehorn} 1479190681Snwhitehorn 1480190681Snwhitehorn/* 1481190681Snwhitehorn * Map the given physical page at the specified virtual address in the 1482190681Snwhitehorn * target pmap with the protection requested. If specified the page 1483190681Snwhitehorn * will be wired down. 1484190681Snwhitehorn * 1485190681Snwhitehorn * The page queues and pmap must be locked. 1486190681Snwhitehorn */ 1487190681Snwhitehorn 1488190681Snwhitehornstatic void 1489190681Snwhitehornmoea64_enter_locked(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot, 1490190681Snwhitehorn boolean_t wired) 1491190681Snwhitehorn{ 1492190681Snwhitehorn struct pvo_head *pvo_head; 1493190681Snwhitehorn uma_zone_t zone; 1494190681Snwhitehorn vm_page_t pg; 1495190681Snwhitehorn uint64_t pte_lo; 1496190681Snwhitehorn u_int pvo_flags; 1497190681Snwhitehorn int error; 1498190681Snwhitehorn 1499190681Snwhitehorn if (!moea64_initialized) { 1500190681Snwhitehorn pvo_head = &moea64_pvo_kunmanaged; 1501190681Snwhitehorn pg = NULL; 1502190681Snwhitehorn zone = moea64_upvo_zone; 1503190681Snwhitehorn pvo_flags = 0; 1504190681Snwhitehorn } else { 1505190681Snwhitehorn pvo_head = vm_page_to_pvoh(m); 1506190681Snwhitehorn pg = m; 1507190681Snwhitehorn zone = moea64_mpvo_zone; 1508190681Snwhitehorn pvo_flags = PVO_MANAGED; 1509190681Snwhitehorn } 1510190681Snwhitehorn 1511190681Snwhitehorn if (pmap_bootstrapped) 1512190681Snwhitehorn mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1513190681Snwhitehorn PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1514209048Salc KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0 || 1515209048Salc (m->oflags & VPO_BUSY) != 0 || VM_OBJECT_LOCKED(m->object), 1516208175Salc ("moea64_enter_locked: page %p is not busy", m)); 1517190681Snwhitehorn 1518190681Snwhitehorn /* XXX change the pvo head for fake pages */ 1519190681Snwhitehorn if ((m->flags & PG_FICTITIOUS) == PG_FICTITIOUS) { 1520190681Snwhitehorn pvo_flags &= ~PVO_MANAGED; 1521190681Snwhitehorn pvo_head = &moea64_pvo_kunmanaged; 1522190681Snwhitehorn zone = moea64_upvo_zone; 1523190681Snwhitehorn } 1524190681Snwhitehorn 1525213307Snwhitehorn pte_lo = moea64_calc_wimg(VM_PAGE_TO_PHYS(m), pmap_page_get_memattr(m)); 1526190681Snwhitehorn 1527190681Snwhitehorn if (prot & VM_PROT_WRITE) { 1528190681Snwhitehorn pte_lo |= LPTE_BW; 1529208810Salc if (pmap_bootstrapped && 1530208810Salc (m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0) 1531190681Snwhitehorn vm_page_flag_set(m, PG_WRITEABLE); 1532190681Snwhitehorn } else 1533190681Snwhitehorn pte_lo |= LPTE_BR; 1534190681Snwhitehorn 1535190681Snwhitehorn if (prot & VM_PROT_EXECUTE) 1536190681Snwhitehorn pvo_flags |= VM_PROT_EXECUTE; 1537190681Snwhitehorn 1538190681Snwhitehorn if (wired) 1539190681Snwhitehorn pvo_flags |= PVO_WIRED; 1540190681Snwhitehorn 1541190681Snwhitehorn if ((m->flags & PG_FICTITIOUS) != 0) 1542190681Snwhitehorn pvo_flags |= PVO_FAKE; 1543190681Snwhitehorn 1544190681Snwhitehorn error = moea64_pvo_enter(pmap, zone, pvo_head, va, VM_PAGE_TO_PHYS(m), 1545198378Snwhitehorn pte_lo, pvo_flags); 1546190681Snwhitehorn 1547190681Snwhitehorn /* 1548190681Snwhitehorn * Flush the page from the instruction cache if this page is 1549190681Snwhitehorn * mapped executable and cacheable. 1550190681Snwhitehorn */ 1551190681Snwhitehorn if ((pte_lo & (LPTE_I | LPTE_G | LPTE_NOEXEC)) == 0) { 1552198341Smarcel moea64_syncicache(pmap, va, VM_PAGE_TO_PHYS(m), PAGE_SIZE); 1553190681Snwhitehorn } 1554190681Snwhitehorn} 1555190681Snwhitehorn 1556190681Snwhitehornstatic void 1557198341Smarcelmoea64_syncicache(pmap_t pmap, vm_offset_t va, vm_offset_t pa, vm_size_t sz) 1558190681Snwhitehorn{ 1559204042Snwhitehorn 1560190681Snwhitehorn /* 1561190681Snwhitehorn * This is much trickier than on older systems because 1562190681Snwhitehorn * we can't sync the icache on physical addresses directly 1563190681Snwhitehorn * without a direct map. Instead we check a couple of cases 1564190681Snwhitehorn * where the memory is already mapped in and, failing that, 1565190681Snwhitehorn * use the same trick we use for page zeroing to create 1566190681Snwhitehorn * a temporary mapping for this physical address. 1567190681Snwhitehorn */ 1568190681Snwhitehorn 1569190681Snwhitehorn if (!pmap_bootstrapped) { 1570190681Snwhitehorn /* 1571190681Snwhitehorn * If PMAP is not bootstrapped, we are likely to be 1572190681Snwhitehorn * in real mode. 1573190681Snwhitehorn */ 1574198341Smarcel __syncicache((void *)pa, sz); 1575190681Snwhitehorn } else if (pmap == kernel_pmap) { 1576198341Smarcel __syncicache((void *)va, sz); 1577209975Snwhitehorn } else if (hw_direct_map) { 1578209975Snwhitehorn __syncicache((void *)pa, sz); 1579190681Snwhitehorn } else { 1580190681Snwhitehorn /* Use the scratch page to set up a temp mapping */ 1581190681Snwhitehorn 1582190681Snwhitehorn mtx_lock(&moea64_scratchpage_mtx); 1583190681Snwhitehorn 1584204042Snwhitehorn moea64_set_scratchpage_pa(1,pa & ~ADDR_POFF); 1585204042Snwhitehorn __syncicache((void *)(moea64_scratchpage_va[1] + 1586204042Snwhitehorn (va & ADDR_POFF)), sz); 1587190681Snwhitehorn 1588190681Snwhitehorn mtx_unlock(&moea64_scratchpage_mtx); 1589190681Snwhitehorn } 1590190681Snwhitehorn} 1591190681Snwhitehorn 1592190681Snwhitehorn/* 1593190681Snwhitehorn * Maps a sequence of resident pages belonging to the same object. 1594190681Snwhitehorn * The sequence begins with the given page m_start. This page is 1595190681Snwhitehorn * mapped at the given virtual address start. Each subsequent page is 1596190681Snwhitehorn * mapped at a virtual address that is offset from start by the same 1597190681Snwhitehorn * amount as the page is offset from m_start within the object. The 1598190681Snwhitehorn * last page in the sequence is the page with the largest offset from 1599190681Snwhitehorn * m_start that can be mapped at a virtual address less than the given 1600190681Snwhitehorn * virtual address end. Not every virtual page between start and end 1601190681Snwhitehorn * is mapped; only those for which a resident page exists with the 1602190681Snwhitehorn * corresponding offset from m_start are mapped. 1603190681Snwhitehorn */ 1604190681Snwhitehornvoid 1605190681Snwhitehornmoea64_enter_object(mmu_t mmu, pmap_t pm, vm_offset_t start, vm_offset_t end, 1606190681Snwhitehorn vm_page_t m_start, vm_prot_t prot) 1607190681Snwhitehorn{ 1608190681Snwhitehorn vm_page_t m; 1609190681Snwhitehorn vm_pindex_t diff, psize; 1610190681Snwhitehorn 1611190681Snwhitehorn psize = atop(end - start); 1612190681Snwhitehorn m = m_start; 1613208574Salc vm_page_lock_queues(); 1614190681Snwhitehorn PMAP_LOCK(pm); 1615190681Snwhitehorn while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 1616190681Snwhitehorn moea64_enter_locked(pm, start + ptoa(diff), m, prot & 1617190681Snwhitehorn (VM_PROT_READ | VM_PROT_EXECUTE), FALSE); 1618190681Snwhitehorn m = TAILQ_NEXT(m, listq); 1619190681Snwhitehorn } 1620208574Salc vm_page_unlock_queues(); 1621190681Snwhitehorn PMAP_UNLOCK(pm); 1622190681Snwhitehorn} 1623190681Snwhitehorn 1624190681Snwhitehornvoid 1625190681Snwhitehornmoea64_enter_quick(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_page_t m, 1626190681Snwhitehorn vm_prot_t prot) 1627190681Snwhitehorn{ 1628207796Salc 1629207796Salc vm_page_lock_queues(); 1630190681Snwhitehorn PMAP_LOCK(pm); 1631190681Snwhitehorn moea64_enter_locked(pm, va, m, prot & (VM_PROT_READ | VM_PROT_EXECUTE), 1632190681Snwhitehorn FALSE); 1633207796Salc vm_page_unlock_queues(); 1634190681Snwhitehorn PMAP_UNLOCK(pm); 1635190681Snwhitehorn} 1636190681Snwhitehorn 1637190681Snwhitehornvm_paddr_t 1638190681Snwhitehornmoea64_extract(mmu_t mmu, pmap_t pm, vm_offset_t va) 1639190681Snwhitehorn{ 1640190681Snwhitehorn struct pvo_entry *pvo; 1641190681Snwhitehorn vm_paddr_t pa; 1642190681Snwhitehorn 1643190681Snwhitehorn PMAP_LOCK(pm); 1644209975Snwhitehorn pvo = moea64_pvo_find_va(pm, va); 1645190681Snwhitehorn if (pvo == NULL) 1646190681Snwhitehorn pa = 0; 1647190681Snwhitehorn else 1648209975Snwhitehorn pa = (pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN) | 1649209975Snwhitehorn (va - PVO_VADDR(pvo)); 1650190681Snwhitehorn PMAP_UNLOCK(pm); 1651190681Snwhitehorn return (pa); 1652190681Snwhitehorn} 1653190681Snwhitehorn 1654190681Snwhitehorn/* 1655190681Snwhitehorn * Atomically extract and hold the physical page with the given 1656190681Snwhitehorn * pmap and virtual address pair if that mapping permits the given 1657190681Snwhitehorn * protection. 1658190681Snwhitehorn */ 1659190681Snwhitehornvm_page_t 1660190681Snwhitehornmoea64_extract_and_hold(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_prot_t prot) 1661190681Snwhitehorn{ 1662190681Snwhitehorn struct pvo_entry *pvo; 1663190681Snwhitehorn vm_page_t m; 1664207410Skmacy vm_paddr_t pa; 1665190681Snwhitehorn 1666190681Snwhitehorn m = NULL; 1667207410Skmacy pa = 0; 1668190681Snwhitehorn PMAP_LOCK(pmap); 1669207410Skmacyretry: 1670209975Snwhitehorn pvo = moea64_pvo_find_va(pmap, va & ~ADDR_POFF); 1671190681Snwhitehorn if (pvo != NULL && (pvo->pvo_pte.lpte.pte_hi & LPTE_VALID) && 1672190681Snwhitehorn ((pvo->pvo_pte.lpte.pte_lo & LPTE_PP) == LPTE_RW || 1673190681Snwhitehorn (prot & VM_PROT_WRITE) == 0)) { 1674207410Skmacy if (vm_page_pa_tryrelock(pmap, 1675207410Skmacy pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN, &pa)) 1676207410Skmacy goto retry; 1677190681Snwhitehorn m = PHYS_TO_VM_PAGE(pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN); 1678190681Snwhitehorn vm_page_hold(m); 1679190681Snwhitehorn } 1680207410Skmacy PA_UNLOCK_COND(pa); 1681190681Snwhitehorn PMAP_UNLOCK(pmap); 1682190681Snwhitehorn return (m); 1683190681Snwhitehorn} 1684190681Snwhitehorn 1685190681Snwhitehornstatic void * 1686190681Snwhitehornmoea64_uma_page_alloc(uma_zone_t zone, int bytes, u_int8_t *flags, int wait) 1687190681Snwhitehorn{ 1688190681Snwhitehorn /* 1689190681Snwhitehorn * This entire routine is a horrible hack to avoid bothering kmem 1690190681Snwhitehorn * for new KVA addresses. Because this can get called from inside 1691190681Snwhitehorn * kmem allocation routines, calling kmem for a new address here 1692190681Snwhitehorn * can lead to multiply locking non-recursive mutexes. 1693190681Snwhitehorn */ 1694190681Snwhitehorn static vm_pindex_t color; 1695190681Snwhitehorn vm_offset_t va; 1696190681Snwhitehorn 1697190681Snwhitehorn vm_page_t m; 1698190681Snwhitehorn int pflags, needed_lock; 1699190681Snwhitehorn 1700190681Snwhitehorn *flags = UMA_SLAB_PRIV; 1701190681Snwhitehorn needed_lock = !PMAP_LOCKED(kernel_pmap); 1702190681Snwhitehorn 1703190681Snwhitehorn if (needed_lock) 1704190681Snwhitehorn PMAP_LOCK(kernel_pmap); 1705190681Snwhitehorn 1706190681Snwhitehorn if ((wait & (M_NOWAIT|M_USE_RESERVE)) == M_NOWAIT) 1707190681Snwhitehorn pflags = VM_ALLOC_INTERRUPT | VM_ALLOC_WIRED; 1708190681Snwhitehorn else 1709190681Snwhitehorn pflags = VM_ALLOC_SYSTEM | VM_ALLOC_WIRED; 1710190681Snwhitehorn if (wait & M_ZERO) 1711190681Snwhitehorn pflags |= VM_ALLOC_ZERO; 1712190681Snwhitehorn 1713190681Snwhitehorn for (;;) { 1714190681Snwhitehorn m = vm_page_alloc(NULL, color++, pflags | VM_ALLOC_NOOBJ); 1715190681Snwhitehorn if (m == NULL) { 1716190681Snwhitehorn if (wait & M_NOWAIT) 1717190681Snwhitehorn return (NULL); 1718190681Snwhitehorn VM_WAIT; 1719190681Snwhitehorn } else 1720190681Snwhitehorn break; 1721190681Snwhitehorn } 1722190681Snwhitehorn 1723204128Snwhitehorn va = VM_PAGE_TO_PHYS(m); 1724190681Snwhitehorn 1725190681Snwhitehorn moea64_pvo_enter(kernel_pmap, moea64_upvo_zone, 1726204128Snwhitehorn &moea64_pvo_kunmanaged, va, VM_PAGE_TO_PHYS(m), LPTE_M, 1727198378Snwhitehorn PVO_WIRED | PVO_BOOTSTRAP); 1728190681Snwhitehorn 1729190681Snwhitehorn if (needed_lock) 1730190681Snwhitehorn PMAP_UNLOCK(kernel_pmap); 1731198378Snwhitehorn 1732190681Snwhitehorn if ((wait & M_ZERO) && (m->flags & PG_ZERO) == 0) 1733190681Snwhitehorn bzero((void *)va, PAGE_SIZE); 1734190681Snwhitehorn 1735190681Snwhitehorn return (void *)va; 1736190681Snwhitehorn} 1737190681Snwhitehorn 1738190681Snwhitehornvoid 1739190681Snwhitehornmoea64_init(mmu_t mmu) 1740190681Snwhitehorn{ 1741190681Snwhitehorn 1742190681Snwhitehorn CTR0(KTR_PMAP, "moea64_init"); 1743190681Snwhitehorn 1744190681Snwhitehorn moea64_upvo_zone = uma_zcreate("UPVO entry", sizeof (struct pvo_entry), 1745190681Snwhitehorn NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, 1746190681Snwhitehorn UMA_ZONE_VM | UMA_ZONE_NOFREE); 1747190681Snwhitehorn moea64_mpvo_zone = uma_zcreate("MPVO entry", sizeof(struct pvo_entry), 1748190681Snwhitehorn NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, 1749190681Snwhitehorn UMA_ZONE_VM | UMA_ZONE_NOFREE); 1750190681Snwhitehorn 1751190681Snwhitehorn if (!hw_direct_map) { 1752190681Snwhitehorn uma_zone_set_allocf(moea64_upvo_zone,moea64_uma_page_alloc); 1753190681Snwhitehorn uma_zone_set_allocf(moea64_mpvo_zone,moea64_uma_page_alloc); 1754190681Snwhitehorn } 1755190681Snwhitehorn 1756190681Snwhitehorn moea64_initialized = TRUE; 1757190681Snwhitehorn} 1758190681Snwhitehorn 1759190681Snwhitehornboolean_t 1760207155Salcmoea64_is_referenced(mmu_t mmu, vm_page_t m) 1761207155Salc{ 1762207155Salc 1763208574Salc KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 1764208574Salc ("moea64_is_referenced: page %p is not managed", m)); 1765207155Salc return (moea64_query_bit(m, PTE_REF)); 1766207155Salc} 1767207155Salc 1768207155Salcboolean_t 1769190681Snwhitehornmoea64_is_modified(mmu_t mmu, vm_page_t m) 1770190681Snwhitehorn{ 1771190681Snwhitehorn 1772208504Salc KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 1773208504Salc ("moea64_is_modified: page %p is not managed", m)); 1774208504Salc 1775208504Salc /* 1776208504Salc * If the page is not VPO_BUSY, then PG_WRITEABLE cannot be 1777208504Salc * concurrently set while the object is locked. Thus, if PG_WRITEABLE 1778208504Salc * is clear, no PTEs can have LPTE_CHG set. 1779208504Salc */ 1780208504Salc VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED); 1781208504Salc if ((m->oflags & VPO_BUSY) == 0 && 1782208504Salc (m->flags & PG_WRITEABLE) == 0) 1783190681Snwhitehorn return (FALSE); 1784208574Salc return (moea64_query_bit(m, LPTE_CHG)); 1785190681Snwhitehorn} 1786190681Snwhitehorn 1787214617Salcboolean_t 1788214617Salcmoea64_is_prefaultable(mmu_t mmu, pmap_t pmap, vm_offset_t va) 1789214617Salc{ 1790214617Salc struct pvo_entry *pvo; 1791214617Salc boolean_t rv; 1792214617Salc 1793214617Salc PMAP_LOCK(pmap); 1794214617Salc pvo = moea64_pvo_find_va(pmap, va & ~ADDR_POFF); 1795214617Salc rv = pvo == NULL || (pvo->pvo_pte.lpte.pte_hi & LPTE_VALID) == 0; 1796214617Salc PMAP_UNLOCK(pmap); 1797214617Salc return (rv); 1798214617Salc} 1799214617Salc 1800190681Snwhitehornvoid 1801190681Snwhitehornmoea64_clear_reference(mmu_t mmu, vm_page_t m) 1802190681Snwhitehorn{ 1803190681Snwhitehorn 1804208504Salc KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 1805208504Salc ("moea64_clear_reference: page %p is not managed", m)); 1806208990Salc moea64_clear_bit(m, LPTE_REF); 1807190681Snwhitehorn} 1808190681Snwhitehorn 1809190681Snwhitehornvoid 1810190681Snwhitehornmoea64_clear_modify(mmu_t mmu, vm_page_t m) 1811190681Snwhitehorn{ 1812190681Snwhitehorn 1813208504Salc KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 1814208504Salc ("moea64_clear_modify: page %p is not managed", m)); 1815208504Salc VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED); 1816208504Salc KASSERT((m->oflags & VPO_BUSY) == 0, 1817208504Salc ("moea64_clear_modify: page %p is busy", m)); 1818208504Salc 1819208504Salc /* 1820208504Salc * If the page is not PG_WRITEABLE, then no PTEs can have LPTE_CHG 1821208504Salc * set. If the object containing the page is locked and the page is 1822208504Salc * not VPO_BUSY, then PG_WRITEABLE cannot be concurrently set. 1823208504Salc */ 1824208504Salc if ((m->flags & PG_WRITEABLE) == 0) 1825190681Snwhitehorn return; 1826208990Salc moea64_clear_bit(m, LPTE_CHG); 1827190681Snwhitehorn} 1828190681Snwhitehorn 1829190681Snwhitehorn/* 1830190681Snwhitehorn * Clear the write and modified bits in each of the given page's mappings. 1831190681Snwhitehorn */ 1832190681Snwhitehornvoid 1833190681Snwhitehornmoea64_remove_write(mmu_t mmu, vm_page_t m) 1834190681Snwhitehorn{ 1835190681Snwhitehorn struct pvo_entry *pvo; 1836190681Snwhitehorn struct lpte *pt; 1837190681Snwhitehorn pmap_t pmap; 1838190681Snwhitehorn uint64_t lo; 1839190681Snwhitehorn 1840208175Salc KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 1841208175Salc ("moea64_remove_write: page %p is not managed", m)); 1842208175Salc 1843208175Salc /* 1844208175Salc * If the page is not VPO_BUSY, then PG_WRITEABLE cannot be set by 1845208175Salc * another thread while the object is locked. Thus, if PG_WRITEABLE 1846208175Salc * is clear, no page table entries need updating. 1847208175Salc */ 1848208175Salc VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED); 1849208175Salc if ((m->oflags & VPO_BUSY) == 0 && 1850190681Snwhitehorn (m->flags & PG_WRITEABLE) == 0) 1851190681Snwhitehorn return; 1852207796Salc vm_page_lock_queues(); 1853190681Snwhitehorn lo = moea64_attr_fetch(m); 1854190681Snwhitehorn SYNC(); 1855190681Snwhitehorn LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1856190681Snwhitehorn pmap = pvo->pvo_pmap; 1857190681Snwhitehorn PMAP_LOCK(pmap); 1858205370Snwhitehorn LOCK_TABLE(); 1859190681Snwhitehorn if ((pvo->pvo_pte.lpte.pte_lo & LPTE_PP) != LPTE_BR) { 1860209975Snwhitehorn pt = moea64_pvo_to_pte(pvo); 1861190681Snwhitehorn pvo->pvo_pte.lpte.pte_lo &= ~LPTE_PP; 1862190681Snwhitehorn pvo->pvo_pte.lpte.pte_lo |= LPTE_BR; 1863190681Snwhitehorn if (pt != NULL) { 1864190681Snwhitehorn moea64_pte_synch(pt, &pvo->pvo_pte.lpte); 1865190681Snwhitehorn lo |= pvo->pvo_pte.lpte.pte_lo; 1866190681Snwhitehorn pvo->pvo_pte.lpte.pte_lo &= ~LPTE_CHG; 1867190681Snwhitehorn moea64_pte_change(pt, &pvo->pvo_pte.lpte, 1868209975Snwhitehorn pvo->pvo_vpn); 1869209975Snwhitehorn if (pvo->pvo_pmap == kernel_pmap) 1870209975Snwhitehorn isync(); 1871190681Snwhitehorn } 1872190681Snwhitehorn } 1873205370Snwhitehorn UNLOCK_TABLE(); 1874190681Snwhitehorn PMAP_UNLOCK(pmap); 1875190681Snwhitehorn } 1876190681Snwhitehorn if ((lo & LPTE_CHG) != 0) { 1877190681Snwhitehorn moea64_attr_clear(m, LPTE_CHG); 1878190681Snwhitehorn vm_page_dirty(m); 1879190681Snwhitehorn } 1880190681Snwhitehorn vm_page_flag_clear(m, PG_WRITEABLE); 1881207796Salc vm_page_unlock_queues(); 1882190681Snwhitehorn} 1883190681Snwhitehorn 1884190681Snwhitehorn/* 1885190681Snwhitehorn * moea64_ts_referenced: 1886190681Snwhitehorn * 1887190681Snwhitehorn * Return a count of reference bits for a page, clearing those bits. 1888190681Snwhitehorn * It is not necessary for every reference bit to be cleared, but it 1889190681Snwhitehorn * is necessary that 0 only be returned when there are truly no 1890190681Snwhitehorn * reference bits set. 1891190681Snwhitehorn * 1892190681Snwhitehorn * XXX: The exact number of bits to check and clear is a matter that 1893190681Snwhitehorn * should be tested and standardized at some point in the future for 1894190681Snwhitehorn * optimal aging of shared pages. 1895190681Snwhitehorn */ 1896190681Snwhitehornboolean_t 1897190681Snwhitehornmoea64_ts_referenced(mmu_t mmu, vm_page_t m) 1898190681Snwhitehorn{ 1899190681Snwhitehorn 1900208990Salc KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 1901208990Salc ("moea64_ts_referenced: page %p is not managed", m)); 1902208990Salc return (moea64_clear_bit(m, LPTE_REF)); 1903190681Snwhitehorn} 1904190681Snwhitehorn 1905190681Snwhitehorn/* 1906213307Snwhitehorn * Modify the WIMG settings of all mappings for a page. 1907213307Snwhitehorn */ 1908213307Snwhitehornvoid 1909213307Snwhitehornmoea64_page_set_memattr(mmu_t mmu, vm_page_t m, vm_memattr_t ma) 1910213307Snwhitehorn{ 1911213307Snwhitehorn struct pvo_entry *pvo; 1912213335Snwhitehorn struct pvo_head *pvo_head; 1913213307Snwhitehorn struct lpte *pt; 1914213307Snwhitehorn pmap_t pmap; 1915213307Snwhitehorn uint64_t lo; 1916213307Snwhitehorn 1917213335Snwhitehorn if (m->flags & PG_FICTITIOUS) { 1918213335Snwhitehorn m->md.mdpg_cache_attrs = ma; 1919213335Snwhitehorn return; 1920213335Snwhitehorn } 1921213335Snwhitehorn 1922213307Snwhitehorn vm_page_lock_queues(); 1923213335Snwhitehorn pvo_head = vm_page_to_pvoh(m); 1924213307Snwhitehorn lo = moea64_calc_wimg(VM_PAGE_TO_PHYS(m), ma); 1925213335Snwhitehorn LIST_FOREACH(pvo, pvo_head, pvo_vlink) { 1926213307Snwhitehorn pmap = pvo->pvo_pmap; 1927213307Snwhitehorn PMAP_LOCK(pmap); 1928213307Snwhitehorn LOCK_TABLE(); 1929213307Snwhitehorn pt = moea64_pvo_to_pte(pvo); 1930213307Snwhitehorn pvo->pvo_pte.lpte.pte_lo &= ~LPTE_WIMG; 1931213307Snwhitehorn pvo->pvo_pte.lpte.pte_lo |= lo; 1932213307Snwhitehorn if (pt != NULL) { 1933213307Snwhitehorn moea64_pte_change(pt, &pvo->pvo_pte.lpte, 1934213307Snwhitehorn pvo->pvo_vpn); 1935213307Snwhitehorn if (pvo->pvo_pmap == kernel_pmap) 1936213307Snwhitehorn isync(); 1937213307Snwhitehorn } 1938213307Snwhitehorn UNLOCK_TABLE(); 1939213307Snwhitehorn PMAP_UNLOCK(pmap); 1940213307Snwhitehorn } 1941213307Snwhitehorn m->md.mdpg_cache_attrs = ma; 1942213307Snwhitehorn vm_page_unlock_queues(); 1943213307Snwhitehorn} 1944213307Snwhitehorn 1945213307Snwhitehorn/* 1946190681Snwhitehorn * Map a wired page into kernel virtual address space. 1947190681Snwhitehorn */ 1948190681Snwhitehornvoid 1949213307Snwhitehornmoea64_kenter_attr(mmu_t mmu, vm_offset_t va, vm_offset_t pa, vm_memattr_t ma) 1950190681Snwhitehorn{ 1951190681Snwhitehorn uint64_t pte_lo; 1952190681Snwhitehorn int error; 1953190681Snwhitehorn 1954213307Snwhitehorn pte_lo = moea64_calc_wimg(pa, ma); 1955190681Snwhitehorn 1956190681Snwhitehorn PMAP_LOCK(kernel_pmap); 1957190681Snwhitehorn error = moea64_pvo_enter(kernel_pmap, moea64_upvo_zone, 1958190681Snwhitehorn &moea64_pvo_kunmanaged, va, pa, pte_lo, 1959198378Snwhitehorn PVO_WIRED | VM_PROT_EXECUTE); 1960190681Snwhitehorn 1961190681Snwhitehorn if (error != 0 && error != ENOENT) 1962209975Snwhitehorn panic("moea64_kenter: failed to enter va %#zx pa %#zx: %d", va, 1963190681Snwhitehorn pa, error); 1964190681Snwhitehorn 1965190681Snwhitehorn /* 1966190681Snwhitehorn * Flush the memory from the instruction cache. 1967190681Snwhitehorn */ 1968190681Snwhitehorn if ((pte_lo & (LPTE_I | LPTE_G)) == 0) { 1969190681Snwhitehorn __syncicache((void *)va, PAGE_SIZE); 1970190681Snwhitehorn } 1971190681Snwhitehorn PMAP_UNLOCK(kernel_pmap); 1972190681Snwhitehorn} 1973190681Snwhitehorn 1974213307Snwhitehornvoid 1975213307Snwhitehornmoea64_kenter(mmu_t mmu, vm_offset_t va, vm_offset_t pa) 1976213307Snwhitehorn{ 1977213307Snwhitehorn 1978213307Snwhitehorn moea64_kenter_attr(mmu, va, pa, VM_MEMATTR_DEFAULT); 1979213307Snwhitehorn} 1980213307Snwhitehorn 1981190681Snwhitehorn/* 1982190681Snwhitehorn * Extract the physical page address associated with the given kernel virtual 1983190681Snwhitehorn * address. 1984190681Snwhitehorn */ 1985190681Snwhitehornvm_offset_t 1986190681Snwhitehornmoea64_kextract(mmu_t mmu, vm_offset_t va) 1987190681Snwhitehorn{ 1988190681Snwhitehorn struct pvo_entry *pvo; 1989190681Snwhitehorn vm_paddr_t pa; 1990190681Snwhitehorn 1991205370Snwhitehorn /* 1992205370Snwhitehorn * Shortcut the direct-mapped case when applicable. We never put 1993205370Snwhitehorn * anything but 1:1 mappings below VM_MIN_KERNEL_ADDRESS. 1994205370Snwhitehorn */ 1995205370Snwhitehorn if (va < VM_MIN_KERNEL_ADDRESS) 1996205370Snwhitehorn return (va); 1997205370Snwhitehorn 1998190681Snwhitehorn PMAP_LOCK(kernel_pmap); 1999209975Snwhitehorn pvo = moea64_pvo_find_va(kernel_pmap, va); 2000209975Snwhitehorn KASSERT(pvo != NULL, ("moea64_kextract: no addr found for %#" PRIxPTR, 2001209975Snwhitehorn va)); 2002209975Snwhitehorn pa = (pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN) + (va - PVO_VADDR(pvo)); 2003190681Snwhitehorn PMAP_UNLOCK(kernel_pmap); 2004190681Snwhitehorn return (pa); 2005190681Snwhitehorn} 2006190681Snwhitehorn 2007190681Snwhitehorn/* 2008190681Snwhitehorn * Remove a wired page from kernel virtual address space. 2009190681Snwhitehorn */ 2010190681Snwhitehornvoid 2011190681Snwhitehornmoea64_kremove(mmu_t mmu, vm_offset_t va) 2012190681Snwhitehorn{ 2013190681Snwhitehorn moea64_remove(mmu, kernel_pmap, va, va + PAGE_SIZE); 2014190681Snwhitehorn} 2015190681Snwhitehorn 2016190681Snwhitehorn/* 2017190681Snwhitehorn * Map a range of physical addresses into kernel virtual address space. 2018190681Snwhitehorn * 2019190681Snwhitehorn * The value passed in *virt is a suggested virtual address for the mapping. 2020190681Snwhitehorn * Architectures which can support a direct-mapped physical to virtual region 2021190681Snwhitehorn * can return the appropriate address within that region, leaving '*virt' 2022190681Snwhitehorn * unchanged. We cannot and therefore do not; *virt is updated with the 2023190681Snwhitehorn * first usable address after the mapped region. 2024190681Snwhitehorn */ 2025190681Snwhitehornvm_offset_t 2026190681Snwhitehornmoea64_map(mmu_t mmu, vm_offset_t *virt, vm_offset_t pa_start, 2027190681Snwhitehorn vm_offset_t pa_end, int prot) 2028190681Snwhitehorn{ 2029190681Snwhitehorn vm_offset_t sva, va; 2030190681Snwhitehorn 2031190681Snwhitehorn sva = *virt; 2032190681Snwhitehorn va = sva; 2033190681Snwhitehorn for (; pa_start < pa_end; pa_start += PAGE_SIZE, va += PAGE_SIZE) 2034190681Snwhitehorn moea64_kenter(mmu, va, pa_start); 2035190681Snwhitehorn *virt = va; 2036190681Snwhitehorn 2037190681Snwhitehorn return (sva); 2038190681Snwhitehorn} 2039190681Snwhitehorn 2040190681Snwhitehorn/* 2041190681Snwhitehorn * Returns true if the pmap's pv is one of the first 2042190681Snwhitehorn * 16 pvs linked to from this page. This count may 2043190681Snwhitehorn * be changed upwards or downwards in the future; it 2044190681Snwhitehorn * is only necessary that true be returned for a small 2045190681Snwhitehorn * subset of pmaps for proper page aging. 2046190681Snwhitehorn */ 2047190681Snwhitehornboolean_t 2048190681Snwhitehornmoea64_page_exists_quick(mmu_t mmu, pmap_t pmap, vm_page_t m) 2049190681Snwhitehorn{ 2050190681Snwhitehorn int loops; 2051190681Snwhitehorn struct pvo_entry *pvo; 2052208990Salc boolean_t rv; 2053190681Snwhitehorn 2054208990Salc KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 2055208990Salc ("moea64_page_exists_quick: page %p is not managed", m)); 2056190681Snwhitehorn loops = 0; 2057208990Salc rv = FALSE; 2058208990Salc vm_page_lock_queues(); 2059190681Snwhitehorn LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2060208990Salc if (pvo->pvo_pmap == pmap) { 2061208990Salc rv = TRUE; 2062208990Salc break; 2063208990Salc } 2064190681Snwhitehorn if (++loops >= 16) 2065190681Snwhitehorn break; 2066190681Snwhitehorn } 2067208990Salc vm_page_unlock_queues(); 2068208990Salc return (rv); 2069190681Snwhitehorn} 2070190681Snwhitehorn 2071190681Snwhitehorn/* 2072190681Snwhitehorn * Return the number of managed mappings to the given physical page 2073190681Snwhitehorn * that are wired. 2074190681Snwhitehorn */ 2075190681Snwhitehornint 2076190681Snwhitehornmoea64_page_wired_mappings(mmu_t mmu, vm_page_t m) 2077190681Snwhitehorn{ 2078190681Snwhitehorn struct pvo_entry *pvo; 2079190681Snwhitehorn int count; 2080190681Snwhitehorn 2081190681Snwhitehorn count = 0; 2082208990Salc if ((m->flags & PG_FICTITIOUS) != 0) 2083190681Snwhitehorn return (count); 2084207796Salc vm_page_lock_queues(); 2085190681Snwhitehorn LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) 2086190681Snwhitehorn if ((pvo->pvo_vaddr & PVO_WIRED) != 0) 2087190681Snwhitehorn count++; 2088207796Salc vm_page_unlock_queues(); 2089190681Snwhitehorn return (count); 2090190681Snwhitehorn} 2091190681Snwhitehorn 2092209975Snwhitehornstatic uintptr_t moea64_vsidcontext; 2093190681Snwhitehorn 2094209975Snwhitehornuintptr_t 2095209975Snwhitehornmoea64_get_unique_vsid(void) { 2096209975Snwhitehorn u_int entropy; 2097209975Snwhitehorn register_t hash; 2098209975Snwhitehorn uint32_t mask; 2099209975Snwhitehorn int i; 2100190681Snwhitehorn 2101190681Snwhitehorn entropy = 0; 2102190681Snwhitehorn __asm __volatile("mftb %0" : "=r"(entropy)); 2103190681Snwhitehorn 2104211967Snwhitehorn mtx_lock(&moea64_slb_mutex); 2105209975Snwhitehorn for (i = 0; i < NVSIDS; i += VSID_NBPW) { 2106209975Snwhitehorn u_int n; 2107190681Snwhitehorn 2108190681Snwhitehorn /* 2109190681Snwhitehorn * Create a new value by mutiplying by a prime and adding in 2110190681Snwhitehorn * entropy from the timebase register. This is to make the 2111190681Snwhitehorn * VSID more random so that the PT hash function collides 2112190681Snwhitehorn * less often. (Note that the prime casues gcc to do shifts 2113190681Snwhitehorn * instead of a multiply.) 2114190681Snwhitehorn */ 2115190681Snwhitehorn moea64_vsidcontext = (moea64_vsidcontext * 0x1105) + entropy; 2116209975Snwhitehorn hash = moea64_vsidcontext & (NVSIDS - 1); 2117190681Snwhitehorn if (hash == 0) /* 0 is special, avoid it */ 2118190681Snwhitehorn continue; 2119190681Snwhitehorn n = hash >> 5; 2120190681Snwhitehorn mask = 1 << (hash & (VSID_NBPW - 1)); 2121209975Snwhitehorn hash = (moea64_vsidcontext & VSID_HASHMASK); 2122190681Snwhitehorn if (moea64_vsid_bitmap[n] & mask) { /* collision? */ 2123190681Snwhitehorn /* anything free in this bucket? */ 2124190681Snwhitehorn if (moea64_vsid_bitmap[n] == 0xffffffff) { 2125190681Snwhitehorn entropy = (moea64_vsidcontext >> 20); 2126190681Snwhitehorn continue; 2127190681Snwhitehorn } 2128212322Snwhitehorn i = ffs(~moea64_vsid_bitmap[n]) - 1; 2129190681Snwhitehorn mask = 1 << i; 2130209975Snwhitehorn hash &= VSID_HASHMASK & ~(VSID_NBPW - 1); 2131190681Snwhitehorn hash |= i; 2132190681Snwhitehorn } 2133212322Snwhitehorn KASSERT(!(moea64_vsid_bitmap[n] & mask), 2134212331Snwhitehorn ("Allocating in-use VSID %#zx\n", hash)); 2135190681Snwhitehorn moea64_vsid_bitmap[n] |= mask; 2136211967Snwhitehorn mtx_unlock(&moea64_slb_mutex); 2137209975Snwhitehorn return (hash); 2138190681Snwhitehorn } 2139190681Snwhitehorn 2140211967Snwhitehorn mtx_unlock(&moea64_slb_mutex); 2141209975Snwhitehorn panic("%s: out of segments",__func__); 2142190681Snwhitehorn} 2143190681Snwhitehorn 2144209975Snwhitehorn#ifdef __powerpc64__ 2145209975Snwhitehornvoid 2146209975Snwhitehornmoea64_pinit(mmu_t mmu, pmap_t pmap) 2147209975Snwhitehorn{ 2148209975Snwhitehorn PMAP_LOCK_INIT(pmap); 2149209975Snwhitehorn 2150212715Snwhitehorn pmap->pm_slb_tree_root = slb_alloc_tree(); 2151209975Snwhitehorn pmap->pm_slb = slb_alloc_user_cache(); 2152212722Snwhitehorn pmap->pm_slb_len = 0; 2153209975Snwhitehorn} 2154209975Snwhitehorn#else 2155209975Snwhitehornvoid 2156209975Snwhitehornmoea64_pinit(mmu_t mmu, pmap_t pmap) 2157209975Snwhitehorn{ 2158209975Snwhitehorn int i; 2159212308Snwhitehorn uint32_t hash; 2160209975Snwhitehorn 2161209975Snwhitehorn PMAP_LOCK_INIT(pmap); 2162209975Snwhitehorn 2163209975Snwhitehorn if (pmap_bootstrapped) 2164209975Snwhitehorn pmap->pmap_phys = (pmap_t)moea64_kextract(mmu, 2165209975Snwhitehorn (vm_offset_t)pmap); 2166209975Snwhitehorn else 2167209975Snwhitehorn pmap->pmap_phys = pmap; 2168209975Snwhitehorn 2169209975Snwhitehorn /* 2170209975Snwhitehorn * Allocate some segment registers for this pmap. 2171209975Snwhitehorn */ 2172209975Snwhitehorn hash = moea64_get_unique_vsid(); 2173209975Snwhitehorn 2174209975Snwhitehorn for (i = 0; i < 16; i++) 2175209975Snwhitehorn pmap->pm_sr[i] = VSID_MAKE(i, hash); 2176212308Snwhitehorn 2177212308Snwhitehorn KASSERT(pmap->pm_sr[0] != 0, ("moea64_pinit: pm_sr[0] = 0")); 2178209975Snwhitehorn} 2179209975Snwhitehorn#endif 2180209975Snwhitehorn 2181190681Snwhitehorn/* 2182190681Snwhitehorn * Initialize the pmap associated with process 0. 2183190681Snwhitehorn */ 2184190681Snwhitehornvoid 2185190681Snwhitehornmoea64_pinit0(mmu_t mmu, pmap_t pm) 2186190681Snwhitehorn{ 2187190681Snwhitehorn moea64_pinit(mmu, pm); 2188190681Snwhitehorn bzero(&pm->pm_stats, sizeof(pm->pm_stats)); 2189190681Snwhitehorn} 2190190681Snwhitehorn 2191190681Snwhitehorn/* 2192190681Snwhitehorn * Set the physical protection on the specified range of this map as requested. 2193190681Snwhitehorn */ 2194190681Snwhitehornvoid 2195190681Snwhitehornmoea64_protect(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva, 2196190681Snwhitehorn vm_prot_t prot) 2197190681Snwhitehorn{ 2198190681Snwhitehorn struct pvo_entry *pvo; 2199190681Snwhitehorn struct lpte *pt; 2200190681Snwhitehorn 2201190681Snwhitehorn CTR4(KTR_PMAP, "moea64_protect: pm=%p sva=%#x eva=%#x prot=%#x", pm, sva, 2202190681Snwhitehorn eva, prot); 2203190681Snwhitehorn 2204190681Snwhitehorn 2205190681Snwhitehorn KASSERT(pm == &curproc->p_vmspace->vm_pmap || pm == kernel_pmap, 2206190681Snwhitehorn ("moea64_protect: non current pmap")); 2207190681Snwhitehorn 2208190681Snwhitehorn if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 2209190681Snwhitehorn moea64_remove(mmu, pm, sva, eva); 2210190681Snwhitehorn return; 2211190681Snwhitehorn } 2212190681Snwhitehorn 2213190681Snwhitehorn vm_page_lock_queues(); 2214190681Snwhitehorn PMAP_LOCK(pm); 2215190681Snwhitehorn for (; sva < eva; sva += PAGE_SIZE) { 2216209975Snwhitehorn pvo = moea64_pvo_find_va(pm, sva); 2217190681Snwhitehorn if (pvo == NULL) 2218190681Snwhitehorn continue; 2219190681Snwhitehorn 2220190681Snwhitehorn /* 2221190681Snwhitehorn * Grab the PTE pointer before we diddle with the cached PTE 2222190681Snwhitehorn * copy. 2223190681Snwhitehorn */ 2224190681Snwhitehorn LOCK_TABLE(); 2225209975Snwhitehorn pt = moea64_pvo_to_pte(pvo); 2226190681Snwhitehorn 2227190681Snwhitehorn /* 2228190681Snwhitehorn * Change the protection of the page. 2229190681Snwhitehorn */ 2230190681Snwhitehorn pvo->pvo_pte.lpte.pte_lo &= ~LPTE_PP; 2231190681Snwhitehorn pvo->pvo_pte.lpte.pte_lo |= LPTE_BR; 2232190681Snwhitehorn pvo->pvo_pte.lpte.pte_lo &= ~LPTE_NOEXEC; 2233190681Snwhitehorn if ((prot & VM_PROT_EXECUTE) == 0) 2234190681Snwhitehorn pvo->pvo_pte.lpte.pte_lo |= LPTE_NOEXEC; 2235190681Snwhitehorn 2236190681Snwhitehorn /* 2237190681Snwhitehorn * If the PVO is in the page table, update that pte as well. 2238190681Snwhitehorn */ 2239190681Snwhitehorn if (pt != NULL) { 2240209975Snwhitehorn moea64_pte_change(pt, &pvo->pvo_pte.lpte, pvo->pvo_vpn); 2241190681Snwhitehorn if ((pvo->pvo_pte.lpte.pte_lo & 2242190681Snwhitehorn (LPTE_I | LPTE_G | LPTE_NOEXEC)) == 0) { 2243198341Smarcel moea64_syncicache(pm, sva, 2244198341Smarcel pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN, 2245198341Smarcel PAGE_SIZE); 2246190681Snwhitehorn } 2247190681Snwhitehorn } 2248190681Snwhitehorn UNLOCK_TABLE(); 2249190681Snwhitehorn } 2250190681Snwhitehorn vm_page_unlock_queues(); 2251190681Snwhitehorn PMAP_UNLOCK(pm); 2252190681Snwhitehorn} 2253190681Snwhitehorn 2254190681Snwhitehorn/* 2255190681Snwhitehorn * Map a list of wired pages into kernel virtual address space. This is 2256190681Snwhitehorn * intended for temporary mappings which do not need page modification or 2257190681Snwhitehorn * references recorded. Existing mappings in the region are overwritten. 2258190681Snwhitehorn */ 2259190681Snwhitehornvoid 2260190681Snwhitehornmoea64_qenter(mmu_t mmu, vm_offset_t va, vm_page_t *m, int count) 2261190681Snwhitehorn{ 2262190681Snwhitehorn while (count-- > 0) { 2263190681Snwhitehorn moea64_kenter(mmu, va, VM_PAGE_TO_PHYS(*m)); 2264190681Snwhitehorn va += PAGE_SIZE; 2265190681Snwhitehorn m++; 2266190681Snwhitehorn } 2267190681Snwhitehorn} 2268190681Snwhitehorn 2269190681Snwhitehorn/* 2270190681Snwhitehorn * Remove page mappings from kernel virtual address space. Intended for 2271190681Snwhitehorn * temporary mappings entered by moea64_qenter. 2272190681Snwhitehorn */ 2273190681Snwhitehornvoid 2274190681Snwhitehornmoea64_qremove(mmu_t mmu, vm_offset_t va, int count) 2275190681Snwhitehorn{ 2276190681Snwhitehorn while (count-- > 0) { 2277190681Snwhitehorn moea64_kremove(mmu, va); 2278190681Snwhitehorn va += PAGE_SIZE; 2279190681Snwhitehorn } 2280190681Snwhitehorn} 2281190681Snwhitehorn 2282190681Snwhitehornvoid 2283209975Snwhitehornmoea64_release_vsid(uint64_t vsid) 2284209975Snwhitehorn{ 2285212044Snwhitehorn int idx, mask; 2286209975Snwhitehorn 2287212044Snwhitehorn mtx_lock(&moea64_slb_mutex); 2288212044Snwhitehorn idx = vsid & (NVSIDS-1); 2289212044Snwhitehorn mask = 1 << (idx % VSID_NBPW); 2290212044Snwhitehorn idx /= VSID_NBPW; 2291212308Snwhitehorn KASSERT(moea64_vsid_bitmap[idx] & mask, 2292212308Snwhitehorn ("Freeing unallocated VSID %#jx", vsid)); 2293212044Snwhitehorn moea64_vsid_bitmap[idx] &= ~mask; 2294212044Snwhitehorn mtx_unlock(&moea64_slb_mutex); 2295209975Snwhitehorn} 2296209975Snwhitehorn 2297209975Snwhitehorn 2298209975Snwhitehornvoid 2299190681Snwhitehornmoea64_release(mmu_t mmu, pmap_t pmap) 2300190681Snwhitehorn{ 2301190681Snwhitehorn 2302190681Snwhitehorn /* 2303209975Snwhitehorn * Free segment registers' VSIDs 2304190681Snwhitehorn */ 2305209975Snwhitehorn #ifdef __powerpc64__ 2306212715Snwhitehorn slb_free_tree(pmap); 2307209975Snwhitehorn slb_free_user_cache(pmap->pm_slb); 2308209975Snwhitehorn #else 2309212308Snwhitehorn KASSERT(pmap->pm_sr[0] != 0, ("moea64_release: pm_sr[0] = 0")); 2310190681Snwhitehorn 2311212308Snwhitehorn moea64_release_vsid(VSID_TO_HASH(pmap->pm_sr[0])); 2312209975Snwhitehorn #endif 2313209975Snwhitehorn 2314190681Snwhitehorn PMAP_LOCK_DESTROY(pmap); 2315190681Snwhitehorn} 2316190681Snwhitehorn 2317190681Snwhitehorn/* 2318190681Snwhitehorn * Remove the given range of addresses from the specified map. 2319190681Snwhitehorn */ 2320190681Snwhitehornvoid 2321190681Snwhitehornmoea64_remove(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva) 2322190681Snwhitehorn{ 2323190681Snwhitehorn struct pvo_entry *pvo; 2324190681Snwhitehorn 2325190681Snwhitehorn vm_page_lock_queues(); 2326190681Snwhitehorn PMAP_LOCK(pm); 2327190681Snwhitehorn for (; sva < eva; sva += PAGE_SIZE) { 2328209975Snwhitehorn pvo = moea64_pvo_find_va(pm, sva); 2329209975Snwhitehorn if (pvo != NULL) 2330209975Snwhitehorn moea64_pvo_remove(pvo); 2331190681Snwhitehorn } 2332190681Snwhitehorn vm_page_unlock_queues(); 2333190681Snwhitehorn PMAP_UNLOCK(pm); 2334190681Snwhitehorn} 2335190681Snwhitehorn 2336190681Snwhitehorn/* 2337190681Snwhitehorn * Remove physical page from all pmaps in which it resides. moea64_pvo_remove() 2338190681Snwhitehorn * will reflect changes in pte's back to the vm_page. 2339190681Snwhitehorn */ 2340190681Snwhitehornvoid 2341190681Snwhitehornmoea64_remove_all(mmu_t mmu, vm_page_t m) 2342190681Snwhitehorn{ 2343190681Snwhitehorn struct pvo_head *pvo_head; 2344190681Snwhitehorn struct pvo_entry *pvo, *next_pvo; 2345190681Snwhitehorn pmap_t pmap; 2346190681Snwhitehorn 2347207796Salc vm_page_lock_queues(); 2348190681Snwhitehorn pvo_head = vm_page_to_pvoh(m); 2349190681Snwhitehorn for (pvo = LIST_FIRST(pvo_head); pvo != NULL; pvo = next_pvo) { 2350190681Snwhitehorn next_pvo = LIST_NEXT(pvo, pvo_vlink); 2351190681Snwhitehorn 2352190681Snwhitehorn MOEA_PVO_CHECK(pvo); /* sanity check */ 2353190681Snwhitehorn pmap = pvo->pvo_pmap; 2354190681Snwhitehorn PMAP_LOCK(pmap); 2355209975Snwhitehorn moea64_pvo_remove(pvo); 2356190681Snwhitehorn PMAP_UNLOCK(pmap); 2357190681Snwhitehorn } 2358204042Snwhitehorn if ((m->flags & PG_WRITEABLE) && moea64_is_modified(mmu, m)) { 2359204042Snwhitehorn moea64_attr_clear(m, LPTE_CHG); 2360204042Snwhitehorn vm_page_dirty(m); 2361204042Snwhitehorn } 2362190681Snwhitehorn vm_page_flag_clear(m, PG_WRITEABLE); 2363207796Salc vm_page_unlock_queues(); 2364190681Snwhitehorn} 2365190681Snwhitehorn 2366190681Snwhitehorn/* 2367190681Snwhitehorn * Allocate a physical page of memory directly from the phys_avail map. 2368190681Snwhitehorn * Can only be called from moea64_bootstrap before avail start and end are 2369190681Snwhitehorn * calculated. 2370190681Snwhitehorn */ 2371190681Snwhitehornstatic vm_offset_t 2372190681Snwhitehornmoea64_bootstrap_alloc(vm_size_t size, u_int align) 2373190681Snwhitehorn{ 2374190681Snwhitehorn vm_offset_t s, e; 2375190681Snwhitehorn int i, j; 2376190681Snwhitehorn 2377190681Snwhitehorn size = round_page(size); 2378190681Snwhitehorn for (i = 0; phys_avail[i + 1] != 0; i += 2) { 2379190681Snwhitehorn if (align != 0) 2380190681Snwhitehorn s = (phys_avail[i] + align - 1) & ~(align - 1); 2381190681Snwhitehorn else 2382190681Snwhitehorn s = phys_avail[i]; 2383190681Snwhitehorn e = s + size; 2384190681Snwhitehorn 2385190681Snwhitehorn if (s < phys_avail[i] || e > phys_avail[i + 1]) 2386190681Snwhitehorn continue; 2387190681Snwhitehorn 2388215159Snwhitehorn if (s + size > platform_real_maxaddr()) 2389215159Snwhitehorn continue; 2390215159Snwhitehorn 2391190681Snwhitehorn if (s == phys_avail[i]) { 2392190681Snwhitehorn phys_avail[i] += size; 2393190681Snwhitehorn } else if (e == phys_avail[i + 1]) { 2394190681Snwhitehorn phys_avail[i + 1] -= size; 2395190681Snwhitehorn } else { 2396190681Snwhitehorn for (j = phys_avail_count * 2; j > i; j -= 2) { 2397190681Snwhitehorn phys_avail[j] = phys_avail[j - 2]; 2398190681Snwhitehorn phys_avail[j + 1] = phys_avail[j - 1]; 2399190681Snwhitehorn } 2400190681Snwhitehorn 2401190681Snwhitehorn phys_avail[i + 3] = phys_avail[i + 1]; 2402190681Snwhitehorn phys_avail[i + 1] = s; 2403190681Snwhitehorn phys_avail[i + 2] = e; 2404190681Snwhitehorn phys_avail_count++; 2405190681Snwhitehorn } 2406190681Snwhitehorn 2407190681Snwhitehorn return (s); 2408190681Snwhitehorn } 2409190681Snwhitehorn panic("moea64_bootstrap_alloc: could not allocate memory"); 2410190681Snwhitehorn} 2411190681Snwhitehorn 2412190681Snwhitehornstatic void 2413190681Snwhitehorntlbia(void) 2414190681Snwhitehorn{ 2415190681Snwhitehorn vm_offset_t i; 2416209975Snwhitehorn #ifndef __powerpc64__ 2417198378Snwhitehorn register_t msr, scratch; 2418209975Snwhitehorn #endif 2419190681Snwhitehorn 2420209975Snwhitehorn TLBSYNC(); 2421209975Snwhitehorn 2422198378Snwhitehorn for (i = 0; i < 0xFF000; i += 0x00001000) { 2423209975Snwhitehorn #ifdef __powerpc64__ 2424209975Snwhitehorn __asm __volatile("tlbiel %0" :: "r"(i)); 2425209975Snwhitehorn #else 2426198378Snwhitehorn __asm __volatile("\ 2427198378Snwhitehorn mfmsr %0; \ 2428198378Snwhitehorn mr %1, %0; \ 2429198378Snwhitehorn insrdi %1,%3,1,0; \ 2430198378Snwhitehorn mtmsrd %1; \ 2431209975Snwhitehorn isync; \ 2432198378Snwhitehorn \ 2433198378Snwhitehorn tlbiel %2; \ 2434198378Snwhitehorn \ 2435198378Snwhitehorn mtmsrd %0; \ 2436209975Snwhitehorn isync;" 2437198378Snwhitehorn : "=r"(msr), "=r"(scratch) : "r"(i), "r"(1)); 2438209975Snwhitehorn #endif 2439198378Snwhitehorn } 2440209975Snwhitehorn 2441209975Snwhitehorn EIEIO(); 2442209975Snwhitehorn TLBSYNC(); 2443190681Snwhitehorn} 2444190681Snwhitehorn 2445209975Snwhitehorn#ifdef __powerpc64__ 2446209975Snwhitehornstatic void 2447209975Snwhitehornslbia(void) 2448209975Snwhitehorn{ 2449209975Snwhitehorn register_t seg0; 2450209975Snwhitehorn 2451209975Snwhitehorn __asm __volatile ("slbia"); 2452209975Snwhitehorn __asm __volatile ("slbmfee %0,%1; slbie %0;" : "=r"(seg0) : "r"(0)); 2453209975Snwhitehorn} 2454209975Snwhitehorn#endif 2455209975Snwhitehorn 2456190681Snwhitehornstatic int 2457190681Snwhitehornmoea64_pvo_enter(pmap_t pm, uma_zone_t zone, struct pvo_head *pvo_head, 2458198378Snwhitehorn vm_offset_t va, vm_offset_t pa, uint64_t pte_lo, int flags) 2459190681Snwhitehorn{ 2460190681Snwhitehorn struct pvo_entry *pvo; 2461190681Snwhitehorn uint64_t vsid; 2462190681Snwhitehorn int first; 2463190681Snwhitehorn u_int ptegidx; 2464190681Snwhitehorn int i; 2465190681Snwhitehorn int bootstrap; 2466190681Snwhitehorn 2467190681Snwhitehorn /* 2468190681Snwhitehorn * One nasty thing that can happen here is that the UMA calls to 2469190681Snwhitehorn * allocate new PVOs need to map more memory, which calls pvo_enter(), 2470190681Snwhitehorn * which calls UMA... 2471190681Snwhitehorn * 2472190681Snwhitehorn * We break the loop by detecting recursion and allocating out of 2473190681Snwhitehorn * the bootstrap pool. 2474190681Snwhitehorn */ 2475190681Snwhitehorn 2476190681Snwhitehorn first = 0; 2477190681Snwhitehorn bootstrap = (flags & PVO_BOOTSTRAP); 2478190681Snwhitehorn 2479190681Snwhitehorn if (!moea64_initialized) 2480190681Snwhitehorn bootstrap = 1; 2481190681Snwhitehorn 2482190681Snwhitehorn /* 2483190681Snwhitehorn * Compute the PTE Group index. 2484190681Snwhitehorn */ 2485190681Snwhitehorn va &= ~ADDR_POFF; 2486190681Snwhitehorn vsid = va_to_vsid(pm, va); 2487209975Snwhitehorn ptegidx = va_to_pteg(vsid, va, flags & PVO_LARGE); 2488190681Snwhitehorn 2489190681Snwhitehorn /* 2490190681Snwhitehorn * Remove any existing mapping for this page. Reuse the pvo entry if 2491190681Snwhitehorn * there is a mapping. 2492190681Snwhitehorn */ 2493198378Snwhitehorn LOCK_TABLE(); 2494190681Snwhitehorn 2495212363Snwhitehorn moea64_pvo_enter_calls++; 2496212363Snwhitehorn 2497190681Snwhitehorn LIST_FOREACH(pvo, &moea64_pvo_table[ptegidx], pvo_olink) { 2498190681Snwhitehorn if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) { 2499190681Snwhitehorn if ((pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN) == pa && 2500190681Snwhitehorn (pvo->pvo_pte.lpte.pte_lo & LPTE_PP) == 2501190681Snwhitehorn (pte_lo & LPTE_PP)) { 2502209975Snwhitehorn if (!(pvo->pvo_pte.lpte.pte_hi & LPTE_VALID)) { 2503209975Snwhitehorn /* Re-insert if spilled */ 2504209975Snwhitehorn i = moea64_pte_insert(ptegidx, 2505209975Snwhitehorn &pvo->pvo_pte.lpte); 2506209975Snwhitehorn if (i >= 0) 2507209975Snwhitehorn PVO_PTEGIDX_SET(pvo, i); 2508209975Snwhitehorn moea64_pte_overflow--; 2509209975Snwhitehorn } 2510198378Snwhitehorn UNLOCK_TABLE(); 2511190681Snwhitehorn return (0); 2512190681Snwhitehorn } 2513209975Snwhitehorn moea64_pvo_remove(pvo); 2514190681Snwhitehorn break; 2515190681Snwhitehorn } 2516190681Snwhitehorn } 2517190681Snwhitehorn 2518190681Snwhitehorn /* 2519190681Snwhitehorn * If we aren't overwriting a mapping, try to allocate. 2520190681Snwhitehorn */ 2521190681Snwhitehorn if (bootstrap) { 2522190681Snwhitehorn if (moea64_bpvo_pool_index >= BPVO_POOL_SIZE) { 2523209975Snwhitehorn panic("moea64_enter: bpvo pool exhausted, %d, %d, %zd", 2524190681Snwhitehorn moea64_bpvo_pool_index, BPVO_POOL_SIZE, 2525190681Snwhitehorn BPVO_POOL_SIZE * sizeof(struct pvo_entry)); 2526190681Snwhitehorn } 2527190681Snwhitehorn pvo = &moea64_bpvo_pool[moea64_bpvo_pool_index]; 2528190681Snwhitehorn moea64_bpvo_pool_index++; 2529190681Snwhitehorn bootstrap = 1; 2530190681Snwhitehorn } else { 2531198378Snwhitehorn /* 2532204719Snwhitehorn * Note: drop the table lock around the UMA allocation in 2533198378Snwhitehorn * case the UMA allocator needs to manipulate the page 2534198378Snwhitehorn * table. The mapping we are working with is already 2535198378Snwhitehorn * protected by the PMAP lock. 2536198378Snwhitehorn */ 2537198378Snwhitehorn UNLOCK_TABLE(); 2538190681Snwhitehorn pvo = uma_zalloc(zone, M_NOWAIT); 2539198378Snwhitehorn LOCK_TABLE(); 2540190681Snwhitehorn } 2541190681Snwhitehorn 2542190681Snwhitehorn if (pvo == NULL) { 2543198378Snwhitehorn UNLOCK_TABLE(); 2544190681Snwhitehorn return (ENOMEM); 2545190681Snwhitehorn } 2546190681Snwhitehorn 2547190681Snwhitehorn moea64_pvo_entries++; 2548190681Snwhitehorn pvo->pvo_vaddr = va; 2549209975Snwhitehorn pvo->pvo_vpn = (uint64_t)((va & ADDR_PIDX) >> ADDR_PIDX_SHFT) 2550209975Snwhitehorn | (vsid << 16); 2551190681Snwhitehorn pvo->pvo_pmap = pm; 2552190681Snwhitehorn LIST_INSERT_HEAD(&moea64_pvo_table[ptegidx], pvo, pvo_olink); 2553190681Snwhitehorn pvo->pvo_vaddr &= ~ADDR_POFF; 2554190681Snwhitehorn 2555190681Snwhitehorn if (!(flags & VM_PROT_EXECUTE)) 2556190681Snwhitehorn pte_lo |= LPTE_NOEXEC; 2557190681Snwhitehorn if (flags & PVO_WIRED) 2558190681Snwhitehorn pvo->pvo_vaddr |= PVO_WIRED; 2559190681Snwhitehorn if (pvo_head != &moea64_pvo_kunmanaged) 2560190681Snwhitehorn pvo->pvo_vaddr |= PVO_MANAGED; 2561190681Snwhitehorn if (bootstrap) 2562190681Snwhitehorn pvo->pvo_vaddr |= PVO_BOOTSTRAP; 2563190681Snwhitehorn if (flags & PVO_FAKE) 2564190681Snwhitehorn pvo->pvo_vaddr |= PVO_FAKE; 2565209975Snwhitehorn if (flags & PVO_LARGE) 2566209975Snwhitehorn pvo->pvo_vaddr |= PVO_LARGE; 2567190681Snwhitehorn 2568190681Snwhitehorn moea64_pte_create(&pvo->pvo_pte.lpte, vsid, va, 2569209975Snwhitehorn (uint64_t)(pa) | pte_lo, flags); 2570190681Snwhitehorn 2571190681Snwhitehorn /* 2572190681Snwhitehorn * Remember if the list was empty and therefore will be the first 2573190681Snwhitehorn * item. 2574190681Snwhitehorn */ 2575190681Snwhitehorn if (LIST_FIRST(pvo_head) == NULL) 2576190681Snwhitehorn first = 1; 2577190681Snwhitehorn LIST_INSERT_HEAD(pvo_head, pvo, pvo_vlink); 2578190681Snwhitehorn 2579209975Snwhitehorn if (pvo->pvo_vaddr & PVO_WIRED) { 2580209975Snwhitehorn pvo->pvo_pte.lpte.pte_hi |= LPTE_WIRED; 2581190681Snwhitehorn pm->pm_stats.wired_count++; 2582209975Snwhitehorn } 2583190681Snwhitehorn pm->pm_stats.resident_count++; 2584190681Snwhitehorn 2585190681Snwhitehorn /* 2586190681Snwhitehorn * We hope this succeeds but it isn't required. 2587190681Snwhitehorn */ 2588190681Snwhitehorn i = moea64_pte_insert(ptegidx, &pvo->pvo_pte.lpte); 2589190681Snwhitehorn if (i >= 0) { 2590190681Snwhitehorn PVO_PTEGIDX_SET(pvo, i); 2591190681Snwhitehorn } else { 2592190681Snwhitehorn panic("moea64_pvo_enter: overflow"); 2593190681Snwhitehorn moea64_pte_overflow++; 2594190681Snwhitehorn } 2595190681Snwhitehorn 2596204042Snwhitehorn if (pm == kernel_pmap) 2597204042Snwhitehorn isync(); 2598204042Snwhitehorn 2599198378Snwhitehorn UNLOCK_TABLE(); 2600190681Snwhitehorn 2601209975Snwhitehorn#ifdef __powerpc64__ 2602209975Snwhitehorn /* 2603209975Snwhitehorn * Make sure all our bootstrap mappings are in the SLB as soon 2604209975Snwhitehorn * as virtual memory is switched on. 2605209975Snwhitehorn */ 2606209975Snwhitehorn if (!pmap_bootstrapped) 2607209975Snwhitehorn moea64_bootstrap_slb_prefault(va, flags & PVO_LARGE); 2608209975Snwhitehorn#endif 2609209975Snwhitehorn 2610190681Snwhitehorn return (first ? ENOENT : 0); 2611190681Snwhitehorn} 2612190681Snwhitehorn 2613190681Snwhitehornstatic void 2614209975Snwhitehornmoea64_pvo_remove(struct pvo_entry *pvo) 2615190681Snwhitehorn{ 2616190681Snwhitehorn struct lpte *pt; 2617190681Snwhitehorn 2618190681Snwhitehorn /* 2619190681Snwhitehorn * If there is an active pte entry, we need to deactivate it (and 2620190681Snwhitehorn * save the ref & cfg bits). 2621190681Snwhitehorn */ 2622190681Snwhitehorn LOCK_TABLE(); 2623209975Snwhitehorn pt = moea64_pvo_to_pte(pvo); 2624190681Snwhitehorn if (pt != NULL) { 2625209975Snwhitehorn moea64_pte_unset(pt, &pvo->pvo_pte.lpte, pvo->pvo_vpn); 2626190681Snwhitehorn PVO_PTEGIDX_CLR(pvo); 2627190681Snwhitehorn } else { 2628190681Snwhitehorn moea64_pte_overflow--; 2629190681Snwhitehorn } 2630190681Snwhitehorn 2631190681Snwhitehorn /* 2632190681Snwhitehorn * Update our statistics. 2633190681Snwhitehorn */ 2634190681Snwhitehorn pvo->pvo_pmap->pm_stats.resident_count--; 2635204042Snwhitehorn if (pvo->pvo_vaddr & PVO_WIRED) 2636190681Snwhitehorn pvo->pvo_pmap->pm_stats.wired_count--; 2637190681Snwhitehorn 2638190681Snwhitehorn /* 2639190681Snwhitehorn * Save the REF/CHG bits into their cache if the page is managed. 2640190681Snwhitehorn */ 2641190681Snwhitehorn if ((pvo->pvo_vaddr & (PVO_MANAGED|PVO_FAKE)) == PVO_MANAGED) { 2642190681Snwhitehorn struct vm_page *pg; 2643190681Snwhitehorn 2644190681Snwhitehorn pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN); 2645190681Snwhitehorn if (pg != NULL) { 2646190681Snwhitehorn moea64_attr_save(pg, pvo->pvo_pte.lpte.pte_lo & 2647190681Snwhitehorn (LPTE_REF | LPTE_CHG)); 2648190681Snwhitehorn } 2649190681Snwhitehorn } 2650190681Snwhitehorn 2651190681Snwhitehorn /* 2652190681Snwhitehorn * Remove this PVO from the PV list. 2653190681Snwhitehorn */ 2654190681Snwhitehorn LIST_REMOVE(pvo, pvo_vlink); 2655190681Snwhitehorn 2656190681Snwhitehorn /* 2657190681Snwhitehorn * Remove this from the overflow list and return it to the pool 2658190681Snwhitehorn * if we aren't going to reuse it. 2659190681Snwhitehorn */ 2660190681Snwhitehorn LIST_REMOVE(pvo, pvo_olink); 2661212363Snwhitehorn 2662212363Snwhitehorn moea64_pvo_entries--; 2663212363Snwhitehorn moea64_pvo_remove_calls++; 2664212363Snwhitehorn 2665204694Snwhitehorn UNLOCK_TABLE(); 2666204694Snwhitehorn 2667190681Snwhitehorn if (!(pvo->pvo_vaddr & PVO_BOOTSTRAP)) 2668204042Snwhitehorn uma_zfree((pvo->pvo_vaddr & PVO_MANAGED) ? moea64_mpvo_zone : 2669190681Snwhitehorn moea64_upvo_zone, pvo); 2670190681Snwhitehorn} 2671190681Snwhitehorn 2672190681Snwhitehornstatic struct pvo_entry * 2673209975Snwhitehornmoea64_pvo_find_va(pmap_t pm, vm_offset_t va) 2674190681Snwhitehorn{ 2675190681Snwhitehorn struct pvo_entry *pvo; 2676190681Snwhitehorn int ptegidx; 2677190681Snwhitehorn uint64_t vsid; 2678209975Snwhitehorn #ifdef __powerpc64__ 2679212715Snwhitehorn uint64_t slbv; 2680190681Snwhitehorn 2681212715Snwhitehorn if (pm == kernel_pmap) { 2682212715Snwhitehorn slbv = kernel_va_to_slbv(va); 2683212715Snwhitehorn } else { 2684212715Snwhitehorn struct slb *slb; 2685212715Snwhitehorn slb = user_va_to_slb_entry(pm, va); 2686212715Snwhitehorn /* The page is not mapped if the segment isn't */ 2687212715Snwhitehorn if (slb == NULL) 2688212715Snwhitehorn return NULL; 2689212715Snwhitehorn slbv = slb->slbv; 2690212715Snwhitehorn } 2691209975Snwhitehorn 2692212715Snwhitehorn vsid = (slbv & SLBV_VSID_MASK) >> SLBV_VSID_SHIFT; 2693212715Snwhitehorn if (slbv & SLBV_L) 2694209975Snwhitehorn va &= ~moea64_large_page_mask; 2695209975Snwhitehorn else 2696209975Snwhitehorn va &= ~ADDR_POFF; 2697212715Snwhitehorn ptegidx = va_to_pteg(vsid, va, slbv & SLBV_L); 2698209975Snwhitehorn #else 2699190681Snwhitehorn va &= ~ADDR_POFF; 2700190681Snwhitehorn vsid = va_to_vsid(pm, va); 2701209975Snwhitehorn ptegidx = va_to_pteg(vsid, va, 0); 2702209975Snwhitehorn #endif 2703190681Snwhitehorn 2704190681Snwhitehorn LOCK_TABLE(); 2705190681Snwhitehorn LIST_FOREACH(pvo, &moea64_pvo_table[ptegidx], pvo_olink) { 2706209975Snwhitehorn if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) 2707190681Snwhitehorn break; 2708190681Snwhitehorn } 2709190681Snwhitehorn UNLOCK_TABLE(); 2710190681Snwhitehorn 2711190681Snwhitehorn return (pvo); 2712190681Snwhitehorn} 2713190681Snwhitehorn 2714190681Snwhitehornstatic struct lpte * 2715209975Snwhitehornmoea64_pvo_to_pte(const struct pvo_entry *pvo) 2716190681Snwhitehorn{ 2717209975Snwhitehorn struct lpte *pt; 2718209975Snwhitehorn int pteidx, ptegidx; 2719209975Snwhitehorn uint64_t vsid; 2720190681Snwhitehorn 2721209975Snwhitehorn ASSERT_TABLE_LOCK(); 2722209975Snwhitehorn 2723209975Snwhitehorn /* If the PTEG index is not set, then there is no page table entry */ 2724209975Snwhitehorn if (!PVO_PTEGIDX_ISSET(pvo)) 2725209975Snwhitehorn return (NULL); 2726209975Snwhitehorn 2727190681Snwhitehorn /* 2728209975Snwhitehorn * Calculate the ptegidx 2729190681Snwhitehorn */ 2730209975Snwhitehorn vsid = PVO_VSID(pvo); 2731209975Snwhitehorn ptegidx = va_to_pteg(vsid, PVO_VADDR(pvo), 2732209975Snwhitehorn pvo->pvo_vaddr & PVO_LARGE); 2733190681Snwhitehorn 2734209975Snwhitehorn /* 2735209975Snwhitehorn * We can find the actual pte entry without searching by grabbing 2736209975Snwhitehorn * the PTEG index from 3 unused bits in pvo_vaddr and by 2737209975Snwhitehorn * noticing the HID bit. 2738209975Snwhitehorn */ 2739209975Snwhitehorn if (pvo->pvo_pte.lpte.pte_hi & LPTE_HID) 2740209975Snwhitehorn ptegidx ^= moea64_pteg_mask; 2741190681Snwhitehorn 2742209975Snwhitehorn pteidx = (ptegidx << 3) | PVO_PTEGIDX_GET(pvo); 2743190681Snwhitehorn 2744190681Snwhitehorn if ((pvo->pvo_pte.lpte.pte_hi & LPTE_VALID) && 2745190681Snwhitehorn !PVO_PTEGIDX_ISSET(pvo)) { 2746190681Snwhitehorn panic("moea64_pvo_to_pte: pvo %p has valid pte in pvo but no " 2747190681Snwhitehorn "valid pte index", pvo); 2748190681Snwhitehorn } 2749190681Snwhitehorn 2750190681Snwhitehorn if ((pvo->pvo_pte.lpte.pte_hi & LPTE_VALID) == 0 && 2751190681Snwhitehorn PVO_PTEGIDX_ISSET(pvo)) { 2752190681Snwhitehorn panic("moea64_pvo_to_pte: pvo %p has valid pte index in pvo " 2753190681Snwhitehorn "pvo but no valid pte", pvo); 2754190681Snwhitehorn } 2755190681Snwhitehorn 2756209975Snwhitehorn pt = &moea64_pteg_table[pteidx >> 3].pt[pteidx & 7]; 2757190681Snwhitehorn if ((pt->pte_hi ^ (pvo->pvo_pte.lpte.pte_hi & ~LPTE_VALID)) == 2758190681Snwhitehorn LPTE_VALID) { 2759190681Snwhitehorn if ((pvo->pvo_pte.lpte.pte_hi & LPTE_VALID) == 0) { 2760190681Snwhitehorn panic("moea64_pvo_to_pte: pvo %p has valid pte in " 2761190681Snwhitehorn "moea64_pteg_table %p but invalid in pvo", pvo, pt); 2762190681Snwhitehorn } 2763190681Snwhitehorn 2764190681Snwhitehorn if (((pt->pte_lo ^ pvo->pvo_pte.lpte.pte_lo) & 2765205163Snwhitehorn ~(LPTE_M|LPTE_CHG|LPTE_REF)) != 0) { 2766190681Snwhitehorn panic("moea64_pvo_to_pte: pvo %p pte does not match " 2767190681Snwhitehorn "pte %p in moea64_pteg_table difference is %#x", 2768190681Snwhitehorn pvo, pt, 2769190681Snwhitehorn (uint32_t)(pt->pte_lo ^ pvo->pvo_pte.lpte.pte_lo)); 2770190681Snwhitehorn } 2771190681Snwhitehorn 2772190681Snwhitehorn return (pt); 2773190681Snwhitehorn } 2774190681Snwhitehorn 2775190681Snwhitehorn if (pvo->pvo_pte.lpte.pte_hi & LPTE_VALID) { 2776190681Snwhitehorn panic("moea64_pvo_to_pte: pvo %p has invalid pte %p in " 2777190681Snwhitehorn "moea64_pteg_table but valid in pvo", pvo, pt); 2778190681Snwhitehorn } 2779190681Snwhitehorn 2780190681Snwhitehorn return (NULL); 2781190681Snwhitehorn} 2782190681Snwhitehorn 2783209975Snwhitehornstatic __inline int 2784209975Snwhitehornmoea64_pte_spillable_ident(u_int ptegidx) 2785209975Snwhitehorn{ 2786209975Snwhitehorn struct lpte *pt; 2787209975Snwhitehorn int i, j, k; 2788209975Snwhitehorn 2789209975Snwhitehorn /* Start at a random slot */ 2790209975Snwhitehorn i = mftb() % 8; 2791209975Snwhitehorn k = -1; 2792209975Snwhitehorn for (j = 0; j < 8; j++) { 2793209975Snwhitehorn pt = &moea64_pteg_table[ptegidx].pt[(i + j) % 8]; 2794209975Snwhitehorn if (pt->pte_hi & (LPTE_LOCKED | LPTE_WIRED)) 2795209975Snwhitehorn continue; 2796209975Snwhitehorn 2797209975Snwhitehorn /* This is a candidate, so remember it */ 2798209975Snwhitehorn k = (i + j) % 8; 2799209975Snwhitehorn 2800209975Snwhitehorn /* Try to get a page that has not been used lately */ 2801209975Snwhitehorn if (!(pt->pte_lo & LPTE_REF)) 2802209975Snwhitehorn return (k); 2803209975Snwhitehorn } 2804209975Snwhitehorn 2805209975Snwhitehorn return (k); 2806209975Snwhitehorn} 2807209975Snwhitehorn 2808190681Snwhitehornstatic int 2809190681Snwhitehornmoea64_pte_insert(u_int ptegidx, struct lpte *pvo_pt) 2810190681Snwhitehorn{ 2811190681Snwhitehorn struct lpte *pt; 2812209975Snwhitehorn struct pvo_entry *pvo; 2813209975Snwhitehorn u_int pteg_bktidx; 2814190681Snwhitehorn int i; 2815190681Snwhitehorn 2816190681Snwhitehorn ASSERT_TABLE_LOCK(); 2817190681Snwhitehorn 2818190681Snwhitehorn /* 2819190681Snwhitehorn * First try primary hash. 2820190681Snwhitehorn */ 2821209975Snwhitehorn pteg_bktidx = ptegidx; 2822209975Snwhitehorn for (pt = moea64_pteg_table[pteg_bktidx].pt, i = 0; i < 8; i++, pt++) { 2823209975Snwhitehorn if ((pt->pte_hi & (LPTE_VALID | LPTE_LOCKED)) == 0) { 2824190681Snwhitehorn pvo_pt->pte_hi &= ~LPTE_HID; 2825190681Snwhitehorn moea64_pte_set(pt, pvo_pt); 2826190681Snwhitehorn return (i); 2827190681Snwhitehorn } 2828190681Snwhitehorn } 2829190681Snwhitehorn 2830190681Snwhitehorn /* 2831190681Snwhitehorn * Now try secondary hash. 2832190681Snwhitehorn */ 2833209975Snwhitehorn pteg_bktidx ^= moea64_pteg_mask; 2834209975Snwhitehorn for (pt = moea64_pteg_table[pteg_bktidx].pt, i = 0; i < 8; i++, pt++) { 2835209975Snwhitehorn if ((pt->pte_hi & (LPTE_VALID | LPTE_LOCKED)) == 0) { 2836190681Snwhitehorn pvo_pt->pte_hi |= LPTE_HID; 2837190681Snwhitehorn moea64_pte_set(pt, pvo_pt); 2838190681Snwhitehorn return (i); 2839190681Snwhitehorn } 2840190681Snwhitehorn } 2841190681Snwhitehorn 2842209975Snwhitehorn /* 2843209975Snwhitehorn * Out of luck. Find a PTE to sacrifice. 2844209975Snwhitehorn */ 2845209975Snwhitehorn pteg_bktidx = ptegidx; 2846209975Snwhitehorn i = moea64_pte_spillable_ident(pteg_bktidx); 2847209975Snwhitehorn if (i < 0) { 2848209975Snwhitehorn pteg_bktidx ^= moea64_pteg_mask; 2849209975Snwhitehorn i = moea64_pte_spillable_ident(pteg_bktidx); 2850209975Snwhitehorn } 2851209975Snwhitehorn 2852209975Snwhitehorn if (i < 0) { 2853209975Snwhitehorn /* No freeable slots in either PTEG? We're hosed. */ 2854209975Snwhitehorn panic("moea64_pte_insert: overflow"); 2855209975Snwhitehorn return (-1); 2856209975Snwhitehorn } 2857209975Snwhitehorn 2858209975Snwhitehorn if (pteg_bktidx == ptegidx) 2859209975Snwhitehorn pvo_pt->pte_hi &= ~LPTE_HID; 2860209975Snwhitehorn else 2861209975Snwhitehorn pvo_pt->pte_hi |= LPTE_HID; 2862209975Snwhitehorn 2863209975Snwhitehorn /* 2864209975Snwhitehorn * Synchronize the sacrifice PTE with its PVO, then mark both 2865209975Snwhitehorn * invalid. The PVO will be reused when/if the VM system comes 2866209975Snwhitehorn * here after a fault. 2867209975Snwhitehorn */ 2868209975Snwhitehorn pt = &moea64_pteg_table[pteg_bktidx].pt[i]; 2869209975Snwhitehorn 2870209975Snwhitehorn if (pt->pte_hi & LPTE_HID) 2871209975Snwhitehorn pteg_bktidx ^= moea64_pteg_mask; /* PTEs indexed by primary */ 2872209975Snwhitehorn 2873209975Snwhitehorn LIST_FOREACH(pvo, &moea64_pvo_table[pteg_bktidx], pvo_olink) { 2874209975Snwhitehorn if (pvo->pvo_pte.lpte.pte_hi == pt->pte_hi) { 2875209975Snwhitehorn KASSERT(pvo->pvo_pte.lpte.pte_hi & LPTE_VALID, 2876209975Snwhitehorn ("Invalid PVO for valid PTE!")); 2877209975Snwhitehorn moea64_pte_unset(pt, &pvo->pvo_pte.lpte, pvo->pvo_vpn); 2878209975Snwhitehorn PVO_PTEGIDX_CLR(pvo); 2879209975Snwhitehorn moea64_pte_overflow++; 2880209975Snwhitehorn break; 2881209975Snwhitehorn } 2882209975Snwhitehorn } 2883209975Snwhitehorn 2884209975Snwhitehorn KASSERT(pvo->pvo_pte.lpte.pte_hi == pt->pte_hi, 2885209975Snwhitehorn ("Unable to find PVO for spilled PTE")); 2886209975Snwhitehorn 2887209975Snwhitehorn /* 2888209975Snwhitehorn * Set the new PTE. 2889209975Snwhitehorn */ 2890209975Snwhitehorn moea64_pte_set(pt, pvo_pt); 2891209975Snwhitehorn 2892209975Snwhitehorn return (i); 2893190681Snwhitehorn} 2894190681Snwhitehorn 2895190681Snwhitehornstatic boolean_t 2896190681Snwhitehornmoea64_query_bit(vm_page_t m, u_int64_t ptebit) 2897190681Snwhitehorn{ 2898190681Snwhitehorn struct pvo_entry *pvo; 2899190681Snwhitehorn struct lpte *pt; 2900190681Snwhitehorn 2901190681Snwhitehorn if (moea64_attr_fetch(m) & ptebit) 2902190681Snwhitehorn return (TRUE); 2903190681Snwhitehorn 2904208574Salc vm_page_lock_queues(); 2905205370Snwhitehorn 2906190681Snwhitehorn LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2907190681Snwhitehorn MOEA_PVO_CHECK(pvo); /* sanity check */ 2908190681Snwhitehorn 2909190681Snwhitehorn /* 2910190681Snwhitehorn * See if we saved the bit off. If so, cache it and return 2911190681Snwhitehorn * success. 2912190681Snwhitehorn */ 2913190681Snwhitehorn if (pvo->pvo_pte.lpte.pte_lo & ptebit) { 2914190681Snwhitehorn moea64_attr_save(m, ptebit); 2915190681Snwhitehorn MOEA_PVO_CHECK(pvo); /* sanity check */ 2916208574Salc vm_page_unlock_queues(); 2917190681Snwhitehorn return (TRUE); 2918190681Snwhitehorn } 2919190681Snwhitehorn } 2920190681Snwhitehorn 2921190681Snwhitehorn /* 2922190681Snwhitehorn * No luck, now go through the hard part of looking at the PTEs 2923190681Snwhitehorn * themselves. Sync so that any pending REF/CHG bits are flushed to 2924190681Snwhitehorn * the PTEs. 2925190681Snwhitehorn */ 2926190681Snwhitehorn SYNC(); 2927190681Snwhitehorn LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2928190681Snwhitehorn MOEA_PVO_CHECK(pvo); /* sanity check */ 2929190681Snwhitehorn 2930190681Snwhitehorn /* 2931190681Snwhitehorn * See if this pvo has a valid PTE. if so, fetch the 2932190681Snwhitehorn * REF/CHG bits from the valid PTE. If the appropriate 2933190681Snwhitehorn * ptebit is set, cache it and return success. 2934190681Snwhitehorn */ 2935205370Snwhitehorn LOCK_TABLE(); 2936209975Snwhitehorn pt = moea64_pvo_to_pte(pvo); 2937190681Snwhitehorn if (pt != NULL) { 2938190681Snwhitehorn moea64_pte_synch(pt, &pvo->pvo_pte.lpte); 2939190681Snwhitehorn if (pvo->pvo_pte.lpte.pte_lo & ptebit) { 2940190681Snwhitehorn UNLOCK_TABLE(); 2941190681Snwhitehorn 2942190681Snwhitehorn moea64_attr_save(m, ptebit); 2943190681Snwhitehorn MOEA_PVO_CHECK(pvo); /* sanity check */ 2944208574Salc vm_page_unlock_queues(); 2945190681Snwhitehorn return (TRUE); 2946190681Snwhitehorn } 2947190681Snwhitehorn } 2948205370Snwhitehorn UNLOCK_TABLE(); 2949190681Snwhitehorn } 2950190681Snwhitehorn 2951208574Salc vm_page_unlock_queues(); 2952190681Snwhitehorn return (FALSE); 2953190681Snwhitehorn} 2954190681Snwhitehorn 2955190681Snwhitehornstatic u_int 2956208990Salcmoea64_clear_bit(vm_page_t m, u_int64_t ptebit) 2957190681Snwhitehorn{ 2958190681Snwhitehorn u_int count; 2959190681Snwhitehorn struct pvo_entry *pvo; 2960190681Snwhitehorn struct lpte *pt; 2961190681Snwhitehorn 2962208990Salc vm_page_lock_queues(); 2963205370Snwhitehorn 2964190681Snwhitehorn /* 2965190681Snwhitehorn * Clear the cached value. 2966190681Snwhitehorn */ 2967190681Snwhitehorn moea64_attr_clear(m, ptebit); 2968190681Snwhitehorn 2969190681Snwhitehorn /* 2970190681Snwhitehorn * Sync so that any pending REF/CHG bits are flushed to the PTEs (so 2971190681Snwhitehorn * we can reset the right ones). note that since the pvo entries and 2972190681Snwhitehorn * list heads are accessed via BAT0 and are never placed in the page 2973190681Snwhitehorn * table, we don't have to worry about further accesses setting the 2974190681Snwhitehorn * REF/CHG bits. 2975190681Snwhitehorn */ 2976190681Snwhitehorn SYNC(); 2977190681Snwhitehorn 2978190681Snwhitehorn /* 2979190681Snwhitehorn * For each pvo entry, clear the pvo's ptebit. If this pvo has a 2980190681Snwhitehorn * valid pte clear the ptebit from the valid pte. 2981190681Snwhitehorn */ 2982190681Snwhitehorn count = 0; 2983190681Snwhitehorn LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2984190681Snwhitehorn MOEA_PVO_CHECK(pvo); /* sanity check */ 2985190681Snwhitehorn 2986205370Snwhitehorn LOCK_TABLE(); 2987209975Snwhitehorn pt = moea64_pvo_to_pte(pvo); 2988190681Snwhitehorn if (pt != NULL) { 2989190681Snwhitehorn moea64_pte_synch(pt, &pvo->pvo_pte.lpte); 2990190681Snwhitehorn if (pvo->pvo_pte.lpte.pte_lo & ptebit) { 2991190681Snwhitehorn count++; 2992209975Snwhitehorn moea64_pte_clear(pt, pvo->pvo_vpn, ptebit); 2993190681Snwhitehorn } 2994190681Snwhitehorn } 2995190681Snwhitehorn pvo->pvo_pte.lpte.pte_lo &= ~ptebit; 2996190681Snwhitehorn MOEA_PVO_CHECK(pvo); /* sanity check */ 2997205370Snwhitehorn UNLOCK_TABLE(); 2998190681Snwhitehorn } 2999190681Snwhitehorn 3000208990Salc vm_page_unlock_queues(); 3001190681Snwhitehorn return (count); 3002190681Snwhitehorn} 3003190681Snwhitehorn 3004190681Snwhitehornboolean_t 3005190681Snwhitehornmoea64_dev_direct_mapped(mmu_t mmu, vm_offset_t pa, vm_size_t size) 3006190681Snwhitehorn{ 3007204296Snwhitehorn struct pvo_entry *pvo; 3008204296Snwhitehorn vm_offset_t ppa; 3009204296Snwhitehorn int error = 0; 3010204296Snwhitehorn 3011204296Snwhitehorn PMAP_LOCK(kernel_pmap); 3012204296Snwhitehorn for (ppa = pa & ~ADDR_POFF; ppa < pa + size; ppa += PAGE_SIZE) { 3013209975Snwhitehorn pvo = moea64_pvo_find_va(kernel_pmap, ppa); 3014204296Snwhitehorn if (pvo == NULL || 3015204296Snwhitehorn (pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN) != ppa) { 3016204296Snwhitehorn error = EFAULT; 3017204296Snwhitehorn break; 3018204296Snwhitehorn } 3019204296Snwhitehorn } 3020204296Snwhitehorn PMAP_UNLOCK(kernel_pmap); 3021204296Snwhitehorn 3022204296Snwhitehorn return (error); 3023190681Snwhitehorn} 3024190681Snwhitehorn 3025190681Snwhitehorn/* 3026190681Snwhitehorn * Map a set of physical memory pages into the kernel virtual 3027190681Snwhitehorn * address space. Return a pointer to where it is mapped. This 3028190681Snwhitehorn * routine is intended to be used for mapping device memory, 3029190681Snwhitehorn * NOT real memory. 3030190681Snwhitehorn */ 3031190681Snwhitehornvoid * 3032213307Snwhitehornmoea64_mapdev_attr(mmu_t mmu, vm_offset_t pa, vm_size_t size, vm_memattr_t ma) 3033190681Snwhitehorn{ 3034190681Snwhitehorn vm_offset_t va, tmpva, ppa, offset; 3035190681Snwhitehorn 3036190681Snwhitehorn ppa = trunc_page(pa); 3037190681Snwhitehorn offset = pa & PAGE_MASK; 3038190681Snwhitehorn size = roundup(offset + size, PAGE_SIZE); 3039190681Snwhitehorn 3040190681Snwhitehorn va = kmem_alloc_nofault(kernel_map, size); 3041190681Snwhitehorn 3042190681Snwhitehorn if (!va) 3043190681Snwhitehorn panic("moea64_mapdev: Couldn't alloc kernel virtual memory"); 3044190681Snwhitehorn 3045190681Snwhitehorn for (tmpva = va; size > 0;) { 3046213307Snwhitehorn moea64_kenter_attr(mmu, tmpva, ppa, ma); 3047190681Snwhitehorn size -= PAGE_SIZE; 3048190681Snwhitehorn tmpva += PAGE_SIZE; 3049190681Snwhitehorn ppa += PAGE_SIZE; 3050190681Snwhitehorn } 3051190681Snwhitehorn 3052190681Snwhitehorn return ((void *)(va + offset)); 3053190681Snwhitehorn} 3054190681Snwhitehorn 3055213307Snwhitehornvoid * 3056213307Snwhitehornmoea64_mapdev(mmu_t mmu, vm_offset_t pa, vm_size_t size) 3057213307Snwhitehorn{ 3058213307Snwhitehorn 3059213307Snwhitehorn return moea64_mapdev_attr(mmu, pa, size, VM_MEMATTR_DEFAULT); 3060213307Snwhitehorn} 3061213307Snwhitehorn 3062190681Snwhitehornvoid 3063190681Snwhitehornmoea64_unmapdev(mmu_t mmu, vm_offset_t va, vm_size_t size) 3064190681Snwhitehorn{ 3065190681Snwhitehorn vm_offset_t base, offset; 3066190681Snwhitehorn 3067190681Snwhitehorn base = trunc_page(va); 3068190681Snwhitehorn offset = va & PAGE_MASK; 3069190681Snwhitehorn size = roundup(offset + size, PAGE_SIZE); 3070190681Snwhitehorn 3071190681Snwhitehorn kmem_free(kernel_map, base, size); 3072190681Snwhitehorn} 3073190681Snwhitehorn 3074198341Smarcelstatic void 3075198341Smarcelmoea64_sync_icache(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_size_t sz) 3076198341Smarcel{ 3077198341Smarcel struct pvo_entry *pvo; 3078198341Smarcel vm_offset_t lim; 3079198341Smarcel vm_paddr_t pa; 3080198341Smarcel vm_size_t len; 3081198341Smarcel 3082198341Smarcel PMAP_LOCK(pm); 3083198341Smarcel while (sz > 0) { 3084198341Smarcel lim = round_page(va); 3085198341Smarcel len = MIN(lim - va, sz); 3086209975Snwhitehorn pvo = moea64_pvo_find_va(pm, va & ~ADDR_POFF); 3087198341Smarcel if (pvo != NULL) { 3088205163Snwhitehorn pa = (pvo->pvo_pte.pte.pte_lo & LPTE_RPGN) | 3089198341Smarcel (va & ADDR_POFF); 3090198341Smarcel moea64_syncicache(pm, va, pa, len); 3091198341Smarcel } 3092198341Smarcel va += len; 3093198341Smarcel sz -= len; 3094198341Smarcel } 3095198341Smarcel PMAP_UNLOCK(pm); 3096198341Smarcel} 3097