mmu_oea64.c revision 212044
1190681Snwhitehorn/*- 2190681Snwhitehorn * Copyright (c) 2001 The NetBSD Foundation, Inc. 3190681Snwhitehorn * All rights reserved. 4190681Snwhitehorn * 5190681Snwhitehorn * This code is derived from software contributed to The NetBSD Foundation 6190681Snwhitehorn * by Matt Thomas <matt@3am-software.com> of Allegro Networks, Inc. 7190681Snwhitehorn * 8190681Snwhitehorn * Redistribution and use in source and binary forms, with or without 9190681Snwhitehorn * modification, are permitted provided that the following conditions 10190681Snwhitehorn * are met: 11190681Snwhitehorn * 1. Redistributions of source code must retain the above copyright 12190681Snwhitehorn * notice, this list of conditions and the following disclaimer. 13190681Snwhitehorn * 2. Redistributions in binary form must reproduce the above copyright 14190681Snwhitehorn * notice, this list of conditions and the following disclaimer in the 15190681Snwhitehorn * documentation and/or other materials provided with the distribution. 16190681Snwhitehorn * 3. All advertising materials mentioning features or use of this software 17190681Snwhitehorn * must display the following acknowledgement: 18190681Snwhitehorn * This product includes software developed by the NetBSD 19190681Snwhitehorn * Foundation, Inc. and its contributors. 20190681Snwhitehorn * 4. Neither the name of The NetBSD Foundation nor the names of its 21190681Snwhitehorn * contributors may be used to endorse or promote products derived 22190681Snwhitehorn * from this software without specific prior written permission. 23190681Snwhitehorn * 24190681Snwhitehorn * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 25190681Snwhitehorn * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 26190681Snwhitehorn * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27190681Snwhitehorn * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 28190681Snwhitehorn * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29190681Snwhitehorn * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30190681Snwhitehorn * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31190681Snwhitehorn * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32190681Snwhitehorn * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33190681Snwhitehorn * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34190681Snwhitehorn * POSSIBILITY OF SUCH DAMAGE. 35190681Snwhitehorn */ 36190681Snwhitehorn/*- 37190681Snwhitehorn * Copyright (C) 1995, 1996 Wolfgang Solfrank. 38190681Snwhitehorn * Copyright (C) 1995, 1996 TooLs GmbH. 39190681Snwhitehorn * All rights reserved. 40190681Snwhitehorn * 41190681Snwhitehorn * Redistribution and use in source and binary forms, with or without 42190681Snwhitehorn * modification, are permitted provided that the following conditions 43190681Snwhitehorn * are met: 44190681Snwhitehorn * 1. Redistributions of source code must retain the above copyright 45190681Snwhitehorn * notice, this list of conditions and the following disclaimer. 46190681Snwhitehorn * 2. Redistributions in binary form must reproduce the above copyright 47190681Snwhitehorn * notice, this list of conditions and the following disclaimer in the 48190681Snwhitehorn * documentation and/or other materials provided with the distribution. 49190681Snwhitehorn * 3. All advertising materials mentioning features or use of this software 50190681Snwhitehorn * must display the following acknowledgement: 51190681Snwhitehorn * This product includes software developed by TooLs GmbH. 52190681Snwhitehorn * 4. The name of TooLs GmbH may not be used to endorse or promote products 53190681Snwhitehorn * derived from this software without specific prior written permission. 54190681Snwhitehorn * 55190681Snwhitehorn * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 56190681Snwhitehorn * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 57190681Snwhitehorn * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 58190681Snwhitehorn * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 59190681Snwhitehorn * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 60190681Snwhitehorn * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 61190681Snwhitehorn * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 62190681Snwhitehorn * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 63190681Snwhitehorn * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 64190681Snwhitehorn * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 65190681Snwhitehorn * 66190681Snwhitehorn * $NetBSD: pmap.c,v 1.28 2000/03/26 20:42:36 kleink Exp $ 67190681Snwhitehorn */ 68190681Snwhitehorn/*- 69190681Snwhitehorn * Copyright (C) 2001 Benno Rice. 70190681Snwhitehorn * All rights reserved. 71190681Snwhitehorn * 72190681Snwhitehorn * Redistribution and use in source and binary forms, with or without 73190681Snwhitehorn * modification, are permitted provided that the following conditions 74190681Snwhitehorn * are met: 75190681Snwhitehorn * 1. Redistributions of source code must retain the above copyright 76190681Snwhitehorn * notice, this list of conditions and the following disclaimer. 77190681Snwhitehorn * 2. Redistributions in binary form must reproduce the above copyright 78190681Snwhitehorn * notice, this list of conditions and the following disclaimer in the 79190681Snwhitehorn * documentation and/or other materials provided with the distribution. 80190681Snwhitehorn * 81190681Snwhitehorn * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR 82190681Snwhitehorn * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 83190681Snwhitehorn * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 84190681Snwhitehorn * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 85190681Snwhitehorn * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 86190681Snwhitehorn * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 87190681Snwhitehorn * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 88190681Snwhitehorn * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 89190681Snwhitehorn * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 90190681Snwhitehorn * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 91190681Snwhitehorn */ 92190681Snwhitehorn 93190681Snwhitehorn#include <sys/cdefs.h> 94190681Snwhitehorn__FBSDID("$FreeBSD: head/sys/powerpc/aim/mmu_oea64.c 212044 2010-08-31 02:07:13Z nwhitehorn $"); 95190681Snwhitehorn 96190681Snwhitehorn/* 97190681Snwhitehorn * Manages physical address maps. 98190681Snwhitehorn * 99190681Snwhitehorn * In addition to hardware address maps, this module is called upon to 100190681Snwhitehorn * provide software-use-only maps which may or may not be stored in the 101190681Snwhitehorn * same form as hardware maps. These pseudo-maps are used to store 102190681Snwhitehorn * intermediate results from copy operations to and from address spaces. 103190681Snwhitehorn * 104190681Snwhitehorn * Since the information managed by this module is also stored by the 105190681Snwhitehorn * logical address mapping module, this module may throw away valid virtual 106190681Snwhitehorn * to physical mappings at almost any time. However, invalidations of 107190681Snwhitehorn * mappings must be done as requested. 108190681Snwhitehorn * 109190681Snwhitehorn * In order to cope with hardware architectures which make virtual to 110190681Snwhitehorn * physical map invalidates expensive, this module may delay invalidate 111190681Snwhitehorn * reduced protection operations until such time as they are actually 112190681Snwhitehorn * necessary. This module is given full information as to which processors 113190681Snwhitehorn * are currently using which maps, and to when physical maps must be made 114190681Snwhitehorn * correct. 115190681Snwhitehorn */ 116190681Snwhitehorn 117190681Snwhitehorn#include "opt_kstack_pages.h" 118190681Snwhitehorn 119190681Snwhitehorn#include <sys/param.h> 120190681Snwhitehorn#include <sys/kernel.h> 121190681Snwhitehorn#include <sys/ktr.h> 122190681Snwhitehorn#include <sys/lock.h> 123190681Snwhitehorn#include <sys/msgbuf.h> 124190681Snwhitehorn#include <sys/mutex.h> 125190681Snwhitehorn#include <sys/proc.h> 126190681Snwhitehorn#include <sys/sysctl.h> 127190681Snwhitehorn#include <sys/systm.h> 128190681Snwhitehorn#include <sys/vmmeter.h> 129190681Snwhitehorn 130190681Snwhitehorn#include <sys/kdb.h> 131190681Snwhitehorn 132190681Snwhitehorn#include <dev/ofw/openfirm.h> 133190681Snwhitehorn 134190681Snwhitehorn#include <vm/vm.h> 135190681Snwhitehorn#include <vm/vm_param.h> 136190681Snwhitehorn#include <vm/vm_kern.h> 137190681Snwhitehorn#include <vm/vm_page.h> 138190681Snwhitehorn#include <vm/vm_map.h> 139190681Snwhitehorn#include <vm/vm_object.h> 140190681Snwhitehorn#include <vm/vm_extern.h> 141190681Snwhitehorn#include <vm/vm_pageout.h> 142190681Snwhitehorn#include <vm/vm_pager.h> 143190681Snwhitehorn#include <vm/uma.h> 144190681Snwhitehorn 145209975Snwhitehorn#include <machine/_inttypes.h> 146190681Snwhitehorn#include <machine/cpu.h> 147192067Snwhitehorn#include <machine/platform.h> 148190681Snwhitehorn#include <machine/frame.h> 149190681Snwhitehorn#include <machine/md_var.h> 150190681Snwhitehorn#include <machine/psl.h> 151190681Snwhitehorn#include <machine/bat.h> 152209975Snwhitehorn#include <machine/hid.h> 153190681Snwhitehorn#include <machine/pte.h> 154190681Snwhitehorn#include <machine/sr.h> 155190681Snwhitehorn#include <machine/trap.h> 156190681Snwhitehorn#include <machine/mmuvar.h> 157190681Snwhitehorn 158190681Snwhitehorn#include "mmu_if.h" 159190681Snwhitehorn 160190681Snwhitehorn#define MOEA_DEBUG 161190681Snwhitehorn 162190681Snwhitehorn#define TODO panic("%s: not implemented", __func__); 163209975Snwhitehornvoid moea64_release_vsid(uint64_t vsid); 164209975Snwhitehornuintptr_t moea64_get_unique_vsid(void); 165190681Snwhitehorn 166209975Snwhitehornstatic __inline register_t 167209975Snwhitehorncntlzd(volatile register_t a) { 168209975Snwhitehorn register_t b; 169209975Snwhitehorn __asm ("cntlzd %0, %1" : "=r"(b) : "r"(a)); 170190681Snwhitehorn return b; 171190681Snwhitehorn} 172190681Snwhitehorn 173204042Snwhitehorn#define PTESYNC() __asm __volatile("ptesync"); 174190681Snwhitehorn#define TLBSYNC() __asm __volatile("tlbsync; ptesync"); 175190681Snwhitehorn#define SYNC() __asm __volatile("sync"); 176190681Snwhitehorn#define EIEIO() __asm __volatile("eieio"); 177190681Snwhitehorn 178190681Snwhitehorn/* 179190681Snwhitehorn * The tlbie instruction must be executed in 64-bit mode 180190681Snwhitehorn * so we have to twiddle MSR[SF] around every invocation. 181190681Snwhitehorn * Just to add to the fun, exceptions must be off as well 182190681Snwhitehorn * so that we can't trap in 64-bit mode. What a pain. 183190681Snwhitehorn */ 184198378Snwhitehornstruct mtx tlbie_mutex; 185190681Snwhitehorn 186190681Snwhitehornstatic __inline void 187209975SnwhitehornTLBIE(uint64_t vpn) { 188209975Snwhitehorn#ifndef __powerpc64__ 189198378Snwhitehorn register_t vpn_hi, vpn_lo; 190190681Snwhitehorn register_t msr; 191190681Snwhitehorn register_t scratch; 192209975Snwhitehorn#endif 193190681Snwhitehorn 194209975Snwhitehorn vpn <<= ADDR_PIDX_SHFT; 195204042Snwhitehorn vpn &= ~(0xffffULL << 48); 196190681Snwhitehorn 197209975Snwhitehorn mtx_lock_spin(&tlbie_mutex); 198209975Snwhitehorn#ifdef __powerpc64__ 199209975Snwhitehorn __asm __volatile("\ 200209975Snwhitehorn ptesync; \ 201209975Snwhitehorn tlbie %0; \ 202209975Snwhitehorn eieio; \ 203209975Snwhitehorn tlbsync; \ 204209975Snwhitehorn ptesync;" 205209975Snwhitehorn :: "r"(vpn) : "memory"); 206209975Snwhitehorn#else 207190681Snwhitehorn vpn_hi = (uint32_t)(vpn >> 32); 208190681Snwhitehorn vpn_lo = (uint32_t)vpn; 209190681Snwhitehorn 210190681Snwhitehorn __asm __volatile("\ 211190681Snwhitehorn mfmsr %0; \ 212204042Snwhitehorn mr %1, %0; \ 213198378Snwhitehorn insrdi %1,%5,1,0; \ 214190681Snwhitehorn mtmsrd %1; \ 215190681Snwhitehorn ptesync; \ 216190681Snwhitehorn \ 217190681Snwhitehorn sld %1,%2,%4; \ 218190681Snwhitehorn or %1,%1,%3; \ 219190681Snwhitehorn tlbie %1; \ 220190681Snwhitehorn \ 221190681Snwhitehorn mtmsrd %0; \ 222190681Snwhitehorn eieio; \ 223190681Snwhitehorn tlbsync; \ 224190681Snwhitehorn ptesync;" 225204042Snwhitehorn : "=r"(msr), "=r"(scratch) : "r"(vpn_hi), "r"(vpn_lo), "r"(32), "r"(1) 226204042Snwhitehorn : "memory"); 227209975Snwhitehorn#endif 228198378Snwhitehorn mtx_unlock_spin(&tlbie_mutex); 229190681Snwhitehorn} 230190681Snwhitehorn 231190681Snwhitehorn#define DISABLE_TRANS(msr) msr = mfmsr(); mtmsr(msr & ~PSL_DR); isync() 232190681Snwhitehorn#define ENABLE_TRANS(msr) mtmsr(msr); isync() 233190681Snwhitehorn 234190681Snwhitehorn#define VSID_MAKE(sr, hash) ((sr) | (((hash) & 0xfffff) << 4)) 235190681Snwhitehorn#define VSID_TO_HASH(vsid) (((vsid) >> 4) & 0xfffff) 236204268Snwhitehorn#define VSID_HASH_MASK 0x0000007fffffffffULL 237190681Snwhitehorn 238204042Snwhitehorn#define PVO_PTEGIDX_MASK 0x007UL /* which PTEG slot */ 239204042Snwhitehorn#define PVO_PTEGIDX_VALID 0x008UL /* slot is valid */ 240204042Snwhitehorn#define PVO_WIRED 0x010UL /* PVO entry is wired */ 241204042Snwhitehorn#define PVO_MANAGED 0x020UL /* PVO entry is managed */ 242204042Snwhitehorn#define PVO_BOOTSTRAP 0x080UL /* PVO entry allocated during 243190681Snwhitehorn bootstrap */ 244204042Snwhitehorn#define PVO_FAKE 0x100UL /* fictitious phys page */ 245209975Snwhitehorn#define PVO_LARGE 0x200UL /* large page */ 246190681Snwhitehorn#define PVO_VADDR(pvo) ((pvo)->pvo_vaddr & ~ADDR_POFF) 247190681Snwhitehorn#define PVO_ISFAKE(pvo) ((pvo)->pvo_vaddr & PVO_FAKE) 248190681Snwhitehorn#define PVO_PTEGIDX_GET(pvo) ((pvo)->pvo_vaddr & PVO_PTEGIDX_MASK) 249190681Snwhitehorn#define PVO_PTEGIDX_ISSET(pvo) ((pvo)->pvo_vaddr & PVO_PTEGIDX_VALID) 250190681Snwhitehorn#define PVO_PTEGIDX_CLR(pvo) \ 251190681Snwhitehorn ((void)((pvo)->pvo_vaddr &= ~(PVO_PTEGIDX_VALID|PVO_PTEGIDX_MASK))) 252190681Snwhitehorn#define PVO_PTEGIDX_SET(pvo, i) \ 253190681Snwhitehorn ((void)((pvo)->pvo_vaddr |= (i)|PVO_PTEGIDX_VALID)) 254209975Snwhitehorn#define PVO_VSID(pvo) ((pvo)->pvo_vpn >> 16) 255190681Snwhitehorn 256190681Snwhitehorn#define MOEA_PVO_CHECK(pvo) 257190681Snwhitehorn 258190681Snwhitehorn#define LOCK_TABLE() mtx_lock(&moea64_table_mutex) 259190681Snwhitehorn#define UNLOCK_TABLE() mtx_unlock(&moea64_table_mutex); 260190681Snwhitehorn#define ASSERT_TABLE_LOCK() mtx_assert(&moea64_table_mutex, MA_OWNED) 261190681Snwhitehorn 262190681Snwhitehornstruct ofw_map { 263209975Snwhitehorn cell_t om_va; 264209975Snwhitehorn cell_t om_len; 265209975Snwhitehorn cell_t om_pa_hi; 266209975Snwhitehorn cell_t om_pa_lo; 267209975Snwhitehorn cell_t om_mode; 268190681Snwhitehorn}; 269190681Snwhitehorn 270190681Snwhitehorn/* 271190681Snwhitehorn * Map of physical memory regions. 272190681Snwhitehorn */ 273190681Snwhitehornstatic struct mem_region *regions; 274190681Snwhitehornstatic struct mem_region *pregions; 275209975Snwhitehornstatic u_int phys_avail_count; 276209975Snwhitehornstatic int regions_sz, pregions_sz; 277190681Snwhitehornextern int ofw_real_mode; 278190681Snwhitehorn 279190681Snwhitehornextern struct pmap ofw_pmap; 280190681Snwhitehorn 281190681Snwhitehornextern void bs_remap_earlyboot(void); 282190681Snwhitehorn 283190681Snwhitehorn 284190681Snwhitehorn/* 285190681Snwhitehorn * Lock for the pteg and pvo tables. 286190681Snwhitehorn */ 287190681Snwhitehornstruct mtx moea64_table_mutex; 288211967Snwhitehornstruct mtx moea64_slb_mutex; 289190681Snwhitehorn 290190681Snwhitehorn/* 291190681Snwhitehorn * PTEG data. 292190681Snwhitehorn */ 293190681Snwhitehornstatic struct lpteg *moea64_pteg_table; 294190681Snwhitehornu_int moea64_pteg_count; 295190681Snwhitehornu_int moea64_pteg_mask; 296190681Snwhitehorn 297190681Snwhitehorn/* 298190681Snwhitehorn * PVO data. 299190681Snwhitehorn */ 300190681Snwhitehornstruct pvo_head *moea64_pvo_table; /* pvo entries by pteg index */ 301190681Snwhitehorn/* lists of unmanaged pages */ 302190681Snwhitehornstruct pvo_head moea64_pvo_kunmanaged = 303190681Snwhitehorn LIST_HEAD_INITIALIZER(moea64_pvo_kunmanaged); 304190681Snwhitehornstruct pvo_head moea64_pvo_unmanaged = 305190681Snwhitehorn LIST_HEAD_INITIALIZER(moea64_pvo_unmanaged); 306190681Snwhitehorn 307190681Snwhitehornuma_zone_t moea64_upvo_zone; /* zone for pvo entries for unmanaged pages */ 308190681Snwhitehornuma_zone_t moea64_mpvo_zone; /* zone for pvo entries for managed pages */ 309190681Snwhitehorn 310190681Snwhitehorn#define BPVO_POOL_SIZE 327680 311190681Snwhitehornstatic struct pvo_entry *moea64_bpvo_pool; 312190681Snwhitehornstatic int moea64_bpvo_pool_index = 0; 313190681Snwhitehorn 314190681Snwhitehorn#define VSID_NBPW (sizeof(u_int32_t) * 8) 315209975Snwhitehorn#ifdef __powerpc64__ 316209975Snwhitehorn#define NVSIDS (NPMAPS * 16) 317209975Snwhitehorn#define VSID_HASHMASK 0xffffffffUL 318209975Snwhitehorn#else 319209975Snwhitehorn#define NVSIDS NPMAPS 320209975Snwhitehorn#define VSID_HASHMASK 0xfffffUL 321209975Snwhitehorn#endif 322209975Snwhitehornstatic u_int moea64_vsid_bitmap[NVSIDS / VSID_NBPW]; 323190681Snwhitehorn 324190681Snwhitehornstatic boolean_t moea64_initialized = FALSE; 325190681Snwhitehorn 326190681Snwhitehorn/* 327190681Snwhitehorn * Statistics. 328190681Snwhitehorn */ 329190681Snwhitehornu_int moea64_pte_valid = 0; 330190681Snwhitehornu_int moea64_pte_overflow = 0; 331190681Snwhitehornu_int moea64_pvo_entries = 0; 332190681Snwhitehornu_int moea64_pvo_enter_calls = 0; 333190681Snwhitehornu_int moea64_pvo_remove_calls = 0; 334190681SnwhitehornSYSCTL_INT(_machdep, OID_AUTO, moea64_pte_valid, CTLFLAG_RD, 335190681Snwhitehorn &moea64_pte_valid, 0, ""); 336190681SnwhitehornSYSCTL_INT(_machdep, OID_AUTO, moea64_pte_overflow, CTLFLAG_RD, 337190681Snwhitehorn &moea64_pte_overflow, 0, ""); 338190681SnwhitehornSYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_entries, CTLFLAG_RD, 339190681Snwhitehorn &moea64_pvo_entries, 0, ""); 340190681SnwhitehornSYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_enter_calls, CTLFLAG_RD, 341190681Snwhitehorn &moea64_pvo_enter_calls, 0, ""); 342190681SnwhitehornSYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_remove_calls, CTLFLAG_RD, 343190681Snwhitehorn &moea64_pvo_remove_calls, 0, ""); 344190681Snwhitehorn 345190681Snwhitehornvm_offset_t moea64_scratchpage_va[2]; 346209975Snwhitehornuint64_t moea64_scratchpage_vpn[2]; 347190681Snwhitehornstruct lpte *moea64_scratchpage_pte[2]; 348190681Snwhitehornstruct mtx moea64_scratchpage_mtx; 349190681Snwhitehorn 350209975Snwhitehornuint64_t moea64_large_page_mask = 0; 351209975Snwhitehornint moea64_large_page_size = 0; 352209975Snwhitehornint moea64_large_page_shift = 0; 353209975Snwhitehorn 354190681Snwhitehorn/* 355190681Snwhitehorn * Allocate physical memory for use in moea64_bootstrap. 356190681Snwhitehorn */ 357190681Snwhitehornstatic vm_offset_t moea64_bootstrap_alloc(vm_size_t, u_int); 358190681Snwhitehorn 359190681Snwhitehorn/* 360190681Snwhitehorn * PTE calls. 361190681Snwhitehorn */ 362190681Snwhitehornstatic int moea64_pte_insert(u_int, struct lpte *); 363190681Snwhitehorn 364190681Snwhitehorn/* 365190681Snwhitehorn * PVO calls. 366190681Snwhitehorn */ 367190681Snwhitehornstatic int moea64_pvo_enter(pmap_t, uma_zone_t, struct pvo_head *, 368198378Snwhitehorn vm_offset_t, vm_offset_t, uint64_t, int); 369209975Snwhitehornstatic void moea64_pvo_remove(struct pvo_entry *); 370209975Snwhitehornstatic struct pvo_entry *moea64_pvo_find_va(pmap_t, vm_offset_t); 371209975Snwhitehornstatic struct lpte *moea64_pvo_to_pte(const struct pvo_entry *); 372190681Snwhitehorn 373190681Snwhitehorn/* 374190681Snwhitehorn * Utility routines. 375190681Snwhitehorn */ 376209975Snwhitehornstatic void moea64_bootstrap(mmu_t mmup, 377190681Snwhitehorn vm_offset_t kernelstart, vm_offset_t kernelend); 378209975Snwhitehornstatic void moea64_cpu_bootstrap(mmu_t, int ap); 379190681Snwhitehornstatic void moea64_enter_locked(pmap_t, vm_offset_t, vm_page_t, 380190681Snwhitehorn vm_prot_t, boolean_t); 381190681Snwhitehornstatic boolean_t moea64_query_bit(vm_page_t, u_int64_t); 382208990Salcstatic u_int moea64_clear_bit(vm_page_t, u_int64_t); 383190681Snwhitehornstatic void moea64_kremove(mmu_t, vm_offset_t); 384190681Snwhitehornstatic void moea64_syncicache(pmap_t pmap, vm_offset_t va, 385198341Smarcel vm_offset_t pa, vm_size_t sz); 386190681Snwhitehornstatic void tlbia(void); 387209975Snwhitehorn#ifdef __powerpc64__ 388209975Snwhitehornstatic void slbia(void); 389209975Snwhitehorn#endif 390190681Snwhitehorn 391190681Snwhitehorn/* 392190681Snwhitehorn * Kernel MMU interface 393190681Snwhitehorn */ 394190681Snwhitehornvoid moea64_change_wiring(mmu_t, pmap_t, vm_offset_t, boolean_t); 395190681Snwhitehornvoid moea64_clear_modify(mmu_t, vm_page_t); 396190681Snwhitehornvoid moea64_clear_reference(mmu_t, vm_page_t); 397190681Snwhitehornvoid moea64_copy_page(mmu_t, vm_page_t, vm_page_t); 398190681Snwhitehornvoid moea64_enter(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t, boolean_t); 399190681Snwhitehornvoid moea64_enter_object(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_page_t, 400190681Snwhitehorn vm_prot_t); 401190681Snwhitehornvoid moea64_enter_quick(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t); 402190681Snwhitehornvm_paddr_t moea64_extract(mmu_t, pmap_t, vm_offset_t); 403190681Snwhitehornvm_page_t moea64_extract_and_hold(mmu_t, pmap_t, vm_offset_t, vm_prot_t); 404190681Snwhitehornvoid moea64_init(mmu_t); 405190681Snwhitehornboolean_t moea64_is_modified(mmu_t, vm_page_t); 406207155Salcboolean_t moea64_is_referenced(mmu_t, vm_page_t); 407190681Snwhitehornboolean_t moea64_ts_referenced(mmu_t, vm_page_t); 408190681Snwhitehornvm_offset_t moea64_map(mmu_t, vm_offset_t *, vm_offset_t, vm_offset_t, int); 409190681Snwhitehornboolean_t moea64_page_exists_quick(mmu_t, pmap_t, vm_page_t); 410190681Snwhitehornint moea64_page_wired_mappings(mmu_t, vm_page_t); 411190681Snwhitehornvoid moea64_pinit(mmu_t, pmap_t); 412190681Snwhitehornvoid moea64_pinit0(mmu_t, pmap_t); 413190681Snwhitehornvoid moea64_protect(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_prot_t); 414190681Snwhitehornvoid moea64_qenter(mmu_t, vm_offset_t, vm_page_t *, int); 415190681Snwhitehornvoid moea64_qremove(mmu_t, vm_offset_t, int); 416190681Snwhitehornvoid moea64_release(mmu_t, pmap_t); 417190681Snwhitehornvoid moea64_remove(mmu_t, pmap_t, vm_offset_t, vm_offset_t); 418190681Snwhitehornvoid moea64_remove_all(mmu_t, vm_page_t); 419190681Snwhitehornvoid moea64_remove_write(mmu_t, vm_page_t); 420190681Snwhitehornvoid moea64_zero_page(mmu_t, vm_page_t); 421190681Snwhitehornvoid moea64_zero_page_area(mmu_t, vm_page_t, int, int); 422190681Snwhitehornvoid moea64_zero_page_idle(mmu_t, vm_page_t); 423190681Snwhitehornvoid moea64_activate(mmu_t, struct thread *); 424190681Snwhitehornvoid moea64_deactivate(mmu_t, struct thread *); 425190681Snwhitehornvoid *moea64_mapdev(mmu_t, vm_offset_t, vm_size_t); 426190681Snwhitehornvoid moea64_unmapdev(mmu_t, vm_offset_t, vm_size_t); 427190681Snwhitehornvm_offset_t moea64_kextract(mmu_t, vm_offset_t); 428190681Snwhitehornvoid moea64_kenter(mmu_t, vm_offset_t, vm_offset_t); 429190681Snwhitehornboolean_t moea64_dev_direct_mapped(mmu_t, vm_offset_t, vm_size_t); 430198341Smarcelstatic void moea64_sync_icache(mmu_t, pmap_t, vm_offset_t, vm_size_t); 431190681Snwhitehorn 432209975Snwhitehornstatic mmu_method_t moea64_methods[] = { 433190681Snwhitehorn MMUMETHOD(mmu_change_wiring, moea64_change_wiring), 434190681Snwhitehorn MMUMETHOD(mmu_clear_modify, moea64_clear_modify), 435190681Snwhitehorn MMUMETHOD(mmu_clear_reference, moea64_clear_reference), 436190681Snwhitehorn MMUMETHOD(mmu_copy_page, moea64_copy_page), 437190681Snwhitehorn MMUMETHOD(mmu_enter, moea64_enter), 438190681Snwhitehorn MMUMETHOD(mmu_enter_object, moea64_enter_object), 439190681Snwhitehorn MMUMETHOD(mmu_enter_quick, moea64_enter_quick), 440190681Snwhitehorn MMUMETHOD(mmu_extract, moea64_extract), 441190681Snwhitehorn MMUMETHOD(mmu_extract_and_hold, moea64_extract_and_hold), 442190681Snwhitehorn MMUMETHOD(mmu_init, moea64_init), 443190681Snwhitehorn MMUMETHOD(mmu_is_modified, moea64_is_modified), 444207155Salc MMUMETHOD(mmu_is_referenced, moea64_is_referenced), 445190681Snwhitehorn MMUMETHOD(mmu_ts_referenced, moea64_ts_referenced), 446190681Snwhitehorn MMUMETHOD(mmu_map, moea64_map), 447190681Snwhitehorn MMUMETHOD(mmu_page_exists_quick,moea64_page_exists_quick), 448190681Snwhitehorn MMUMETHOD(mmu_page_wired_mappings,moea64_page_wired_mappings), 449190681Snwhitehorn MMUMETHOD(mmu_pinit, moea64_pinit), 450190681Snwhitehorn MMUMETHOD(mmu_pinit0, moea64_pinit0), 451190681Snwhitehorn MMUMETHOD(mmu_protect, moea64_protect), 452190681Snwhitehorn MMUMETHOD(mmu_qenter, moea64_qenter), 453190681Snwhitehorn MMUMETHOD(mmu_qremove, moea64_qremove), 454190681Snwhitehorn MMUMETHOD(mmu_release, moea64_release), 455190681Snwhitehorn MMUMETHOD(mmu_remove, moea64_remove), 456190681Snwhitehorn MMUMETHOD(mmu_remove_all, moea64_remove_all), 457190681Snwhitehorn MMUMETHOD(mmu_remove_write, moea64_remove_write), 458198341Smarcel MMUMETHOD(mmu_sync_icache, moea64_sync_icache), 459190681Snwhitehorn MMUMETHOD(mmu_zero_page, moea64_zero_page), 460190681Snwhitehorn MMUMETHOD(mmu_zero_page_area, moea64_zero_page_area), 461190681Snwhitehorn MMUMETHOD(mmu_zero_page_idle, moea64_zero_page_idle), 462190681Snwhitehorn MMUMETHOD(mmu_activate, moea64_activate), 463190681Snwhitehorn MMUMETHOD(mmu_deactivate, moea64_deactivate), 464190681Snwhitehorn 465190681Snwhitehorn /* Internal interfaces */ 466209975Snwhitehorn MMUMETHOD(mmu_bootstrap, moea64_bootstrap), 467209975Snwhitehorn MMUMETHOD(mmu_cpu_bootstrap, moea64_cpu_bootstrap), 468190681Snwhitehorn MMUMETHOD(mmu_mapdev, moea64_mapdev), 469190681Snwhitehorn MMUMETHOD(mmu_unmapdev, moea64_unmapdev), 470190681Snwhitehorn MMUMETHOD(mmu_kextract, moea64_kextract), 471190681Snwhitehorn MMUMETHOD(mmu_kenter, moea64_kenter), 472190681Snwhitehorn MMUMETHOD(mmu_dev_direct_mapped,moea64_dev_direct_mapped), 473190681Snwhitehorn 474190681Snwhitehorn { 0, 0 } 475190681Snwhitehorn}; 476190681Snwhitehorn 477209975Snwhitehornstatic mmu_def_t oea64_mmu = { 478190681Snwhitehorn MMU_TYPE_G5, 479209975Snwhitehorn moea64_methods, 480190681Snwhitehorn 0 481190681Snwhitehorn}; 482209975SnwhitehornMMU_DEF(oea64_mmu); 483190681Snwhitehorn 484190681Snwhitehornstatic __inline u_int 485209975Snwhitehornva_to_pteg(uint64_t vsid, vm_offset_t addr, int large) 486190681Snwhitehorn{ 487204268Snwhitehorn uint64_t hash; 488209975Snwhitehorn int shift; 489190681Snwhitehorn 490209975Snwhitehorn shift = large ? moea64_large_page_shift : ADDR_PIDX_SHFT; 491204268Snwhitehorn hash = (vsid & VSID_HASH_MASK) ^ (((uint64_t)addr & ADDR_PIDX) >> 492209975Snwhitehorn shift); 493190681Snwhitehorn return (hash & moea64_pteg_mask); 494190681Snwhitehorn} 495190681Snwhitehorn 496190681Snwhitehornstatic __inline struct pvo_head * 497190681Snwhitehornpa_to_pvoh(vm_offset_t pa, vm_page_t *pg_p) 498190681Snwhitehorn{ 499190681Snwhitehorn struct vm_page *pg; 500190681Snwhitehorn 501190681Snwhitehorn pg = PHYS_TO_VM_PAGE(pa); 502190681Snwhitehorn 503190681Snwhitehorn if (pg_p != NULL) 504190681Snwhitehorn *pg_p = pg; 505190681Snwhitehorn 506190681Snwhitehorn if (pg == NULL) 507190681Snwhitehorn return (&moea64_pvo_unmanaged); 508190681Snwhitehorn 509190681Snwhitehorn return (&pg->md.mdpg_pvoh); 510190681Snwhitehorn} 511190681Snwhitehorn 512190681Snwhitehornstatic __inline struct pvo_head * 513190681Snwhitehornvm_page_to_pvoh(vm_page_t m) 514190681Snwhitehorn{ 515190681Snwhitehorn 516190681Snwhitehorn return (&m->md.mdpg_pvoh); 517190681Snwhitehorn} 518190681Snwhitehorn 519190681Snwhitehornstatic __inline void 520190681Snwhitehornmoea64_attr_clear(vm_page_t m, u_int64_t ptebit) 521190681Snwhitehorn{ 522190681Snwhitehorn 523190681Snwhitehorn mtx_assert(&vm_page_queue_mtx, MA_OWNED); 524190681Snwhitehorn m->md.mdpg_attrs &= ~ptebit; 525190681Snwhitehorn} 526190681Snwhitehorn 527190681Snwhitehornstatic __inline u_int64_t 528190681Snwhitehornmoea64_attr_fetch(vm_page_t m) 529190681Snwhitehorn{ 530190681Snwhitehorn 531190681Snwhitehorn return (m->md.mdpg_attrs); 532190681Snwhitehorn} 533190681Snwhitehorn 534190681Snwhitehornstatic __inline void 535190681Snwhitehornmoea64_attr_save(vm_page_t m, u_int64_t ptebit) 536190681Snwhitehorn{ 537190681Snwhitehorn 538190681Snwhitehorn mtx_assert(&vm_page_queue_mtx, MA_OWNED); 539190681Snwhitehorn m->md.mdpg_attrs |= ptebit; 540190681Snwhitehorn} 541190681Snwhitehorn 542190681Snwhitehornstatic __inline void 543190681Snwhitehornmoea64_pte_create(struct lpte *pt, uint64_t vsid, vm_offset_t va, 544209975Snwhitehorn uint64_t pte_lo, int flags) 545190681Snwhitehorn{ 546209975Snwhitehorn 547190681Snwhitehorn ASSERT_TABLE_LOCK(); 548190681Snwhitehorn 549190681Snwhitehorn /* 550190681Snwhitehorn * Construct a PTE. Default to IMB initially. Valid bit only gets 551190681Snwhitehorn * set when the real pte is set in memory. 552190681Snwhitehorn * 553190681Snwhitehorn * Note: Don't set the valid bit for correct operation of tlb update. 554190681Snwhitehorn */ 555190681Snwhitehorn pt->pte_hi = (vsid << LPTE_VSID_SHIFT) | 556190681Snwhitehorn (((uint64_t)(va & ADDR_PIDX) >> ADDR_API_SHFT64) & LPTE_API); 557190681Snwhitehorn 558209975Snwhitehorn if (flags & PVO_LARGE) 559209975Snwhitehorn pt->pte_hi |= LPTE_BIG; 560209975Snwhitehorn 561190681Snwhitehorn pt->pte_lo = pte_lo; 562190681Snwhitehorn} 563190681Snwhitehorn 564190681Snwhitehornstatic __inline void 565190681Snwhitehornmoea64_pte_synch(struct lpte *pt, struct lpte *pvo_pt) 566190681Snwhitehorn{ 567190681Snwhitehorn 568190681Snwhitehorn ASSERT_TABLE_LOCK(); 569190681Snwhitehorn 570190681Snwhitehorn pvo_pt->pte_lo |= pt->pte_lo & (LPTE_REF | LPTE_CHG); 571190681Snwhitehorn} 572190681Snwhitehorn 573190681Snwhitehornstatic __inline void 574209975Snwhitehornmoea64_pte_clear(struct lpte *pt, uint64_t vpn, u_int64_t ptebit) 575190681Snwhitehorn{ 576190681Snwhitehorn ASSERT_TABLE_LOCK(); 577190681Snwhitehorn 578190681Snwhitehorn /* 579190681Snwhitehorn * As shown in Section 7.6.3.2.3 580190681Snwhitehorn */ 581190681Snwhitehorn pt->pte_lo &= ~ptebit; 582209975Snwhitehorn TLBIE(vpn); 583190681Snwhitehorn} 584190681Snwhitehorn 585190681Snwhitehornstatic __inline void 586190681Snwhitehornmoea64_pte_set(struct lpte *pt, struct lpte *pvo_pt) 587190681Snwhitehorn{ 588190681Snwhitehorn 589190681Snwhitehorn ASSERT_TABLE_LOCK(); 590190681Snwhitehorn pvo_pt->pte_hi |= LPTE_VALID; 591190681Snwhitehorn 592190681Snwhitehorn /* 593190681Snwhitehorn * Update the PTE as defined in section 7.6.3.1. 594190681Snwhitehorn * Note that the REF/CHG bits are from pvo_pt and thus should have 595190681Snwhitehorn * been saved so this routine can restore them (if desired). 596190681Snwhitehorn */ 597190681Snwhitehorn pt->pte_lo = pvo_pt->pte_lo; 598190681Snwhitehorn EIEIO(); 599190681Snwhitehorn pt->pte_hi = pvo_pt->pte_hi; 600204042Snwhitehorn PTESYNC(); 601190681Snwhitehorn moea64_pte_valid++; 602190681Snwhitehorn} 603190681Snwhitehorn 604190681Snwhitehornstatic __inline void 605209975Snwhitehornmoea64_pte_unset(struct lpte *pt, struct lpte *pvo_pt, uint64_t vpn) 606190681Snwhitehorn{ 607190681Snwhitehorn ASSERT_TABLE_LOCK(); 608190681Snwhitehorn pvo_pt->pte_hi &= ~LPTE_VALID; 609190681Snwhitehorn 610190681Snwhitehorn /* 611190681Snwhitehorn * Force the reg & chg bits back into the PTEs. 612190681Snwhitehorn */ 613190681Snwhitehorn SYNC(); 614190681Snwhitehorn 615190681Snwhitehorn /* 616190681Snwhitehorn * Invalidate the pte. 617190681Snwhitehorn */ 618190681Snwhitehorn pt->pte_hi &= ~LPTE_VALID; 619209975Snwhitehorn TLBIE(vpn); 620190681Snwhitehorn 621190681Snwhitehorn /* 622190681Snwhitehorn * Save the reg & chg bits. 623190681Snwhitehorn */ 624190681Snwhitehorn moea64_pte_synch(pt, pvo_pt); 625190681Snwhitehorn moea64_pte_valid--; 626190681Snwhitehorn} 627190681Snwhitehorn 628190681Snwhitehornstatic __inline void 629209975Snwhitehornmoea64_pte_change(struct lpte *pt, struct lpte *pvo_pt, uint64_t vpn) 630190681Snwhitehorn{ 631190681Snwhitehorn 632190681Snwhitehorn /* 633190681Snwhitehorn * Invalidate the PTE 634190681Snwhitehorn */ 635209975Snwhitehorn moea64_pte_unset(pt, pvo_pt, vpn); 636190681Snwhitehorn moea64_pte_set(pt, pvo_pt); 637190681Snwhitehorn} 638190681Snwhitehorn 639190681Snwhitehornstatic __inline uint64_t 640190681Snwhitehornmoea64_calc_wimg(vm_offset_t pa) 641190681Snwhitehorn{ 642190681Snwhitehorn uint64_t pte_lo; 643190681Snwhitehorn int i; 644190681Snwhitehorn 645190681Snwhitehorn /* 646190681Snwhitehorn * Assume the page is cache inhibited and access is guarded unless 647190681Snwhitehorn * it's in our available memory array. 648190681Snwhitehorn */ 649190681Snwhitehorn pte_lo = LPTE_I | LPTE_G; 650190681Snwhitehorn for (i = 0; i < pregions_sz; i++) { 651190681Snwhitehorn if ((pa >= pregions[i].mr_start) && 652190681Snwhitehorn (pa < (pregions[i].mr_start + pregions[i].mr_size))) { 653190681Snwhitehorn pte_lo &= ~(LPTE_I | LPTE_G); 654190681Snwhitehorn pte_lo |= LPTE_M; 655190681Snwhitehorn break; 656190681Snwhitehorn } 657190681Snwhitehorn } 658190681Snwhitehorn 659190681Snwhitehorn return pte_lo; 660190681Snwhitehorn} 661190681Snwhitehorn 662190681Snwhitehorn/* 663190681Snwhitehorn * Quick sort callout for comparing memory regions. 664190681Snwhitehorn */ 665190681Snwhitehornstatic int mr_cmp(const void *a, const void *b); 666190681Snwhitehornstatic int om_cmp(const void *a, const void *b); 667190681Snwhitehorn 668190681Snwhitehornstatic int 669190681Snwhitehornmr_cmp(const void *a, const void *b) 670190681Snwhitehorn{ 671190681Snwhitehorn const struct mem_region *regiona; 672190681Snwhitehorn const struct mem_region *regionb; 673190681Snwhitehorn 674190681Snwhitehorn regiona = a; 675190681Snwhitehorn regionb = b; 676190681Snwhitehorn if (regiona->mr_start < regionb->mr_start) 677190681Snwhitehorn return (-1); 678190681Snwhitehorn else if (regiona->mr_start > regionb->mr_start) 679190681Snwhitehorn return (1); 680190681Snwhitehorn else 681190681Snwhitehorn return (0); 682190681Snwhitehorn} 683190681Snwhitehorn 684190681Snwhitehornstatic int 685190681Snwhitehornom_cmp(const void *a, const void *b) 686190681Snwhitehorn{ 687190681Snwhitehorn const struct ofw_map *mapa; 688190681Snwhitehorn const struct ofw_map *mapb; 689190681Snwhitehorn 690190681Snwhitehorn mapa = a; 691190681Snwhitehorn mapb = b; 692190681Snwhitehorn if (mapa->om_pa_hi < mapb->om_pa_hi) 693190681Snwhitehorn return (-1); 694190681Snwhitehorn else if (mapa->om_pa_hi > mapb->om_pa_hi) 695190681Snwhitehorn return (1); 696190681Snwhitehorn else if (mapa->om_pa_lo < mapb->om_pa_lo) 697190681Snwhitehorn return (-1); 698190681Snwhitehorn else if (mapa->om_pa_lo > mapb->om_pa_lo) 699190681Snwhitehorn return (1); 700190681Snwhitehorn else 701190681Snwhitehorn return (0); 702190681Snwhitehorn} 703190681Snwhitehorn 704190681Snwhitehornstatic void 705209975Snwhitehornmoea64_cpu_bootstrap(mmu_t mmup, int ap) 706190681Snwhitehorn{ 707190681Snwhitehorn int i = 0; 708209975Snwhitehorn #ifdef __powerpc64__ 709209975Snwhitehorn struct slb *slb = PCPU_GET(slb); 710209975Snwhitehorn #endif 711190681Snwhitehorn 712190681Snwhitehorn /* 713190681Snwhitehorn * Initialize segment registers and MMU 714190681Snwhitehorn */ 715190681Snwhitehorn 716190681Snwhitehorn mtmsr(mfmsr() & ~PSL_DR & ~PSL_IR); isync(); 717209975Snwhitehorn 718209975Snwhitehorn /* 719209975Snwhitehorn * Install kernel SLB entries 720209975Snwhitehorn */ 721209975Snwhitehorn 722209975Snwhitehorn #ifdef __powerpc64__ 723209975Snwhitehorn slbia(); 724209975Snwhitehorn 725209975Snwhitehorn for (i = 0; i < 64; i++) { 726209975Snwhitehorn if (!(slb[i].slbe & SLBE_VALID)) 727209975Snwhitehorn continue; 728209975Snwhitehorn 729209975Snwhitehorn __asm __volatile ("slbmte %0, %1" :: 730209975Snwhitehorn "r"(slb[i].slbv), "r"(slb[i].slbe)); 731209975Snwhitehorn } 732209975Snwhitehorn #else 733209975Snwhitehorn for (i = 0; i < 16; i++) 734209975Snwhitehorn mtsrin(i << ADDR_SR_SHFT, kernel_pmap->pm_sr[i]); 735209975Snwhitehorn #endif 736209975Snwhitehorn 737209975Snwhitehorn /* 738209975Snwhitehorn * Install page table 739209975Snwhitehorn */ 740209975Snwhitehorn 741204042Snwhitehorn __asm __volatile ("ptesync; mtsdr1 %0; isync" 742209975Snwhitehorn :: "r"((uintptr_t)moea64_pteg_table 743209975Snwhitehorn | (64 - cntlzd(moea64_pteg_mask >> 11)))); 744190681Snwhitehorn tlbia(); 745190681Snwhitehorn} 746190681Snwhitehorn 747190681Snwhitehornstatic void 748199226Snwhitehornmoea64_add_ofw_mappings(mmu_t mmup, phandle_t mmu, size_t sz) 749199226Snwhitehorn{ 750199226Snwhitehorn struct ofw_map translations[sz/sizeof(struct ofw_map)]; 751199226Snwhitehorn register_t msr; 752199226Snwhitehorn vm_offset_t off; 753204128Snwhitehorn vm_paddr_t pa_base; 754199226Snwhitehorn int i, ofw_mappings; 755199226Snwhitehorn 756199226Snwhitehorn bzero(translations, sz); 757199226Snwhitehorn if (OF_getprop(mmu, "translations", translations, sz) == -1) 758199226Snwhitehorn panic("moea64_bootstrap: can't get ofw translations"); 759199226Snwhitehorn 760199226Snwhitehorn CTR0(KTR_PMAP, "moea64_add_ofw_mappings: translations"); 761199226Snwhitehorn sz /= sizeof(*translations); 762199226Snwhitehorn qsort(translations, sz, sizeof (*translations), om_cmp); 763199226Snwhitehorn 764199226Snwhitehorn for (i = 0, ofw_mappings = 0; i < sz; i++) { 765199226Snwhitehorn CTR3(KTR_PMAP, "translation: pa=%#x va=%#x len=%#x", 766199226Snwhitehorn (uint32_t)(translations[i].om_pa_lo), translations[i].om_va, 767199226Snwhitehorn translations[i].om_len); 768199226Snwhitehorn 769199226Snwhitehorn if (translations[i].om_pa_lo % PAGE_SIZE) 770199226Snwhitehorn panic("OFW translation not page-aligned!"); 771199226Snwhitehorn 772209975Snwhitehorn pa_base = translations[i].om_pa_lo; 773209975Snwhitehorn 774209975Snwhitehorn #ifdef __powerpc64__ 775209975Snwhitehorn pa_base += (vm_offset_t)translations[i].om_pa_hi << 32; 776209975Snwhitehorn #else 777199226Snwhitehorn if (translations[i].om_pa_hi) 778199226Snwhitehorn panic("OFW translations above 32-bit boundary!"); 779209975Snwhitehorn #endif 780199226Snwhitehorn 781199226Snwhitehorn /* Now enter the pages for this mapping */ 782199226Snwhitehorn 783199226Snwhitehorn DISABLE_TRANS(msr); 784199226Snwhitehorn for (off = 0; off < translations[i].om_len; off += PAGE_SIZE) { 785209975Snwhitehorn if (moea64_pvo_find_va(kernel_pmap, 786209975Snwhitehorn translations[i].om_va + off) != NULL) 787209975Snwhitehorn continue; 788209975Snwhitehorn 789204128Snwhitehorn moea64_kenter(mmup, translations[i].om_va + off, 790204128Snwhitehorn pa_base + off); 791199226Snwhitehorn 792199226Snwhitehorn ofw_mappings++; 793199226Snwhitehorn } 794199226Snwhitehorn ENABLE_TRANS(msr); 795199226Snwhitehorn } 796199226Snwhitehorn} 797199226Snwhitehorn 798209975Snwhitehorn#ifdef __powerpc64__ 799199226Snwhitehornstatic void 800209975Snwhitehornmoea64_probe_large_page(void) 801190681Snwhitehorn{ 802209975Snwhitehorn uint16_t pvr = mfpvr() >> 16; 803209975Snwhitehorn 804209975Snwhitehorn switch (pvr) { 805209975Snwhitehorn case IBM970: 806209975Snwhitehorn case IBM970FX: 807209975Snwhitehorn case IBM970MP: 808209975Snwhitehorn powerpc_sync(); isync(); 809209975Snwhitehorn mtspr(SPR_HID4, mfspr(SPR_HID4) & ~HID4_970_DISABLE_LG_PG); 810209975Snwhitehorn powerpc_sync(); isync(); 811209975Snwhitehorn 812209975Snwhitehorn /* FALLTHROUGH */ 813209975Snwhitehorn case IBMCELLBE: 814209975Snwhitehorn moea64_large_page_size = 0x1000000; /* 16 MB */ 815209975Snwhitehorn moea64_large_page_shift = 24; 816209975Snwhitehorn break; 817209975Snwhitehorn default: 818209975Snwhitehorn moea64_large_page_size = 0; 819209975Snwhitehorn } 820209975Snwhitehorn 821209975Snwhitehorn moea64_large_page_mask = moea64_large_page_size - 1; 822209975Snwhitehorn} 823209975Snwhitehorn 824209975Snwhitehornstatic void 825209975Snwhitehornmoea64_bootstrap_slb_prefault(vm_offset_t va, int large) 826209975Snwhitehorn{ 827209975Snwhitehorn struct slb *cache; 828209975Snwhitehorn struct slb entry; 829209975Snwhitehorn uint64_t esid, slbe; 830209975Snwhitehorn uint64_t i; 831209975Snwhitehorn 832209975Snwhitehorn cache = PCPU_GET(slb); 833209975Snwhitehorn esid = va >> ADDR_SR_SHFT; 834209975Snwhitehorn slbe = (esid << SLBE_ESID_SHIFT) | SLBE_VALID; 835209975Snwhitehorn 836209975Snwhitehorn for (i = 0; i < 64; i++) { 837209975Snwhitehorn if (cache[i].slbe == (slbe | i)) 838209975Snwhitehorn return; 839209975Snwhitehorn } 840209975Snwhitehorn 841209975Snwhitehorn entry.slbe = slbe; 842210704Snwhitehorn entry.slbv = KERNEL_VSID(esid) << SLBV_VSID_SHIFT; 843209975Snwhitehorn if (large) 844209975Snwhitehorn entry.slbv |= SLBV_L; 845209975Snwhitehorn 846209975Snwhitehorn slb_insert(kernel_pmap, cache, &entry); 847209975Snwhitehorn} 848209975Snwhitehorn#endif 849209975Snwhitehorn 850209975Snwhitehornstatic void 851209975Snwhitehornmoea64_setup_direct_map(mmu_t mmup, vm_offset_t kernelstart, 852209975Snwhitehorn vm_offset_t kernelend) 853209975Snwhitehorn{ 854209975Snwhitehorn register_t msr; 855209975Snwhitehorn vm_paddr_t pa; 856209975Snwhitehorn vm_offset_t size, off; 857209975Snwhitehorn uint64_t pte_lo; 858209975Snwhitehorn int i; 859209975Snwhitehorn 860209975Snwhitehorn if (moea64_large_page_size == 0) 861209975Snwhitehorn hw_direct_map = 0; 862209975Snwhitehorn 863209975Snwhitehorn DISABLE_TRANS(msr); 864209975Snwhitehorn if (hw_direct_map) { 865209975Snwhitehorn PMAP_LOCK(kernel_pmap); 866209975Snwhitehorn for (i = 0; i < pregions_sz; i++) { 867209975Snwhitehorn for (pa = pregions[i].mr_start; pa < pregions[i].mr_start + 868209975Snwhitehorn pregions[i].mr_size; pa += moea64_large_page_size) { 869209975Snwhitehorn pte_lo = LPTE_M; 870209975Snwhitehorn 871209975Snwhitehorn /* 872209975Snwhitehorn * Set memory access as guarded if prefetch within 873209975Snwhitehorn * the page could exit the available physmem area. 874209975Snwhitehorn */ 875209975Snwhitehorn if (pa & moea64_large_page_mask) { 876209975Snwhitehorn pa &= moea64_large_page_mask; 877209975Snwhitehorn pte_lo |= LPTE_G; 878209975Snwhitehorn } 879209975Snwhitehorn if (pa + moea64_large_page_size > 880209975Snwhitehorn pregions[i].mr_start + pregions[i].mr_size) 881209975Snwhitehorn pte_lo |= LPTE_G; 882209975Snwhitehorn 883209975Snwhitehorn moea64_pvo_enter(kernel_pmap, moea64_upvo_zone, 884209975Snwhitehorn &moea64_pvo_kunmanaged, pa, pa, 885209975Snwhitehorn pte_lo, PVO_WIRED | PVO_LARGE | 886209975Snwhitehorn VM_PROT_EXECUTE); 887209975Snwhitehorn } 888209975Snwhitehorn } 889209975Snwhitehorn PMAP_UNLOCK(kernel_pmap); 890209975Snwhitehorn } else { 891209975Snwhitehorn size = moea64_pteg_count * sizeof(struct lpteg); 892209975Snwhitehorn off = (vm_offset_t)(moea64_pteg_table); 893209975Snwhitehorn for (pa = off; pa < off + size; pa += PAGE_SIZE) 894209975Snwhitehorn moea64_kenter(mmup, pa, pa); 895209975Snwhitehorn size = sizeof(struct pvo_head) * moea64_pteg_count; 896209975Snwhitehorn off = (vm_offset_t)(moea64_pvo_table); 897209975Snwhitehorn for (pa = off; pa < off + size; pa += PAGE_SIZE) 898209975Snwhitehorn moea64_kenter(mmup, pa, pa); 899209975Snwhitehorn size = BPVO_POOL_SIZE*sizeof(struct pvo_entry); 900209975Snwhitehorn off = (vm_offset_t)(moea64_bpvo_pool); 901209975Snwhitehorn for (pa = off; pa < off + size; pa += PAGE_SIZE) 902209975Snwhitehorn moea64_kenter(mmup, pa, pa); 903209975Snwhitehorn 904209975Snwhitehorn /* 905209975Snwhitehorn * Map certain important things, like ourselves. 906209975Snwhitehorn * 907209975Snwhitehorn * NOTE: We do not map the exception vector space. That code is 908209975Snwhitehorn * used only in real mode, and leaving it unmapped allows us to 909209975Snwhitehorn * catch NULL pointer deferences, instead of making NULL a valid 910209975Snwhitehorn * address. 911209975Snwhitehorn */ 912209975Snwhitehorn 913209975Snwhitehorn for (pa = kernelstart & ~PAGE_MASK; pa < kernelend; 914209975Snwhitehorn pa += PAGE_SIZE) 915209975Snwhitehorn moea64_kenter(mmup, pa, pa); 916209975Snwhitehorn } 917209975Snwhitehorn ENABLE_TRANS(msr); 918209975Snwhitehorn} 919209975Snwhitehorn 920209975Snwhitehornstatic void 921209975Snwhitehornmoea64_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend) 922209975Snwhitehorn{ 923190681Snwhitehorn ihandle_t mmui; 924190681Snwhitehorn phandle_t chosen; 925190681Snwhitehorn phandle_t mmu; 926199226Snwhitehorn size_t sz; 927190681Snwhitehorn int i, j; 928190681Snwhitehorn vm_size_t size, physsz, hwphyssz; 929209975Snwhitehorn vm_offset_t pa, va; 930199226Snwhitehorn register_t msr; 931194784Sjeff void *dpcpu; 932190681Snwhitehorn 933209975Snwhitehorn#ifndef __powerpc64__ 934190681Snwhitehorn /* We don't have a direct map since there is no BAT */ 935190681Snwhitehorn hw_direct_map = 0; 936190681Snwhitehorn 937190681Snwhitehorn /* Make sure battable is zero, since we have no BAT */ 938190681Snwhitehorn for (i = 0; i < 16; i++) { 939190681Snwhitehorn battable[i].batu = 0; 940190681Snwhitehorn battable[i].batl = 0; 941190681Snwhitehorn } 942209975Snwhitehorn#else 943209975Snwhitehorn moea64_probe_large_page(); 944190681Snwhitehorn 945209975Snwhitehorn /* Use a direct map if we have large page support */ 946209975Snwhitehorn if (moea64_large_page_size > 0) 947209975Snwhitehorn hw_direct_map = 1; 948209975Snwhitehorn else 949209975Snwhitehorn hw_direct_map = 0; 950209975Snwhitehorn#endif 951209975Snwhitehorn 952190681Snwhitehorn /* Get physical memory regions from firmware */ 953190681Snwhitehorn mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz); 954190681Snwhitehorn CTR0(KTR_PMAP, "moea64_bootstrap: physical memory"); 955190681Snwhitehorn 956190681Snwhitehorn qsort(pregions, pregions_sz, sizeof(*pregions), mr_cmp); 957190681Snwhitehorn if (sizeof(phys_avail)/sizeof(phys_avail[0]) < regions_sz) 958190681Snwhitehorn panic("moea64_bootstrap: phys_avail too small"); 959190681Snwhitehorn qsort(regions, regions_sz, sizeof(*regions), mr_cmp); 960190681Snwhitehorn phys_avail_count = 0; 961190681Snwhitehorn physsz = 0; 962190681Snwhitehorn hwphyssz = 0; 963190681Snwhitehorn TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz); 964190681Snwhitehorn for (i = 0, j = 0; i < regions_sz; i++, j += 2) { 965190681Snwhitehorn CTR3(KTR_PMAP, "region: %#x - %#x (%#x)", regions[i].mr_start, 966190681Snwhitehorn regions[i].mr_start + regions[i].mr_size, 967190681Snwhitehorn regions[i].mr_size); 968190681Snwhitehorn if (hwphyssz != 0 && 969190681Snwhitehorn (physsz + regions[i].mr_size) >= hwphyssz) { 970190681Snwhitehorn if (physsz < hwphyssz) { 971190681Snwhitehorn phys_avail[j] = regions[i].mr_start; 972190681Snwhitehorn phys_avail[j + 1] = regions[i].mr_start + 973190681Snwhitehorn hwphyssz - physsz; 974190681Snwhitehorn physsz = hwphyssz; 975190681Snwhitehorn phys_avail_count++; 976190681Snwhitehorn } 977190681Snwhitehorn break; 978190681Snwhitehorn } 979190681Snwhitehorn phys_avail[j] = regions[i].mr_start; 980190681Snwhitehorn phys_avail[j + 1] = regions[i].mr_start + regions[i].mr_size; 981190681Snwhitehorn phys_avail_count++; 982190681Snwhitehorn physsz += regions[i].mr_size; 983190681Snwhitehorn } 984209975Snwhitehorn 985209975Snwhitehorn /* Check for overlap with the kernel and exception vectors */ 986209975Snwhitehorn for (j = 0; j < 2*phys_avail_count; j+=2) { 987209975Snwhitehorn if (phys_avail[j] < EXC_LAST) 988209975Snwhitehorn phys_avail[j] += EXC_LAST; 989209975Snwhitehorn 990209975Snwhitehorn if (kernelstart >= phys_avail[j] && 991209975Snwhitehorn kernelstart < phys_avail[j+1]) { 992209975Snwhitehorn if (kernelend < phys_avail[j+1]) { 993209975Snwhitehorn phys_avail[2*phys_avail_count] = 994209975Snwhitehorn (kernelend & ~PAGE_MASK) + PAGE_SIZE; 995209975Snwhitehorn phys_avail[2*phys_avail_count + 1] = 996209975Snwhitehorn phys_avail[j+1]; 997209975Snwhitehorn phys_avail_count++; 998209975Snwhitehorn } 999209975Snwhitehorn 1000209975Snwhitehorn phys_avail[j+1] = kernelstart & ~PAGE_MASK; 1001209975Snwhitehorn } 1002209975Snwhitehorn 1003209975Snwhitehorn if (kernelend >= phys_avail[j] && 1004209975Snwhitehorn kernelend < phys_avail[j+1]) { 1005209975Snwhitehorn if (kernelstart > phys_avail[j]) { 1006209975Snwhitehorn phys_avail[2*phys_avail_count] = phys_avail[j]; 1007209975Snwhitehorn phys_avail[2*phys_avail_count + 1] = 1008209975Snwhitehorn kernelstart & ~PAGE_MASK; 1009209975Snwhitehorn phys_avail_count++; 1010209975Snwhitehorn } 1011209975Snwhitehorn 1012209975Snwhitehorn phys_avail[j] = (kernelend & ~PAGE_MASK) + PAGE_SIZE; 1013209975Snwhitehorn } 1014209975Snwhitehorn } 1015209975Snwhitehorn 1016190681Snwhitehorn physmem = btoc(physsz); 1017190681Snwhitehorn 1018190681Snwhitehorn /* 1019190681Snwhitehorn * Allocate PTEG table. 1020190681Snwhitehorn */ 1021190681Snwhitehorn#ifdef PTEGCOUNT 1022190681Snwhitehorn moea64_pteg_count = PTEGCOUNT; 1023190681Snwhitehorn#else 1024190681Snwhitehorn moea64_pteg_count = 0x1000; 1025190681Snwhitehorn 1026190681Snwhitehorn while (moea64_pteg_count < physmem) 1027190681Snwhitehorn moea64_pteg_count <<= 1; 1028209975Snwhitehorn 1029209975Snwhitehorn moea64_pteg_count >>= 1; 1030190681Snwhitehorn#endif /* PTEGCOUNT */ 1031190681Snwhitehorn 1032190681Snwhitehorn size = moea64_pteg_count * sizeof(struct lpteg); 1033190681Snwhitehorn CTR2(KTR_PMAP, "moea64_bootstrap: %d PTEGs, %d bytes", 1034190681Snwhitehorn moea64_pteg_count, size); 1035190681Snwhitehorn 1036190681Snwhitehorn /* 1037190681Snwhitehorn * We now need to allocate memory. This memory, to be allocated, 1038190681Snwhitehorn * has to reside in a page table. The page table we are about to 1039190681Snwhitehorn * allocate. We don't have BAT. So drop to data real mode for a minute 1040190681Snwhitehorn * as a measure of last resort. We do this a couple times. 1041190681Snwhitehorn */ 1042190681Snwhitehorn 1043190681Snwhitehorn moea64_pteg_table = (struct lpteg *)moea64_bootstrap_alloc(size, size); 1044190681Snwhitehorn DISABLE_TRANS(msr); 1045190681Snwhitehorn bzero((void *)moea64_pteg_table, moea64_pteg_count * sizeof(struct lpteg)); 1046190681Snwhitehorn ENABLE_TRANS(msr); 1047190681Snwhitehorn 1048190681Snwhitehorn moea64_pteg_mask = moea64_pteg_count - 1; 1049190681Snwhitehorn 1050190681Snwhitehorn CTR1(KTR_PMAP, "moea64_bootstrap: PTEG table at %p", moea64_pteg_table); 1051190681Snwhitehorn 1052190681Snwhitehorn /* 1053190681Snwhitehorn * Allocate pv/overflow lists. 1054190681Snwhitehorn */ 1055190681Snwhitehorn size = sizeof(struct pvo_head) * moea64_pteg_count; 1056190681Snwhitehorn 1057190681Snwhitehorn moea64_pvo_table = (struct pvo_head *)moea64_bootstrap_alloc(size, 1058190681Snwhitehorn PAGE_SIZE); 1059190681Snwhitehorn CTR1(KTR_PMAP, "moea64_bootstrap: PVO table at %p", moea64_pvo_table); 1060190681Snwhitehorn 1061190681Snwhitehorn DISABLE_TRANS(msr); 1062190681Snwhitehorn for (i = 0; i < moea64_pteg_count; i++) 1063190681Snwhitehorn LIST_INIT(&moea64_pvo_table[i]); 1064190681Snwhitehorn ENABLE_TRANS(msr); 1065190681Snwhitehorn 1066190681Snwhitehorn /* 1067190681Snwhitehorn * Initialize the lock that synchronizes access to the pteg and pvo 1068190681Snwhitehorn * tables. 1069190681Snwhitehorn */ 1070190681Snwhitehorn mtx_init(&moea64_table_mutex, "pmap table", NULL, MTX_DEF | 1071190681Snwhitehorn MTX_RECURSE); 1072211967Snwhitehorn mtx_init(&moea64_slb_mutex, "SLB table", NULL, MTX_DEF); 1073190681Snwhitehorn 1074190681Snwhitehorn /* 1075198378Snwhitehorn * Initialize the TLBIE lock. TLBIE can only be executed by one CPU. 1076198378Snwhitehorn */ 1077198378Snwhitehorn mtx_init(&tlbie_mutex, "tlbie mutex", NULL, MTX_SPIN); 1078198378Snwhitehorn 1079198378Snwhitehorn /* 1080190681Snwhitehorn * Initialise the unmanaged pvo pool. 1081190681Snwhitehorn */ 1082190681Snwhitehorn moea64_bpvo_pool = (struct pvo_entry *)moea64_bootstrap_alloc( 1083190681Snwhitehorn BPVO_POOL_SIZE*sizeof(struct pvo_entry), 0); 1084190681Snwhitehorn moea64_bpvo_pool_index = 0; 1085190681Snwhitehorn 1086190681Snwhitehorn /* 1087190681Snwhitehorn * Make sure kernel vsid is allocated as well as VSID 0. 1088190681Snwhitehorn */ 1089209975Snwhitehorn #ifndef __powerpc64__ 1090209975Snwhitehorn moea64_vsid_bitmap[(KERNEL_VSIDBITS & (NVSIDS - 1)) / VSID_NBPW] 1091190681Snwhitehorn |= 1 << (KERNEL_VSIDBITS % VSID_NBPW); 1092190681Snwhitehorn moea64_vsid_bitmap[0] |= 1; 1093209975Snwhitehorn #endif 1094190681Snwhitehorn 1095190681Snwhitehorn /* 1096190681Snwhitehorn * Initialize the kernel pmap (which is statically allocated). 1097190681Snwhitehorn */ 1098209975Snwhitehorn #ifdef __powerpc64__ 1099209975Snwhitehorn for (i = 0; i < 64; i++) { 1100209975Snwhitehorn pcpup->pc_slb[i].slbv = 0; 1101209975Snwhitehorn pcpup->pc_slb[i].slbe = 0; 1102209975Snwhitehorn } 1103209975Snwhitehorn #else 1104190681Snwhitehorn for (i = 0; i < 16; i++) 1105190681Snwhitehorn kernel_pmap->pm_sr[i] = EMPTY_SEGMENT + i; 1106209975Snwhitehorn #endif 1107190681Snwhitehorn 1108190681Snwhitehorn kernel_pmap->pmap_phys = kernel_pmap; 1109190681Snwhitehorn kernel_pmap->pm_active = ~0; 1110190681Snwhitehorn 1111190681Snwhitehorn PMAP_LOCK_INIT(kernel_pmap); 1112190681Snwhitehorn 1113190681Snwhitehorn /* 1114190681Snwhitehorn * Now map in all the other buffers we allocated earlier 1115190681Snwhitehorn */ 1116190681Snwhitehorn 1117209975Snwhitehorn moea64_setup_direct_map(mmup, kernelstart, kernelend); 1118190681Snwhitehorn 1119190681Snwhitehorn /* 1120209975Snwhitehorn * Set up the Open Firmware pmap and add its mappings if not in real 1121209975Snwhitehorn * mode. 1122190681Snwhitehorn */ 1123190681Snwhitehorn 1124190681Snwhitehorn if (!ofw_real_mode) { 1125209975Snwhitehorn #ifndef __powerpc64__ 1126209975Snwhitehorn moea64_pinit(mmup, &ofw_pmap); 1127190681Snwhitehorn 1128204128Snwhitehorn for (i = 0; i < 16; i++) 1129204128Snwhitehorn ofw_pmap.pm_sr[i] = kernel_pmap->pm_sr[i]; 1130209975Snwhitehorn #endif 1131190681Snwhitehorn 1132190681Snwhitehorn if ((chosen = OF_finddevice("/chosen")) == -1) 1133190681Snwhitehorn panic("moea64_bootstrap: can't find /chosen"); 1134190681Snwhitehorn OF_getprop(chosen, "mmu", &mmui, 4); 1135209975Snwhitehorn 1136190681Snwhitehorn if ((mmu = OF_instance_to_package(mmui)) == -1) 1137190681Snwhitehorn panic("moea64_bootstrap: can't get mmu package"); 1138190681Snwhitehorn if ((sz = OF_getproplen(mmu, "translations")) == -1) 1139190681Snwhitehorn panic("moea64_bootstrap: can't get ofw translation count"); 1140199226Snwhitehorn if (sz > 6144 /* tmpstksz - 2 KB headroom */) 1141199226Snwhitehorn panic("moea64_bootstrap: too many ofw translations"); 1142190681Snwhitehorn 1143199226Snwhitehorn moea64_add_ofw_mappings(mmup, mmu, sz); 1144190681Snwhitehorn } 1145190681Snwhitehorn 1146190681Snwhitehorn#ifdef SMP 1147190681Snwhitehorn TLBSYNC(); 1148190681Snwhitehorn#endif 1149190681Snwhitehorn 1150190681Snwhitehorn /* 1151190681Snwhitehorn * Calculate the last available physical address. 1152190681Snwhitehorn */ 1153190681Snwhitehorn for (i = 0; phys_avail[i + 2] != 0; i += 2) 1154190681Snwhitehorn ; 1155190681Snwhitehorn Maxmem = powerpc_btop(phys_avail[i + 1]); 1156190681Snwhitehorn 1157190681Snwhitehorn /* 1158190681Snwhitehorn * Initialize MMU and remap early physical mappings 1159190681Snwhitehorn */ 1160209975Snwhitehorn moea64_cpu_bootstrap(mmup,0); 1161190681Snwhitehorn mtmsr(mfmsr() | PSL_DR | PSL_IR); isync(); 1162190681Snwhitehorn pmap_bootstrapped++; 1163190681Snwhitehorn bs_remap_earlyboot(); 1164190681Snwhitehorn 1165190681Snwhitehorn /* 1166190681Snwhitehorn * Set the start and end of kva. 1167190681Snwhitehorn */ 1168190681Snwhitehorn virtual_avail = VM_MIN_KERNEL_ADDRESS; 1169204128Snwhitehorn virtual_end = VM_MAX_SAFE_KERNEL_ADDRESS; 1170190681Snwhitehorn 1171190681Snwhitehorn /* 1172209975Snwhitehorn * Map the entire KVA range into the SLB. We must not fault there. 1173209975Snwhitehorn */ 1174209975Snwhitehorn #ifdef __powerpc64__ 1175209975Snwhitehorn for (va = virtual_avail; va < virtual_end; va += SEGMENT_LENGTH) 1176209975Snwhitehorn moea64_bootstrap_slb_prefault(va, 0); 1177209975Snwhitehorn #endif 1178209975Snwhitehorn 1179209975Snwhitehorn /* 1180204128Snwhitehorn * Figure out how far we can extend virtual_end into segment 16 1181204128Snwhitehorn * without running into existing mappings. Segment 16 is guaranteed 1182204128Snwhitehorn * to contain neither RAM nor devices (at least on Apple hardware), 1183204128Snwhitehorn * but will generally contain some OFW mappings we should not 1184204128Snwhitehorn * step on. 1185190681Snwhitehorn */ 1186190681Snwhitehorn 1187209975Snwhitehorn #ifndef __powerpc64__ /* KVA is in high memory on PPC64 */ 1188204128Snwhitehorn PMAP_LOCK(kernel_pmap); 1189209975Snwhitehorn while (virtual_end < VM_MAX_KERNEL_ADDRESS && 1190209975Snwhitehorn moea64_pvo_find_va(kernel_pmap, virtual_end+1) == NULL) 1191204128Snwhitehorn virtual_end += PAGE_SIZE; 1192204128Snwhitehorn PMAP_UNLOCK(kernel_pmap); 1193209975Snwhitehorn #endif 1194190681Snwhitehorn 1195190681Snwhitehorn /* 1196204694Snwhitehorn * Allocate some things for page zeroing. We put this directly 1197204694Snwhitehorn * in the page table, marked with LPTE_LOCKED, to avoid any 1198204694Snwhitehorn * of the PVO book-keeping or other parts of the VM system 1199204694Snwhitehorn * from even knowing that this hack exists. 1200190681Snwhitehorn */ 1201190681Snwhitehorn 1202209975Snwhitehorn if (!hw_direct_map) { 1203209975Snwhitehorn mtx_init(&moea64_scratchpage_mtx, "pvo zero page", NULL, 1204209975Snwhitehorn MTX_DEF); 1205209975Snwhitehorn for (i = 0; i < 2; i++) { 1206209975Snwhitehorn struct lpte pt; 1207209975Snwhitehorn uint64_t vsid; 1208209975Snwhitehorn int pteidx, ptegidx; 1209204694Snwhitehorn 1210209975Snwhitehorn moea64_scratchpage_va[i] = (virtual_end+1) - PAGE_SIZE; 1211209975Snwhitehorn virtual_end -= PAGE_SIZE; 1212190681Snwhitehorn 1213209975Snwhitehorn LOCK_TABLE(); 1214209975Snwhitehorn 1215209975Snwhitehorn vsid = va_to_vsid(kernel_pmap, 1216209975Snwhitehorn moea64_scratchpage_va[i]); 1217209975Snwhitehorn moea64_pte_create(&pt, vsid, moea64_scratchpage_va[i], 1218209975Snwhitehorn LPTE_NOEXEC, 0); 1219209975Snwhitehorn pt.pte_hi |= LPTE_LOCKED; 1220190681Snwhitehorn 1221209975Snwhitehorn moea64_scratchpage_vpn[i] = (vsid << 16) | 1222209975Snwhitehorn ((moea64_scratchpage_va[i] & ADDR_PIDX) >> 1223209975Snwhitehorn ADDR_PIDX_SHFT); 1224209975Snwhitehorn ptegidx = va_to_pteg(vsid, moea64_scratchpage_va[i], 0); 1225209975Snwhitehorn pteidx = moea64_pte_insert(ptegidx, &pt); 1226209975Snwhitehorn if (pt.pte_hi & LPTE_HID) 1227209975Snwhitehorn ptegidx ^= moea64_pteg_mask; 1228204694Snwhitehorn 1229209975Snwhitehorn moea64_scratchpage_pte[i] = 1230209975Snwhitehorn &moea64_pteg_table[ptegidx].pt[pteidx]; 1231204694Snwhitehorn 1232209975Snwhitehorn UNLOCK_TABLE(); 1233209975Snwhitehorn } 1234190681Snwhitehorn } 1235190681Snwhitehorn 1236190681Snwhitehorn /* 1237190681Snwhitehorn * Allocate a kernel stack with a guard page for thread0 and map it 1238190681Snwhitehorn * into the kernel page map. 1239190681Snwhitehorn */ 1240190681Snwhitehorn pa = moea64_bootstrap_alloc(KSTACK_PAGES * PAGE_SIZE, PAGE_SIZE); 1241190681Snwhitehorn va = virtual_avail + KSTACK_GUARD_PAGES * PAGE_SIZE; 1242190681Snwhitehorn virtual_avail = va + KSTACK_PAGES * PAGE_SIZE; 1243190681Snwhitehorn CTR2(KTR_PMAP, "moea_bootstrap: kstack0 at %#x (%#x)", pa, va); 1244190681Snwhitehorn thread0.td_kstack = va; 1245190681Snwhitehorn thread0.td_kstack_pages = KSTACK_PAGES; 1246190681Snwhitehorn for (i = 0; i < KSTACK_PAGES; i++) { 1247201758Smbr moea64_kenter(mmup, va, pa); 1248190681Snwhitehorn pa += PAGE_SIZE; 1249190681Snwhitehorn va += PAGE_SIZE; 1250190681Snwhitehorn } 1251190681Snwhitehorn 1252190681Snwhitehorn /* 1253190681Snwhitehorn * Allocate virtual address space for the message buffer. 1254190681Snwhitehorn */ 1255190681Snwhitehorn pa = msgbuf_phys = moea64_bootstrap_alloc(MSGBUF_SIZE, PAGE_SIZE); 1256204297Snwhitehorn msgbufp = (struct msgbuf *)virtual_avail; 1257204297Snwhitehorn va = virtual_avail; 1258204297Snwhitehorn virtual_avail += round_page(MSGBUF_SIZE); 1259204297Snwhitehorn while (va < virtual_avail) { 1260204297Snwhitehorn moea64_kenter(mmup, va, pa); 1261190681Snwhitehorn pa += PAGE_SIZE; 1262204297Snwhitehorn va += PAGE_SIZE; 1263190681Snwhitehorn } 1264194784Sjeff 1265194784Sjeff /* 1266194784Sjeff * Allocate virtual address space for the dynamic percpu area. 1267194784Sjeff */ 1268194784Sjeff pa = moea64_bootstrap_alloc(DPCPU_SIZE, PAGE_SIZE); 1269204297Snwhitehorn dpcpu = (void *)virtual_avail; 1270209975Snwhitehorn va = virtual_avail; 1271204297Snwhitehorn virtual_avail += DPCPU_SIZE; 1272204297Snwhitehorn while (va < virtual_avail) { 1273204297Snwhitehorn moea64_kenter(mmup, va, pa); 1274194784Sjeff pa += PAGE_SIZE; 1275204297Snwhitehorn va += PAGE_SIZE; 1276194784Sjeff } 1277194784Sjeff dpcpu_init(dpcpu, 0); 1278190681Snwhitehorn} 1279190681Snwhitehorn 1280190681Snwhitehorn/* 1281209975Snwhitehorn * Activate a user pmap. The pmap must be activated before its address 1282190681Snwhitehorn * space can be accessed in any way. 1283190681Snwhitehorn */ 1284190681Snwhitehornvoid 1285190681Snwhitehornmoea64_activate(mmu_t mmu, struct thread *td) 1286190681Snwhitehorn{ 1287209975Snwhitehorn pmap_t pm; 1288190681Snwhitehorn 1289190681Snwhitehorn pm = &td->td_proc->p_vmspace->vm_pmap; 1290209975Snwhitehorn pm->pm_active |= PCPU_GET(cpumask); 1291190681Snwhitehorn 1292209975Snwhitehorn #ifdef __powerpc64__ 1293209975Snwhitehorn PCPU_SET(userslb, pm->pm_slb); 1294209975Snwhitehorn #else 1295209975Snwhitehorn PCPU_SET(curpmap, pm->pmap_phys); 1296209975Snwhitehorn #endif 1297190681Snwhitehorn} 1298190681Snwhitehorn 1299190681Snwhitehornvoid 1300190681Snwhitehornmoea64_deactivate(mmu_t mmu, struct thread *td) 1301190681Snwhitehorn{ 1302190681Snwhitehorn pmap_t pm; 1303190681Snwhitehorn 1304190681Snwhitehorn pm = &td->td_proc->p_vmspace->vm_pmap; 1305190681Snwhitehorn pm->pm_active &= ~(PCPU_GET(cpumask)); 1306209975Snwhitehorn #ifdef __powerpc64__ 1307209975Snwhitehorn PCPU_SET(userslb, NULL); 1308209975Snwhitehorn #else 1309190681Snwhitehorn PCPU_SET(curpmap, NULL); 1310209975Snwhitehorn #endif 1311190681Snwhitehorn} 1312190681Snwhitehorn 1313190681Snwhitehornvoid 1314190681Snwhitehornmoea64_change_wiring(mmu_t mmu, pmap_t pm, vm_offset_t va, boolean_t wired) 1315190681Snwhitehorn{ 1316190681Snwhitehorn struct pvo_entry *pvo; 1317209975Snwhitehorn struct lpte *pt; 1318209975Snwhitehorn uint64_t vsid; 1319209975Snwhitehorn int i, ptegidx; 1320190681Snwhitehorn 1321190681Snwhitehorn PMAP_LOCK(pm); 1322209975Snwhitehorn pvo = moea64_pvo_find_va(pm, va & ~ADDR_POFF); 1323190681Snwhitehorn 1324190681Snwhitehorn if (pvo != NULL) { 1325209975Snwhitehorn LOCK_TABLE(); 1326209975Snwhitehorn pt = moea64_pvo_to_pte(pvo); 1327209975Snwhitehorn 1328190681Snwhitehorn if (wired) { 1329190681Snwhitehorn if ((pvo->pvo_vaddr & PVO_WIRED) == 0) 1330190681Snwhitehorn pm->pm_stats.wired_count++; 1331190681Snwhitehorn pvo->pvo_vaddr |= PVO_WIRED; 1332209975Snwhitehorn pvo->pvo_pte.lpte.pte_hi |= LPTE_WIRED; 1333190681Snwhitehorn } else { 1334190681Snwhitehorn if ((pvo->pvo_vaddr & PVO_WIRED) != 0) 1335190681Snwhitehorn pm->pm_stats.wired_count--; 1336190681Snwhitehorn pvo->pvo_vaddr &= ~PVO_WIRED; 1337209975Snwhitehorn pvo->pvo_pte.lpte.pte_hi &= ~LPTE_WIRED; 1338190681Snwhitehorn } 1339209975Snwhitehorn 1340209975Snwhitehorn if (pt != NULL) { 1341209975Snwhitehorn /* Update wiring flag in page table. */ 1342209975Snwhitehorn moea64_pte_change(pt, &pvo->pvo_pte.lpte, 1343209975Snwhitehorn pvo->pvo_vpn); 1344209975Snwhitehorn } else if (wired) { 1345209975Snwhitehorn /* 1346209975Snwhitehorn * If we are wiring the page, and it wasn't in the 1347209975Snwhitehorn * page table before, add it. 1348209975Snwhitehorn */ 1349209975Snwhitehorn vsid = PVO_VSID(pvo); 1350209975Snwhitehorn ptegidx = va_to_pteg(vsid, PVO_VADDR(pvo), 1351209975Snwhitehorn pvo->pvo_vaddr & PVO_LARGE); 1352209975Snwhitehorn 1353209975Snwhitehorn i = moea64_pte_insert(ptegidx, &pvo->pvo_pte.lpte); 1354209975Snwhitehorn if (i >= 0) { 1355209975Snwhitehorn PVO_PTEGIDX_CLR(pvo); 1356209975Snwhitehorn PVO_PTEGIDX_SET(pvo, i); 1357209975Snwhitehorn } 1358209975Snwhitehorn } 1359209975Snwhitehorn 1360209975Snwhitehorn UNLOCK_TABLE(); 1361190681Snwhitehorn } 1362190681Snwhitehorn PMAP_UNLOCK(pm); 1363190681Snwhitehorn} 1364190681Snwhitehorn 1365190681Snwhitehorn/* 1366190681Snwhitehorn * This goes through and sets the physical address of our 1367190681Snwhitehorn * special scratch PTE to the PA we want to zero or copy. Because 1368190681Snwhitehorn * of locking issues (this can get called in pvo_enter() by 1369190681Snwhitehorn * the UMA allocator), we can't use most other utility functions here 1370190681Snwhitehorn */ 1371190681Snwhitehorn 1372190681Snwhitehornstatic __inline 1373190681Snwhitehornvoid moea64_set_scratchpage_pa(int which, vm_offset_t pa) { 1374204694Snwhitehorn 1375209975Snwhitehorn KASSERT(!hw_direct_map, ("Using OEA64 scratchpage with a direct map!")); 1376204268Snwhitehorn mtx_assert(&moea64_scratchpage_mtx, MA_OWNED); 1377204268Snwhitehorn 1378190681Snwhitehorn moea64_scratchpage_pte[which]->pte_hi &= ~LPTE_VALID; 1379209975Snwhitehorn TLBIE(moea64_scratchpage_vpn[which]); 1380190681Snwhitehorn 1381204694Snwhitehorn moea64_scratchpage_pte[which]->pte_lo &= 1382204694Snwhitehorn ~(LPTE_WIMG | LPTE_RPGN); 1383204694Snwhitehorn moea64_scratchpage_pte[which]->pte_lo |= 1384204694Snwhitehorn moea64_calc_wimg(pa) | (uint64_t)pa; 1385190681Snwhitehorn EIEIO(); 1386190681Snwhitehorn 1387190681Snwhitehorn moea64_scratchpage_pte[which]->pte_hi |= LPTE_VALID; 1388204042Snwhitehorn PTESYNC(); isync(); 1389190681Snwhitehorn} 1390190681Snwhitehorn 1391190681Snwhitehornvoid 1392190681Snwhitehornmoea64_copy_page(mmu_t mmu, vm_page_t msrc, vm_page_t mdst) 1393190681Snwhitehorn{ 1394190681Snwhitehorn vm_offset_t dst; 1395190681Snwhitehorn vm_offset_t src; 1396190681Snwhitehorn 1397190681Snwhitehorn dst = VM_PAGE_TO_PHYS(mdst); 1398190681Snwhitehorn src = VM_PAGE_TO_PHYS(msrc); 1399190681Snwhitehorn 1400209975Snwhitehorn if (hw_direct_map) { 1401209975Snwhitehorn kcopy((void *)src, (void *)dst, PAGE_SIZE); 1402209975Snwhitehorn } else { 1403209975Snwhitehorn mtx_lock(&moea64_scratchpage_mtx); 1404190681Snwhitehorn 1405209975Snwhitehorn moea64_set_scratchpage_pa(0,src); 1406209975Snwhitehorn moea64_set_scratchpage_pa(1,dst); 1407190681Snwhitehorn 1408209975Snwhitehorn kcopy((void *)moea64_scratchpage_va[0], 1409209975Snwhitehorn (void *)moea64_scratchpage_va[1], PAGE_SIZE); 1410190681Snwhitehorn 1411209975Snwhitehorn mtx_unlock(&moea64_scratchpage_mtx); 1412209975Snwhitehorn } 1413190681Snwhitehorn} 1414190681Snwhitehorn 1415190681Snwhitehornvoid 1416190681Snwhitehornmoea64_zero_page_area(mmu_t mmu, vm_page_t m, int off, int size) 1417190681Snwhitehorn{ 1418190681Snwhitehorn vm_offset_t pa = VM_PAGE_TO_PHYS(m); 1419190681Snwhitehorn 1420190681Snwhitehorn if (!moea64_initialized) 1421209975Snwhitehorn panic("moea64_zero_page: can't zero pa %#" PRIxPTR, pa); 1422190681Snwhitehorn if (size + off > PAGE_SIZE) 1423190681Snwhitehorn panic("moea64_zero_page: size + off > PAGE_SIZE"); 1424190681Snwhitehorn 1425209975Snwhitehorn if (hw_direct_map) { 1426209975Snwhitehorn bzero((caddr_t)pa + off, size); 1427209975Snwhitehorn } else { 1428209975Snwhitehorn mtx_lock(&moea64_scratchpage_mtx); 1429209975Snwhitehorn moea64_set_scratchpage_pa(0,pa); 1430209975Snwhitehorn bzero((caddr_t)moea64_scratchpage_va[0] + off, size); 1431209975Snwhitehorn mtx_unlock(&moea64_scratchpage_mtx); 1432209975Snwhitehorn } 1433190681Snwhitehorn} 1434190681Snwhitehorn 1435204269Snwhitehorn/* 1436204269Snwhitehorn * Zero a page of physical memory by temporarily mapping it 1437204269Snwhitehorn */ 1438190681Snwhitehornvoid 1439204269Snwhitehornmoea64_zero_page(mmu_t mmu, vm_page_t m) 1440204269Snwhitehorn{ 1441204269Snwhitehorn vm_offset_t pa = VM_PAGE_TO_PHYS(m); 1442209975Snwhitehorn vm_offset_t va, off; 1443204269Snwhitehorn 1444204269Snwhitehorn if (!moea64_initialized) 1445209975Snwhitehorn panic("moea64_zero_page: can't zero pa %#zx", pa); 1446204269Snwhitehorn 1447209975Snwhitehorn if (!hw_direct_map) { 1448209975Snwhitehorn mtx_lock(&moea64_scratchpage_mtx); 1449204269Snwhitehorn 1450209975Snwhitehorn moea64_set_scratchpage_pa(0,pa); 1451209975Snwhitehorn va = moea64_scratchpage_va[0]; 1452209975Snwhitehorn } else { 1453209975Snwhitehorn va = pa; 1454209975Snwhitehorn } 1455209975Snwhitehorn 1456204269Snwhitehorn for (off = 0; off < PAGE_SIZE; off += cacheline_size) 1457209975Snwhitehorn __asm __volatile("dcbz 0,%0" :: "r"(va + off)); 1458209975Snwhitehorn 1459209975Snwhitehorn if (!hw_direct_map) 1460209975Snwhitehorn mtx_unlock(&moea64_scratchpage_mtx); 1461204269Snwhitehorn} 1462204269Snwhitehorn 1463204269Snwhitehornvoid 1464190681Snwhitehornmoea64_zero_page_idle(mmu_t mmu, vm_page_t m) 1465190681Snwhitehorn{ 1466190681Snwhitehorn 1467190681Snwhitehorn moea64_zero_page(mmu, m); 1468190681Snwhitehorn} 1469190681Snwhitehorn 1470190681Snwhitehorn/* 1471190681Snwhitehorn * Map the given physical page at the specified virtual address in the 1472190681Snwhitehorn * target pmap with the protection requested. If specified the page 1473190681Snwhitehorn * will be wired down. 1474190681Snwhitehorn */ 1475190681Snwhitehornvoid 1476190681Snwhitehornmoea64_enter(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, 1477190681Snwhitehorn vm_prot_t prot, boolean_t wired) 1478190681Snwhitehorn{ 1479190681Snwhitehorn 1480190681Snwhitehorn vm_page_lock_queues(); 1481190681Snwhitehorn PMAP_LOCK(pmap); 1482190681Snwhitehorn moea64_enter_locked(pmap, va, m, prot, wired); 1483190681Snwhitehorn vm_page_unlock_queues(); 1484190681Snwhitehorn PMAP_UNLOCK(pmap); 1485190681Snwhitehorn} 1486190681Snwhitehorn 1487190681Snwhitehorn/* 1488190681Snwhitehorn * Map the given physical page at the specified virtual address in the 1489190681Snwhitehorn * target pmap with the protection requested. If specified the page 1490190681Snwhitehorn * will be wired down. 1491190681Snwhitehorn * 1492190681Snwhitehorn * The page queues and pmap must be locked. 1493190681Snwhitehorn */ 1494190681Snwhitehorn 1495190681Snwhitehornstatic void 1496190681Snwhitehornmoea64_enter_locked(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot, 1497190681Snwhitehorn boolean_t wired) 1498190681Snwhitehorn{ 1499190681Snwhitehorn struct pvo_head *pvo_head; 1500190681Snwhitehorn uma_zone_t zone; 1501190681Snwhitehorn vm_page_t pg; 1502190681Snwhitehorn uint64_t pte_lo; 1503190681Snwhitehorn u_int pvo_flags; 1504190681Snwhitehorn int error; 1505190681Snwhitehorn 1506190681Snwhitehorn if (!moea64_initialized) { 1507190681Snwhitehorn pvo_head = &moea64_pvo_kunmanaged; 1508190681Snwhitehorn pg = NULL; 1509190681Snwhitehorn zone = moea64_upvo_zone; 1510190681Snwhitehorn pvo_flags = 0; 1511190681Snwhitehorn } else { 1512190681Snwhitehorn pvo_head = vm_page_to_pvoh(m); 1513190681Snwhitehorn pg = m; 1514190681Snwhitehorn zone = moea64_mpvo_zone; 1515190681Snwhitehorn pvo_flags = PVO_MANAGED; 1516190681Snwhitehorn } 1517190681Snwhitehorn 1518190681Snwhitehorn if (pmap_bootstrapped) 1519190681Snwhitehorn mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1520190681Snwhitehorn PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1521209048Salc KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0 || 1522209048Salc (m->oflags & VPO_BUSY) != 0 || VM_OBJECT_LOCKED(m->object), 1523208175Salc ("moea64_enter_locked: page %p is not busy", m)); 1524190681Snwhitehorn 1525190681Snwhitehorn /* XXX change the pvo head for fake pages */ 1526190681Snwhitehorn if ((m->flags & PG_FICTITIOUS) == PG_FICTITIOUS) { 1527190681Snwhitehorn pvo_flags &= ~PVO_MANAGED; 1528190681Snwhitehorn pvo_head = &moea64_pvo_kunmanaged; 1529190681Snwhitehorn zone = moea64_upvo_zone; 1530190681Snwhitehorn } 1531190681Snwhitehorn 1532190681Snwhitehorn pte_lo = moea64_calc_wimg(VM_PAGE_TO_PHYS(m)); 1533190681Snwhitehorn 1534190681Snwhitehorn if (prot & VM_PROT_WRITE) { 1535190681Snwhitehorn pte_lo |= LPTE_BW; 1536208810Salc if (pmap_bootstrapped && 1537208810Salc (m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0) 1538190681Snwhitehorn vm_page_flag_set(m, PG_WRITEABLE); 1539190681Snwhitehorn } else 1540190681Snwhitehorn pte_lo |= LPTE_BR; 1541190681Snwhitehorn 1542190681Snwhitehorn if (prot & VM_PROT_EXECUTE) 1543190681Snwhitehorn pvo_flags |= VM_PROT_EXECUTE; 1544190681Snwhitehorn 1545190681Snwhitehorn if (wired) 1546190681Snwhitehorn pvo_flags |= PVO_WIRED; 1547190681Snwhitehorn 1548190681Snwhitehorn if ((m->flags & PG_FICTITIOUS) != 0) 1549190681Snwhitehorn pvo_flags |= PVO_FAKE; 1550190681Snwhitehorn 1551190681Snwhitehorn error = moea64_pvo_enter(pmap, zone, pvo_head, va, VM_PAGE_TO_PHYS(m), 1552198378Snwhitehorn pte_lo, pvo_flags); 1553190681Snwhitehorn 1554190681Snwhitehorn /* 1555190681Snwhitehorn * Flush the page from the instruction cache if this page is 1556190681Snwhitehorn * mapped executable and cacheable. 1557190681Snwhitehorn */ 1558190681Snwhitehorn if ((pte_lo & (LPTE_I | LPTE_G | LPTE_NOEXEC)) == 0) { 1559198341Smarcel moea64_syncicache(pmap, va, VM_PAGE_TO_PHYS(m), PAGE_SIZE); 1560190681Snwhitehorn } 1561190681Snwhitehorn} 1562190681Snwhitehorn 1563190681Snwhitehornstatic void 1564198341Smarcelmoea64_syncicache(pmap_t pmap, vm_offset_t va, vm_offset_t pa, vm_size_t sz) 1565190681Snwhitehorn{ 1566204042Snwhitehorn 1567190681Snwhitehorn /* 1568190681Snwhitehorn * This is much trickier than on older systems because 1569190681Snwhitehorn * we can't sync the icache on physical addresses directly 1570190681Snwhitehorn * without a direct map. Instead we check a couple of cases 1571190681Snwhitehorn * where the memory is already mapped in and, failing that, 1572190681Snwhitehorn * use the same trick we use for page zeroing to create 1573190681Snwhitehorn * a temporary mapping for this physical address. 1574190681Snwhitehorn */ 1575190681Snwhitehorn 1576190681Snwhitehorn if (!pmap_bootstrapped) { 1577190681Snwhitehorn /* 1578190681Snwhitehorn * If PMAP is not bootstrapped, we are likely to be 1579190681Snwhitehorn * in real mode. 1580190681Snwhitehorn */ 1581198341Smarcel __syncicache((void *)pa, sz); 1582190681Snwhitehorn } else if (pmap == kernel_pmap) { 1583198341Smarcel __syncicache((void *)va, sz); 1584209975Snwhitehorn } else if (hw_direct_map) { 1585209975Snwhitehorn __syncicache((void *)pa, sz); 1586190681Snwhitehorn } else { 1587190681Snwhitehorn /* Use the scratch page to set up a temp mapping */ 1588190681Snwhitehorn 1589190681Snwhitehorn mtx_lock(&moea64_scratchpage_mtx); 1590190681Snwhitehorn 1591204042Snwhitehorn moea64_set_scratchpage_pa(1,pa & ~ADDR_POFF); 1592204042Snwhitehorn __syncicache((void *)(moea64_scratchpage_va[1] + 1593204042Snwhitehorn (va & ADDR_POFF)), sz); 1594190681Snwhitehorn 1595190681Snwhitehorn mtx_unlock(&moea64_scratchpage_mtx); 1596190681Snwhitehorn } 1597190681Snwhitehorn} 1598190681Snwhitehorn 1599190681Snwhitehorn/* 1600190681Snwhitehorn * Maps a sequence of resident pages belonging to the same object. 1601190681Snwhitehorn * The sequence begins with the given page m_start. This page is 1602190681Snwhitehorn * mapped at the given virtual address start. Each subsequent page is 1603190681Snwhitehorn * mapped at a virtual address that is offset from start by the same 1604190681Snwhitehorn * amount as the page is offset from m_start within the object. The 1605190681Snwhitehorn * last page in the sequence is the page with the largest offset from 1606190681Snwhitehorn * m_start that can be mapped at a virtual address less than the given 1607190681Snwhitehorn * virtual address end. Not every virtual page between start and end 1608190681Snwhitehorn * is mapped; only those for which a resident page exists with the 1609190681Snwhitehorn * corresponding offset from m_start are mapped. 1610190681Snwhitehorn */ 1611190681Snwhitehornvoid 1612190681Snwhitehornmoea64_enter_object(mmu_t mmu, pmap_t pm, vm_offset_t start, vm_offset_t end, 1613190681Snwhitehorn vm_page_t m_start, vm_prot_t prot) 1614190681Snwhitehorn{ 1615190681Snwhitehorn vm_page_t m; 1616190681Snwhitehorn vm_pindex_t diff, psize; 1617190681Snwhitehorn 1618190681Snwhitehorn psize = atop(end - start); 1619190681Snwhitehorn m = m_start; 1620208574Salc vm_page_lock_queues(); 1621190681Snwhitehorn PMAP_LOCK(pm); 1622190681Snwhitehorn while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 1623190681Snwhitehorn moea64_enter_locked(pm, start + ptoa(diff), m, prot & 1624190681Snwhitehorn (VM_PROT_READ | VM_PROT_EXECUTE), FALSE); 1625190681Snwhitehorn m = TAILQ_NEXT(m, listq); 1626190681Snwhitehorn } 1627208574Salc vm_page_unlock_queues(); 1628190681Snwhitehorn PMAP_UNLOCK(pm); 1629190681Snwhitehorn} 1630190681Snwhitehorn 1631190681Snwhitehornvoid 1632190681Snwhitehornmoea64_enter_quick(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_page_t m, 1633190681Snwhitehorn vm_prot_t prot) 1634190681Snwhitehorn{ 1635207796Salc 1636207796Salc vm_page_lock_queues(); 1637190681Snwhitehorn PMAP_LOCK(pm); 1638190681Snwhitehorn moea64_enter_locked(pm, va, m, prot & (VM_PROT_READ | VM_PROT_EXECUTE), 1639190681Snwhitehorn FALSE); 1640207796Salc vm_page_unlock_queues(); 1641190681Snwhitehorn PMAP_UNLOCK(pm); 1642190681Snwhitehorn} 1643190681Snwhitehorn 1644190681Snwhitehornvm_paddr_t 1645190681Snwhitehornmoea64_extract(mmu_t mmu, pmap_t pm, vm_offset_t va) 1646190681Snwhitehorn{ 1647190681Snwhitehorn struct pvo_entry *pvo; 1648190681Snwhitehorn vm_paddr_t pa; 1649190681Snwhitehorn 1650190681Snwhitehorn PMAP_LOCK(pm); 1651209975Snwhitehorn pvo = moea64_pvo_find_va(pm, va); 1652190681Snwhitehorn if (pvo == NULL) 1653190681Snwhitehorn pa = 0; 1654190681Snwhitehorn else 1655209975Snwhitehorn pa = (pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN) | 1656209975Snwhitehorn (va - PVO_VADDR(pvo)); 1657190681Snwhitehorn PMAP_UNLOCK(pm); 1658190681Snwhitehorn return (pa); 1659190681Snwhitehorn} 1660190681Snwhitehorn 1661190681Snwhitehorn/* 1662190681Snwhitehorn * Atomically extract and hold the physical page with the given 1663190681Snwhitehorn * pmap and virtual address pair if that mapping permits the given 1664190681Snwhitehorn * protection. 1665190681Snwhitehorn */ 1666190681Snwhitehornvm_page_t 1667190681Snwhitehornmoea64_extract_and_hold(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_prot_t prot) 1668190681Snwhitehorn{ 1669190681Snwhitehorn struct pvo_entry *pvo; 1670190681Snwhitehorn vm_page_t m; 1671207410Skmacy vm_paddr_t pa; 1672190681Snwhitehorn 1673190681Snwhitehorn m = NULL; 1674207410Skmacy pa = 0; 1675190681Snwhitehorn PMAP_LOCK(pmap); 1676207410Skmacyretry: 1677209975Snwhitehorn pvo = moea64_pvo_find_va(pmap, va & ~ADDR_POFF); 1678190681Snwhitehorn if (pvo != NULL && (pvo->pvo_pte.lpte.pte_hi & LPTE_VALID) && 1679190681Snwhitehorn ((pvo->pvo_pte.lpte.pte_lo & LPTE_PP) == LPTE_RW || 1680190681Snwhitehorn (prot & VM_PROT_WRITE) == 0)) { 1681207410Skmacy if (vm_page_pa_tryrelock(pmap, 1682207410Skmacy pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN, &pa)) 1683207410Skmacy goto retry; 1684190681Snwhitehorn m = PHYS_TO_VM_PAGE(pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN); 1685190681Snwhitehorn vm_page_hold(m); 1686190681Snwhitehorn } 1687207410Skmacy PA_UNLOCK_COND(pa); 1688190681Snwhitehorn PMAP_UNLOCK(pmap); 1689190681Snwhitehorn return (m); 1690190681Snwhitehorn} 1691190681Snwhitehorn 1692190681Snwhitehornstatic void * 1693190681Snwhitehornmoea64_uma_page_alloc(uma_zone_t zone, int bytes, u_int8_t *flags, int wait) 1694190681Snwhitehorn{ 1695190681Snwhitehorn /* 1696190681Snwhitehorn * This entire routine is a horrible hack to avoid bothering kmem 1697190681Snwhitehorn * for new KVA addresses. Because this can get called from inside 1698190681Snwhitehorn * kmem allocation routines, calling kmem for a new address here 1699190681Snwhitehorn * can lead to multiply locking non-recursive mutexes. 1700190681Snwhitehorn */ 1701190681Snwhitehorn static vm_pindex_t color; 1702190681Snwhitehorn vm_offset_t va; 1703190681Snwhitehorn 1704190681Snwhitehorn vm_page_t m; 1705190681Snwhitehorn int pflags, needed_lock; 1706190681Snwhitehorn 1707190681Snwhitehorn *flags = UMA_SLAB_PRIV; 1708190681Snwhitehorn needed_lock = !PMAP_LOCKED(kernel_pmap); 1709190681Snwhitehorn 1710190681Snwhitehorn if (needed_lock) 1711190681Snwhitehorn PMAP_LOCK(kernel_pmap); 1712190681Snwhitehorn 1713190681Snwhitehorn if ((wait & (M_NOWAIT|M_USE_RESERVE)) == M_NOWAIT) 1714190681Snwhitehorn pflags = VM_ALLOC_INTERRUPT | VM_ALLOC_WIRED; 1715190681Snwhitehorn else 1716190681Snwhitehorn pflags = VM_ALLOC_SYSTEM | VM_ALLOC_WIRED; 1717190681Snwhitehorn if (wait & M_ZERO) 1718190681Snwhitehorn pflags |= VM_ALLOC_ZERO; 1719190681Snwhitehorn 1720190681Snwhitehorn for (;;) { 1721190681Snwhitehorn m = vm_page_alloc(NULL, color++, pflags | VM_ALLOC_NOOBJ); 1722190681Snwhitehorn if (m == NULL) { 1723190681Snwhitehorn if (wait & M_NOWAIT) 1724190681Snwhitehorn return (NULL); 1725190681Snwhitehorn VM_WAIT; 1726190681Snwhitehorn } else 1727190681Snwhitehorn break; 1728190681Snwhitehorn } 1729190681Snwhitehorn 1730204128Snwhitehorn va = VM_PAGE_TO_PHYS(m); 1731190681Snwhitehorn 1732190681Snwhitehorn moea64_pvo_enter(kernel_pmap, moea64_upvo_zone, 1733204128Snwhitehorn &moea64_pvo_kunmanaged, va, VM_PAGE_TO_PHYS(m), LPTE_M, 1734198378Snwhitehorn PVO_WIRED | PVO_BOOTSTRAP); 1735190681Snwhitehorn 1736190681Snwhitehorn if (needed_lock) 1737190681Snwhitehorn PMAP_UNLOCK(kernel_pmap); 1738198378Snwhitehorn 1739190681Snwhitehorn if ((wait & M_ZERO) && (m->flags & PG_ZERO) == 0) 1740190681Snwhitehorn bzero((void *)va, PAGE_SIZE); 1741190681Snwhitehorn 1742190681Snwhitehorn return (void *)va; 1743190681Snwhitehorn} 1744190681Snwhitehorn 1745190681Snwhitehornvoid 1746190681Snwhitehornmoea64_init(mmu_t mmu) 1747190681Snwhitehorn{ 1748190681Snwhitehorn 1749190681Snwhitehorn CTR0(KTR_PMAP, "moea64_init"); 1750190681Snwhitehorn 1751190681Snwhitehorn moea64_upvo_zone = uma_zcreate("UPVO entry", sizeof (struct pvo_entry), 1752190681Snwhitehorn NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, 1753190681Snwhitehorn UMA_ZONE_VM | UMA_ZONE_NOFREE); 1754190681Snwhitehorn moea64_mpvo_zone = uma_zcreate("MPVO entry", sizeof(struct pvo_entry), 1755190681Snwhitehorn NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, 1756190681Snwhitehorn UMA_ZONE_VM | UMA_ZONE_NOFREE); 1757190681Snwhitehorn 1758190681Snwhitehorn if (!hw_direct_map) { 1759190681Snwhitehorn uma_zone_set_allocf(moea64_upvo_zone,moea64_uma_page_alloc); 1760190681Snwhitehorn uma_zone_set_allocf(moea64_mpvo_zone,moea64_uma_page_alloc); 1761190681Snwhitehorn } 1762190681Snwhitehorn 1763190681Snwhitehorn moea64_initialized = TRUE; 1764190681Snwhitehorn} 1765190681Snwhitehorn 1766190681Snwhitehornboolean_t 1767207155Salcmoea64_is_referenced(mmu_t mmu, vm_page_t m) 1768207155Salc{ 1769207155Salc 1770208574Salc KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 1771208574Salc ("moea64_is_referenced: page %p is not managed", m)); 1772207155Salc return (moea64_query_bit(m, PTE_REF)); 1773207155Salc} 1774207155Salc 1775207155Salcboolean_t 1776190681Snwhitehornmoea64_is_modified(mmu_t mmu, vm_page_t m) 1777190681Snwhitehorn{ 1778190681Snwhitehorn 1779208504Salc KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 1780208504Salc ("moea64_is_modified: page %p is not managed", m)); 1781208504Salc 1782208504Salc /* 1783208504Salc * If the page is not VPO_BUSY, then PG_WRITEABLE cannot be 1784208504Salc * concurrently set while the object is locked. Thus, if PG_WRITEABLE 1785208504Salc * is clear, no PTEs can have LPTE_CHG set. 1786208504Salc */ 1787208504Salc VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED); 1788208504Salc if ((m->oflags & VPO_BUSY) == 0 && 1789208504Salc (m->flags & PG_WRITEABLE) == 0) 1790190681Snwhitehorn return (FALSE); 1791208574Salc return (moea64_query_bit(m, LPTE_CHG)); 1792190681Snwhitehorn} 1793190681Snwhitehorn 1794190681Snwhitehornvoid 1795190681Snwhitehornmoea64_clear_reference(mmu_t mmu, vm_page_t m) 1796190681Snwhitehorn{ 1797190681Snwhitehorn 1798208504Salc KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 1799208504Salc ("moea64_clear_reference: page %p is not managed", m)); 1800208990Salc moea64_clear_bit(m, LPTE_REF); 1801190681Snwhitehorn} 1802190681Snwhitehorn 1803190681Snwhitehornvoid 1804190681Snwhitehornmoea64_clear_modify(mmu_t mmu, vm_page_t m) 1805190681Snwhitehorn{ 1806190681Snwhitehorn 1807208504Salc KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 1808208504Salc ("moea64_clear_modify: page %p is not managed", m)); 1809208504Salc VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED); 1810208504Salc KASSERT((m->oflags & VPO_BUSY) == 0, 1811208504Salc ("moea64_clear_modify: page %p is busy", m)); 1812208504Salc 1813208504Salc /* 1814208504Salc * If the page is not PG_WRITEABLE, then no PTEs can have LPTE_CHG 1815208504Salc * set. If the object containing the page is locked and the page is 1816208504Salc * not VPO_BUSY, then PG_WRITEABLE cannot be concurrently set. 1817208504Salc */ 1818208504Salc if ((m->flags & PG_WRITEABLE) == 0) 1819190681Snwhitehorn return; 1820208990Salc moea64_clear_bit(m, LPTE_CHG); 1821190681Snwhitehorn} 1822190681Snwhitehorn 1823190681Snwhitehorn/* 1824190681Snwhitehorn * Clear the write and modified bits in each of the given page's mappings. 1825190681Snwhitehorn */ 1826190681Snwhitehornvoid 1827190681Snwhitehornmoea64_remove_write(mmu_t mmu, vm_page_t m) 1828190681Snwhitehorn{ 1829190681Snwhitehorn struct pvo_entry *pvo; 1830190681Snwhitehorn struct lpte *pt; 1831190681Snwhitehorn pmap_t pmap; 1832190681Snwhitehorn uint64_t lo; 1833190681Snwhitehorn 1834208175Salc KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 1835208175Salc ("moea64_remove_write: page %p is not managed", m)); 1836208175Salc 1837208175Salc /* 1838208175Salc * If the page is not VPO_BUSY, then PG_WRITEABLE cannot be set by 1839208175Salc * another thread while the object is locked. Thus, if PG_WRITEABLE 1840208175Salc * is clear, no page table entries need updating. 1841208175Salc */ 1842208175Salc VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED); 1843208175Salc if ((m->oflags & VPO_BUSY) == 0 && 1844190681Snwhitehorn (m->flags & PG_WRITEABLE) == 0) 1845190681Snwhitehorn return; 1846207796Salc vm_page_lock_queues(); 1847190681Snwhitehorn lo = moea64_attr_fetch(m); 1848190681Snwhitehorn SYNC(); 1849190681Snwhitehorn LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1850190681Snwhitehorn pmap = pvo->pvo_pmap; 1851190681Snwhitehorn PMAP_LOCK(pmap); 1852205370Snwhitehorn LOCK_TABLE(); 1853190681Snwhitehorn if ((pvo->pvo_pte.lpte.pte_lo & LPTE_PP) != LPTE_BR) { 1854209975Snwhitehorn pt = moea64_pvo_to_pte(pvo); 1855190681Snwhitehorn pvo->pvo_pte.lpte.pte_lo &= ~LPTE_PP; 1856190681Snwhitehorn pvo->pvo_pte.lpte.pte_lo |= LPTE_BR; 1857190681Snwhitehorn if (pt != NULL) { 1858190681Snwhitehorn moea64_pte_synch(pt, &pvo->pvo_pte.lpte); 1859190681Snwhitehorn lo |= pvo->pvo_pte.lpte.pte_lo; 1860190681Snwhitehorn pvo->pvo_pte.lpte.pte_lo &= ~LPTE_CHG; 1861190681Snwhitehorn moea64_pte_change(pt, &pvo->pvo_pte.lpte, 1862209975Snwhitehorn pvo->pvo_vpn); 1863209975Snwhitehorn if (pvo->pvo_pmap == kernel_pmap) 1864209975Snwhitehorn isync(); 1865190681Snwhitehorn } 1866190681Snwhitehorn } 1867205370Snwhitehorn UNLOCK_TABLE(); 1868190681Snwhitehorn PMAP_UNLOCK(pmap); 1869190681Snwhitehorn } 1870190681Snwhitehorn if ((lo & LPTE_CHG) != 0) { 1871190681Snwhitehorn moea64_attr_clear(m, LPTE_CHG); 1872190681Snwhitehorn vm_page_dirty(m); 1873190681Snwhitehorn } 1874190681Snwhitehorn vm_page_flag_clear(m, PG_WRITEABLE); 1875207796Salc vm_page_unlock_queues(); 1876190681Snwhitehorn} 1877190681Snwhitehorn 1878190681Snwhitehorn/* 1879190681Snwhitehorn * moea64_ts_referenced: 1880190681Snwhitehorn * 1881190681Snwhitehorn * Return a count of reference bits for a page, clearing those bits. 1882190681Snwhitehorn * It is not necessary for every reference bit to be cleared, but it 1883190681Snwhitehorn * is necessary that 0 only be returned when there are truly no 1884190681Snwhitehorn * reference bits set. 1885190681Snwhitehorn * 1886190681Snwhitehorn * XXX: The exact number of bits to check and clear is a matter that 1887190681Snwhitehorn * should be tested and standardized at some point in the future for 1888190681Snwhitehorn * optimal aging of shared pages. 1889190681Snwhitehorn */ 1890190681Snwhitehornboolean_t 1891190681Snwhitehornmoea64_ts_referenced(mmu_t mmu, vm_page_t m) 1892190681Snwhitehorn{ 1893190681Snwhitehorn 1894208990Salc KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 1895208990Salc ("moea64_ts_referenced: page %p is not managed", m)); 1896208990Salc return (moea64_clear_bit(m, LPTE_REF)); 1897190681Snwhitehorn} 1898190681Snwhitehorn 1899190681Snwhitehorn/* 1900190681Snwhitehorn * Map a wired page into kernel virtual address space. 1901190681Snwhitehorn */ 1902190681Snwhitehornvoid 1903190681Snwhitehornmoea64_kenter(mmu_t mmu, vm_offset_t va, vm_offset_t pa) 1904190681Snwhitehorn{ 1905190681Snwhitehorn uint64_t pte_lo; 1906190681Snwhitehorn int error; 1907190681Snwhitehorn 1908204128Snwhitehorn#if 0 1909190681Snwhitehorn if (!pmap_bootstrapped) { 1910204128Snwhitehorn if (va >= VM_MIN_KERNEL_ADDRESS && va < virtual_end) 1911209975Snwhitehorn panic("Trying to enter an address in KVA -- %#" 1912209975Snwhitehorn PRIxPTR "!\n",pa); 1913190681Snwhitehorn } 1914204128Snwhitehorn#endif 1915190681Snwhitehorn 1916190681Snwhitehorn pte_lo = moea64_calc_wimg(pa); 1917190681Snwhitehorn 1918190681Snwhitehorn PMAP_LOCK(kernel_pmap); 1919190681Snwhitehorn error = moea64_pvo_enter(kernel_pmap, moea64_upvo_zone, 1920190681Snwhitehorn &moea64_pvo_kunmanaged, va, pa, pte_lo, 1921198378Snwhitehorn PVO_WIRED | VM_PROT_EXECUTE); 1922190681Snwhitehorn 1923190681Snwhitehorn if (error != 0 && error != ENOENT) 1924209975Snwhitehorn panic("moea64_kenter: failed to enter va %#zx pa %#zx: %d", va, 1925190681Snwhitehorn pa, error); 1926190681Snwhitehorn 1927190681Snwhitehorn /* 1928190681Snwhitehorn * Flush the memory from the instruction cache. 1929190681Snwhitehorn */ 1930190681Snwhitehorn if ((pte_lo & (LPTE_I | LPTE_G)) == 0) { 1931190681Snwhitehorn __syncicache((void *)va, PAGE_SIZE); 1932190681Snwhitehorn } 1933190681Snwhitehorn PMAP_UNLOCK(kernel_pmap); 1934190681Snwhitehorn} 1935190681Snwhitehorn 1936190681Snwhitehorn/* 1937190681Snwhitehorn * Extract the physical page address associated with the given kernel virtual 1938190681Snwhitehorn * address. 1939190681Snwhitehorn */ 1940190681Snwhitehornvm_offset_t 1941190681Snwhitehornmoea64_kextract(mmu_t mmu, vm_offset_t va) 1942190681Snwhitehorn{ 1943190681Snwhitehorn struct pvo_entry *pvo; 1944190681Snwhitehorn vm_paddr_t pa; 1945190681Snwhitehorn 1946205370Snwhitehorn /* 1947205370Snwhitehorn * Shortcut the direct-mapped case when applicable. We never put 1948205370Snwhitehorn * anything but 1:1 mappings below VM_MIN_KERNEL_ADDRESS. 1949205370Snwhitehorn */ 1950205370Snwhitehorn if (va < VM_MIN_KERNEL_ADDRESS) 1951205370Snwhitehorn return (va); 1952205370Snwhitehorn 1953190681Snwhitehorn PMAP_LOCK(kernel_pmap); 1954209975Snwhitehorn pvo = moea64_pvo_find_va(kernel_pmap, va); 1955209975Snwhitehorn KASSERT(pvo != NULL, ("moea64_kextract: no addr found for %#" PRIxPTR, 1956209975Snwhitehorn va)); 1957209975Snwhitehorn pa = (pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN) + (va - PVO_VADDR(pvo)); 1958190681Snwhitehorn PMAP_UNLOCK(kernel_pmap); 1959190681Snwhitehorn return (pa); 1960190681Snwhitehorn} 1961190681Snwhitehorn 1962190681Snwhitehorn/* 1963190681Snwhitehorn * Remove a wired page from kernel virtual address space. 1964190681Snwhitehorn */ 1965190681Snwhitehornvoid 1966190681Snwhitehornmoea64_kremove(mmu_t mmu, vm_offset_t va) 1967190681Snwhitehorn{ 1968190681Snwhitehorn moea64_remove(mmu, kernel_pmap, va, va + PAGE_SIZE); 1969190681Snwhitehorn} 1970190681Snwhitehorn 1971190681Snwhitehorn/* 1972190681Snwhitehorn * Map a range of physical addresses into kernel virtual address space. 1973190681Snwhitehorn * 1974190681Snwhitehorn * The value passed in *virt is a suggested virtual address for the mapping. 1975190681Snwhitehorn * Architectures which can support a direct-mapped physical to virtual region 1976190681Snwhitehorn * can return the appropriate address within that region, leaving '*virt' 1977190681Snwhitehorn * unchanged. We cannot and therefore do not; *virt is updated with the 1978190681Snwhitehorn * first usable address after the mapped region. 1979190681Snwhitehorn */ 1980190681Snwhitehornvm_offset_t 1981190681Snwhitehornmoea64_map(mmu_t mmu, vm_offset_t *virt, vm_offset_t pa_start, 1982190681Snwhitehorn vm_offset_t pa_end, int prot) 1983190681Snwhitehorn{ 1984190681Snwhitehorn vm_offset_t sva, va; 1985190681Snwhitehorn 1986190681Snwhitehorn sva = *virt; 1987190681Snwhitehorn va = sva; 1988190681Snwhitehorn for (; pa_start < pa_end; pa_start += PAGE_SIZE, va += PAGE_SIZE) 1989190681Snwhitehorn moea64_kenter(mmu, va, pa_start); 1990190681Snwhitehorn *virt = va; 1991190681Snwhitehorn 1992190681Snwhitehorn return (sva); 1993190681Snwhitehorn} 1994190681Snwhitehorn 1995190681Snwhitehorn/* 1996190681Snwhitehorn * Returns true if the pmap's pv is one of the first 1997190681Snwhitehorn * 16 pvs linked to from this page. This count may 1998190681Snwhitehorn * be changed upwards or downwards in the future; it 1999190681Snwhitehorn * is only necessary that true be returned for a small 2000190681Snwhitehorn * subset of pmaps for proper page aging. 2001190681Snwhitehorn */ 2002190681Snwhitehornboolean_t 2003190681Snwhitehornmoea64_page_exists_quick(mmu_t mmu, pmap_t pmap, vm_page_t m) 2004190681Snwhitehorn{ 2005190681Snwhitehorn int loops; 2006190681Snwhitehorn struct pvo_entry *pvo; 2007208990Salc boolean_t rv; 2008190681Snwhitehorn 2009208990Salc KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 2010208990Salc ("moea64_page_exists_quick: page %p is not managed", m)); 2011190681Snwhitehorn loops = 0; 2012208990Salc rv = FALSE; 2013208990Salc vm_page_lock_queues(); 2014190681Snwhitehorn LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2015208990Salc if (pvo->pvo_pmap == pmap) { 2016208990Salc rv = TRUE; 2017208990Salc break; 2018208990Salc } 2019190681Snwhitehorn if (++loops >= 16) 2020190681Snwhitehorn break; 2021190681Snwhitehorn } 2022208990Salc vm_page_unlock_queues(); 2023208990Salc return (rv); 2024190681Snwhitehorn} 2025190681Snwhitehorn 2026190681Snwhitehorn/* 2027190681Snwhitehorn * Return the number of managed mappings to the given physical page 2028190681Snwhitehorn * that are wired. 2029190681Snwhitehorn */ 2030190681Snwhitehornint 2031190681Snwhitehornmoea64_page_wired_mappings(mmu_t mmu, vm_page_t m) 2032190681Snwhitehorn{ 2033190681Snwhitehorn struct pvo_entry *pvo; 2034190681Snwhitehorn int count; 2035190681Snwhitehorn 2036190681Snwhitehorn count = 0; 2037208990Salc if ((m->flags & PG_FICTITIOUS) != 0) 2038190681Snwhitehorn return (count); 2039207796Salc vm_page_lock_queues(); 2040190681Snwhitehorn LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) 2041190681Snwhitehorn if ((pvo->pvo_vaddr & PVO_WIRED) != 0) 2042190681Snwhitehorn count++; 2043207796Salc vm_page_unlock_queues(); 2044190681Snwhitehorn return (count); 2045190681Snwhitehorn} 2046190681Snwhitehorn 2047209975Snwhitehornstatic uintptr_t moea64_vsidcontext; 2048190681Snwhitehorn 2049209975Snwhitehornuintptr_t 2050209975Snwhitehornmoea64_get_unique_vsid(void) { 2051209975Snwhitehorn u_int entropy; 2052209975Snwhitehorn register_t hash; 2053209975Snwhitehorn uint32_t mask; 2054209975Snwhitehorn int i; 2055190681Snwhitehorn 2056190681Snwhitehorn entropy = 0; 2057190681Snwhitehorn __asm __volatile("mftb %0" : "=r"(entropy)); 2058190681Snwhitehorn 2059211967Snwhitehorn mtx_lock(&moea64_slb_mutex); 2060209975Snwhitehorn for (i = 0; i < NVSIDS; i += VSID_NBPW) { 2061209975Snwhitehorn u_int n; 2062190681Snwhitehorn 2063190681Snwhitehorn /* 2064190681Snwhitehorn * Create a new value by mutiplying by a prime and adding in 2065190681Snwhitehorn * entropy from the timebase register. This is to make the 2066190681Snwhitehorn * VSID more random so that the PT hash function collides 2067190681Snwhitehorn * less often. (Note that the prime casues gcc to do shifts 2068190681Snwhitehorn * instead of a multiply.) 2069190681Snwhitehorn */ 2070190681Snwhitehorn moea64_vsidcontext = (moea64_vsidcontext * 0x1105) + entropy; 2071209975Snwhitehorn hash = moea64_vsidcontext & (NVSIDS - 1); 2072190681Snwhitehorn if (hash == 0) /* 0 is special, avoid it */ 2073190681Snwhitehorn continue; 2074190681Snwhitehorn n = hash >> 5; 2075190681Snwhitehorn mask = 1 << (hash & (VSID_NBPW - 1)); 2076209975Snwhitehorn hash = (moea64_vsidcontext & VSID_HASHMASK); 2077190681Snwhitehorn if (moea64_vsid_bitmap[n] & mask) { /* collision? */ 2078190681Snwhitehorn /* anything free in this bucket? */ 2079190681Snwhitehorn if (moea64_vsid_bitmap[n] == 0xffffffff) { 2080190681Snwhitehorn entropy = (moea64_vsidcontext >> 20); 2081190681Snwhitehorn continue; 2082190681Snwhitehorn } 2083190681Snwhitehorn i = ffs(~moea64_vsid_bitmap[i]) - 1; 2084190681Snwhitehorn mask = 1 << i; 2085209975Snwhitehorn hash &= VSID_HASHMASK & ~(VSID_NBPW - 1); 2086190681Snwhitehorn hash |= i; 2087190681Snwhitehorn } 2088190681Snwhitehorn moea64_vsid_bitmap[n] |= mask; 2089211967Snwhitehorn mtx_unlock(&moea64_slb_mutex); 2090209975Snwhitehorn return (hash); 2091190681Snwhitehorn } 2092190681Snwhitehorn 2093211967Snwhitehorn mtx_unlock(&moea64_slb_mutex); 2094209975Snwhitehorn panic("%s: out of segments",__func__); 2095190681Snwhitehorn} 2096190681Snwhitehorn 2097209975Snwhitehorn#ifdef __powerpc64__ 2098209975Snwhitehornvoid 2099209975Snwhitehornmoea64_pinit(mmu_t mmu, pmap_t pmap) 2100209975Snwhitehorn{ 2101209975Snwhitehorn PMAP_LOCK_INIT(pmap); 2102209975Snwhitehorn 2103209975Snwhitehorn SPLAY_INIT(&pmap->pm_slbtree); 2104209975Snwhitehorn pmap->pm_slb = slb_alloc_user_cache(); 2105209975Snwhitehorn} 2106209975Snwhitehorn#else 2107209975Snwhitehornvoid 2108209975Snwhitehornmoea64_pinit(mmu_t mmu, pmap_t pmap) 2109209975Snwhitehorn{ 2110209975Snwhitehorn int i; 2111209975Snwhitehorn register_t hash; 2112209975Snwhitehorn 2113209975Snwhitehorn PMAP_LOCK_INIT(pmap); 2114209975Snwhitehorn 2115209975Snwhitehorn if (pmap_bootstrapped) 2116209975Snwhitehorn pmap->pmap_phys = (pmap_t)moea64_kextract(mmu, 2117209975Snwhitehorn (vm_offset_t)pmap); 2118209975Snwhitehorn else 2119209975Snwhitehorn pmap->pmap_phys = pmap; 2120209975Snwhitehorn 2121209975Snwhitehorn /* 2122209975Snwhitehorn * Allocate some segment registers for this pmap. 2123209975Snwhitehorn */ 2124209975Snwhitehorn hash = moea64_get_unique_vsid(); 2125209975Snwhitehorn 2126209975Snwhitehorn for (i = 0; i < 16; i++) 2127209975Snwhitehorn pmap->pm_sr[i] = VSID_MAKE(i, hash); 2128209975Snwhitehorn} 2129209975Snwhitehorn#endif 2130209975Snwhitehorn 2131190681Snwhitehorn/* 2132190681Snwhitehorn * Initialize the pmap associated with process 0. 2133190681Snwhitehorn */ 2134190681Snwhitehornvoid 2135190681Snwhitehornmoea64_pinit0(mmu_t mmu, pmap_t pm) 2136190681Snwhitehorn{ 2137190681Snwhitehorn moea64_pinit(mmu, pm); 2138190681Snwhitehorn bzero(&pm->pm_stats, sizeof(pm->pm_stats)); 2139190681Snwhitehorn} 2140190681Snwhitehorn 2141190681Snwhitehorn/* 2142190681Snwhitehorn * Set the physical protection on the specified range of this map as requested. 2143190681Snwhitehorn */ 2144190681Snwhitehornvoid 2145190681Snwhitehornmoea64_protect(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva, 2146190681Snwhitehorn vm_prot_t prot) 2147190681Snwhitehorn{ 2148190681Snwhitehorn struct pvo_entry *pvo; 2149190681Snwhitehorn struct lpte *pt; 2150190681Snwhitehorn 2151190681Snwhitehorn CTR4(KTR_PMAP, "moea64_protect: pm=%p sva=%#x eva=%#x prot=%#x", pm, sva, 2152190681Snwhitehorn eva, prot); 2153190681Snwhitehorn 2154190681Snwhitehorn 2155190681Snwhitehorn KASSERT(pm == &curproc->p_vmspace->vm_pmap || pm == kernel_pmap, 2156190681Snwhitehorn ("moea64_protect: non current pmap")); 2157190681Snwhitehorn 2158190681Snwhitehorn if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 2159190681Snwhitehorn moea64_remove(mmu, pm, sva, eva); 2160190681Snwhitehorn return; 2161190681Snwhitehorn } 2162190681Snwhitehorn 2163190681Snwhitehorn vm_page_lock_queues(); 2164190681Snwhitehorn PMAP_LOCK(pm); 2165190681Snwhitehorn for (; sva < eva; sva += PAGE_SIZE) { 2166209975Snwhitehorn pvo = moea64_pvo_find_va(pm, sva); 2167190681Snwhitehorn if (pvo == NULL) 2168190681Snwhitehorn continue; 2169190681Snwhitehorn 2170190681Snwhitehorn /* 2171190681Snwhitehorn * Grab the PTE pointer before we diddle with the cached PTE 2172190681Snwhitehorn * copy. 2173190681Snwhitehorn */ 2174190681Snwhitehorn LOCK_TABLE(); 2175209975Snwhitehorn pt = moea64_pvo_to_pte(pvo); 2176190681Snwhitehorn 2177190681Snwhitehorn /* 2178190681Snwhitehorn * Change the protection of the page. 2179190681Snwhitehorn */ 2180190681Snwhitehorn pvo->pvo_pte.lpte.pte_lo &= ~LPTE_PP; 2181190681Snwhitehorn pvo->pvo_pte.lpte.pte_lo |= LPTE_BR; 2182190681Snwhitehorn pvo->pvo_pte.lpte.pte_lo &= ~LPTE_NOEXEC; 2183190681Snwhitehorn if ((prot & VM_PROT_EXECUTE) == 0) 2184190681Snwhitehorn pvo->pvo_pte.lpte.pte_lo |= LPTE_NOEXEC; 2185190681Snwhitehorn 2186190681Snwhitehorn /* 2187190681Snwhitehorn * If the PVO is in the page table, update that pte as well. 2188190681Snwhitehorn */ 2189190681Snwhitehorn if (pt != NULL) { 2190209975Snwhitehorn moea64_pte_change(pt, &pvo->pvo_pte.lpte, pvo->pvo_vpn); 2191190681Snwhitehorn if ((pvo->pvo_pte.lpte.pte_lo & 2192190681Snwhitehorn (LPTE_I | LPTE_G | LPTE_NOEXEC)) == 0) { 2193198341Smarcel moea64_syncicache(pm, sva, 2194198341Smarcel pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN, 2195198341Smarcel PAGE_SIZE); 2196190681Snwhitehorn } 2197190681Snwhitehorn } 2198190681Snwhitehorn UNLOCK_TABLE(); 2199190681Snwhitehorn } 2200190681Snwhitehorn vm_page_unlock_queues(); 2201190681Snwhitehorn PMAP_UNLOCK(pm); 2202190681Snwhitehorn} 2203190681Snwhitehorn 2204190681Snwhitehorn/* 2205190681Snwhitehorn * Map a list of wired pages into kernel virtual address space. This is 2206190681Snwhitehorn * intended for temporary mappings which do not need page modification or 2207190681Snwhitehorn * references recorded. Existing mappings in the region are overwritten. 2208190681Snwhitehorn */ 2209190681Snwhitehornvoid 2210190681Snwhitehornmoea64_qenter(mmu_t mmu, vm_offset_t va, vm_page_t *m, int count) 2211190681Snwhitehorn{ 2212190681Snwhitehorn while (count-- > 0) { 2213190681Snwhitehorn moea64_kenter(mmu, va, VM_PAGE_TO_PHYS(*m)); 2214190681Snwhitehorn va += PAGE_SIZE; 2215190681Snwhitehorn m++; 2216190681Snwhitehorn } 2217190681Snwhitehorn} 2218190681Snwhitehorn 2219190681Snwhitehorn/* 2220190681Snwhitehorn * Remove page mappings from kernel virtual address space. Intended for 2221190681Snwhitehorn * temporary mappings entered by moea64_qenter. 2222190681Snwhitehorn */ 2223190681Snwhitehornvoid 2224190681Snwhitehornmoea64_qremove(mmu_t mmu, vm_offset_t va, int count) 2225190681Snwhitehorn{ 2226190681Snwhitehorn while (count-- > 0) { 2227190681Snwhitehorn moea64_kremove(mmu, va); 2228190681Snwhitehorn va += PAGE_SIZE; 2229190681Snwhitehorn } 2230190681Snwhitehorn} 2231190681Snwhitehorn 2232190681Snwhitehornvoid 2233209975Snwhitehornmoea64_release_vsid(uint64_t vsid) 2234209975Snwhitehorn{ 2235212044Snwhitehorn int idx, mask; 2236209975Snwhitehorn 2237212044Snwhitehorn mtx_lock(&moea64_slb_mutex); 2238212044Snwhitehorn idx = vsid & (NVSIDS-1); 2239212044Snwhitehorn mask = 1 << (idx % VSID_NBPW); 2240212044Snwhitehorn idx /= VSID_NBPW; 2241212044Snwhitehorn moea64_vsid_bitmap[idx] &= ~mask; 2242212044Snwhitehorn mtx_unlock(&moea64_slb_mutex); 2243209975Snwhitehorn} 2244209975Snwhitehorn 2245209975Snwhitehorn 2246209975Snwhitehornvoid 2247190681Snwhitehornmoea64_release(mmu_t mmu, pmap_t pmap) 2248190681Snwhitehorn{ 2249190681Snwhitehorn 2250190681Snwhitehorn /* 2251209975Snwhitehorn * Free segment registers' VSIDs 2252190681Snwhitehorn */ 2253209975Snwhitehorn #ifdef __powerpc64__ 2254209975Snwhitehorn free_vsids(pmap); 2255209975Snwhitehorn slb_free_user_cache(pmap->pm_slb); 2256209975Snwhitehorn #else 2257190681Snwhitehorn if (pmap->pm_sr[0] == 0) 2258212044Snwhitehorn panic("moea64_release: pm_sr[0] = 0"); 2259190681Snwhitehorn 2260209975Snwhitehorn moea64_release_vsid(pmap->pm_sr[0]); 2261209975Snwhitehorn #endif 2262209975Snwhitehorn 2263190681Snwhitehorn PMAP_LOCK_DESTROY(pmap); 2264190681Snwhitehorn} 2265190681Snwhitehorn 2266190681Snwhitehorn/* 2267190681Snwhitehorn * Remove the given range of addresses from the specified map. 2268190681Snwhitehorn */ 2269190681Snwhitehornvoid 2270190681Snwhitehornmoea64_remove(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva) 2271190681Snwhitehorn{ 2272190681Snwhitehorn struct pvo_entry *pvo; 2273190681Snwhitehorn 2274190681Snwhitehorn vm_page_lock_queues(); 2275190681Snwhitehorn PMAP_LOCK(pm); 2276190681Snwhitehorn for (; sva < eva; sva += PAGE_SIZE) { 2277209975Snwhitehorn pvo = moea64_pvo_find_va(pm, sva); 2278209975Snwhitehorn if (pvo != NULL) 2279209975Snwhitehorn moea64_pvo_remove(pvo); 2280190681Snwhitehorn } 2281190681Snwhitehorn vm_page_unlock_queues(); 2282190681Snwhitehorn PMAP_UNLOCK(pm); 2283190681Snwhitehorn} 2284190681Snwhitehorn 2285190681Snwhitehorn/* 2286190681Snwhitehorn * Remove physical page from all pmaps in which it resides. moea64_pvo_remove() 2287190681Snwhitehorn * will reflect changes in pte's back to the vm_page. 2288190681Snwhitehorn */ 2289190681Snwhitehornvoid 2290190681Snwhitehornmoea64_remove_all(mmu_t mmu, vm_page_t m) 2291190681Snwhitehorn{ 2292190681Snwhitehorn struct pvo_head *pvo_head; 2293190681Snwhitehorn struct pvo_entry *pvo, *next_pvo; 2294190681Snwhitehorn pmap_t pmap; 2295190681Snwhitehorn 2296207796Salc vm_page_lock_queues(); 2297190681Snwhitehorn pvo_head = vm_page_to_pvoh(m); 2298190681Snwhitehorn for (pvo = LIST_FIRST(pvo_head); pvo != NULL; pvo = next_pvo) { 2299190681Snwhitehorn next_pvo = LIST_NEXT(pvo, pvo_vlink); 2300190681Snwhitehorn 2301190681Snwhitehorn MOEA_PVO_CHECK(pvo); /* sanity check */ 2302190681Snwhitehorn pmap = pvo->pvo_pmap; 2303190681Snwhitehorn PMAP_LOCK(pmap); 2304209975Snwhitehorn moea64_pvo_remove(pvo); 2305190681Snwhitehorn PMAP_UNLOCK(pmap); 2306190681Snwhitehorn } 2307204042Snwhitehorn if ((m->flags & PG_WRITEABLE) && moea64_is_modified(mmu, m)) { 2308204042Snwhitehorn moea64_attr_clear(m, LPTE_CHG); 2309204042Snwhitehorn vm_page_dirty(m); 2310204042Snwhitehorn } 2311190681Snwhitehorn vm_page_flag_clear(m, PG_WRITEABLE); 2312207796Salc vm_page_unlock_queues(); 2313190681Snwhitehorn} 2314190681Snwhitehorn 2315190681Snwhitehorn/* 2316190681Snwhitehorn * Allocate a physical page of memory directly from the phys_avail map. 2317190681Snwhitehorn * Can only be called from moea64_bootstrap before avail start and end are 2318190681Snwhitehorn * calculated. 2319190681Snwhitehorn */ 2320190681Snwhitehornstatic vm_offset_t 2321190681Snwhitehornmoea64_bootstrap_alloc(vm_size_t size, u_int align) 2322190681Snwhitehorn{ 2323190681Snwhitehorn vm_offset_t s, e; 2324190681Snwhitehorn int i, j; 2325190681Snwhitehorn 2326190681Snwhitehorn size = round_page(size); 2327190681Snwhitehorn for (i = 0; phys_avail[i + 1] != 0; i += 2) { 2328190681Snwhitehorn if (align != 0) 2329190681Snwhitehorn s = (phys_avail[i] + align - 1) & ~(align - 1); 2330190681Snwhitehorn else 2331190681Snwhitehorn s = phys_avail[i]; 2332190681Snwhitehorn e = s + size; 2333190681Snwhitehorn 2334190681Snwhitehorn if (s < phys_avail[i] || e > phys_avail[i + 1]) 2335190681Snwhitehorn continue; 2336190681Snwhitehorn 2337190681Snwhitehorn if (s == phys_avail[i]) { 2338190681Snwhitehorn phys_avail[i] += size; 2339190681Snwhitehorn } else if (e == phys_avail[i + 1]) { 2340190681Snwhitehorn phys_avail[i + 1] -= size; 2341190681Snwhitehorn } else { 2342190681Snwhitehorn for (j = phys_avail_count * 2; j > i; j -= 2) { 2343190681Snwhitehorn phys_avail[j] = phys_avail[j - 2]; 2344190681Snwhitehorn phys_avail[j + 1] = phys_avail[j - 1]; 2345190681Snwhitehorn } 2346190681Snwhitehorn 2347190681Snwhitehorn phys_avail[i + 3] = phys_avail[i + 1]; 2348190681Snwhitehorn phys_avail[i + 1] = s; 2349190681Snwhitehorn phys_avail[i + 2] = e; 2350190681Snwhitehorn phys_avail_count++; 2351190681Snwhitehorn } 2352190681Snwhitehorn 2353190681Snwhitehorn return (s); 2354190681Snwhitehorn } 2355190681Snwhitehorn panic("moea64_bootstrap_alloc: could not allocate memory"); 2356190681Snwhitehorn} 2357190681Snwhitehorn 2358190681Snwhitehornstatic void 2359190681Snwhitehorntlbia(void) 2360190681Snwhitehorn{ 2361190681Snwhitehorn vm_offset_t i; 2362209975Snwhitehorn #ifndef __powerpc64__ 2363198378Snwhitehorn register_t msr, scratch; 2364209975Snwhitehorn #endif 2365190681Snwhitehorn 2366209975Snwhitehorn TLBSYNC(); 2367209975Snwhitehorn 2368198378Snwhitehorn for (i = 0; i < 0xFF000; i += 0x00001000) { 2369209975Snwhitehorn #ifdef __powerpc64__ 2370209975Snwhitehorn __asm __volatile("tlbiel %0" :: "r"(i)); 2371209975Snwhitehorn #else 2372198378Snwhitehorn __asm __volatile("\ 2373198378Snwhitehorn mfmsr %0; \ 2374198378Snwhitehorn mr %1, %0; \ 2375198378Snwhitehorn insrdi %1,%3,1,0; \ 2376198378Snwhitehorn mtmsrd %1; \ 2377209975Snwhitehorn isync; \ 2378198378Snwhitehorn \ 2379198378Snwhitehorn tlbiel %2; \ 2380198378Snwhitehorn \ 2381198378Snwhitehorn mtmsrd %0; \ 2382209975Snwhitehorn isync;" 2383198378Snwhitehorn : "=r"(msr), "=r"(scratch) : "r"(i), "r"(1)); 2384209975Snwhitehorn #endif 2385198378Snwhitehorn } 2386209975Snwhitehorn 2387209975Snwhitehorn EIEIO(); 2388209975Snwhitehorn TLBSYNC(); 2389190681Snwhitehorn} 2390190681Snwhitehorn 2391209975Snwhitehorn#ifdef __powerpc64__ 2392209975Snwhitehornstatic void 2393209975Snwhitehornslbia(void) 2394209975Snwhitehorn{ 2395209975Snwhitehorn register_t seg0; 2396209975Snwhitehorn 2397209975Snwhitehorn __asm __volatile ("slbia"); 2398209975Snwhitehorn __asm __volatile ("slbmfee %0,%1; slbie %0;" : "=r"(seg0) : "r"(0)); 2399209975Snwhitehorn} 2400209975Snwhitehorn#endif 2401209975Snwhitehorn 2402190681Snwhitehornstatic int 2403190681Snwhitehornmoea64_pvo_enter(pmap_t pm, uma_zone_t zone, struct pvo_head *pvo_head, 2404198378Snwhitehorn vm_offset_t va, vm_offset_t pa, uint64_t pte_lo, int flags) 2405190681Snwhitehorn{ 2406190681Snwhitehorn struct pvo_entry *pvo; 2407190681Snwhitehorn uint64_t vsid; 2408190681Snwhitehorn int first; 2409190681Snwhitehorn u_int ptegidx; 2410190681Snwhitehorn int i; 2411190681Snwhitehorn int bootstrap; 2412190681Snwhitehorn 2413190681Snwhitehorn /* 2414190681Snwhitehorn * One nasty thing that can happen here is that the UMA calls to 2415190681Snwhitehorn * allocate new PVOs need to map more memory, which calls pvo_enter(), 2416190681Snwhitehorn * which calls UMA... 2417190681Snwhitehorn * 2418190681Snwhitehorn * We break the loop by detecting recursion and allocating out of 2419190681Snwhitehorn * the bootstrap pool. 2420190681Snwhitehorn */ 2421190681Snwhitehorn 2422190681Snwhitehorn moea64_pvo_enter_calls++; 2423190681Snwhitehorn first = 0; 2424190681Snwhitehorn bootstrap = (flags & PVO_BOOTSTRAP); 2425190681Snwhitehorn 2426190681Snwhitehorn if (!moea64_initialized) 2427190681Snwhitehorn bootstrap = 1; 2428190681Snwhitehorn 2429190681Snwhitehorn /* 2430190681Snwhitehorn * Compute the PTE Group index. 2431190681Snwhitehorn */ 2432190681Snwhitehorn va &= ~ADDR_POFF; 2433190681Snwhitehorn vsid = va_to_vsid(pm, va); 2434209975Snwhitehorn ptegidx = va_to_pteg(vsid, va, flags & PVO_LARGE); 2435190681Snwhitehorn 2436190681Snwhitehorn /* 2437190681Snwhitehorn * Remove any existing mapping for this page. Reuse the pvo entry if 2438190681Snwhitehorn * there is a mapping. 2439190681Snwhitehorn */ 2440198378Snwhitehorn LOCK_TABLE(); 2441190681Snwhitehorn 2442190681Snwhitehorn LIST_FOREACH(pvo, &moea64_pvo_table[ptegidx], pvo_olink) { 2443190681Snwhitehorn if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) { 2444190681Snwhitehorn if ((pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN) == pa && 2445190681Snwhitehorn (pvo->pvo_pte.lpte.pte_lo & LPTE_PP) == 2446190681Snwhitehorn (pte_lo & LPTE_PP)) { 2447209975Snwhitehorn if (!(pvo->pvo_pte.lpte.pte_hi & LPTE_VALID)) { 2448209975Snwhitehorn /* Re-insert if spilled */ 2449209975Snwhitehorn i = moea64_pte_insert(ptegidx, 2450209975Snwhitehorn &pvo->pvo_pte.lpte); 2451209975Snwhitehorn if (i >= 0) 2452209975Snwhitehorn PVO_PTEGIDX_SET(pvo, i); 2453209975Snwhitehorn moea64_pte_overflow--; 2454209975Snwhitehorn } 2455198378Snwhitehorn UNLOCK_TABLE(); 2456190681Snwhitehorn return (0); 2457190681Snwhitehorn } 2458209975Snwhitehorn moea64_pvo_remove(pvo); 2459190681Snwhitehorn break; 2460190681Snwhitehorn } 2461190681Snwhitehorn } 2462190681Snwhitehorn 2463190681Snwhitehorn /* 2464190681Snwhitehorn * If we aren't overwriting a mapping, try to allocate. 2465190681Snwhitehorn */ 2466190681Snwhitehorn if (bootstrap) { 2467190681Snwhitehorn if (moea64_bpvo_pool_index >= BPVO_POOL_SIZE) { 2468209975Snwhitehorn panic("moea64_enter: bpvo pool exhausted, %d, %d, %zd", 2469190681Snwhitehorn moea64_bpvo_pool_index, BPVO_POOL_SIZE, 2470190681Snwhitehorn BPVO_POOL_SIZE * sizeof(struct pvo_entry)); 2471190681Snwhitehorn } 2472190681Snwhitehorn pvo = &moea64_bpvo_pool[moea64_bpvo_pool_index]; 2473190681Snwhitehorn moea64_bpvo_pool_index++; 2474190681Snwhitehorn bootstrap = 1; 2475190681Snwhitehorn } else { 2476198378Snwhitehorn /* 2477204719Snwhitehorn * Note: drop the table lock around the UMA allocation in 2478198378Snwhitehorn * case the UMA allocator needs to manipulate the page 2479198378Snwhitehorn * table. The mapping we are working with is already 2480198378Snwhitehorn * protected by the PMAP lock. 2481198378Snwhitehorn */ 2482198378Snwhitehorn UNLOCK_TABLE(); 2483190681Snwhitehorn pvo = uma_zalloc(zone, M_NOWAIT); 2484198378Snwhitehorn LOCK_TABLE(); 2485190681Snwhitehorn } 2486190681Snwhitehorn 2487190681Snwhitehorn if (pvo == NULL) { 2488198378Snwhitehorn UNLOCK_TABLE(); 2489190681Snwhitehorn return (ENOMEM); 2490190681Snwhitehorn } 2491190681Snwhitehorn 2492190681Snwhitehorn moea64_pvo_entries++; 2493190681Snwhitehorn pvo->pvo_vaddr = va; 2494209975Snwhitehorn pvo->pvo_vpn = (uint64_t)((va & ADDR_PIDX) >> ADDR_PIDX_SHFT) 2495209975Snwhitehorn | (vsid << 16); 2496190681Snwhitehorn pvo->pvo_pmap = pm; 2497190681Snwhitehorn LIST_INSERT_HEAD(&moea64_pvo_table[ptegidx], pvo, pvo_olink); 2498190681Snwhitehorn pvo->pvo_vaddr &= ~ADDR_POFF; 2499190681Snwhitehorn 2500190681Snwhitehorn if (!(flags & VM_PROT_EXECUTE)) 2501190681Snwhitehorn pte_lo |= LPTE_NOEXEC; 2502190681Snwhitehorn if (flags & PVO_WIRED) 2503190681Snwhitehorn pvo->pvo_vaddr |= PVO_WIRED; 2504190681Snwhitehorn if (pvo_head != &moea64_pvo_kunmanaged) 2505190681Snwhitehorn pvo->pvo_vaddr |= PVO_MANAGED; 2506190681Snwhitehorn if (bootstrap) 2507190681Snwhitehorn pvo->pvo_vaddr |= PVO_BOOTSTRAP; 2508190681Snwhitehorn if (flags & PVO_FAKE) 2509190681Snwhitehorn pvo->pvo_vaddr |= PVO_FAKE; 2510209975Snwhitehorn if (flags & PVO_LARGE) 2511209975Snwhitehorn pvo->pvo_vaddr |= PVO_LARGE; 2512190681Snwhitehorn 2513190681Snwhitehorn moea64_pte_create(&pvo->pvo_pte.lpte, vsid, va, 2514209975Snwhitehorn (uint64_t)(pa) | pte_lo, flags); 2515190681Snwhitehorn 2516190681Snwhitehorn /* 2517190681Snwhitehorn * Remember if the list was empty and therefore will be the first 2518190681Snwhitehorn * item. 2519190681Snwhitehorn */ 2520190681Snwhitehorn if (LIST_FIRST(pvo_head) == NULL) 2521190681Snwhitehorn first = 1; 2522190681Snwhitehorn LIST_INSERT_HEAD(pvo_head, pvo, pvo_vlink); 2523190681Snwhitehorn 2524209975Snwhitehorn if (pvo->pvo_vaddr & PVO_WIRED) { 2525209975Snwhitehorn pvo->pvo_pte.lpte.pte_hi |= LPTE_WIRED; 2526190681Snwhitehorn pm->pm_stats.wired_count++; 2527209975Snwhitehorn } 2528190681Snwhitehorn pm->pm_stats.resident_count++; 2529190681Snwhitehorn 2530190681Snwhitehorn /* 2531190681Snwhitehorn * We hope this succeeds but it isn't required. 2532190681Snwhitehorn */ 2533190681Snwhitehorn i = moea64_pte_insert(ptegidx, &pvo->pvo_pte.lpte); 2534190681Snwhitehorn if (i >= 0) { 2535190681Snwhitehorn PVO_PTEGIDX_SET(pvo, i); 2536190681Snwhitehorn } else { 2537190681Snwhitehorn panic("moea64_pvo_enter: overflow"); 2538190681Snwhitehorn moea64_pte_overflow++; 2539190681Snwhitehorn } 2540190681Snwhitehorn 2541204042Snwhitehorn if (pm == kernel_pmap) 2542204042Snwhitehorn isync(); 2543204042Snwhitehorn 2544198378Snwhitehorn UNLOCK_TABLE(); 2545190681Snwhitehorn 2546209975Snwhitehorn#ifdef __powerpc64__ 2547209975Snwhitehorn /* 2548209975Snwhitehorn * Make sure all our bootstrap mappings are in the SLB as soon 2549209975Snwhitehorn * as virtual memory is switched on. 2550209975Snwhitehorn */ 2551209975Snwhitehorn if (!pmap_bootstrapped) 2552209975Snwhitehorn moea64_bootstrap_slb_prefault(va, flags & PVO_LARGE); 2553209975Snwhitehorn#endif 2554209975Snwhitehorn 2555190681Snwhitehorn return (first ? ENOENT : 0); 2556190681Snwhitehorn} 2557190681Snwhitehorn 2558190681Snwhitehornstatic void 2559209975Snwhitehornmoea64_pvo_remove(struct pvo_entry *pvo) 2560190681Snwhitehorn{ 2561190681Snwhitehorn struct lpte *pt; 2562190681Snwhitehorn 2563190681Snwhitehorn /* 2564190681Snwhitehorn * If there is an active pte entry, we need to deactivate it (and 2565190681Snwhitehorn * save the ref & cfg bits). 2566190681Snwhitehorn */ 2567190681Snwhitehorn LOCK_TABLE(); 2568209975Snwhitehorn pt = moea64_pvo_to_pte(pvo); 2569190681Snwhitehorn if (pt != NULL) { 2570209975Snwhitehorn moea64_pte_unset(pt, &pvo->pvo_pte.lpte, pvo->pvo_vpn); 2571190681Snwhitehorn PVO_PTEGIDX_CLR(pvo); 2572190681Snwhitehorn } else { 2573190681Snwhitehorn moea64_pte_overflow--; 2574190681Snwhitehorn } 2575190681Snwhitehorn 2576190681Snwhitehorn /* 2577190681Snwhitehorn * Update our statistics. 2578190681Snwhitehorn */ 2579190681Snwhitehorn pvo->pvo_pmap->pm_stats.resident_count--; 2580204042Snwhitehorn if (pvo->pvo_vaddr & PVO_WIRED) 2581190681Snwhitehorn pvo->pvo_pmap->pm_stats.wired_count--; 2582190681Snwhitehorn 2583190681Snwhitehorn /* 2584190681Snwhitehorn * Save the REF/CHG bits into their cache if the page is managed. 2585190681Snwhitehorn */ 2586190681Snwhitehorn if ((pvo->pvo_vaddr & (PVO_MANAGED|PVO_FAKE)) == PVO_MANAGED) { 2587190681Snwhitehorn struct vm_page *pg; 2588190681Snwhitehorn 2589190681Snwhitehorn pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN); 2590190681Snwhitehorn if (pg != NULL) { 2591190681Snwhitehorn moea64_attr_save(pg, pvo->pvo_pte.lpte.pte_lo & 2592190681Snwhitehorn (LPTE_REF | LPTE_CHG)); 2593190681Snwhitehorn } 2594190681Snwhitehorn } 2595190681Snwhitehorn 2596190681Snwhitehorn /* 2597190681Snwhitehorn * Remove this PVO from the PV list. 2598190681Snwhitehorn */ 2599190681Snwhitehorn LIST_REMOVE(pvo, pvo_vlink); 2600190681Snwhitehorn 2601190681Snwhitehorn /* 2602190681Snwhitehorn * Remove this from the overflow list and return it to the pool 2603190681Snwhitehorn * if we aren't going to reuse it. 2604190681Snwhitehorn */ 2605190681Snwhitehorn LIST_REMOVE(pvo, pvo_olink); 2606204694Snwhitehorn UNLOCK_TABLE(); 2607204694Snwhitehorn 2608190681Snwhitehorn if (!(pvo->pvo_vaddr & PVO_BOOTSTRAP)) 2609204042Snwhitehorn uma_zfree((pvo->pvo_vaddr & PVO_MANAGED) ? moea64_mpvo_zone : 2610190681Snwhitehorn moea64_upvo_zone, pvo); 2611204694Snwhitehorn 2612190681Snwhitehorn moea64_pvo_entries--; 2613190681Snwhitehorn moea64_pvo_remove_calls++; 2614190681Snwhitehorn} 2615190681Snwhitehorn 2616190681Snwhitehornstatic struct pvo_entry * 2617209975Snwhitehornmoea64_pvo_find_va(pmap_t pm, vm_offset_t va) 2618190681Snwhitehorn{ 2619190681Snwhitehorn struct pvo_entry *pvo; 2620190681Snwhitehorn int ptegidx; 2621190681Snwhitehorn uint64_t vsid; 2622209975Snwhitehorn #ifdef __powerpc64__ 2623209975Snwhitehorn struct slb slb; 2624190681Snwhitehorn 2625209975Snwhitehorn /* The page is not mapped if the segment isn't */ 2626209975Snwhitehorn if (va_to_slb_entry(pm, va, &slb) != 0) 2627209975Snwhitehorn return NULL; 2628209975Snwhitehorn 2629209975Snwhitehorn vsid = (slb.slbv & SLBV_VSID_MASK) >> SLBV_VSID_SHIFT; 2630209975Snwhitehorn if (slb.slbv & SLBV_L) 2631209975Snwhitehorn va &= ~moea64_large_page_mask; 2632209975Snwhitehorn else 2633209975Snwhitehorn va &= ~ADDR_POFF; 2634209975Snwhitehorn ptegidx = va_to_pteg(vsid, va, slb.slbv & SLBV_L); 2635209975Snwhitehorn #else 2636190681Snwhitehorn va &= ~ADDR_POFF; 2637190681Snwhitehorn vsid = va_to_vsid(pm, va); 2638209975Snwhitehorn ptegidx = va_to_pteg(vsid, va, 0); 2639209975Snwhitehorn #endif 2640190681Snwhitehorn 2641190681Snwhitehorn LOCK_TABLE(); 2642190681Snwhitehorn LIST_FOREACH(pvo, &moea64_pvo_table[ptegidx], pvo_olink) { 2643209975Snwhitehorn if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) 2644190681Snwhitehorn break; 2645190681Snwhitehorn } 2646190681Snwhitehorn UNLOCK_TABLE(); 2647190681Snwhitehorn 2648190681Snwhitehorn return (pvo); 2649190681Snwhitehorn} 2650190681Snwhitehorn 2651190681Snwhitehornstatic struct lpte * 2652209975Snwhitehornmoea64_pvo_to_pte(const struct pvo_entry *pvo) 2653190681Snwhitehorn{ 2654209975Snwhitehorn struct lpte *pt; 2655209975Snwhitehorn int pteidx, ptegidx; 2656209975Snwhitehorn uint64_t vsid; 2657190681Snwhitehorn 2658209975Snwhitehorn ASSERT_TABLE_LOCK(); 2659209975Snwhitehorn 2660209975Snwhitehorn /* If the PTEG index is not set, then there is no page table entry */ 2661209975Snwhitehorn if (!PVO_PTEGIDX_ISSET(pvo)) 2662209975Snwhitehorn return (NULL); 2663209975Snwhitehorn 2664190681Snwhitehorn /* 2665209975Snwhitehorn * Calculate the ptegidx 2666190681Snwhitehorn */ 2667209975Snwhitehorn vsid = PVO_VSID(pvo); 2668209975Snwhitehorn ptegidx = va_to_pteg(vsid, PVO_VADDR(pvo), 2669209975Snwhitehorn pvo->pvo_vaddr & PVO_LARGE); 2670190681Snwhitehorn 2671209975Snwhitehorn /* 2672209975Snwhitehorn * We can find the actual pte entry without searching by grabbing 2673209975Snwhitehorn * the PTEG index from 3 unused bits in pvo_vaddr and by 2674209975Snwhitehorn * noticing the HID bit. 2675209975Snwhitehorn */ 2676209975Snwhitehorn if (pvo->pvo_pte.lpte.pte_hi & LPTE_HID) 2677209975Snwhitehorn ptegidx ^= moea64_pteg_mask; 2678190681Snwhitehorn 2679209975Snwhitehorn pteidx = (ptegidx << 3) | PVO_PTEGIDX_GET(pvo); 2680190681Snwhitehorn 2681190681Snwhitehorn if ((pvo->pvo_pte.lpte.pte_hi & LPTE_VALID) && 2682190681Snwhitehorn !PVO_PTEGIDX_ISSET(pvo)) { 2683190681Snwhitehorn panic("moea64_pvo_to_pte: pvo %p has valid pte in pvo but no " 2684190681Snwhitehorn "valid pte index", pvo); 2685190681Snwhitehorn } 2686190681Snwhitehorn 2687190681Snwhitehorn if ((pvo->pvo_pte.lpte.pte_hi & LPTE_VALID) == 0 && 2688190681Snwhitehorn PVO_PTEGIDX_ISSET(pvo)) { 2689190681Snwhitehorn panic("moea64_pvo_to_pte: pvo %p has valid pte index in pvo " 2690190681Snwhitehorn "pvo but no valid pte", pvo); 2691190681Snwhitehorn } 2692190681Snwhitehorn 2693209975Snwhitehorn pt = &moea64_pteg_table[pteidx >> 3].pt[pteidx & 7]; 2694190681Snwhitehorn if ((pt->pte_hi ^ (pvo->pvo_pte.lpte.pte_hi & ~LPTE_VALID)) == 2695190681Snwhitehorn LPTE_VALID) { 2696190681Snwhitehorn if ((pvo->pvo_pte.lpte.pte_hi & LPTE_VALID) == 0) { 2697190681Snwhitehorn panic("moea64_pvo_to_pte: pvo %p has valid pte in " 2698190681Snwhitehorn "moea64_pteg_table %p but invalid in pvo", pvo, pt); 2699190681Snwhitehorn } 2700190681Snwhitehorn 2701190681Snwhitehorn if (((pt->pte_lo ^ pvo->pvo_pte.lpte.pte_lo) & 2702205163Snwhitehorn ~(LPTE_M|LPTE_CHG|LPTE_REF)) != 0) { 2703190681Snwhitehorn panic("moea64_pvo_to_pte: pvo %p pte does not match " 2704190681Snwhitehorn "pte %p in moea64_pteg_table difference is %#x", 2705190681Snwhitehorn pvo, pt, 2706190681Snwhitehorn (uint32_t)(pt->pte_lo ^ pvo->pvo_pte.lpte.pte_lo)); 2707190681Snwhitehorn } 2708190681Snwhitehorn 2709190681Snwhitehorn return (pt); 2710190681Snwhitehorn } 2711190681Snwhitehorn 2712190681Snwhitehorn if (pvo->pvo_pte.lpte.pte_hi & LPTE_VALID) { 2713190681Snwhitehorn panic("moea64_pvo_to_pte: pvo %p has invalid pte %p in " 2714190681Snwhitehorn "moea64_pteg_table but valid in pvo", pvo, pt); 2715190681Snwhitehorn } 2716190681Snwhitehorn 2717190681Snwhitehorn return (NULL); 2718190681Snwhitehorn} 2719190681Snwhitehorn 2720209975Snwhitehornstatic __inline int 2721209975Snwhitehornmoea64_pte_spillable_ident(u_int ptegidx) 2722209975Snwhitehorn{ 2723209975Snwhitehorn struct lpte *pt; 2724209975Snwhitehorn int i, j, k; 2725209975Snwhitehorn 2726209975Snwhitehorn /* Start at a random slot */ 2727209975Snwhitehorn i = mftb() % 8; 2728209975Snwhitehorn k = -1; 2729209975Snwhitehorn for (j = 0; j < 8; j++) { 2730209975Snwhitehorn pt = &moea64_pteg_table[ptegidx].pt[(i + j) % 8]; 2731209975Snwhitehorn if (pt->pte_hi & (LPTE_LOCKED | LPTE_WIRED)) 2732209975Snwhitehorn continue; 2733209975Snwhitehorn 2734209975Snwhitehorn /* This is a candidate, so remember it */ 2735209975Snwhitehorn k = (i + j) % 8; 2736209975Snwhitehorn 2737209975Snwhitehorn /* Try to get a page that has not been used lately */ 2738209975Snwhitehorn if (!(pt->pte_lo & LPTE_REF)) 2739209975Snwhitehorn return (k); 2740209975Snwhitehorn } 2741209975Snwhitehorn 2742209975Snwhitehorn return (k); 2743209975Snwhitehorn} 2744209975Snwhitehorn 2745190681Snwhitehornstatic int 2746190681Snwhitehornmoea64_pte_insert(u_int ptegidx, struct lpte *pvo_pt) 2747190681Snwhitehorn{ 2748190681Snwhitehorn struct lpte *pt; 2749209975Snwhitehorn struct pvo_entry *pvo; 2750209975Snwhitehorn u_int pteg_bktidx; 2751190681Snwhitehorn int i; 2752190681Snwhitehorn 2753190681Snwhitehorn ASSERT_TABLE_LOCK(); 2754190681Snwhitehorn 2755190681Snwhitehorn /* 2756190681Snwhitehorn * First try primary hash. 2757190681Snwhitehorn */ 2758209975Snwhitehorn pteg_bktidx = ptegidx; 2759209975Snwhitehorn for (pt = moea64_pteg_table[pteg_bktidx].pt, i = 0; i < 8; i++, pt++) { 2760209975Snwhitehorn if ((pt->pte_hi & (LPTE_VALID | LPTE_LOCKED)) == 0) { 2761190681Snwhitehorn pvo_pt->pte_hi &= ~LPTE_HID; 2762190681Snwhitehorn moea64_pte_set(pt, pvo_pt); 2763190681Snwhitehorn return (i); 2764190681Snwhitehorn } 2765190681Snwhitehorn } 2766190681Snwhitehorn 2767190681Snwhitehorn /* 2768190681Snwhitehorn * Now try secondary hash. 2769190681Snwhitehorn */ 2770209975Snwhitehorn pteg_bktidx ^= moea64_pteg_mask; 2771209975Snwhitehorn for (pt = moea64_pteg_table[pteg_bktidx].pt, i = 0; i < 8; i++, pt++) { 2772209975Snwhitehorn if ((pt->pte_hi & (LPTE_VALID | LPTE_LOCKED)) == 0) { 2773190681Snwhitehorn pvo_pt->pte_hi |= LPTE_HID; 2774190681Snwhitehorn moea64_pte_set(pt, pvo_pt); 2775190681Snwhitehorn return (i); 2776190681Snwhitehorn } 2777190681Snwhitehorn } 2778190681Snwhitehorn 2779209975Snwhitehorn /* 2780209975Snwhitehorn * Out of luck. Find a PTE to sacrifice. 2781209975Snwhitehorn */ 2782209975Snwhitehorn pteg_bktidx = ptegidx; 2783209975Snwhitehorn i = moea64_pte_spillable_ident(pteg_bktidx); 2784209975Snwhitehorn if (i < 0) { 2785209975Snwhitehorn pteg_bktidx ^= moea64_pteg_mask; 2786209975Snwhitehorn i = moea64_pte_spillable_ident(pteg_bktidx); 2787209975Snwhitehorn } 2788209975Snwhitehorn 2789209975Snwhitehorn if (i < 0) { 2790209975Snwhitehorn /* No freeable slots in either PTEG? We're hosed. */ 2791209975Snwhitehorn panic("moea64_pte_insert: overflow"); 2792209975Snwhitehorn return (-1); 2793209975Snwhitehorn } 2794209975Snwhitehorn 2795209975Snwhitehorn if (pteg_bktidx == ptegidx) 2796209975Snwhitehorn pvo_pt->pte_hi &= ~LPTE_HID; 2797209975Snwhitehorn else 2798209975Snwhitehorn pvo_pt->pte_hi |= LPTE_HID; 2799209975Snwhitehorn 2800209975Snwhitehorn /* 2801209975Snwhitehorn * Synchronize the sacrifice PTE with its PVO, then mark both 2802209975Snwhitehorn * invalid. The PVO will be reused when/if the VM system comes 2803209975Snwhitehorn * here after a fault. 2804209975Snwhitehorn */ 2805209975Snwhitehorn pt = &moea64_pteg_table[pteg_bktidx].pt[i]; 2806209975Snwhitehorn 2807209975Snwhitehorn if (pt->pte_hi & LPTE_HID) 2808209975Snwhitehorn pteg_bktidx ^= moea64_pteg_mask; /* PTEs indexed by primary */ 2809209975Snwhitehorn 2810209975Snwhitehorn LIST_FOREACH(pvo, &moea64_pvo_table[pteg_bktidx], pvo_olink) { 2811209975Snwhitehorn if (pvo->pvo_pte.lpte.pte_hi == pt->pte_hi) { 2812209975Snwhitehorn KASSERT(pvo->pvo_pte.lpte.pte_hi & LPTE_VALID, 2813209975Snwhitehorn ("Invalid PVO for valid PTE!")); 2814209975Snwhitehorn moea64_pte_unset(pt, &pvo->pvo_pte.lpte, pvo->pvo_vpn); 2815209975Snwhitehorn PVO_PTEGIDX_CLR(pvo); 2816209975Snwhitehorn moea64_pte_overflow++; 2817209975Snwhitehorn break; 2818209975Snwhitehorn } 2819209975Snwhitehorn } 2820209975Snwhitehorn 2821209975Snwhitehorn KASSERT(pvo->pvo_pte.lpte.pte_hi == pt->pte_hi, 2822209975Snwhitehorn ("Unable to find PVO for spilled PTE")); 2823209975Snwhitehorn 2824209975Snwhitehorn /* 2825209975Snwhitehorn * Set the new PTE. 2826209975Snwhitehorn */ 2827209975Snwhitehorn moea64_pte_set(pt, pvo_pt); 2828209975Snwhitehorn 2829209975Snwhitehorn return (i); 2830190681Snwhitehorn} 2831190681Snwhitehorn 2832190681Snwhitehornstatic boolean_t 2833190681Snwhitehornmoea64_query_bit(vm_page_t m, u_int64_t ptebit) 2834190681Snwhitehorn{ 2835190681Snwhitehorn struct pvo_entry *pvo; 2836190681Snwhitehorn struct lpte *pt; 2837190681Snwhitehorn 2838190681Snwhitehorn if (moea64_attr_fetch(m) & ptebit) 2839190681Snwhitehorn return (TRUE); 2840190681Snwhitehorn 2841208574Salc vm_page_lock_queues(); 2842205370Snwhitehorn 2843190681Snwhitehorn LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2844190681Snwhitehorn MOEA_PVO_CHECK(pvo); /* sanity check */ 2845190681Snwhitehorn 2846190681Snwhitehorn /* 2847190681Snwhitehorn * See if we saved the bit off. If so, cache it and return 2848190681Snwhitehorn * success. 2849190681Snwhitehorn */ 2850190681Snwhitehorn if (pvo->pvo_pte.lpte.pte_lo & ptebit) { 2851190681Snwhitehorn moea64_attr_save(m, ptebit); 2852190681Snwhitehorn MOEA_PVO_CHECK(pvo); /* sanity check */ 2853208574Salc vm_page_unlock_queues(); 2854190681Snwhitehorn return (TRUE); 2855190681Snwhitehorn } 2856190681Snwhitehorn } 2857190681Snwhitehorn 2858190681Snwhitehorn /* 2859190681Snwhitehorn * No luck, now go through the hard part of looking at the PTEs 2860190681Snwhitehorn * themselves. Sync so that any pending REF/CHG bits are flushed to 2861190681Snwhitehorn * the PTEs. 2862190681Snwhitehorn */ 2863190681Snwhitehorn SYNC(); 2864190681Snwhitehorn LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2865190681Snwhitehorn MOEA_PVO_CHECK(pvo); /* sanity check */ 2866190681Snwhitehorn 2867190681Snwhitehorn /* 2868190681Snwhitehorn * See if this pvo has a valid PTE. if so, fetch the 2869190681Snwhitehorn * REF/CHG bits from the valid PTE. If the appropriate 2870190681Snwhitehorn * ptebit is set, cache it and return success. 2871190681Snwhitehorn */ 2872205370Snwhitehorn LOCK_TABLE(); 2873209975Snwhitehorn pt = moea64_pvo_to_pte(pvo); 2874190681Snwhitehorn if (pt != NULL) { 2875190681Snwhitehorn moea64_pte_synch(pt, &pvo->pvo_pte.lpte); 2876190681Snwhitehorn if (pvo->pvo_pte.lpte.pte_lo & ptebit) { 2877190681Snwhitehorn UNLOCK_TABLE(); 2878190681Snwhitehorn 2879190681Snwhitehorn moea64_attr_save(m, ptebit); 2880190681Snwhitehorn MOEA_PVO_CHECK(pvo); /* sanity check */ 2881208574Salc vm_page_unlock_queues(); 2882190681Snwhitehorn return (TRUE); 2883190681Snwhitehorn } 2884190681Snwhitehorn } 2885205370Snwhitehorn UNLOCK_TABLE(); 2886190681Snwhitehorn } 2887190681Snwhitehorn 2888208574Salc vm_page_unlock_queues(); 2889190681Snwhitehorn return (FALSE); 2890190681Snwhitehorn} 2891190681Snwhitehorn 2892190681Snwhitehornstatic u_int 2893208990Salcmoea64_clear_bit(vm_page_t m, u_int64_t ptebit) 2894190681Snwhitehorn{ 2895190681Snwhitehorn u_int count; 2896190681Snwhitehorn struct pvo_entry *pvo; 2897190681Snwhitehorn struct lpte *pt; 2898190681Snwhitehorn 2899208990Salc vm_page_lock_queues(); 2900205370Snwhitehorn 2901190681Snwhitehorn /* 2902190681Snwhitehorn * Clear the cached value. 2903190681Snwhitehorn */ 2904190681Snwhitehorn moea64_attr_clear(m, ptebit); 2905190681Snwhitehorn 2906190681Snwhitehorn /* 2907190681Snwhitehorn * Sync so that any pending REF/CHG bits are flushed to the PTEs (so 2908190681Snwhitehorn * we can reset the right ones). note that since the pvo entries and 2909190681Snwhitehorn * list heads are accessed via BAT0 and are never placed in the page 2910190681Snwhitehorn * table, we don't have to worry about further accesses setting the 2911190681Snwhitehorn * REF/CHG bits. 2912190681Snwhitehorn */ 2913190681Snwhitehorn SYNC(); 2914190681Snwhitehorn 2915190681Snwhitehorn /* 2916190681Snwhitehorn * For each pvo entry, clear the pvo's ptebit. If this pvo has a 2917190681Snwhitehorn * valid pte clear the ptebit from the valid pte. 2918190681Snwhitehorn */ 2919190681Snwhitehorn count = 0; 2920190681Snwhitehorn LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2921190681Snwhitehorn MOEA_PVO_CHECK(pvo); /* sanity check */ 2922190681Snwhitehorn 2923205370Snwhitehorn LOCK_TABLE(); 2924209975Snwhitehorn pt = moea64_pvo_to_pte(pvo); 2925190681Snwhitehorn if (pt != NULL) { 2926190681Snwhitehorn moea64_pte_synch(pt, &pvo->pvo_pte.lpte); 2927190681Snwhitehorn if (pvo->pvo_pte.lpte.pte_lo & ptebit) { 2928190681Snwhitehorn count++; 2929209975Snwhitehorn moea64_pte_clear(pt, pvo->pvo_vpn, ptebit); 2930190681Snwhitehorn } 2931190681Snwhitehorn } 2932190681Snwhitehorn pvo->pvo_pte.lpte.pte_lo &= ~ptebit; 2933190681Snwhitehorn MOEA_PVO_CHECK(pvo); /* sanity check */ 2934205370Snwhitehorn UNLOCK_TABLE(); 2935190681Snwhitehorn } 2936190681Snwhitehorn 2937208990Salc vm_page_unlock_queues(); 2938190681Snwhitehorn return (count); 2939190681Snwhitehorn} 2940190681Snwhitehorn 2941190681Snwhitehornboolean_t 2942190681Snwhitehornmoea64_dev_direct_mapped(mmu_t mmu, vm_offset_t pa, vm_size_t size) 2943190681Snwhitehorn{ 2944204296Snwhitehorn struct pvo_entry *pvo; 2945204296Snwhitehorn vm_offset_t ppa; 2946204296Snwhitehorn int error = 0; 2947204296Snwhitehorn 2948204296Snwhitehorn PMAP_LOCK(kernel_pmap); 2949204296Snwhitehorn for (ppa = pa & ~ADDR_POFF; ppa < pa + size; ppa += PAGE_SIZE) { 2950209975Snwhitehorn pvo = moea64_pvo_find_va(kernel_pmap, ppa); 2951204296Snwhitehorn if (pvo == NULL || 2952204296Snwhitehorn (pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN) != ppa) { 2953204296Snwhitehorn error = EFAULT; 2954204296Snwhitehorn break; 2955204296Snwhitehorn } 2956204296Snwhitehorn } 2957204296Snwhitehorn PMAP_UNLOCK(kernel_pmap); 2958204296Snwhitehorn 2959204296Snwhitehorn return (error); 2960190681Snwhitehorn} 2961190681Snwhitehorn 2962190681Snwhitehorn/* 2963190681Snwhitehorn * Map a set of physical memory pages into the kernel virtual 2964190681Snwhitehorn * address space. Return a pointer to where it is mapped. This 2965190681Snwhitehorn * routine is intended to be used for mapping device memory, 2966190681Snwhitehorn * NOT real memory. 2967190681Snwhitehorn */ 2968190681Snwhitehornvoid * 2969190681Snwhitehornmoea64_mapdev(mmu_t mmu, vm_offset_t pa, vm_size_t size) 2970190681Snwhitehorn{ 2971190681Snwhitehorn vm_offset_t va, tmpva, ppa, offset; 2972190681Snwhitehorn 2973190681Snwhitehorn ppa = trunc_page(pa); 2974190681Snwhitehorn offset = pa & PAGE_MASK; 2975190681Snwhitehorn size = roundup(offset + size, PAGE_SIZE); 2976190681Snwhitehorn 2977190681Snwhitehorn va = kmem_alloc_nofault(kernel_map, size); 2978190681Snwhitehorn 2979190681Snwhitehorn if (!va) 2980190681Snwhitehorn panic("moea64_mapdev: Couldn't alloc kernel virtual memory"); 2981190681Snwhitehorn 2982190681Snwhitehorn for (tmpva = va; size > 0;) { 2983190681Snwhitehorn moea64_kenter(mmu, tmpva, ppa); 2984190681Snwhitehorn size -= PAGE_SIZE; 2985190681Snwhitehorn tmpva += PAGE_SIZE; 2986190681Snwhitehorn ppa += PAGE_SIZE; 2987190681Snwhitehorn } 2988190681Snwhitehorn 2989190681Snwhitehorn return ((void *)(va + offset)); 2990190681Snwhitehorn} 2991190681Snwhitehorn 2992190681Snwhitehornvoid 2993190681Snwhitehornmoea64_unmapdev(mmu_t mmu, vm_offset_t va, vm_size_t size) 2994190681Snwhitehorn{ 2995190681Snwhitehorn vm_offset_t base, offset; 2996190681Snwhitehorn 2997190681Snwhitehorn base = trunc_page(va); 2998190681Snwhitehorn offset = va & PAGE_MASK; 2999190681Snwhitehorn size = roundup(offset + size, PAGE_SIZE); 3000190681Snwhitehorn 3001190681Snwhitehorn kmem_free(kernel_map, base, size); 3002190681Snwhitehorn} 3003190681Snwhitehorn 3004198341Smarcelstatic void 3005198341Smarcelmoea64_sync_icache(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_size_t sz) 3006198341Smarcel{ 3007198341Smarcel struct pvo_entry *pvo; 3008198341Smarcel vm_offset_t lim; 3009198341Smarcel vm_paddr_t pa; 3010198341Smarcel vm_size_t len; 3011198341Smarcel 3012198341Smarcel PMAP_LOCK(pm); 3013198341Smarcel while (sz > 0) { 3014198341Smarcel lim = round_page(va); 3015198341Smarcel len = MIN(lim - va, sz); 3016209975Snwhitehorn pvo = moea64_pvo_find_va(pm, va & ~ADDR_POFF); 3017198341Smarcel if (pvo != NULL) { 3018205163Snwhitehorn pa = (pvo->pvo_pte.pte.pte_lo & LPTE_RPGN) | 3019198341Smarcel (va & ADDR_POFF); 3020198341Smarcel moea64_syncicache(pm, va, pa, len); 3021198341Smarcel } 3022198341Smarcel va += len; 3023198341Smarcel sz -= len; 3024198341Smarcel } 3025198341Smarcel PMAP_UNLOCK(pm); 3026198341Smarcel} 3027