mmu_oea64.c revision 204296
1/*- 2 * Copyright (c) 2001 The NetBSD Foundation, Inc. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to The NetBSD Foundation 6 * by Matt Thomas <matt@3am-software.com> of Allegro Networks, Inc. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by the NetBSD 19 * Foundation, Inc. and its contributors. 20 * 4. Neither the name of The NetBSD Foundation nor the names of its 21 * contributors may be used to endorse or promote products derived 22 * from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 */ 36/*- 37 * Copyright (C) 1995, 1996 Wolfgang Solfrank. 38 * Copyright (C) 1995, 1996 TooLs GmbH. 39 * All rights reserved. 40 * 41 * Redistribution and use in source and binary forms, with or without 42 * modification, are permitted provided that the following conditions 43 * are met: 44 * 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * 2. Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in the 48 * documentation and/or other materials provided with the distribution. 49 * 3. All advertising materials mentioning features or use of this software 50 * must display the following acknowledgement: 51 * This product includes software developed by TooLs GmbH. 52 * 4. The name of TooLs GmbH may not be used to endorse or promote products 53 * derived from this software without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 56 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 57 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 58 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 59 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 60 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 61 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 62 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 63 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 64 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 65 * 66 * $NetBSD: pmap.c,v 1.28 2000/03/26 20:42:36 kleink Exp $ 67 */ 68/*- 69 * Copyright (C) 2001 Benno Rice. 70 * All rights reserved. 71 * 72 * Redistribution and use in source and binary forms, with or without 73 * modification, are permitted provided that the following conditions 74 * are met: 75 * 1. Redistributions of source code must retain the above copyright 76 * notice, this list of conditions and the following disclaimer. 77 * 2. Redistributions in binary form must reproduce the above copyright 78 * notice, this list of conditions and the following disclaimer in the 79 * documentation and/or other materials provided with the distribution. 80 * 81 * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR 82 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 83 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 84 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 85 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 86 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 87 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 88 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 89 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 90 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 91 */ 92 93#include <sys/cdefs.h> 94__FBSDID("$FreeBSD: head/sys/powerpc/aim/mmu_oea64.c 204296 2010-02-25 03:49:17Z nwhitehorn $"); 95 96/* 97 * Manages physical address maps. 98 * 99 * In addition to hardware address maps, this module is called upon to 100 * provide software-use-only maps which may or may not be stored in the 101 * same form as hardware maps. These pseudo-maps are used to store 102 * intermediate results from copy operations to and from address spaces. 103 * 104 * Since the information managed by this module is also stored by the 105 * logical address mapping module, this module may throw away valid virtual 106 * to physical mappings at almost any time. However, invalidations of 107 * mappings must be done as requested. 108 * 109 * In order to cope with hardware architectures which make virtual to 110 * physical map invalidates expensive, this module may delay invalidate 111 * reduced protection operations until such time as they are actually 112 * necessary. This module is given full information as to which processors 113 * are currently using which maps, and to when physical maps must be made 114 * correct. 115 */ 116 117#include "opt_kstack_pages.h" 118 119#include <sys/param.h> 120#include <sys/kernel.h> 121#include <sys/ktr.h> 122#include <sys/lock.h> 123#include <sys/msgbuf.h> 124#include <sys/mutex.h> 125#include <sys/proc.h> 126#include <sys/sysctl.h> 127#include <sys/systm.h> 128#include <sys/vmmeter.h> 129 130#include <sys/kdb.h> 131 132#include <dev/ofw/openfirm.h> 133 134#include <vm/vm.h> 135#include <vm/vm_param.h> 136#include <vm/vm_kern.h> 137#include <vm/vm_page.h> 138#include <vm/vm_map.h> 139#include <vm/vm_object.h> 140#include <vm/vm_extern.h> 141#include <vm/vm_pageout.h> 142#include <vm/vm_pager.h> 143#include <vm/uma.h> 144 145#include <machine/cpu.h> 146#include <machine/platform.h> 147#include <machine/frame.h> 148#include <machine/md_var.h> 149#include <machine/psl.h> 150#include <machine/bat.h> 151#include <machine/pte.h> 152#include <machine/sr.h> 153#include <machine/trap.h> 154#include <machine/mmuvar.h> 155 156#include "mmu_if.h" 157 158#define MOEA_DEBUG 159 160#define TODO panic("%s: not implemented", __func__); 161 162static __inline u_int32_t 163cntlzw(volatile u_int32_t a) { 164 u_int32_t b; 165 __asm ("cntlzw %0, %1" : "=r"(b) : "r"(a)); 166 return b; 167} 168 169static __inline uint64_t 170va_to_vsid(pmap_t pm, vm_offset_t va) 171{ 172 return ((pm->pm_sr[(uintptr_t)va >> ADDR_SR_SHFT]) & SR_VSID_MASK); 173} 174 175#define PTESYNC() __asm __volatile("ptesync"); 176#define TLBSYNC() __asm __volatile("tlbsync; ptesync"); 177#define SYNC() __asm __volatile("sync"); 178#define EIEIO() __asm __volatile("eieio"); 179 180/* 181 * The tlbie instruction must be executed in 64-bit mode 182 * so we have to twiddle MSR[SF] around every invocation. 183 * Just to add to the fun, exceptions must be off as well 184 * so that we can't trap in 64-bit mode. What a pain. 185 */ 186struct mtx tlbie_mutex; 187 188static __inline void 189TLBIE(pmap_t pmap, vm_offset_t va) { 190 uint64_t vpn; 191 register_t vpn_hi, vpn_lo; 192 register_t msr; 193 register_t scratch; 194 195 vpn = (uint64_t)(va & ADDR_PIDX); 196 if (pmap != NULL) 197 vpn |= (va_to_vsid(pmap,va) << 28); 198 vpn &= ~(0xffffULL << 48); 199 200 vpn_hi = (uint32_t)(vpn >> 32); 201 vpn_lo = (uint32_t)vpn; 202 203 mtx_lock_spin(&tlbie_mutex); 204 __asm __volatile("\ 205 mfmsr %0; \ 206 mr %1, %0; \ 207 insrdi %1,%5,1,0; \ 208 mtmsrd %1; \ 209 ptesync; \ 210 \ 211 sld %1,%2,%4; \ 212 or %1,%1,%3; \ 213 tlbie %1; \ 214 \ 215 mtmsrd %0; \ 216 eieio; \ 217 tlbsync; \ 218 ptesync;" 219 : "=r"(msr), "=r"(scratch) : "r"(vpn_hi), "r"(vpn_lo), "r"(32), "r"(1) 220 : "memory"); 221 mtx_unlock_spin(&tlbie_mutex); 222} 223 224#define DISABLE_TRANS(msr) msr = mfmsr(); mtmsr(msr & ~PSL_DR); isync() 225#define ENABLE_TRANS(msr) mtmsr(msr); isync() 226 227#define VSID_MAKE(sr, hash) ((sr) | (((hash) & 0xfffff) << 4)) 228#define VSID_TO_SR(vsid) ((vsid) & 0xf) 229#define VSID_TO_HASH(vsid) (((vsid) >> 4) & 0xfffff) 230#define VSID_HASH_MASK 0x0000007fffffffffULL 231 232#define PVO_PTEGIDX_MASK 0x007UL /* which PTEG slot */ 233#define PVO_PTEGIDX_VALID 0x008UL /* slot is valid */ 234#define PVO_WIRED 0x010UL /* PVO entry is wired */ 235#define PVO_MANAGED 0x020UL /* PVO entry is managed */ 236#define PVO_BOOTSTRAP 0x080UL /* PVO entry allocated during 237 bootstrap */ 238#define PVO_FAKE 0x100UL /* fictitious phys page */ 239#define PVO_VADDR(pvo) ((pvo)->pvo_vaddr & ~ADDR_POFF) 240#define PVO_ISFAKE(pvo) ((pvo)->pvo_vaddr & PVO_FAKE) 241#define PVO_PTEGIDX_GET(pvo) ((pvo)->pvo_vaddr & PVO_PTEGIDX_MASK) 242#define PVO_PTEGIDX_ISSET(pvo) ((pvo)->pvo_vaddr & PVO_PTEGIDX_VALID) 243#define PVO_PTEGIDX_CLR(pvo) \ 244 ((void)((pvo)->pvo_vaddr &= ~(PVO_PTEGIDX_VALID|PVO_PTEGIDX_MASK))) 245#define PVO_PTEGIDX_SET(pvo, i) \ 246 ((void)((pvo)->pvo_vaddr |= (i)|PVO_PTEGIDX_VALID)) 247 248#define MOEA_PVO_CHECK(pvo) 249 250#define LOCK_TABLE() mtx_lock(&moea64_table_mutex) 251#define UNLOCK_TABLE() mtx_unlock(&moea64_table_mutex); 252#define ASSERT_TABLE_LOCK() mtx_assert(&moea64_table_mutex, MA_OWNED) 253 254struct ofw_map { 255 vm_offset_t om_va; 256 vm_size_t om_len; 257 vm_offset_t om_pa_hi; 258 vm_offset_t om_pa_lo; 259 u_int om_mode; 260}; 261 262/* 263 * Map of physical memory regions. 264 */ 265static struct mem_region *regions; 266static struct mem_region *pregions; 267extern u_int phys_avail_count; 268extern int regions_sz, pregions_sz; 269extern int ofw_real_mode; 270 271extern struct pmap ofw_pmap; 272 273extern void bs_remap_earlyboot(void); 274 275 276/* 277 * Lock for the pteg and pvo tables. 278 */ 279struct mtx moea64_table_mutex; 280 281/* 282 * PTEG data. 283 */ 284static struct lpteg *moea64_pteg_table; 285u_int moea64_pteg_count; 286u_int moea64_pteg_mask; 287 288/* 289 * PVO data. 290 */ 291struct pvo_head *moea64_pvo_table; /* pvo entries by pteg index */ 292/* lists of unmanaged pages */ 293struct pvo_head moea64_pvo_kunmanaged = 294 LIST_HEAD_INITIALIZER(moea64_pvo_kunmanaged); 295struct pvo_head moea64_pvo_unmanaged = 296 LIST_HEAD_INITIALIZER(moea64_pvo_unmanaged); 297 298uma_zone_t moea64_upvo_zone; /* zone for pvo entries for unmanaged pages */ 299uma_zone_t moea64_mpvo_zone; /* zone for pvo entries for managed pages */ 300 301#define BPVO_POOL_SIZE 327680 302static struct pvo_entry *moea64_bpvo_pool; 303static int moea64_bpvo_pool_index = 0; 304 305#define VSID_NBPW (sizeof(u_int32_t) * 8) 306static u_int moea64_vsid_bitmap[NPMAPS / VSID_NBPW]; 307 308static boolean_t moea64_initialized = FALSE; 309 310/* 311 * Statistics. 312 */ 313u_int moea64_pte_valid = 0; 314u_int moea64_pte_overflow = 0; 315u_int moea64_pvo_entries = 0; 316u_int moea64_pvo_enter_calls = 0; 317u_int moea64_pvo_remove_calls = 0; 318SYSCTL_INT(_machdep, OID_AUTO, moea64_pte_valid, CTLFLAG_RD, 319 &moea64_pte_valid, 0, ""); 320SYSCTL_INT(_machdep, OID_AUTO, moea64_pte_overflow, CTLFLAG_RD, 321 &moea64_pte_overflow, 0, ""); 322SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_entries, CTLFLAG_RD, 323 &moea64_pvo_entries, 0, ""); 324SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_enter_calls, CTLFLAG_RD, 325 &moea64_pvo_enter_calls, 0, ""); 326SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_remove_calls, CTLFLAG_RD, 327 &moea64_pvo_remove_calls, 0, ""); 328 329vm_offset_t moea64_scratchpage_va[2]; 330struct pvo_entry *moea64_scratchpage_pvo[2]; 331struct lpte *moea64_scratchpage_pte[2]; 332struct mtx moea64_scratchpage_mtx; 333 334/* 335 * Allocate physical memory for use in moea64_bootstrap. 336 */ 337static vm_offset_t moea64_bootstrap_alloc(vm_size_t, u_int); 338 339/* 340 * PTE calls. 341 */ 342static int moea64_pte_insert(u_int, struct lpte *); 343 344/* 345 * PVO calls. 346 */ 347static int moea64_pvo_enter(pmap_t, uma_zone_t, struct pvo_head *, 348 vm_offset_t, vm_offset_t, uint64_t, int); 349static void moea64_pvo_remove(struct pvo_entry *, int); 350static struct pvo_entry *moea64_pvo_find_va(pmap_t, vm_offset_t, int *); 351static struct lpte *moea64_pvo_to_pte(const struct pvo_entry *, int); 352 353/* 354 * Utility routines. 355 */ 356static void moea64_bridge_bootstrap(mmu_t mmup, 357 vm_offset_t kernelstart, vm_offset_t kernelend); 358static void moea64_bridge_cpu_bootstrap(mmu_t, int ap); 359static void moea64_enter_locked(pmap_t, vm_offset_t, vm_page_t, 360 vm_prot_t, boolean_t); 361static boolean_t moea64_query_bit(vm_page_t, u_int64_t); 362static u_int moea64_clear_bit(vm_page_t, u_int64_t, u_int64_t *); 363static void moea64_kremove(mmu_t, vm_offset_t); 364static void moea64_syncicache(pmap_t pmap, vm_offset_t va, 365 vm_offset_t pa, vm_size_t sz); 366static void tlbia(void); 367 368/* 369 * Kernel MMU interface 370 */ 371void moea64_change_wiring(mmu_t, pmap_t, vm_offset_t, boolean_t); 372void moea64_clear_modify(mmu_t, vm_page_t); 373void moea64_clear_reference(mmu_t, vm_page_t); 374void moea64_copy_page(mmu_t, vm_page_t, vm_page_t); 375void moea64_enter(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t, boolean_t); 376void moea64_enter_object(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_page_t, 377 vm_prot_t); 378void moea64_enter_quick(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t); 379vm_paddr_t moea64_extract(mmu_t, pmap_t, vm_offset_t); 380vm_page_t moea64_extract_and_hold(mmu_t, pmap_t, vm_offset_t, vm_prot_t); 381void moea64_init(mmu_t); 382boolean_t moea64_is_modified(mmu_t, vm_page_t); 383boolean_t moea64_ts_referenced(mmu_t, vm_page_t); 384vm_offset_t moea64_map(mmu_t, vm_offset_t *, vm_offset_t, vm_offset_t, int); 385boolean_t moea64_page_exists_quick(mmu_t, pmap_t, vm_page_t); 386int moea64_page_wired_mappings(mmu_t, vm_page_t); 387void moea64_pinit(mmu_t, pmap_t); 388void moea64_pinit0(mmu_t, pmap_t); 389void moea64_protect(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_prot_t); 390void moea64_qenter(mmu_t, vm_offset_t, vm_page_t *, int); 391void moea64_qremove(mmu_t, vm_offset_t, int); 392void moea64_release(mmu_t, pmap_t); 393void moea64_remove(mmu_t, pmap_t, vm_offset_t, vm_offset_t); 394void moea64_remove_all(mmu_t, vm_page_t); 395void moea64_remove_write(mmu_t, vm_page_t); 396void moea64_zero_page(mmu_t, vm_page_t); 397void moea64_zero_page_area(mmu_t, vm_page_t, int, int); 398void moea64_zero_page_idle(mmu_t, vm_page_t); 399void moea64_activate(mmu_t, struct thread *); 400void moea64_deactivate(mmu_t, struct thread *); 401void *moea64_mapdev(mmu_t, vm_offset_t, vm_size_t); 402void moea64_unmapdev(mmu_t, vm_offset_t, vm_size_t); 403vm_offset_t moea64_kextract(mmu_t, vm_offset_t); 404void moea64_kenter(mmu_t, vm_offset_t, vm_offset_t); 405boolean_t moea64_dev_direct_mapped(mmu_t, vm_offset_t, vm_size_t); 406static void moea64_sync_icache(mmu_t, pmap_t, vm_offset_t, vm_size_t); 407 408static mmu_method_t moea64_bridge_methods[] = { 409 MMUMETHOD(mmu_change_wiring, moea64_change_wiring), 410 MMUMETHOD(mmu_clear_modify, moea64_clear_modify), 411 MMUMETHOD(mmu_clear_reference, moea64_clear_reference), 412 MMUMETHOD(mmu_copy_page, moea64_copy_page), 413 MMUMETHOD(mmu_enter, moea64_enter), 414 MMUMETHOD(mmu_enter_object, moea64_enter_object), 415 MMUMETHOD(mmu_enter_quick, moea64_enter_quick), 416 MMUMETHOD(mmu_extract, moea64_extract), 417 MMUMETHOD(mmu_extract_and_hold, moea64_extract_and_hold), 418 MMUMETHOD(mmu_init, moea64_init), 419 MMUMETHOD(mmu_is_modified, moea64_is_modified), 420 MMUMETHOD(mmu_ts_referenced, moea64_ts_referenced), 421 MMUMETHOD(mmu_map, moea64_map), 422 MMUMETHOD(mmu_page_exists_quick,moea64_page_exists_quick), 423 MMUMETHOD(mmu_page_wired_mappings,moea64_page_wired_mappings), 424 MMUMETHOD(mmu_pinit, moea64_pinit), 425 MMUMETHOD(mmu_pinit0, moea64_pinit0), 426 MMUMETHOD(mmu_protect, moea64_protect), 427 MMUMETHOD(mmu_qenter, moea64_qenter), 428 MMUMETHOD(mmu_qremove, moea64_qremove), 429 MMUMETHOD(mmu_release, moea64_release), 430 MMUMETHOD(mmu_remove, moea64_remove), 431 MMUMETHOD(mmu_remove_all, moea64_remove_all), 432 MMUMETHOD(mmu_remove_write, moea64_remove_write), 433 MMUMETHOD(mmu_sync_icache, moea64_sync_icache), 434 MMUMETHOD(mmu_zero_page, moea64_zero_page), 435 MMUMETHOD(mmu_zero_page_area, moea64_zero_page_area), 436 MMUMETHOD(mmu_zero_page_idle, moea64_zero_page_idle), 437 MMUMETHOD(mmu_activate, moea64_activate), 438 MMUMETHOD(mmu_deactivate, moea64_deactivate), 439 440 /* Internal interfaces */ 441 MMUMETHOD(mmu_bootstrap, moea64_bridge_bootstrap), 442 MMUMETHOD(mmu_cpu_bootstrap, moea64_bridge_cpu_bootstrap), 443 MMUMETHOD(mmu_mapdev, moea64_mapdev), 444 MMUMETHOD(mmu_unmapdev, moea64_unmapdev), 445 MMUMETHOD(mmu_kextract, moea64_kextract), 446 MMUMETHOD(mmu_kenter, moea64_kenter), 447 MMUMETHOD(mmu_dev_direct_mapped,moea64_dev_direct_mapped), 448 449 { 0, 0 } 450}; 451 452static mmu_def_t oea64_bridge_mmu = { 453 MMU_TYPE_G5, 454 moea64_bridge_methods, 455 0 456}; 457MMU_DEF(oea64_bridge_mmu); 458 459static __inline u_int 460va_to_pteg(uint64_t vsid, vm_offset_t addr) 461{ 462 uint64_t hash; 463 464 hash = (vsid & VSID_HASH_MASK) ^ (((uint64_t)addr & ADDR_PIDX) >> 465 ADDR_PIDX_SHFT); 466 return (hash & moea64_pteg_mask); 467} 468 469static __inline struct pvo_head * 470pa_to_pvoh(vm_offset_t pa, vm_page_t *pg_p) 471{ 472 struct vm_page *pg; 473 474 pg = PHYS_TO_VM_PAGE(pa); 475 476 if (pg_p != NULL) 477 *pg_p = pg; 478 479 if (pg == NULL) 480 return (&moea64_pvo_unmanaged); 481 482 return (&pg->md.mdpg_pvoh); 483} 484 485static __inline struct pvo_head * 486vm_page_to_pvoh(vm_page_t m) 487{ 488 489 return (&m->md.mdpg_pvoh); 490} 491 492static __inline void 493moea64_attr_clear(vm_page_t m, u_int64_t ptebit) 494{ 495 496 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 497 m->md.mdpg_attrs &= ~ptebit; 498} 499 500static __inline u_int64_t 501moea64_attr_fetch(vm_page_t m) 502{ 503 504 return (m->md.mdpg_attrs); 505} 506 507static __inline void 508moea64_attr_save(vm_page_t m, u_int64_t ptebit) 509{ 510 511 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 512 m->md.mdpg_attrs |= ptebit; 513} 514 515static __inline void 516moea64_pte_create(struct lpte *pt, uint64_t vsid, vm_offset_t va, 517 uint64_t pte_lo) 518{ 519 ASSERT_TABLE_LOCK(); 520 521 /* 522 * Construct a PTE. Default to IMB initially. Valid bit only gets 523 * set when the real pte is set in memory. 524 * 525 * Note: Don't set the valid bit for correct operation of tlb update. 526 */ 527 pt->pte_hi = (vsid << LPTE_VSID_SHIFT) | 528 (((uint64_t)(va & ADDR_PIDX) >> ADDR_API_SHFT64) & LPTE_API); 529 530 pt->pte_lo = pte_lo; 531} 532 533static __inline void 534moea64_pte_synch(struct lpte *pt, struct lpte *pvo_pt) 535{ 536 537 ASSERT_TABLE_LOCK(); 538 539 pvo_pt->pte_lo |= pt->pte_lo & (LPTE_REF | LPTE_CHG); 540} 541 542static __inline void 543moea64_pte_clear(struct lpte *pt, pmap_t pmap, vm_offset_t va, u_int64_t ptebit) 544{ 545 ASSERT_TABLE_LOCK(); 546 547 /* 548 * As shown in Section 7.6.3.2.3 549 */ 550 pt->pte_lo &= ~ptebit; 551 TLBIE(pmap,va); 552} 553 554static __inline void 555moea64_pte_set(struct lpte *pt, struct lpte *pvo_pt) 556{ 557 558 ASSERT_TABLE_LOCK(); 559 pvo_pt->pte_hi |= LPTE_VALID; 560 561 /* 562 * Update the PTE as defined in section 7.6.3.1. 563 * Note that the REF/CHG bits are from pvo_pt and thus should have 564 * been saved so this routine can restore them (if desired). 565 */ 566 pt->pte_lo = pvo_pt->pte_lo; 567 EIEIO(); 568 pt->pte_hi = pvo_pt->pte_hi; 569 PTESYNC(); 570 moea64_pte_valid++; 571} 572 573static __inline void 574moea64_pte_unset(struct lpte *pt, struct lpte *pvo_pt, pmap_t pmap, vm_offset_t va) 575{ 576 ASSERT_TABLE_LOCK(); 577 pvo_pt->pte_hi &= ~LPTE_VALID; 578 579 /* 580 * Force the reg & chg bits back into the PTEs. 581 */ 582 SYNC(); 583 584 /* 585 * Invalidate the pte. 586 */ 587 pt->pte_hi &= ~LPTE_VALID; 588 TLBIE(pmap,va); 589 590 /* 591 * Save the reg & chg bits. 592 */ 593 moea64_pte_synch(pt, pvo_pt); 594 moea64_pte_valid--; 595} 596 597static __inline void 598moea64_pte_change(struct lpte *pt, struct lpte *pvo_pt, pmap_t pmap, vm_offset_t va) 599{ 600 601 /* 602 * Invalidate the PTE 603 */ 604 moea64_pte_unset(pt, pvo_pt, pmap, va); 605 moea64_pte_set(pt, pvo_pt); 606 if (pmap == kernel_pmap) 607 isync(); 608} 609 610static __inline uint64_t 611moea64_calc_wimg(vm_offset_t pa) 612{ 613 uint64_t pte_lo; 614 int i; 615 616 /* 617 * Assume the page is cache inhibited and access is guarded unless 618 * it's in our available memory array. 619 */ 620 pte_lo = LPTE_I | LPTE_G; 621 for (i = 0; i < pregions_sz; i++) { 622 if ((pa >= pregions[i].mr_start) && 623 (pa < (pregions[i].mr_start + pregions[i].mr_size))) { 624 pte_lo &= ~(LPTE_I | LPTE_G); 625 pte_lo |= LPTE_M; 626 break; 627 } 628 } 629 630 return pte_lo; 631} 632 633/* 634 * Quick sort callout for comparing memory regions. 635 */ 636static int mr_cmp(const void *a, const void *b); 637static int om_cmp(const void *a, const void *b); 638 639static int 640mr_cmp(const void *a, const void *b) 641{ 642 const struct mem_region *regiona; 643 const struct mem_region *regionb; 644 645 regiona = a; 646 regionb = b; 647 if (regiona->mr_start < regionb->mr_start) 648 return (-1); 649 else if (regiona->mr_start > regionb->mr_start) 650 return (1); 651 else 652 return (0); 653} 654 655static int 656om_cmp(const void *a, const void *b) 657{ 658 const struct ofw_map *mapa; 659 const struct ofw_map *mapb; 660 661 mapa = a; 662 mapb = b; 663 if (mapa->om_pa_hi < mapb->om_pa_hi) 664 return (-1); 665 else if (mapa->om_pa_hi > mapb->om_pa_hi) 666 return (1); 667 else if (mapa->om_pa_lo < mapb->om_pa_lo) 668 return (-1); 669 else if (mapa->om_pa_lo > mapb->om_pa_lo) 670 return (1); 671 else 672 return (0); 673} 674 675static void 676moea64_bridge_cpu_bootstrap(mmu_t mmup, int ap) 677{ 678 int i = 0; 679 680 /* 681 * Initialize segment registers and MMU 682 */ 683 684 mtmsr(mfmsr() & ~PSL_DR & ~PSL_IR); isync(); 685 for (i = 0; i < 16; i++) { 686 mtsrin(i << ADDR_SR_SHFT, kernel_pmap->pm_sr[i]); 687 } 688 __asm __volatile ("ptesync; mtsdr1 %0; isync" 689 :: "r"((u_int)moea64_pteg_table 690 | (32 - cntlzw(moea64_pteg_mask >> 11)))); 691 tlbia(); 692} 693 694static void 695moea64_add_ofw_mappings(mmu_t mmup, phandle_t mmu, size_t sz) 696{ 697 struct ofw_map translations[sz/sizeof(struct ofw_map)]; 698 register_t msr; 699 vm_offset_t off; 700 vm_paddr_t pa_base; 701 int i, ofw_mappings; 702 703 bzero(translations, sz); 704 if (OF_getprop(mmu, "translations", translations, sz) == -1) 705 panic("moea64_bootstrap: can't get ofw translations"); 706 707 CTR0(KTR_PMAP, "moea64_add_ofw_mappings: translations"); 708 sz /= sizeof(*translations); 709 qsort(translations, sz, sizeof (*translations), om_cmp); 710 711 for (i = 0, ofw_mappings = 0; i < sz; i++) { 712 CTR3(KTR_PMAP, "translation: pa=%#x va=%#x len=%#x", 713 (uint32_t)(translations[i].om_pa_lo), translations[i].om_va, 714 translations[i].om_len); 715 716 if (translations[i].om_pa_lo % PAGE_SIZE) 717 panic("OFW translation not page-aligned!"); 718 719 if (translations[i].om_pa_hi) 720 panic("OFW translations above 32-bit boundary!"); 721 722 pa_base = translations[i].om_pa_lo; 723 724 /* Now enter the pages for this mapping */ 725 726 DISABLE_TRANS(msr); 727 for (off = 0; off < translations[i].om_len; off += PAGE_SIZE) { 728 moea64_kenter(mmup, translations[i].om_va + off, 729 pa_base + off); 730 731 ofw_mappings++; 732 } 733 ENABLE_TRANS(msr); 734 } 735} 736 737static void 738moea64_bridge_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend) 739{ 740 ihandle_t mmui; 741 phandle_t chosen; 742 phandle_t mmu; 743 size_t sz; 744 int i, j; 745 vm_size_t size, physsz, hwphyssz; 746 vm_offset_t pa, va, off; 747 register_t msr; 748 void *dpcpu; 749 750 /* We don't have a direct map since there is no BAT */ 751 hw_direct_map = 0; 752 753 /* Make sure battable is zero, since we have no BAT */ 754 for (i = 0; i < 16; i++) { 755 battable[i].batu = 0; 756 battable[i].batl = 0; 757 } 758 759 /* Get physical memory regions from firmware */ 760 mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz); 761 CTR0(KTR_PMAP, "moea64_bootstrap: physical memory"); 762 763 qsort(pregions, pregions_sz, sizeof(*pregions), mr_cmp); 764 if (sizeof(phys_avail)/sizeof(phys_avail[0]) < regions_sz) 765 panic("moea64_bootstrap: phys_avail too small"); 766 qsort(regions, regions_sz, sizeof(*regions), mr_cmp); 767 phys_avail_count = 0; 768 physsz = 0; 769 hwphyssz = 0; 770 TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz); 771 for (i = 0, j = 0; i < regions_sz; i++, j += 2) { 772 CTR3(KTR_PMAP, "region: %#x - %#x (%#x)", regions[i].mr_start, 773 regions[i].mr_start + regions[i].mr_size, 774 regions[i].mr_size); 775 if (hwphyssz != 0 && 776 (physsz + regions[i].mr_size) >= hwphyssz) { 777 if (physsz < hwphyssz) { 778 phys_avail[j] = regions[i].mr_start; 779 phys_avail[j + 1] = regions[i].mr_start + 780 hwphyssz - physsz; 781 physsz = hwphyssz; 782 phys_avail_count++; 783 } 784 break; 785 } 786 phys_avail[j] = regions[i].mr_start; 787 phys_avail[j + 1] = regions[i].mr_start + regions[i].mr_size; 788 phys_avail_count++; 789 physsz += regions[i].mr_size; 790 } 791 physmem = btoc(physsz); 792 793 /* 794 * Allocate PTEG table. 795 */ 796#ifdef PTEGCOUNT 797 moea64_pteg_count = PTEGCOUNT; 798#else 799 moea64_pteg_count = 0x1000; 800 801 while (moea64_pteg_count < physmem) 802 moea64_pteg_count <<= 1; 803#endif /* PTEGCOUNT */ 804 805 size = moea64_pteg_count * sizeof(struct lpteg); 806 CTR2(KTR_PMAP, "moea64_bootstrap: %d PTEGs, %d bytes", 807 moea64_pteg_count, size); 808 809 /* 810 * We now need to allocate memory. This memory, to be allocated, 811 * has to reside in a page table. The page table we are about to 812 * allocate. We don't have BAT. So drop to data real mode for a minute 813 * as a measure of last resort. We do this a couple times. 814 */ 815 816 moea64_pteg_table = (struct lpteg *)moea64_bootstrap_alloc(size, size); 817 DISABLE_TRANS(msr); 818 bzero((void *)moea64_pteg_table, moea64_pteg_count * sizeof(struct lpteg)); 819 ENABLE_TRANS(msr); 820 821 moea64_pteg_mask = moea64_pteg_count - 1; 822 823 CTR1(KTR_PMAP, "moea64_bootstrap: PTEG table at %p", moea64_pteg_table); 824 825 /* 826 * Allocate pv/overflow lists. 827 */ 828 size = sizeof(struct pvo_head) * moea64_pteg_count; 829 830 moea64_pvo_table = (struct pvo_head *)moea64_bootstrap_alloc(size, 831 PAGE_SIZE); 832 CTR1(KTR_PMAP, "moea64_bootstrap: PVO table at %p", moea64_pvo_table); 833 834 DISABLE_TRANS(msr); 835 for (i = 0; i < moea64_pteg_count; i++) 836 LIST_INIT(&moea64_pvo_table[i]); 837 ENABLE_TRANS(msr); 838 839 /* 840 * Initialize the lock that synchronizes access to the pteg and pvo 841 * tables. 842 */ 843 mtx_init(&moea64_table_mutex, "pmap table", NULL, MTX_DEF | 844 MTX_RECURSE); 845 846 /* 847 * Initialize the TLBIE lock. TLBIE can only be executed by one CPU. 848 */ 849 mtx_init(&tlbie_mutex, "tlbie mutex", NULL, MTX_SPIN); 850 851 /* 852 * Initialise the unmanaged pvo pool. 853 */ 854 moea64_bpvo_pool = (struct pvo_entry *)moea64_bootstrap_alloc( 855 BPVO_POOL_SIZE*sizeof(struct pvo_entry), 0); 856 moea64_bpvo_pool_index = 0; 857 858 /* 859 * Make sure kernel vsid is allocated as well as VSID 0. 860 */ 861 moea64_vsid_bitmap[(KERNEL_VSIDBITS & (NPMAPS - 1)) / VSID_NBPW] 862 |= 1 << (KERNEL_VSIDBITS % VSID_NBPW); 863 moea64_vsid_bitmap[0] |= 1; 864 865 /* 866 * Initialize the kernel pmap (which is statically allocated). 867 */ 868 for (i = 0; i < 16; i++) 869 kernel_pmap->pm_sr[i] = EMPTY_SEGMENT + i; 870 871 kernel_pmap->pmap_phys = kernel_pmap; 872 kernel_pmap->pm_active = ~0; 873 874 PMAP_LOCK_INIT(kernel_pmap); 875 876 /* 877 * Now map in all the other buffers we allocated earlier 878 */ 879 880 DISABLE_TRANS(msr); 881 size = moea64_pteg_count * sizeof(struct lpteg); 882 off = (vm_offset_t)(moea64_pteg_table); 883 for (pa = off; pa < off + size; pa += PAGE_SIZE) 884 moea64_kenter(mmup, pa, pa); 885 size = sizeof(struct pvo_head) * moea64_pteg_count; 886 off = (vm_offset_t)(moea64_pvo_table); 887 for (pa = off; pa < off + size; pa += PAGE_SIZE) 888 moea64_kenter(mmup, pa, pa); 889 size = BPVO_POOL_SIZE*sizeof(struct pvo_entry); 890 off = (vm_offset_t)(moea64_bpvo_pool); 891 for (pa = off; pa < off + size; pa += PAGE_SIZE) 892 moea64_kenter(mmup, pa, pa); 893 894 /* 895 * Map certain important things, like ourselves. 896 * 897 * NOTE: We do not map the exception vector space. That code is 898 * used only in real mode, and leaving it unmapped allows us to 899 * catch NULL pointer deferences, instead of making NULL a valid 900 * address. 901 */ 902 903 for (pa = kernelstart & ~PAGE_MASK; pa < kernelend; pa += PAGE_SIZE) 904 moea64_kenter(mmup, pa, pa); 905 ENABLE_TRANS(msr); 906 907 if (!ofw_real_mode) { 908 /* 909 * Set up the Open Firmware pmap and add its mappings. 910 */ 911 912 moea64_pinit(mmup, &ofw_pmap); 913 for (i = 0; i < 16; i++) 914 ofw_pmap.pm_sr[i] = kernel_pmap->pm_sr[i]; 915 916 if ((chosen = OF_finddevice("/chosen")) == -1) 917 panic("moea64_bootstrap: can't find /chosen"); 918 OF_getprop(chosen, "mmu", &mmui, 4); 919 if ((mmu = OF_instance_to_package(mmui)) == -1) 920 panic("moea64_bootstrap: can't get mmu package"); 921 if ((sz = OF_getproplen(mmu, "translations")) == -1) 922 panic("moea64_bootstrap: can't get ofw translation count"); 923 if (sz > 6144 /* tmpstksz - 2 KB headroom */) 924 panic("moea64_bootstrap: too many ofw translations"); 925 926 moea64_add_ofw_mappings(mmup, mmu, sz); 927 } 928 929#ifdef SMP 930 TLBSYNC(); 931#endif 932 933 /* 934 * Calculate the last available physical address. 935 */ 936 for (i = 0; phys_avail[i + 2] != 0; i += 2) 937 ; 938 Maxmem = powerpc_btop(phys_avail[i + 1]); 939 940 /* 941 * Initialize MMU and remap early physical mappings 942 */ 943 moea64_bridge_cpu_bootstrap(mmup,0); 944 mtmsr(mfmsr() | PSL_DR | PSL_IR); isync(); 945 pmap_bootstrapped++; 946 bs_remap_earlyboot(); 947 948 /* 949 * Set the start and end of kva. 950 */ 951 virtual_avail = VM_MIN_KERNEL_ADDRESS; 952 virtual_end = VM_MAX_SAFE_KERNEL_ADDRESS; 953 954 /* 955 * Figure out how far we can extend virtual_end into segment 16 956 * without running into existing mappings. Segment 16 is guaranteed 957 * to contain neither RAM nor devices (at least on Apple hardware), 958 * but will generally contain some OFW mappings we should not 959 * step on. 960 */ 961 962 PMAP_LOCK(kernel_pmap); 963 while (moea64_pvo_find_va(kernel_pmap, virtual_end+1, NULL) == NULL) 964 virtual_end += PAGE_SIZE; 965 PMAP_UNLOCK(kernel_pmap); 966 967 /* 968 * Allocate some things for page zeroing 969 */ 970 971 mtx_init(&moea64_scratchpage_mtx, "pvo zero page", NULL, MTX_DEF); 972 for (i = 0; i < 2; i++) { 973 moea64_scratchpage_va[i] = virtual_avail; 974 virtual_avail += PAGE_SIZE; 975 976 moea64_kenter(mmup,moea64_scratchpage_va[i],kernelstart); 977 978 LOCK_TABLE(); 979 moea64_scratchpage_pvo[i] = moea64_pvo_find_va(kernel_pmap, 980 moea64_scratchpage_va[i],&j); 981 moea64_scratchpage_pte[i] = moea64_pvo_to_pte( 982 moea64_scratchpage_pvo[i],j); 983 moea64_scratchpage_pte[i]->pte_hi |= LPTE_LOCKED; 984 UNLOCK_TABLE(); 985 } 986 987 /* 988 * Allocate a kernel stack with a guard page for thread0 and map it 989 * into the kernel page map. 990 */ 991 pa = moea64_bootstrap_alloc(KSTACK_PAGES * PAGE_SIZE, PAGE_SIZE); 992 va = virtual_avail + KSTACK_GUARD_PAGES * PAGE_SIZE; 993 virtual_avail = va + KSTACK_PAGES * PAGE_SIZE; 994 CTR2(KTR_PMAP, "moea_bootstrap: kstack0 at %#x (%#x)", pa, va); 995 thread0.td_kstack = va; 996 thread0.td_kstack_pages = KSTACK_PAGES; 997 for (i = 0; i < KSTACK_PAGES; i++) { 998 moea64_kenter(mmup, va, pa); 999 pa += PAGE_SIZE; 1000 va += PAGE_SIZE; 1001 } 1002 1003 /* 1004 * Allocate virtual address space for the message buffer. 1005 */ 1006 pa = msgbuf_phys = moea64_bootstrap_alloc(MSGBUF_SIZE, PAGE_SIZE); 1007 msgbufp = (struct msgbuf *)msgbuf_phys; 1008 while (pa - msgbuf_phys < MSGBUF_SIZE) { 1009 moea64_kenter(mmup, pa, pa); 1010 pa += PAGE_SIZE; 1011 } 1012 1013 /* 1014 * Allocate virtual address space for the dynamic percpu area. 1015 */ 1016 pa = moea64_bootstrap_alloc(DPCPU_SIZE, PAGE_SIZE); 1017 dpcpu = (void *)pa; 1018 while (pa - (vm_offset_t)dpcpu < DPCPU_SIZE) { 1019 moea64_kenter(mmup, pa, pa); 1020 pa += PAGE_SIZE; 1021 } 1022 dpcpu_init(dpcpu, 0); 1023} 1024 1025/* 1026 * Activate a user pmap. The pmap must be activated before it's address 1027 * space can be accessed in any way. 1028 */ 1029void 1030moea64_activate(mmu_t mmu, struct thread *td) 1031{ 1032 pmap_t pm, pmr; 1033 1034 /* 1035 * Load all the data we need up front to encourage the compiler to 1036 * not issue any loads while we have interrupts disabled below. 1037 */ 1038 pm = &td->td_proc->p_vmspace->vm_pmap; 1039 pmr = pm->pmap_phys; 1040 1041 pm->pm_active |= PCPU_GET(cpumask); 1042 PCPU_SET(curpmap, pmr); 1043} 1044 1045void 1046moea64_deactivate(mmu_t mmu, struct thread *td) 1047{ 1048 pmap_t pm; 1049 1050 pm = &td->td_proc->p_vmspace->vm_pmap; 1051 pm->pm_active &= ~(PCPU_GET(cpumask)); 1052 PCPU_SET(curpmap, NULL); 1053} 1054 1055void 1056moea64_change_wiring(mmu_t mmu, pmap_t pm, vm_offset_t va, boolean_t wired) 1057{ 1058 struct pvo_entry *pvo; 1059 1060 PMAP_LOCK(pm); 1061 pvo = moea64_pvo_find_va(pm, va & ~ADDR_POFF, NULL); 1062 1063 if (pvo != NULL) { 1064 if (wired) { 1065 if ((pvo->pvo_vaddr & PVO_WIRED) == 0) 1066 pm->pm_stats.wired_count++; 1067 pvo->pvo_vaddr |= PVO_WIRED; 1068 } else { 1069 if ((pvo->pvo_vaddr & PVO_WIRED) != 0) 1070 pm->pm_stats.wired_count--; 1071 pvo->pvo_vaddr &= ~PVO_WIRED; 1072 } 1073 } 1074 PMAP_UNLOCK(pm); 1075} 1076 1077/* 1078 * This goes through and sets the physical address of our 1079 * special scratch PTE to the PA we want to zero or copy. Because 1080 * of locking issues (this can get called in pvo_enter() by 1081 * the UMA allocator), we can't use most other utility functions here 1082 */ 1083 1084static __inline 1085void moea64_set_scratchpage_pa(int which, vm_offset_t pa) { 1086 mtx_assert(&moea64_scratchpage_mtx, MA_OWNED); 1087 1088 moea64_scratchpage_pvo[which]->pvo_pte.lpte.pte_lo &= 1089 ~(LPTE_WIMG | LPTE_RPGN); 1090 moea64_scratchpage_pvo[which]->pvo_pte.lpte.pte_lo |= 1091 moea64_calc_wimg(pa) | (uint64_t)pa; 1092 1093 moea64_scratchpage_pte[which]->pte_hi &= ~LPTE_VALID; 1094 TLBIE(kernel_pmap, moea64_scratchpage_va[which]); 1095 1096 moea64_scratchpage_pte[which]->pte_lo = 1097 moea64_scratchpage_pvo[which]->pvo_pte.lpte.pte_lo; 1098 EIEIO(); 1099 1100 moea64_scratchpage_pte[which]->pte_hi |= LPTE_VALID; 1101 PTESYNC(); isync(); 1102} 1103 1104void 1105moea64_copy_page(mmu_t mmu, vm_page_t msrc, vm_page_t mdst) 1106{ 1107 vm_offset_t dst; 1108 vm_offset_t src; 1109 1110 dst = VM_PAGE_TO_PHYS(mdst); 1111 src = VM_PAGE_TO_PHYS(msrc); 1112 1113 mtx_lock(&moea64_scratchpage_mtx); 1114 1115 moea64_set_scratchpage_pa(0,src); 1116 moea64_set_scratchpage_pa(1,dst); 1117 1118 kcopy((void *)moea64_scratchpage_va[0], 1119 (void *)moea64_scratchpage_va[1], PAGE_SIZE); 1120 1121 mtx_unlock(&moea64_scratchpage_mtx); 1122} 1123 1124void 1125moea64_zero_page_area(mmu_t mmu, vm_page_t m, int off, int size) 1126{ 1127 vm_offset_t pa = VM_PAGE_TO_PHYS(m); 1128 1129 if (!moea64_initialized) 1130 panic("moea64_zero_page: can't zero pa %#x", pa); 1131 if (size + off > PAGE_SIZE) 1132 panic("moea64_zero_page: size + off > PAGE_SIZE"); 1133 1134 mtx_lock(&moea64_scratchpage_mtx); 1135 1136 moea64_set_scratchpage_pa(0,pa); 1137 bzero((caddr_t)moea64_scratchpage_va[0] + off, size); 1138 mtx_unlock(&moea64_scratchpage_mtx); 1139} 1140 1141/* 1142 * Zero a page of physical memory by temporarily mapping it 1143 */ 1144void 1145moea64_zero_page(mmu_t mmu, vm_page_t m) 1146{ 1147 vm_offset_t pa = VM_PAGE_TO_PHYS(m); 1148 vm_offset_t off; 1149 1150 if (!moea64_initialized) 1151 panic("moea64_zero_page: can't zero pa %#x", pa); 1152 1153 mtx_lock(&moea64_scratchpage_mtx); 1154 1155 moea64_set_scratchpage_pa(0,pa); 1156 for (off = 0; off < PAGE_SIZE; off += cacheline_size) 1157 __asm __volatile("dcbz 0,%0" :: 1158 "r"(moea64_scratchpage_va[0] + off)); 1159 mtx_unlock(&moea64_scratchpage_mtx); 1160} 1161 1162void 1163moea64_zero_page_idle(mmu_t mmu, vm_page_t m) 1164{ 1165 1166 moea64_zero_page(mmu, m); 1167} 1168 1169/* 1170 * Map the given physical page at the specified virtual address in the 1171 * target pmap with the protection requested. If specified the page 1172 * will be wired down. 1173 */ 1174void 1175moea64_enter(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, 1176 vm_prot_t prot, boolean_t wired) 1177{ 1178 1179 vm_page_lock_queues(); 1180 PMAP_LOCK(pmap); 1181 moea64_enter_locked(pmap, va, m, prot, wired); 1182 vm_page_unlock_queues(); 1183 PMAP_UNLOCK(pmap); 1184} 1185 1186/* 1187 * Map the given physical page at the specified virtual address in the 1188 * target pmap with the protection requested. If specified the page 1189 * will be wired down. 1190 * 1191 * The page queues and pmap must be locked. 1192 */ 1193 1194static void 1195moea64_enter_locked(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot, 1196 boolean_t wired) 1197{ 1198 struct pvo_head *pvo_head; 1199 uma_zone_t zone; 1200 vm_page_t pg; 1201 uint64_t pte_lo; 1202 u_int pvo_flags; 1203 int error; 1204 1205 if (!moea64_initialized) { 1206 pvo_head = &moea64_pvo_kunmanaged; 1207 pg = NULL; 1208 zone = moea64_upvo_zone; 1209 pvo_flags = 0; 1210 } else { 1211 pvo_head = vm_page_to_pvoh(m); 1212 pg = m; 1213 zone = moea64_mpvo_zone; 1214 pvo_flags = PVO_MANAGED; 1215 } 1216 1217 if (pmap_bootstrapped) 1218 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1219 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1220 1221 /* XXX change the pvo head for fake pages */ 1222 if ((m->flags & PG_FICTITIOUS) == PG_FICTITIOUS) { 1223 pvo_flags &= ~PVO_MANAGED; 1224 pvo_head = &moea64_pvo_kunmanaged; 1225 zone = moea64_upvo_zone; 1226 } 1227 1228 pte_lo = moea64_calc_wimg(VM_PAGE_TO_PHYS(m)); 1229 1230 if (prot & VM_PROT_WRITE) { 1231 pte_lo |= LPTE_BW; 1232 if (pmap_bootstrapped) 1233 vm_page_flag_set(m, PG_WRITEABLE); 1234 } else 1235 pte_lo |= LPTE_BR; 1236 1237 if (prot & VM_PROT_EXECUTE) 1238 pvo_flags |= VM_PROT_EXECUTE; 1239 1240 if (wired) 1241 pvo_flags |= PVO_WIRED; 1242 1243 if ((m->flags & PG_FICTITIOUS) != 0) 1244 pvo_flags |= PVO_FAKE; 1245 1246 error = moea64_pvo_enter(pmap, zone, pvo_head, va, VM_PAGE_TO_PHYS(m), 1247 pte_lo, pvo_flags); 1248 1249 /* 1250 * Flush the page from the instruction cache if this page is 1251 * mapped executable and cacheable. 1252 */ 1253 if ((pte_lo & (LPTE_I | LPTE_G | LPTE_NOEXEC)) == 0) { 1254 moea64_syncicache(pmap, va, VM_PAGE_TO_PHYS(m), PAGE_SIZE); 1255 } 1256} 1257 1258static void 1259moea64_syncicache(pmap_t pmap, vm_offset_t va, vm_offset_t pa, vm_size_t sz) 1260{ 1261 1262 /* 1263 * This is much trickier than on older systems because 1264 * we can't sync the icache on physical addresses directly 1265 * without a direct map. Instead we check a couple of cases 1266 * where the memory is already mapped in and, failing that, 1267 * use the same trick we use for page zeroing to create 1268 * a temporary mapping for this physical address. 1269 */ 1270 1271 if (!pmap_bootstrapped) { 1272 /* 1273 * If PMAP is not bootstrapped, we are likely to be 1274 * in real mode. 1275 */ 1276 __syncicache((void *)pa, sz); 1277 } else if (pmap == kernel_pmap) { 1278 __syncicache((void *)va, sz); 1279 } else { 1280 /* Use the scratch page to set up a temp mapping */ 1281 1282 mtx_lock(&moea64_scratchpage_mtx); 1283 1284 moea64_set_scratchpage_pa(1,pa & ~ADDR_POFF); 1285 __syncicache((void *)(moea64_scratchpage_va[1] + 1286 (va & ADDR_POFF)), sz); 1287 1288 mtx_unlock(&moea64_scratchpage_mtx); 1289 } 1290} 1291 1292/* 1293 * Maps a sequence of resident pages belonging to the same object. 1294 * The sequence begins with the given page m_start. This page is 1295 * mapped at the given virtual address start. Each subsequent page is 1296 * mapped at a virtual address that is offset from start by the same 1297 * amount as the page is offset from m_start within the object. The 1298 * last page in the sequence is the page with the largest offset from 1299 * m_start that can be mapped at a virtual address less than the given 1300 * virtual address end. Not every virtual page between start and end 1301 * is mapped; only those for which a resident page exists with the 1302 * corresponding offset from m_start are mapped. 1303 */ 1304void 1305moea64_enter_object(mmu_t mmu, pmap_t pm, vm_offset_t start, vm_offset_t end, 1306 vm_page_t m_start, vm_prot_t prot) 1307{ 1308 vm_page_t m; 1309 vm_pindex_t diff, psize; 1310 1311 psize = atop(end - start); 1312 m = m_start; 1313 PMAP_LOCK(pm); 1314 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 1315 moea64_enter_locked(pm, start + ptoa(diff), m, prot & 1316 (VM_PROT_READ | VM_PROT_EXECUTE), FALSE); 1317 m = TAILQ_NEXT(m, listq); 1318 } 1319 PMAP_UNLOCK(pm); 1320} 1321 1322void 1323moea64_enter_quick(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_page_t m, 1324 vm_prot_t prot) 1325{ 1326 PMAP_LOCK(pm); 1327 moea64_enter_locked(pm, va, m, prot & (VM_PROT_READ | VM_PROT_EXECUTE), 1328 FALSE); 1329 PMAP_UNLOCK(pm); 1330 1331} 1332 1333vm_paddr_t 1334moea64_extract(mmu_t mmu, pmap_t pm, vm_offset_t va) 1335{ 1336 struct pvo_entry *pvo; 1337 vm_paddr_t pa; 1338 1339 PMAP_LOCK(pm); 1340 pvo = moea64_pvo_find_va(pm, va & ~ADDR_POFF, NULL); 1341 if (pvo == NULL) 1342 pa = 0; 1343 else 1344 pa = (pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN) | (va & ADDR_POFF); 1345 PMAP_UNLOCK(pm); 1346 return (pa); 1347} 1348 1349/* 1350 * Atomically extract and hold the physical page with the given 1351 * pmap and virtual address pair if that mapping permits the given 1352 * protection. 1353 */ 1354vm_page_t 1355moea64_extract_and_hold(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_prot_t prot) 1356{ 1357 struct pvo_entry *pvo; 1358 vm_page_t m; 1359 1360 m = NULL; 1361 vm_page_lock_queues(); 1362 PMAP_LOCK(pmap); 1363 pvo = moea64_pvo_find_va(pmap, va & ~ADDR_POFF, NULL); 1364 if (pvo != NULL && (pvo->pvo_pte.lpte.pte_hi & LPTE_VALID) && 1365 ((pvo->pvo_pte.lpte.pte_lo & LPTE_PP) == LPTE_RW || 1366 (prot & VM_PROT_WRITE) == 0)) { 1367 m = PHYS_TO_VM_PAGE(pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN); 1368 vm_page_hold(m); 1369 } 1370 vm_page_unlock_queues(); 1371 PMAP_UNLOCK(pmap); 1372 return (m); 1373} 1374 1375static void * 1376moea64_uma_page_alloc(uma_zone_t zone, int bytes, u_int8_t *flags, int wait) 1377{ 1378 /* 1379 * This entire routine is a horrible hack to avoid bothering kmem 1380 * for new KVA addresses. Because this can get called from inside 1381 * kmem allocation routines, calling kmem for a new address here 1382 * can lead to multiply locking non-recursive mutexes. 1383 */ 1384 static vm_pindex_t color; 1385 vm_offset_t va; 1386 1387 vm_page_t m; 1388 int pflags, needed_lock; 1389 1390 *flags = UMA_SLAB_PRIV; 1391 needed_lock = !PMAP_LOCKED(kernel_pmap); 1392 1393 if (needed_lock) 1394 PMAP_LOCK(kernel_pmap); 1395 1396 if ((wait & (M_NOWAIT|M_USE_RESERVE)) == M_NOWAIT) 1397 pflags = VM_ALLOC_INTERRUPT | VM_ALLOC_WIRED; 1398 else 1399 pflags = VM_ALLOC_SYSTEM | VM_ALLOC_WIRED; 1400 if (wait & M_ZERO) 1401 pflags |= VM_ALLOC_ZERO; 1402 1403 for (;;) { 1404 m = vm_page_alloc(NULL, color++, pflags | VM_ALLOC_NOOBJ); 1405 if (m == NULL) { 1406 if (wait & M_NOWAIT) 1407 return (NULL); 1408 VM_WAIT; 1409 } else 1410 break; 1411 } 1412 1413 va = VM_PAGE_TO_PHYS(m); 1414 1415 moea64_pvo_enter(kernel_pmap, moea64_upvo_zone, 1416 &moea64_pvo_kunmanaged, va, VM_PAGE_TO_PHYS(m), LPTE_M, 1417 PVO_WIRED | PVO_BOOTSTRAP); 1418 1419 if (needed_lock) 1420 PMAP_UNLOCK(kernel_pmap); 1421 1422 if ((wait & M_ZERO) && (m->flags & PG_ZERO) == 0) 1423 bzero((void *)va, PAGE_SIZE); 1424 1425 return (void *)va; 1426} 1427 1428void 1429moea64_init(mmu_t mmu) 1430{ 1431 1432 CTR0(KTR_PMAP, "moea64_init"); 1433 1434 moea64_upvo_zone = uma_zcreate("UPVO entry", sizeof (struct pvo_entry), 1435 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, 1436 UMA_ZONE_VM | UMA_ZONE_NOFREE); 1437 moea64_mpvo_zone = uma_zcreate("MPVO entry", sizeof(struct pvo_entry), 1438 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, 1439 UMA_ZONE_VM | UMA_ZONE_NOFREE); 1440 1441 if (!hw_direct_map) { 1442 uma_zone_set_allocf(moea64_upvo_zone,moea64_uma_page_alloc); 1443 uma_zone_set_allocf(moea64_mpvo_zone,moea64_uma_page_alloc); 1444 } 1445 1446 moea64_initialized = TRUE; 1447} 1448 1449boolean_t 1450moea64_is_modified(mmu_t mmu, vm_page_t m) 1451{ 1452 1453 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0) 1454 return (FALSE); 1455 1456 return (moea64_query_bit(m, LPTE_CHG)); 1457} 1458 1459void 1460moea64_clear_reference(mmu_t mmu, vm_page_t m) 1461{ 1462 1463 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0) 1464 return; 1465 moea64_clear_bit(m, LPTE_REF, NULL); 1466} 1467 1468void 1469moea64_clear_modify(mmu_t mmu, vm_page_t m) 1470{ 1471 1472 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0) 1473 return; 1474 moea64_clear_bit(m, LPTE_CHG, NULL); 1475} 1476 1477/* 1478 * Clear the write and modified bits in each of the given page's mappings. 1479 */ 1480void 1481moea64_remove_write(mmu_t mmu, vm_page_t m) 1482{ 1483 struct pvo_entry *pvo; 1484 struct lpte *pt; 1485 pmap_t pmap; 1486 uint64_t lo; 1487 1488 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1489 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0 || 1490 (m->flags & PG_WRITEABLE) == 0) 1491 return; 1492 lo = moea64_attr_fetch(m); 1493 SYNC(); 1494 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1495 pmap = pvo->pvo_pmap; 1496 PMAP_LOCK(pmap); 1497 if ((pvo->pvo_pte.lpte.pte_lo & LPTE_PP) != LPTE_BR) { 1498 LOCK_TABLE(); 1499 pt = moea64_pvo_to_pte(pvo, -1); 1500 pvo->pvo_pte.lpte.pte_lo &= ~LPTE_PP; 1501 pvo->pvo_pte.lpte.pte_lo |= LPTE_BR; 1502 if (pt != NULL) { 1503 moea64_pte_synch(pt, &pvo->pvo_pte.lpte); 1504 lo |= pvo->pvo_pte.lpte.pte_lo; 1505 pvo->pvo_pte.lpte.pte_lo &= ~LPTE_CHG; 1506 moea64_pte_change(pt, &pvo->pvo_pte.lpte, 1507 pvo->pvo_pmap, PVO_VADDR(pvo)); 1508 } 1509 UNLOCK_TABLE(); 1510 } 1511 PMAP_UNLOCK(pmap); 1512 } 1513 if ((lo & LPTE_CHG) != 0) { 1514 moea64_attr_clear(m, LPTE_CHG); 1515 vm_page_dirty(m); 1516 } 1517 vm_page_flag_clear(m, PG_WRITEABLE); 1518} 1519 1520/* 1521 * moea64_ts_referenced: 1522 * 1523 * Return a count of reference bits for a page, clearing those bits. 1524 * It is not necessary for every reference bit to be cleared, but it 1525 * is necessary that 0 only be returned when there are truly no 1526 * reference bits set. 1527 * 1528 * XXX: The exact number of bits to check and clear is a matter that 1529 * should be tested and standardized at some point in the future for 1530 * optimal aging of shared pages. 1531 */ 1532boolean_t 1533moea64_ts_referenced(mmu_t mmu, vm_page_t m) 1534{ 1535 int count; 1536 1537 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0) 1538 return (0); 1539 1540 count = moea64_clear_bit(m, LPTE_REF, NULL); 1541 1542 return (count); 1543} 1544 1545/* 1546 * Map a wired page into kernel virtual address space. 1547 */ 1548void 1549moea64_kenter(mmu_t mmu, vm_offset_t va, vm_offset_t pa) 1550{ 1551 uint64_t pte_lo; 1552 int error; 1553 1554#if 0 1555 if (!pmap_bootstrapped) { 1556 if (va >= VM_MIN_KERNEL_ADDRESS && va < virtual_end) 1557 panic("Trying to enter an address in KVA -- %#x!\n",pa); 1558 } 1559#endif 1560 1561 pte_lo = moea64_calc_wimg(pa); 1562 1563 PMAP_LOCK(kernel_pmap); 1564 error = moea64_pvo_enter(kernel_pmap, moea64_upvo_zone, 1565 &moea64_pvo_kunmanaged, va, pa, pte_lo, 1566 PVO_WIRED | VM_PROT_EXECUTE); 1567 1568 if (error != 0 && error != ENOENT) 1569 panic("moea64_kenter: failed to enter va %#x pa %#x: %d", va, 1570 pa, error); 1571 1572 /* 1573 * Flush the memory from the instruction cache. 1574 */ 1575 if ((pte_lo & (LPTE_I | LPTE_G)) == 0) { 1576 __syncicache((void *)va, PAGE_SIZE); 1577 } 1578 PMAP_UNLOCK(kernel_pmap); 1579} 1580 1581/* 1582 * Extract the physical page address associated with the given kernel virtual 1583 * address. 1584 */ 1585vm_offset_t 1586moea64_kextract(mmu_t mmu, vm_offset_t va) 1587{ 1588 struct pvo_entry *pvo; 1589 vm_paddr_t pa; 1590 1591 PMAP_LOCK(kernel_pmap); 1592 pvo = moea64_pvo_find_va(kernel_pmap, va & ~ADDR_POFF, NULL); 1593 KASSERT(pvo != NULL, ("moea64_kextract: no addr found")); 1594 pa = (pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN) | (va & ADDR_POFF); 1595 PMAP_UNLOCK(kernel_pmap); 1596 return (pa); 1597} 1598 1599/* 1600 * Remove a wired page from kernel virtual address space. 1601 */ 1602void 1603moea64_kremove(mmu_t mmu, vm_offset_t va) 1604{ 1605 moea64_remove(mmu, kernel_pmap, va, va + PAGE_SIZE); 1606} 1607 1608/* 1609 * Map a range of physical addresses into kernel virtual address space. 1610 * 1611 * The value passed in *virt is a suggested virtual address for the mapping. 1612 * Architectures which can support a direct-mapped physical to virtual region 1613 * can return the appropriate address within that region, leaving '*virt' 1614 * unchanged. We cannot and therefore do not; *virt is updated with the 1615 * first usable address after the mapped region. 1616 */ 1617vm_offset_t 1618moea64_map(mmu_t mmu, vm_offset_t *virt, vm_offset_t pa_start, 1619 vm_offset_t pa_end, int prot) 1620{ 1621 vm_offset_t sva, va; 1622 1623 sva = *virt; 1624 va = sva; 1625 for (; pa_start < pa_end; pa_start += PAGE_SIZE, va += PAGE_SIZE) 1626 moea64_kenter(mmu, va, pa_start); 1627 *virt = va; 1628 1629 return (sva); 1630} 1631 1632/* 1633 * Returns true if the pmap's pv is one of the first 1634 * 16 pvs linked to from this page. This count may 1635 * be changed upwards or downwards in the future; it 1636 * is only necessary that true be returned for a small 1637 * subset of pmaps for proper page aging. 1638 */ 1639boolean_t 1640moea64_page_exists_quick(mmu_t mmu, pmap_t pmap, vm_page_t m) 1641{ 1642 int loops; 1643 struct pvo_entry *pvo; 1644 1645 if (!moea64_initialized || (m->flags & PG_FICTITIOUS)) 1646 return FALSE; 1647 1648 loops = 0; 1649 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1650 if (pvo->pvo_pmap == pmap) 1651 return (TRUE); 1652 if (++loops >= 16) 1653 break; 1654 } 1655 1656 return (FALSE); 1657} 1658 1659/* 1660 * Return the number of managed mappings to the given physical page 1661 * that are wired. 1662 */ 1663int 1664moea64_page_wired_mappings(mmu_t mmu, vm_page_t m) 1665{ 1666 struct pvo_entry *pvo; 1667 int count; 1668 1669 count = 0; 1670 if (!moea64_initialized || (m->flags & PG_FICTITIOUS) != 0) 1671 return (count); 1672 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1673 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) 1674 if ((pvo->pvo_vaddr & PVO_WIRED) != 0) 1675 count++; 1676 return (count); 1677} 1678 1679static u_int moea64_vsidcontext; 1680 1681void 1682moea64_pinit(mmu_t mmu, pmap_t pmap) 1683{ 1684 int i, mask; 1685 u_int entropy; 1686 1687 PMAP_LOCK_INIT(pmap); 1688 1689 entropy = 0; 1690 __asm __volatile("mftb %0" : "=r"(entropy)); 1691 1692 if (pmap_bootstrapped) 1693 pmap->pmap_phys = (pmap_t)moea64_kextract(mmu, (vm_offset_t)pmap); 1694 else 1695 pmap->pmap_phys = pmap; 1696 1697 /* 1698 * Allocate some segment registers for this pmap. 1699 */ 1700 for (i = 0; i < NPMAPS; i += VSID_NBPW) { 1701 u_int hash, n; 1702 1703 /* 1704 * Create a new value by mutiplying by a prime and adding in 1705 * entropy from the timebase register. This is to make the 1706 * VSID more random so that the PT hash function collides 1707 * less often. (Note that the prime casues gcc to do shifts 1708 * instead of a multiply.) 1709 */ 1710 moea64_vsidcontext = (moea64_vsidcontext * 0x1105) + entropy; 1711 hash = moea64_vsidcontext & (NPMAPS - 1); 1712 if (hash == 0) /* 0 is special, avoid it */ 1713 continue; 1714 n = hash >> 5; 1715 mask = 1 << (hash & (VSID_NBPW - 1)); 1716 hash = (moea64_vsidcontext & 0xfffff); 1717 if (moea64_vsid_bitmap[n] & mask) { /* collision? */ 1718 /* anything free in this bucket? */ 1719 if (moea64_vsid_bitmap[n] == 0xffffffff) { 1720 entropy = (moea64_vsidcontext >> 20); 1721 continue; 1722 } 1723 i = ffs(~moea64_vsid_bitmap[i]) - 1; 1724 mask = 1 << i; 1725 hash &= 0xfffff & ~(VSID_NBPW - 1); 1726 hash |= i; 1727 } 1728 moea64_vsid_bitmap[n] |= mask; 1729 for (i = 0; i < 16; i++) { 1730 pmap->pm_sr[i] = VSID_MAKE(i, hash); 1731 } 1732 return; 1733 } 1734 1735 panic("moea64_pinit: out of segments"); 1736} 1737 1738/* 1739 * Initialize the pmap associated with process 0. 1740 */ 1741void 1742moea64_pinit0(mmu_t mmu, pmap_t pm) 1743{ 1744 moea64_pinit(mmu, pm); 1745 bzero(&pm->pm_stats, sizeof(pm->pm_stats)); 1746} 1747 1748/* 1749 * Set the physical protection on the specified range of this map as requested. 1750 */ 1751void 1752moea64_protect(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva, 1753 vm_prot_t prot) 1754{ 1755 struct pvo_entry *pvo; 1756 struct lpte *pt; 1757 int pteidx; 1758 1759 CTR4(KTR_PMAP, "moea64_protect: pm=%p sva=%#x eva=%#x prot=%#x", pm, sva, 1760 eva, prot); 1761 1762 1763 KASSERT(pm == &curproc->p_vmspace->vm_pmap || pm == kernel_pmap, 1764 ("moea64_protect: non current pmap")); 1765 1766 if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 1767 moea64_remove(mmu, pm, sva, eva); 1768 return; 1769 } 1770 1771 vm_page_lock_queues(); 1772 PMAP_LOCK(pm); 1773 for (; sva < eva; sva += PAGE_SIZE) { 1774 pvo = moea64_pvo_find_va(pm, sva, &pteidx); 1775 if (pvo == NULL) 1776 continue; 1777 1778 /* 1779 * Grab the PTE pointer before we diddle with the cached PTE 1780 * copy. 1781 */ 1782 LOCK_TABLE(); 1783 pt = moea64_pvo_to_pte(pvo, pteidx); 1784 1785 /* 1786 * Change the protection of the page. 1787 */ 1788 pvo->pvo_pte.lpte.pte_lo &= ~LPTE_PP; 1789 pvo->pvo_pte.lpte.pte_lo |= LPTE_BR; 1790 pvo->pvo_pte.lpte.pte_lo &= ~LPTE_NOEXEC; 1791 if ((prot & VM_PROT_EXECUTE) == 0) 1792 pvo->pvo_pte.lpte.pte_lo |= LPTE_NOEXEC; 1793 1794 /* 1795 * If the PVO is in the page table, update that pte as well. 1796 */ 1797 if (pt != NULL) { 1798 moea64_pte_change(pt, &pvo->pvo_pte.lpte, 1799 pvo->pvo_pmap, PVO_VADDR(pvo)); 1800 if ((pvo->pvo_pte.lpte.pte_lo & 1801 (LPTE_I | LPTE_G | LPTE_NOEXEC)) == 0) { 1802 moea64_syncicache(pm, sva, 1803 pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN, 1804 PAGE_SIZE); 1805 } 1806 } 1807 UNLOCK_TABLE(); 1808 } 1809 vm_page_unlock_queues(); 1810 PMAP_UNLOCK(pm); 1811} 1812 1813/* 1814 * Map a list of wired pages into kernel virtual address space. This is 1815 * intended for temporary mappings which do not need page modification or 1816 * references recorded. Existing mappings in the region are overwritten. 1817 */ 1818void 1819moea64_qenter(mmu_t mmu, vm_offset_t va, vm_page_t *m, int count) 1820{ 1821 while (count-- > 0) { 1822 moea64_kenter(mmu, va, VM_PAGE_TO_PHYS(*m)); 1823 va += PAGE_SIZE; 1824 m++; 1825 } 1826} 1827 1828/* 1829 * Remove page mappings from kernel virtual address space. Intended for 1830 * temporary mappings entered by moea64_qenter. 1831 */ 1832void 1833moea64_qremove(mmu_t mmu, vm_offset_t va, int count) 1834{ 1835 while (count-- > 0) { 1836 moea64_kremove(mmu, va); 1837 va += PAGE_SIZE; 1838 } 1839} 1840 1841void 1842moea64_release(mmu_t mmu, pmap_t pmap) 1843{ 1844 int idx, mask; 1845 1846 /* 1847 * Free segment register's VSID 1848 */ 1849 if (pmap->pm_sr[0] == 0) 1850 panic("moea64_release"); 1851 1852 idx = VSID_TO_HASH(pmap->pm_sr[0]) & (NPMAPS-1); 1853 mask = 1 << (idx % VSID_NBPW); 1854 idx /= VSID_NBPW; 1855 moea64_vsid_bitmap[idx] &= ~mask; 1856 PMAP_LOCK_DESTROY(pmap); 1857} 1858 1859/* 1860 * Remove the given range of addresses from the specified map. 1861 */ 1862void 1863moea64_remove(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva) 1864{ 1865 struct pvo_entry *pvo; 1866 int pteidx; 1867 1868 vm_page_lock_queues(); 1869 PMAP_LOCK(pm); 1870 for (; sva < eva; sva += PAGE_SIZE) { 1871 pvo = moea64_pvo_find_va(pm, sva, &pteidx); 1872 if (pvo != NULL) { 1873 moea64_pvo_remove(pvo, pteidx); 1874 } 1875 } 1876 vm_page_unlock_queues(); 1877 PMAP_UNLOCK(pm); 1878} 1879 1880/* 1881 * Remove physical page from all pmaps in which it resides. moea64_pvo_remove() 1882 * will reflect changes in pte's back to the vm_page. 1883 */ 1884void 1885moea64_remove_all(mmu_t mmu, vm_page_t m) 1886{ 1887 struct pvo_head *pvo_head; 1888 struct pvo_entry *pvo, *next_pvo; 1889 pmap_t pmap; 1890 1891 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1892 1893 pvo_head = vm_page_to_pvoh(m); 1894 for (pvo = LIST_FIRST(pvo_head); pvo != NULL; pvo = next_pvo) { 1895 next_pvo = LIST_NEXT(pvo, pvo_vlink); 1896 1897 MOEA_PVO_CHECK(pvo); /* sanity check */ 1898 pmap = pvo->pvo_pmap; 1899 PMAP_LOCK(pmap); 1900 moea64_pvo_remove(pvo, -1); 1901 PMAP_UNLOCK(pmap); 1902 } 1903 if ((m->flags & PG_WRITEABLE) && moea64_is_modified(mmu, m)) { 1904 moea64_attr_clear(m, LPTE_CHG); 1905 vm_page_dirty(m); 1906 } 1907 vm_page_flag_clear(m, PG_WRITEABLE); 1908} 1909 1910/* 1911 * Allocate a physical page of memory directly from the phys_avail map. 1912 * Can only be called from moea64_bootstrap before avail start and end are 1913 * calculated. 1914 */ 1915static vm_offset_t 1916moea64_bootstrap_alloc(vm_size_t size, u_int align) 1917{ 1918 vm_offset_t s, e; 1919 int i, j; 1920 1921 size = round_page(size); 1922 for (i = 0; phys_avail[i + 1] != 0; i += 2) { 1923 if (align != 0) 1924 s = (phys_avail[i] + align - 1) & ~(align - 1); 1925 else 1926 s = phys_avail[i]; 1927 e = s + size; 1928 1929 if (s < phys_avail[i] || e > phys_avail[i + 1]) 1930 continue; 1931 1932 if (s == phys_avail[i]) { 1933 phys_avail[i] += size; 1934 } else if (e == phys_avail[i + 1]) { 1935 phys_avail[i + 1] -= size; 1936 } else { 1937 for (j = phys_avail_count * 2; j > i; j -= 2) { 1938 phys_avail[j] = phys_avail[j - 2]; 1939 phys_avail[j + 1] = phys_avail[j - 1]; 1940 } 1941 1942 phys_avail[i + 3] = phys_avail[i + 1]; 1943 phys_avail[i + 1] = s; 1944 phys_avail[i + 2] = e; 1945 phys_avail_count++; 1946 } 1947 1948 return (s); 1949 } 1950 panic("moea64_bootstrap_alloc: could not allocate memory"); 1951} 1952 1953static void 1954tlbia(void) 1955{ 1956 vm_offset_t i; 1957 register_t msr, scratch; 1958 1959 for (i = 0; i < 0xFF000; i += 0x00001000) { 1960 __asm __volatile("\ 1961 mfmsr %0; \ 1962 mr %1, %0; \ 1963 insrdi %1,%3,1,0; \ 1964 mtmsrd %1; \ 1965 ptesync; \ 1966 \ 1967 tlbiel %2; \ 1968 \ 1969 mtmsrd %0; \ 1970 eieio; \ 1971 tlbsync; \ 1972 ptesync;" 1973 : "=r"(msr), "=r"(scratch) : "r"(i), "r"(1)); 1974 } 1975} 1976 1977static int 1978moea64_pvo_enter(pmap_t pm, uma_zone_t zone, struct pvo_head *pvo_head, 1979 vm_offset_t va, vm_offset_t pa, uint64_t pte_lo, int flags) 1980{ 1981 struct pvo_entry *pvo; 1982 uint64_t vsid; 1983 int first; 1984 u_int ptegidx; 1985 int i; 1986 int bootstrap; 1987 1988 /* 1989 * One nasty thing that can happen here is that the UMA calls to 1990 * allocate new PVOs need to map more memory, which calls pvo_enter(), 1991 * which calls UMA... 1992 * 1993 * We break the loop by detecting recursion and allocating out of 1994 * the bootstrap pool. 1995 */ 1996 1997 moea64_pvo_enter_calls++; 1998 first = 0; 1999 bootstrap = (flags & PVO_BOOTSTRAP); 2000 2001 if (!moea64_initialized) 2002 bootstrap = 1; 2003 2004 /* 2005 * Compute the PTE Group index. 2006 */ 2007 va &= ~ADDR_POFF; 2008 vsid = va_to_vsid(pm, va); 2009 ptegidx = va_to_pteg(vsid, va); 2010 2011 /* 2012 * Remove any existing mapping for this page. Reuse the pvo entry if 2013 * there is a mapping. 2014 */ 2015 LOCK_TABLE(); 2016 2017 LIST_FOREACH(pvo, &moea64_pvo_table[ptegidx], pvo_olink) { 2018 if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) { 2019 if ((pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN) == pa && 2020 (pvo->pvo_pte.lpte.pte_lo & LPTE_PP) == 2021 (pte_lo & LPTE_PP)) { 2022 UNLOCK_TABLE(); 2023 return (0); 2024 } 2025 moea64_pvo_remove(pvo, -1); 2026 break; 2027 } 2028 } 2029 2030 /* 2031 * If we aren't overwriting a mapping, try to allocate. 2032 */ 2033 if (bootstrap) { 2034 if (moea64_bpvo_pool_index >= BPVO_POOL_SIZE) { 2035 panic("moea64_enter: bpvo pool exhausted, %d, %d, %d", 2036 moea64_bpvo_pool_index, BPVO_POOL_SIZE, 2037 BPVO_POOL_SIZE * sizeof(struct pvo_entry)); 2038 } 2039 pvo = &moea64_bpvo_pool[moea64_bpvo_pool_index]; 2040 moea64_bpvo_pool_index++; 2041 bootstrap = 1; 2042 } else { 2043 /* 2044 * Note: drop the table around the UMA allocation in 2045 * case the UMA allocator needs to manipulate the page 2046 * table. The mapping we are working with is already 2047 * protected by the PMAP lock. 2048 */ 2049 UNLOCK_TABLE(); 2050 pvo = uma_zalloc(zone, M_NOWAIT); 2051 LOCK_TABLE(); 2052 } 2053 2054 if (pvo == NULL) { 2055 UNLOCK_TABLE(); 2056 return (ENOMEM); 2057 } 2058 2059 moea64_pvo_entries++; 2060 pvo->pvo_vaddr = va; 2061 pvo->pvo_pmap = pm; 2062 LIST_INSERT_HEAD(&moea64_pvo_table[ptegidx], pvo, pvo_olink); 2063 pvo->pvo_vaddr &= ~ADDR_POFF; 2064 2065 if (!(flags & VM_PROT_EXECUTE)) 2066 pte_lo |= LPTE_NOEXEC; 2067 if (flags & PVO_WIRED) 2068 pvo->pvo_vaddr |= PVO_WIRED; 2069 if (pvo_head != &moea64_pvo_kunmanaged) 2070 pvo->pvo_vaddr |= PVO_MANAGED; 2071 if (bootstrap) 2072 pvo->pvo_vaddr |= PVO_BOOTSTRAP; 2073 if (flags & PVO_FAKE) 2074 pvo->pvo_vaddr |= PVO_FAKE; 2075 2076 moea64_pte_create(&pvo->pvo_pte.lpte, vsid, va, 2077 (uint64_t)(pa) | pte_lo); 2078 2079 /* 2080 * Remember if the list was empty and therefore will be the first 2081 * item. 2082 */ 2083 if (LIST_FIRST(pvo_head) == NULL) 2084 first = 1; 2085 LIST_INSERT_HEAD(pvo_head, pvo, pvo_vlink); 2086 2087 if (pvo->pvo_vaddr & PVO_WIRED) 2088 pm->pm_stats.wired_count++; 2089 pm->pm_stats.resident_count++; 2090 2091 /* 2092 * We hope this succeeds but it isn't required. 2093 */ 2094 i = moea64_pte_insert(ptegidx, &pvo->pvo_pte.lpte); 2095 if (i >= 0) { 2096 PVO_PTEGIDX_SET(pvo, i); 2097 } else { 2098 panic("moea64_pvo_enter: overflow"); 2099 moea64_pte_overflow++; 2100 } 2101 2102 if (pm == kernel_pmap) 2103 isync(); 2104 2105 UNLOCK_TABLE(); 2106 2107 return (first ? ENOENT : 0); 2108} 2109 2110static void 2111moea64_pvo_remove(struct pvo_entry *pvo, int pteidx) 2112{ 2113 struct lpte *pt; 2114 2115 /* 2116 * If there is an active pte entry, we need to deactivate it (and 2117 * save the ref & cfg bits). 2118 */ 2119 LOCK_TABLE(); 2120 pt = moea64_pvo_to_pte(pvo, pteidx); 2121 if (pt != NULL) { 2122 moea64_pte_unset(pt, &pvo->pvo_pte.lpte, pvo->pvo_pmap, 2123 PVO_VADDR(pvo)); 2124 PVO_PTEGIDX_CLR(pvo); 2125 } else { 2126 moea64_pte_overflow--; 2127 } 2128 UNLOCK_TABLE(); 2129 2130 /* 2131 * Update our statistics. 2132 */ 2133 pvo->pvo_pmap->pm_stats.resident_count--; 2134 if (pvo->pvo_vaddr & PVO_WIRED) 2135 pvo->pvo_pmap->pm_stats.wired_count--; 2136 2137 /* 2138 * Save the REF/CHG bits into their cache if the page is managed. 2139 */ 2140 if ((pvo->pvo_vaddr & (PVO_MANAGED|PVO_FAKE)) == PVO_MANAGED) { 2141 struct vm_page *pg; 2142 2143 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN); 2144 if (pg != NULL) { 2145 moea64_attr_save(pg, pvo->pvo_pte.lpte.pte_lo & 2146 (LPTE_REF | LPTE_CHG)); 2147 } 2148 } 2149 2150 /* 2151 * Remove this PVO from the PV list. 2152 */ 2153 LIST_REMOVE(pvo, pvo_vlink); 2154 2155 /* 2156 * Remove this from the overflow list and return it to the pool 2157 * if we aren't going to reuse it. 2158 */ 2159 LIST_REMOVE(pvo, pvo_olink); 2160 if (!(pvo->pvo_vaddr & PVO_BOOTSTRAP)) 2161 uma_zfree((pvo->pvo_vaddr & PVO_MANAGED) ? moea64_mpvo_zone : 2162 moea64_upvo_zone, pvo); 2163 moea64_pvo_entries--; 2164 moea64_pvo_remove_calls++; 2165} 2166 2167static __inline int 2168moea64_pvo_pte_index(const struct pvo_entry *pvo, int ptegidx) 2169{ 2170 2171 /* 2172 * We can find the actual pte entry without searching by grabbing 2173 * the PTEG index from 3 unused bits in pvo_vaddr and by 2174 * noticing the HID bit. 2175 */ 2176 if (pvo->pvo_pte.lpte.pte_hi & LPTE_HID) 2177 ptegidx ^= moea64_pteg_mask; 2178 2179 return ((ptegidx << 3) | PVO_PTEGIDX_GET(pvo)); 2180} 2181 2182static struct pvo_entry * 2183moea64_pvo_find_va(pmap_t pm, vm_offset_t va, int *pteidx_p) 2184{ 2185 struct pvo_entry *pvo; 2186 int ptegidx; 2187 uint64_t vsid; 2188 2189 va &= ~ADDR_POFF; 2190 vsid = va_to_vsid(pm, va); 2191 ptegidx = va_to_pteg(vsid, va); 2192 2193 LOCK_TABLE(); 2194 LIST_FOREACH(pvo, &moea64_pvo_table[ptegidx], pvo_olink) { 2195 if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) { 2196 if (pteidx_p) 2197 *pteidx_p = moea64_pvo_pte_index(pvo, ptegidx); 2198 break; 2199 } 2200 } 2201 UNLOCK_TABLE(); 2202 2203 return (pvo); 2204} 2205 2206static struct lpte * 2207moea64_pvo_to_pte(const struct pvo_entry *pvo, int pteidx) 2208{ 2209 struct lpte *pt; 2210 2211 /* 2212 * If we haven't been supplied the ptegidx, calculate it. 2213 */ 2214 if (pteidx == -1) { 2215 int ptegidx; 2216 uint64_t vsid; 2217 2218 vsid = va_to_vsid(pvo->pvo_pmap, PVO_VADDR(pvo)); 2219 ptegidx = va_to_pteg(vsid, PVO_VADDR(pvo)); 2220 pteidx = moea64_pvo_pte_index(pvo, ptegidx); 2221 } 2222 2223 pt = &moea64_pteg_table[pteidx >> 3].pt[pteidx & 7]; 2224 2225 if ((pvo->pvo_pte.lpte.pte_hi & LPTE_VALID) && 2226 !PVO_PTEGIDX_ISSET(pvo)) { 2227 panic("moea64_pvo_to_pte: pvo %p has valid pte in pvo but no " 2228 "valid pte index", pvo); 2229 } 2230 2231 if ((pvo->pvo_pte.lpte.pte_hi & LPTE_VALID) == 0 && 2232 PVO_PTEGIDX_ISSET(pvo)) { 2233 panic("moea64_pvo_to_pte: pvo %p has valid pte index in pvo " 2234 "pvo but no valid pte", pvo); 2235 } 2236 2237 if ((pt->pte_hi ^ (pvo->pvo_pte.lpte.pte_hi & ~LPTE_VALID)) == 2238 LPTE_VALID) { 2239 if ((pvo->pvo_pte.lpte.pte_hi & LPTE_VALID) == 0) { 2240 panic("moea64_pvo_to_pte: pvo %p has valid pte in " 2241 "moea64_pteg_table %p but invalid in pvo", pvo, pt); 2242 } 2243 2244 if (((pt->pte_lo ^ pvo->pvo_pte.lpte.pte_lo) & 2245 ~(LPTE_CHG|LPTE_REF)) != 0) { 2246 panic("moea64_pvo_to_pte: pvo %p pte does not match " 2247 "pte %p in moea64_pteg_table difference is %#x", 2248 pvo, pt, 2249 (uint32_t)(pt->pte_lo ^ pvo->pvo_pte.lpte.pte_lo)); 2250 } 2251 2252 ASSERT_TABLE_LOCK(); 2253 return (pt); 2254 } 2255 2256 if (pvo->pvo_pte.lpte.pte_hi & LPTE_VALID) { 2257 panic("moea64_pvo_to_pte: pvo %p has invalid pte %p in " 2258 "moea64_pteg_table but valid in pvo", pvo, pt); 2259 } 2260 2261 return (NULL); 2262} 2263 2264static int 2265moea64_pte_insert(u_int ptegidx, struct lpte *pvo_pt) 2266{ 2267 struct lpte *pt; 2268 int i; 2269 2270 ASSERT_TABLE_LOCK(); 2271 2272 /* 2273 * First try primary hash. 2274 */ 2275 for (pt = moea64_pteg_table[ptegidx].pt, i = 0; i < 8; i++, pt++) { 2276 if ((pt->pte_hi & LPTE_VALID) == 0 && 2277 (pt->pte_hi & LPTE_LOCKED) == 0) { 2278 pvo_pt->pte_hi &= ~LPTE_HID; 2279 moea64_pte_set(pt, pvo_pt); 2280 return (i); 2281 } 2282 } 2283 2284 /* 2285 * Now try secondary hash. 2286 */ 2287 ptegidx ^= moea64_pteg_mask; 2288 2289 for (pt = moea64_pteg_table[ptegidx].pt, i = 0; i < 8; i++, pt++) { 2290 if ((pt->pte_hi & LPTE_VALID) == 0 && 2291 (pt->pte_hi & LPTE_LOCKED) == 0) { 2292 pvo_pt->pte_hi |= LPTE_HID; 2293 moea64_pte_set(pt, pvo_pt); 2294 return (i); 2295 } 2296 } 2297 2298 panic("moea64_pte_insert: overflow"); 2299 return (-1); 2300} 2301 2302static boolean_t 2303moea64_query_bit(vm_page_t m, u_int64_t ptebit) 2304{ 2305 struct pvo_entry *pvo; 2306 struct lpte *pt; 2307 2308 if (moea64_attr_fetch(m) & ptebit) 2309 return (TRUE); 2310 2311 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2312 MOEA_PVO_CHECK(pvo); /* sanity check */ 2313 2314 /* 2315 * See if we saved the bit off. If so, cache it and return 2316 * success. 2317 */ 2318 if (pvo->pvo_pte.lpte.pte_lo & ptebit) { 2319 moea64_attr_save(m, ptebit); 2320 MOEA_PVO_CHECK(pvo); /* sanity check */ 2321 return (TRUE); 2322 } 2323 } 2324 2325 /* 2326 * No luck, now go through the hard part of looking at the PTEs 2327 * themselves. Sync so that any pending REF/CHG bits are flushed to 2328 * the PTEs. 2329 */ 2330 SYNC(); 2331 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2332 MOEA_PVO_CHECK(pvo); /* sanity check */ 2333 2334 /* 2335 * See if this pvo has a valid PTE. if so, fetch the 2336 * REF/CHG bits from the valid PTE. If the appropriate 2337 * ptebit is set, cache it and return success. 2338 */ 2339 LOCK_TABLE(); 2340 pt = moea64_pvo_to_pte(pvo, -1); 2341 if (pt != NULL) { 2342 moea64_pte_synch(pt, &pvo->pvo_pte.lpte); 2343 if (pvo->pvo_pte.lpte.pte_lo & ptebit) { 2344 UNLOCK_TABLE(); 2345 2346 moea64_attr_save(m, ptebit); 2347 MOEA_PVO_CHECK(pvo); /* sanity check */ 2348 return (TRUE); 2349 } 2350 } 2351 UNLOCK_TABLE(); 2352 } 2353 2354 return (FALSE); 2355} 2356 2357static u_int 2358moea64_clear_bit(vm_page_t m, u_int64_t ptebit, u_int64_t *origbit) 2359{ 2360 u_int count; 2361 struct pvo_entry *pvo; 2362 struct lpte *pt; 2363 uint64_t rv; 2364 2365 /* 2366 * Clear the cached value. 2367 */ 2368 rv = moea64_attr_fetch(m); 2369 moea64_attr_clear(m, ptebit); 2370 2371 /* 2372 * Sync so that any pending REF/CHG bits are flushed to the PTEs (so 2373 * we can reset the right ones). note that since the pvo entries and 2374 * list heads are accessed via BAT0 and are never placed in the page 2375 * table, we don't have to worry about further accesses setting the 2376 * REF/CHG bits. 2377 */ 2378 SYNC(); 2379 2380 /* 2381 * For each pvo entry, clear the pvo's ptebit. If this pvo has a 2382 * valid pte clear the ptebit from the valid pte. 2383 */ 2384 count = 0; 2385 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2386 MOEA_PVO_CHECK(pvo); /* sanity check */ 2387 2388 LOCK_TABLE(); 2389 pt = moea64_pvo_to_pte(pvo, -1); 2390 if (pt != NULL) { 2391 moea64_pte_synch(pt, &pvo->pvo_pte.lpte); 2392 if (pvo->pvo_pte.lpte.pte_lo & ptebit) { 2393 count++; 2394 moea64_pte_clear(pt, pvo->pvo_pmap, PVO_VADDR(pvo), ptebit); 2395 } 2396 } 2397 UNLOCK_TABLE(); 2398 rv |= pvo->pvo_pte.lpte.pte_lo; 2399 pvo->pvo_pte.lpte.pte_lo &= ~ptebit; 2400 MOEA_PVO_CHECK(pvo); /* sanity check */ 2401 } 2402 2403 if (origbit != NULL) { 2404 *origbit = rv; 2405 } 2406 2407 return (count); 2408} 2409 2410boolean_t 2411moea64_dev_direct_mapped(mmu_t mmu, vm_offset_t pa, vm_size_t size) 2412{ 2413 struct pvo_entry *pvo; 2414 vm_offset_t ppa; 2415 int error = 0; 2416 2417 PMAP_LOCK(kernel_pmap); 2418 for (ppa = pa & ~ADDR_POFF; ppa < pa + size; ppa += PAGE_SIZE) { 2419 pvo = moea64_pvo_find_va(kernel_pmap, ppa, NULL); 2420 if (pvo == NULL || 2421 (pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN) != ppa) { 2422 error = EFAULT; 2423 break; 2424 } 2425 } 2426 PMAP_UNLOCK(kernel_pmap); 2427 2428 return (error); 2429} 2430 2431/* 2432 * Map a set of physical memory pages into the kernel virtual 2433 * address space. Return a pointer to where it is mapped. This 2434 * routine is intended to be used for mapping device memory, 2435 * NOT real memory. 2436 */ 2437void * 2438moea64_mapdev(mmu_t mmu, vm_offset_t pa, vm_size_t size) 2439{ 2440 vm_offset_t va, tmpva, ppa, offset; 2441 2442 ppa = trunc_page(pa); 2443 offset = pa & PAGE_MASK; 2444 size = roundup(offset + size, PAGE_SIZE); 2445 2446 va = kmem_alloc_nofault(kernel_map, size); 2447 2448 if (!va) 2449 panic("moea64_mapdev: Couldn't alloc kernel virtual memory"); 2450 2451 for (tmpva = va; size > 0;) { 2452 moea64_kenter(mmu, tmpva, ppa); 2453 size -= PAGE_SIZE; 2454 tmpva += PAGE_SIZE; 2455 ppa += PAGE_SIZE; 2456 } 2457 2458 return ((void *)(va + offset)); 2459} 2460 2461void 2462moea64_unmapdev(mmu_t mmu, vm_offset_t va, vm_size_t size) 2463{ 2464 vm_offset_t base, offset; 2465 2466 base = trunc_page(va); 2467 offset = va & PAGE_MASK; 2468 size = roundup(offset + size, PAGE_SIZE); 2469 2470 kmem_free(kernel_map, base, size); 2471} 2472 2473static void 2474moea64_sync_icache(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_size_t sz) 2475{ 2476 struct pvo_entry *pvo; 2477 vm_offset_t lim; 2478 vm_paddr_t pa; 2479 vm_size_t len; 2480 2481 PMAP_LOCK(pm); 2482 while (sz > 0) { 2483 lim = round_page(va); 2484 len = MIN(lim - va, sz); 2485 pvo = moea64_pvo_find_va(pm, va & ~ADDR_POFF, NULL); 2486 if (pvo != NULL) { 2487 pa = (pvo->pvo_pte.pte.pte_lo & PTE_RPGN) | 2488 (va & ADDR_POFF); 2489 moea64_syncicache(pm, va, pa, len); 2490 } 2491 va += len; 2492 sz -= len; 2493 } 2494 PMAP_UNLOCK(pm); 2495} 2496