sio.c revision 93134
1/*- 2 * Copyright (c) 1991 The Regents of the University of California. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by the University of 16 * California, Berkeley and its contributors. 17 * 4. Neither the name of the University nor the names of its contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 25 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 31 * SUCH DAMAGE. 32 * 33 * $FreeBSD: head/sys/pc98/cbus/sio.c 93134 2002-03-25 12:44:03Z nyan $ 34 * from: @(#)com.c 7.5 (Berkeley) 5/16/91 35 * from: i386/isa sio.c,v 1.234 36 */ 37 38#include "opt_comconsole.h" 39#include "opt_compat.h" 40#include "opt_ddb.h" 41#include "opt_sio.h" 42 43/* 44 * Serial driver, based on 386BSD-0.1 com driver. 45 * Mostly rewritten to use pseudo-DMA. 46 * Works for National Semiconductor NS8250-NS16550AF UARTs. 47 * COM driver, based on HP dca driver. 48 * 49 * Changes for PC-Card integration: 50 * - Added PC-Card driver table and handlers 51 */ 52/*=============================================================== 53 * 386BSD(98),FreeBSD-1.1x(98) com driver. 54 * ----- 55 * modified for PC9801 by M.Ishii 56 * Kyoto University Microcomputer Club (KMC) 57 * Chou "TEFUTEFU" Hirotomi 58 * Kyoto Univ. the faculty of medicine 59 *=============================================================== 60 * FreeBSD-2.0.1(98) sio driver. 61 * ----- 62 * modified for pc98 Internal i8251 and MICRO CORE MC16550II 63 * T.Koike(hfc01340@niftyserve.or.jp) 64 * implement kernel device configuration 65 * aizu@orient.center.nitech.ac.jp 66 * 67 * Notes. 68 * ----- 69 * PC98 localization based on 386BSD(98) com driver. Using its PC98 local 70 * functions. 71 * This driver is under debugging,has bugs. 72 * 73 * 1) config 74 * options COM_MULTIPORT #if using MC16550II 75 * device sio0 at nec? port 0x30 tty irq 4 #internal 76 * device sio1 at nec? port 0xd2 tty irq 5 flags 0x101 #mc1 77 * device sio2 at nec? port 0x8d2 tty flags 0x101 #mc2 78 * # ~~~~~iobase ~~multi port flag 79 * # ~ master device is sio1 80 * 2) device 81 * cd /dev; MAKEDEV ttyd0 ttyd1 .. 82 * 3) /etc/rc.serial 83 * 57600bps is too fast for sio0(internal8251) 84 * my ex. 85 * #set default speed 9600 86 * modem() 87 * : 88 * stty </dev/ttyid$i crtscts 9600 89 * : # ~~~~ default speed(can change after init.) 90 * modem 0 1 2 91 * 4) COMCONSOLE 92 * not changed. 93 * 5) PC9861K,PIO9032B,B98_01 94 * not tested. 95 */ 96/* 97 * modified for AIWA B98-01 98 * by T.Hatanou <hatanou@yasuda.comm.waseda.ac.jp> last update: 15 Sep.1995 99 * 100 * How to configure... 101 * # options COM_MULTIPORT # support for MICROCORE MC16550II 102 * ... comment-out this line, which will conflict with B98_01. 103 * options "B98_01" # support for AIWA B98-01 104 * device sio1 at nec? port 0x00d1 tty irq ? 105 * device sio2 at nec? port 0x00d5 tty irq ? 106 * ... you can leave these lines `irq ?', irq will be autodetected. 107 */ 108/* 109 * Modified by Y.Takahashi of Kogakuin University. 110 */ 111/* 112 * modified for 8251(FIFO) by Seigo TANIMURA <tanimura@FreeBSD.org> 113 */ 114 115#include <sys/param.h> 116#include <sys/systm.h> 117#include <sys/bus.h> 118#include <sys/conf.h> 119#include <sys/dkstat.h> 120#include <sys/fcntl.h> 121#include <sys/interrupt.h> 122#include <sys/kernel.h> 123#include <sys/lock.h> 124#include <sys/malloc.h> 125#include <sys/module.h> 126#include <sys/mutex.h> 127#include <sys/proc.h> 128#include <sys/reboot.h> 129#include <sys/sysctl.h> 130#include <sys/syslog.h> 131#include <sys/tty.h> 132#include <machine/bus.h> 133#include <sys/rman.h> 134#include <sys/timetc.h> 135#include <sys/timepps.h> 136 137#include <isa/isavar.h> 138 139#include <machine/resource.h> 140 141#include <dev/sio/sioreg.h> 142#include <dev/sio/siovar.h> 143 144#ifdef PC98 145#include <pc98/pc98/pc98.h> 146#include <pc98/pc98/pc98_machdep.h> 147#endif 148 149#ifdef COM_ESP 150#include <dev/ic/esp.h> 151#endif 152#include <dev/ic/ns16550.h> 153#ifdef PC98 154#include <dev/ic/i8251.h> 155#include <dev/ic/rsa.h> 156#endif 157 158#define LOTS_OF_EVENTS 64 /* helps separate urgent events from input */ 159 160#define CALLOUT_MASK 0x80 161#define CONTROL_MASK 0x60 162#define CONTROL_INIT_STATE 0x20 163#define CONTROL_LOCK_STATE 0x40 164#define DEV_TO_UNIT(dev) (MINOR_TO_UNIT(minor(dev))) 165#define MINOR_MAGIC_MASK (CALLOUT_MASK | CONTROL_MASK) 166#define MINOR_TO_UNIT(mynor) ((mynor) & ~MINOR_MAGIC_MASK) 167 168#ifdef COM_MULTIPORT 169/* checks in flags for multiport and which is multiport "master chip" 170 * for a given card 171 */ 172#define COM_ISMULTIPORT(flags) ((flags) & 0x01) 173#define COM_MPMASTER(flags) (((flags) >> 8) & 0x0ff) 174#define COM_NOTAST4(flags) ((flags) & 0x04) 175#endif /* COM_MULTIPORT */ 176 177#define COM_CONSOLE(flags) ((flags) & 0x10) 178#define COM_FORCECONSOLE(flags) ((flags) & 0x20) 179#define COM_LLCONSOLE(flags) ((flags) & 0x40) 180#define COM_DEBUGGER(flags) ((flags) & 0x80) 181#define COM_LOSESOUTINTS(flags) ((flags) & 0x08) 182#define COM_NOFIFO(flags) ((flags) & 0x02) 183#define COM_ST16650A(flags) ((flags) & 0x20000) 184#define COM_C_NOPROBE (0x40000) 185#define COM_NOPROBE(flags) ((flags) & COM_C_NOPROBE) 186#define COM_C_IIR_TXRDYBUG (0x80000) 187#define COM_IIR_TXRDYBUG(flags) ((flags) & COM_C_IIR_TXRDYBUG) 188#define COM_FIFOSIZE(flags) (((flags) & 0xff000000) >> 24) 189 190#ifdef PC98 191#define com_emr com_msr /* Extension mode register for RSB-2000/3000 */ 192#endif 193#define com_scr 7 /* scratch register for 16450-16550 (R/W) */ 194 195#define sio_getreg(com, off) \ 196 (bus_space_read_1((com)->bst, (com)->bsh, (off))) 197#define sio_setreg(com, off, value) \ 198 (bus_space_write_1((com)->bst, (com)->bsh, (off), (value))) 199 200/* 201 * com state bits. 202 * (CS_BUSY | CS_TTGO) and (CS_BUSY | CS_TTGO | CS_ODEVREADY) must be higher 203 * than the other bits so that they can be tested as a group without masking 204 * off the low bits. 205 * 206 * The following com and tty flags correspond closely: 207 * CS_BUSY = TS_BUSY (maintained by comstart(), siopoll() and 208 * comstop()) 209 * CS_TTGO = ~TS_TTSTOP (maintained by comparam() and comstart()) 210 * CS_CTS_OFLOW = CCTS_OFLOW (maintained by comparam()) 211 * CS_RTS_IFLOW = CRTS_IFLOW (maintained by comparam()) 212 * TS_FLUSH is not used. 213 * XXX I think TIOCSETA doesn't clear TS_TTSTOP when it clears IXON. 214 * XXX CS_*FLOW should be CF_*FLOW in com->flags (control flags not state). 215 */ 216#define CS_BUSY 0x80 /* output in progress */ 217#define CS_TTGO 0x40 /* output not stopped by XOFF */ 218#define CS_ODEVREADY 0x20 /* external device h/w ready (CTS) */ 219#define CS_CHECKMSR 1 /* check of MSR scheduled */ 220#define CS_CTS_OFLOW 2 /* use CTS output flow control */ 221#define CS_DTR_OFF 0x10 /* DTR held off */ 222#define CS_ODONE 4 /* output completed */ 223#define CS_RTS_IFLOW 8 /* use RTS input flow control */ 224#define CSE_BUSYCHECK 1 /* siobusycheck() scheduled */ 225 226static char const * const error_desc[] = { 227#define CE_OVERRUN 0 228 "silo overflow", 229#define CE_INTERRUPT_BUF_OVERFLOW 1 230 "interrupt-level buffer overflow", 231#define CE_TTY_BUF_OVERFLOW 2 232 "tty-level buffer overflow", 233}; 234 235#define CE_NTYPES 3 236#define CE_RECORD(com, errnum) (++(com)->delta_error_counts[errnum]) 237 238/* types. XXX - should be elsewhere */ 239typedef u_int Port_t; /* hardware port */ 240typedef u_char bool_t; /* boolean */ 241 242/* queue of linear buffers */ 243struct lbq { 244 u_char *l_head; /* next char to process */ 245 u_char *l_tail; /* one past the last char to process */ 246 struct lbq *l_next; /* next in queue */ 247 bool_t l_queued; /* nonzero if queued */ 248}; 249 250/* com device structure */ 251struct com_s { 252 u_int flags; /* Copy isa device flags */ 253 u_char state; /* miscellaneous flag bits */ 254 bool_t active_out; /* nonzero if the callout device is open */ 255 u_char cfcr_image; /* copy of value written to CFCR */ 256#ifdef COM_ESP 257 bool_t esp; /* is this unit a hayes esp board? */ 258#endif 259 u_char extra_state; /* more flag bits, separate for order trick */ 260 u_char fifo_image; /* copy of value written to FIFO */ 261 bool_t hasfifo; /* nonzero for 16550 UARTs */ 262 bool_t st16650a; /* Is a Startech 16650A or RTS/CTS compat */ 263 bool_t loses_outints; /* nonzero if device loses output interrupts */ 264 u_char mcr_image; /* copy of value written to MCR */ 265#ifdef COM_MULTIPORT 266 bool_t multiport; /* is this unit part of a multiport device? */ 267#endif /* COM_MULTIPORT */ 268 bool_t no_irq; /* nonzero if irq is not attached */ 269 bool_t gone; /* hardware disappeared */ 270 bool_t poll; /* nonzero if polling is required */ 271 bool_t poll_output; /* nonzero if polling for output is required */ 272 int unit; /* unit number */ 273 int dtr_wait; /* time to hold DTR down on close (* 1/hz) */ 274 u_int tx_fifo_size; 275 u_int wopeners; /* # processes waiting for DCD in open() */ 276 277 /* 278 * The high level of the driver never reads status registers directly 279 * because there would be too many side effects to handle conveniently. 280 * Instead, it reads copies of the registers stored here by the 281 * interrupt handler. 282 */ 283 u_char last_modem_status; /* last MSR read by intr handler */ 284 u_char prev_modem_status; /* last MSR handled by high level */ 285 286 u_char hotchar; /* ldisc-specific char to be handled ASAP */ 287 u_char *ibuf; /* start of input buffer */ 288 u_char *ibufend; /* end of input buffer */ 289 u_char *ibufold; /* old input buffer, to be freed */ 290 u_char *ihighwater; /* threshold in input buffer */ 291 u_char *iptr; /* next free spot in input buffer */ 292 int ibufsize; /* size of ibuf (not include error bytes) */ 293 int ierroff; /* offset of error bytes in ibuf */ 294 295 struct lbq obufq; /* head of queue of output buffers */ 296 struct lbq obufs[2]; /* output buffers */ 297 298 bus_space_tag_t bst; 299 bus_space_handle_t bsh; 300 301#ifdef PC98 302 Port_t cmd_port; 303 Port_t sts_port; 304 Port_t in_modem_port; 305 Port_t intr_ctrl_port; 306 Port_t rsabase; /* iobase address of a I/O-DATA RSA board */ 307 int intr_enable; 308 int pc98_prev_modem_status; 309 int pc98_modem_delta; 310 int modem_car_chg_timer; 311 int pc98_prev_siocmd; 312 int pc98_prev_siomod; 313 int modem_checking; 314 int pc98_if_type; 315 316 bool_t pc98_8251fifo; 317 bool_t pc98_8251fifo_enable; 318#endif /* PC98 */ 319 Port_t data_port; /* i/o ports */ 320#ifdef COM_ESP 321 Port_t esp_port; 322#endif 323 Port_t int_id_port; 324 Port_t modem_ctl_port; 325 Port_t line_status_port; 326 Port_t modem_status_port; 327 Port_t intr_ctl_port; /* Ports of IIR register */ 328 329 struct tty *tp; /* cross reference */ 330 331 /* Initial state. */ 332 struct termios it_in; /* should be in struct tty */ 333 struct termios it_out; 334 335 /* Lock state. */ 336 struct termios lt_in; /* should be in struct tty */ 337 struct termios lt_out; 338 339 bool_t do_timestamp; 340 bool_t do_dcd_timestamp; 341 struct timeval timestamp; 342 struct timeval dcd_timestamp; 343 struct pps_state pps; 344 345 u_long bytes_in; /* statistics */ 346 u_long bytes_out; 347 u_int delta_error_counts[CE_NTYPES]; 348 u_long error_counts[CE_NTYPES]; 349 350 u_long rclk; 351 352 struct resource *irqres; 353 struct resource *ioportres; 354 void *cookie; 355 dev_t devs[6]; 356 357 /* 358 * Data area for output buffers. Someday we should build the output 359 * buffer queue without copying data. 360 */ 361#ifdef PC98 362 int obufsize; 363 u_char *obuf1; 364 u_char *obuf2; 365#else 366 u_char obuf1[256]; 367 u_char obuf2[256]; 368#endif 369}; 370 371#ifdef COM_ESP 372static int espattach(struct com_s *com, Port_t esp_port); 373#endif 374 375static timeout_t siobusycheck; 376static u_int siodivisor(u_long rclk, speed_t speed); 377static timeout_t siodtrwakeup; 378static void comhardclose(struct com_s *com); 379static void sioinput(struct com_s *com); 380static void siointr1(struct com_s *com); 381static void siointr(void *arg); 382static int commctl(struct com_s *com, int bits, int how); 383static int comparam(struct tty *tp, struct termios *t); 384static void siopoll(void *); 385static void siosettimeout(void); 386static int siosetwater(struct com_s *com, speed_t speed); 387static void comstart(struct tty *tp); 388static void comstop(struct tty *tp, int rw); 389static timeout_t comwakeup; 390static void disc_optim(struct tty *tp, struct termios *t, 391 struct com_s *com); 392 393char sio_driver_name[] = "sio"; 394static struct mtx sio_lock; 395static int sio_inited; 396 397/* table and macro for fast conversion from a unit number to its com struct */ 398devclass_t sio_devclass; 399#define com_addr(unit) ((struct com_s *) \ 400 devclass_get_softc(sio_devclass, unit)) /* XXX */ 401 402static d_open_t sioopen; 403static d_close_t sioclose; 404static d_read_t sioread; 405static d_write_t siowrite; 406static d_ioctl_t sioioctl; 407 408#define CDEV_MAJOR 28 409static struct cdevsw sio_cdevsw = { 410 /* open */ sioopen, 411 /* close */ sioclose, 412 /* read */ sioread, 413 /* write */ siowrite, 414 /* ioctl */ sioioctl, 415 /* poll */ ttypoll, 416 /* mmap */ nommap, 417 /* strategy */ nostrategy, 418 /* name */ sio_driver_name, 419 /* maj */ CDEV_MAJOR, 420 /* dump */ nodump, 421 /* psize */ nopsize, 422 /* flags */ D_TTY | D_KQFILTER, 423 /* kqfilter */ ttykqfilter, 424}; 425 426int comconsole = -1; 427static volatile speed_t comdefaultrate = CONSPEED; 428static u_long comdefaultrclk = DEFAULT_RCLK; 429SYSCTL_ULONG(_machdep, OID_AUTO, conrclk, CTLFLAG_RW, &comdefaultrclk, 0, ""); 430#ifdef __alpha__ 431static volatile speed_t gdbdefaultrate = CONSPEED; 432#endif 433static u_int com_events; /* input chars + weighted output completions */ 434static Port_t siocniobase; 435#ifndef __alpha__ 436static int siocnunit; 437#endif 438static Port_t siogdbiobase; 439static int siogdbunit = -1; 440static void *sio_slow_ih; 441static void *sio_fast_ih; 442static int sio_timeout; 443static int sio_timeouts_until_log; 444static struct callout_handle sio_timeout_handle 445 = CALLOUT_HANDLE_INITIALIZER(&sio_timeout_handle); 446static int sio_numunits; 447 448#ifdef PC98 449struct siodev { 450 short if_type; 451 short irq; 452 Port_t cmd, sts, ctrl, mod; 453}; 454static int sysclock; 455 456#define COM_INT_DISABLE {int previpri; previpri=spltty(); 457#define COM_INT_ENABLE splx(previpri);} 458#define IEN_TxFLAG IEN_Tx 459 460#define COM_CARRIER_DETECT_EMULATE 0 461#define PC98_CHECK_MODEM_INTERVAL (hz/10) 462#define DCD_OFF_TOLERANCE 2 463#define DCD_ON_RECOGNITION 2 464#define IS_8251(if_type) (!(if_type & 0x10)) 465#define COM1_EXT_CLOCK 0x40000 466 467static void commint(dev_t dev); 468static void com_tiocm_set(struct com_s *com, int msr); 469static void com_tiocm_bis(struct com_s *com, int msr); 470static void com_tiocm_bic(struct com_s *com, int msr); 471static int com_tiocm_get(struct com_s *com); 472static int com_tiocm_get_delta(struct com_s *com); 473static void pc98_msrint_start(dev_t dev); 474static void com_cflag_and_speed_set(struct com_s *com, int cflag, int speed); 475static int pc98_ttspeedtab(struct com_s *com, int speed, u_int *divisor); 476static int pc98_get_modem_status(struct com_s *com); 477static timeout_t pc98_check_msr; 478static void pc98_set_baud_rate(struct com_s *com, u_int count); 479static void pc98_i8251_reset(struct com_s *com, int mode, int command); 480static void pc98_disable_i8251_interrupt(struct com_s *com, int mod); 481static void pc98_enable_i8251_interrupt(struct com_s *com, int mod); 482static int pc98_check_i8251_interrupt(struct com_s *com); 483static int pc98_i8251_get_cmd(struct com_s *com); 484static int pc98_i8251_get_mod(struct com_s *com); 485static void pc98_i8251_set_cmd(struct com_s *com, int x); 486static void pc98_i8251_or_cmd(struct com_s *com, int x); 487static void pc98_i8251_clear_cmd(struct com_s *com, int x); 488static void pc98_i8251_clear_or_cmd(struct com_s *com, int clr, int x); 489static int pc98_check_if_type(device_t dev, struct siodev *iod); 490static int pc98_check_8251vfast(void); 491static int pc98_check_8251fifo(void); 492static void pc98_check_sysclock(void); 493static void pc98_set_ioport(struct com_s *com); 494 495#define com_int_Tx_disable(com) \ 496 pc98_disable_i8251_interrupt(com,IEN_Tx|IEN_TxEMP) 497#define com_int_Tx_enable(com) \ 498 pc98_enable_i8251_interrupt(com,IEN_TxFLAG) 499#define com_int_Rx_disable(com) \ 500 pc98_disable_i8251_interrupt(com,IEN_Rx) 501#define com_int_Rx_enable(com) \ 502 pc98_enable_i8251_interrupt(com,IEN_Rx) 503#define com_int_TxRx_disable(com) \ 504 pc98_disable_i8251_interrupt(com,IEN_Tx|IEN_TxEMP|IEN_Rx) 505#define com_int_TxRx_enable(com) \ 506 pc98_enable_i8251_interrupt(com,IEN_TxFLAG|IEN_Rx) 507#define com_send_break_on(com) \ 508 pc98_i8251_or_cmd(com,CMD8251_SBRK) 509#define com_send_break_off(com) \ 510 pc98_i8251_clear_cmd(com,CMD8251_SBRK) 511 512static struct speedtab pc98speedtab[] = { /* internal RS232C interface */ 513 { 0, 0, }, 514 { 50, 50, }, 515 { 75, 75, }, 516 { 150, 150, }, 517 { 200, 200, }, 518 { 300, 300, }, 519 { 600, 600, }, 520 { 1200, 1200, }, 521 { 2400, 2400, }, 522 { 4800, 4800, }, 523 { 9600, 9600, }, 524 { 19200, 19200, }, 525 { 38400, 38400, }, 526 { 51200, 51200, }, 527 { 76800, 76800, }, 528 { 20800, 20800, }, 529 { 31200, 31200, }, 530 { 41600, 41600, }, 531 { 62400, 62400, }, 532 { -1, -1 } 533}; 534static struct speedtab pc98fast_speedtab[] = { 535 { 9600, 0x80 | (DEFAULT_RCLK / (16 * (9600))), }, 536 { 19200, 0x80 | (DEFAULT_RCLK / (16 * (19200))), }, 537 { 38400, 0x80 | (DEFAULT_RCLK / (16 * (38400))), }, 538 { 57600, 0x80 | (DEFAULT_RCLK / (16 * (57600))), }, 539 { 115200, 0x80 | (DEFAULT_RCLK / (16 * (115200))), }, 540 { -1, -1 } 541}; 542static struct speedtab comspeedtab_pio9032b[] = { 543 { 300, 6, }, 544 { 600, 5, }, 545 { 1200, 4, }, 546 { 2400, 3, }, 547 { 4800, 2, }, 548 { 9600, 1, }, 549 { 19200, 0, }, 550 { 38400, 7, }, 551 { -1, -1 } 552}; 553static struct speedtab comspeedtab_b98_01[] = { 554 { 75, 11, }, 555 { 150, 10, }, 556 { 300, 9, }, 557 { 600, 8, }, 558 { 1200, 7, }, 559 { 2400, 6, }, 560 { 4800, 5, }, 561 { 9600, 4, }, 562 { 19200, 3, }, 563 { 38400, 2, }, 564 { 76800, 1, }, 565 { 153600, 0, }, 566 { -1, -1 } 567}; 568static struct speedtab comspeedtab_ind[] = { 569 { 300, 1536, }, 570 { 600, 768, }, 571 { 1200, 384, }, 572 { 2400, 192, }, 573 { 4800, 96, }, 574 { 9600, 48, }, 575 { 19200, 24, }, 576 { 38400, 12, }, 577 { 57600, 8, }, 578 { 115200, 4, }, 579 { 153600, 3, }, 580 { 230400, 2, }, 581 { 460800, 1, }, 582 { -1, -1 } 583}; 584 585struct { 586 char *name; 587 short port_table[7]; 588 short irr_mask; 589 struct speedtab *speedtab; 590 short check_irq; 591} if_8251_type[] = { 592 /* COM_IF_INTERNAL */ 593 { " (internal)", {0x30, 0x32, 0x32, 0x33, 0x35, -1, -1}, 594 -1, pc98speedtab, 1 }, 595 /* COM_IF_PC9861K_1 */ 596 { " (PC9861K)", {0xb1, 0xb3, 0xb3, 0xb0, 0xb0, -1, -1}, 597 3, NULL, 1 }, 598 /* COM_IF_PC9861K_2 */ 599 { " (PC9861K)", {0xb9, 0xbb, 0xbb, 0xb2, 0xb2, -1, -1}, 600 3, NULL, 1 }, 601 /* COM_IF_IND_SS_1 */ 602 { " (IND-SS)", {0xb1, 0xb3, 0xb3, 0xb0, 0xb0, 0xb3, -1}, 603 3, comspeedtab_ind, 1 }, 604 /* COM_IF_IND_SS_2 */ 605 { " (IND-SS)", {0xb9, 0xbb, 0xbb, 0xb2, 0xb2, 0xbb, -1}, 606 3, comspeedtab_ind, 1 }, 607 /* COM_IF_PIO9032B_1 */ 608 { " (PIO9032B)", {0xb1, 0xb3, 0xb3, 0xb0, 0xb0, 0xb8, -1}, 609 7, comspeedtab_pio9032b, 1 }, 610 /* COM_IF_PIO9032B_2 */ 611 { " (PIO9032B)", {0xb9, 0xbb, 0xbb, 0xb2, 0xb2, 0xba, -1}, 612 7, comspeedtab_pio9032b, 1 }, 613 /* COM_IF_B98_01_1 */ 614 { " (B98-01)", {0xb1, 0xb3, 0xb3, 0xb0, 0xb0, 0xd1, 0xd3}, 615 7, comspeedtab_b98_01, 0 }, 616 /* COM_IF_B98_01_2 */ 617 { " (B98-01)", {0xb9, 0xbb, 0xbb, 0xb2, 0xb2, 0xd5, 0xd7}, 618 7, comspeedtab_b98_01, 0 }, 619}; 620#define PC98SIO_data_port(type) (if_8251_type[type].port_table[0]) 621#define PC98SIO_cmd_port(type) (if_8251_type[type].port_table[1]) 622#define PC98SIO_sts_port(type) (if_8251_type[type].port_table[2]) 623#define PC98SIO_in_modem_port(type) (if_8251_type[type].port_table[3]) 624#define PC98SIO_intr_ctrl_port(type) (if_8251_type[type].port_table[4]) 625#define PC98SIO_baud_rate_port(type) (if_8251_type[type].port_table[5]) 626#define PC98SIO_func_port(type) (if_8251_type[type].port_table[6]) 627 628#define I8251F_data 0x130 629#define I8251F_lsr 0x132 630#define I8251F_msr 0x134 631#define I8251F_iir 0x136 632#define I8251F_fcr 0x138 633#define I8251F_div 0x13a 634 635 636static bus_addr_t port_table_0[] = 637 {0x000, 0x001, 0x002, 0x003, 0x004, 0x005, 0x006, 0x007}; 638static bus_addr_t port_table_1[] = 639 {0x000, 0x002, 0x004, 0x006, 0x008, 0x00a, 0x00c, 0x00e}; 640static bus_addr_t port_table_8[] = 641 {0x000, 0x100, 0x200, 0x300, 0x400, 0x500, 0x600, 0x700}; 642static bus_addr_t port_table_rsa[] = { 643 0x008, 0x009, 0x00a, 0x00b, 0x00c, 0x00d, 0x00e, 0x00f, 644 0x000, 0x001, 0x002, 0x003, 0x004, 0x005, 0x006, 0x007 645}; 646 647struct { 648 char *name; 649 short irr_read; 650 short irr_write; 651 bus_addr_t *iat; 652 bus_size_t iatsz; 653 u_long rclk; 654} if_16550a_type[] = { 655 /* COM_IF_RSA98 */ 656 {" (RSA-98)", -1, -1, port_table_0, IO_COMSIZE, DEFAULT_RCLK}, 657 /* COM_IF_NS16550 */ 658 {"", -1, -1, port_table_0, IO_COMSIZE, DEFAULT_RCLK}, 659 /* COM_IF_SECOND_CCU */ 660 {"", -1, -1, port_table_0, IO_COMSIZE, DEFAULT_RCLK}, 661 /* COM_IF_MC16550II */ 662 {" (MC16550II)", -1, 0x1000, port_table_8, IO_COMSIZE, 663 DEFAULT_RCLK * 4}, 664 /* COM_IF_MCRS98 */ 665 {" (MC-RS98)", -1, 0x1000, port_table_8, IO_COMSIZE, DEFAULT_RCLK * 4}, 666 /* COM_IF_RSB3000 */ 667 {" (RSB-3000)", 0xbf, -1, port_table_1, IO_COMSIZE, DEFAULT_RCLK * 10}, 668 /* COM_IF_RSB384 */ 669 {" (RSB-384)", 0xbf, -1, port_table_1, IO_COMSIZE, DEFAULT_RCLK * 10}, 670 /* COM_IF_MODEM_CARD */ 671 {"", -1, -1, port_table_0, IO_COMSIZE, DEFAULT_RCLK}, 672 /* COM_IF_RSA98III */ 673 {" (RSA-98III)", -1, -1, port_table_rsa, 16, DEFAULT_RCLK * 8}, 674 /* COM_IF_ESP98 */ 675 {" (ESP98)", -1, -1, port_table_1, IO_COMSIZE, DEFAULT_RCLK * 4}, 676}; 677#endif /* PC98 */ 678 679#ifdef COM_ESP 680#ifdef PC98 681 682/* XXX configure this properly. */ 683/* XXX quite broken for new-bus. */ 684static Port_t likely_com_ports[] = { 0, 0xb0, 0xb1, 0 }; 685static Port_t likely_esp_ports[] = { 0xc0d0, 0 }; 686 687#define ESP98_CMD1 (ESP_CMD1 * 0x100) 688#define ESP98_CMD2 (ESP_CMD2 * 0x100) 689#define ESP98_STATUS1 (ESP_STATUS1 * 0x100) 690#define ESP98_STATUS2 (ESP_STATUS2 * 0x100) 691 692#else /* PC98 */ 693 694/* XXX configure this properly. */ 695static Port_t likely_com_ports[] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8, }; 696static Port_t likely_esp_ports[] = { 0x140, 0x180, 0x280, 0 }; 697 698#endif /* PC98 */ 699#endif 700 701/* 702 * handle sysctl read/write requests for console speed 703 * 704 * In addition to setting comdefaultrate for I/O through /dev/console, 705 * also set the initial and lock values for the /dev/ttyXX device 706 * if there is one associated with the console. Finally, if the /dev/tty 707 * device has already been open, change the speed on the open running port 708 * itself. 709 */ 710 711static int 712sysctl_machdep_comdefaultrate(SYSCTL_HANDLER_ARGS) 713{ 714 int error, s; 715 speed_t newspeed; 716 struct com_s *com; 717 struct tty *tp; 718 719 newspeed = comdefaultrate; 720 721 error = sysctl_handle_opaque(oidp, &newspeed, sizeof newspeed, req); 722 if (error || !req->newptr) 723 return (error); 724 725 comdefaultrate = newspeed; 726 727 if (comconsole < 0) /* serial console not selected? */ 728 return (0); 729 730 com = com_addr(comconsole); 731 if (com == NULL) 732 return (ENXIO); 733 734 /* 735 * set the initial and lock rates for /dev/ttydXX and /dev/cuaXX 736 * (note, the lock rates really are boolean -- if non-zero, disallow 737 * speed changes) 738 */ 739 com->it_in.c_ispeed = com->it_in.c_ospeed = 740 com->lt_in.c_ispeed = com->lt_in.c_ospeed = 741 com->it_out.c_ispeed = com->it_out.c_ospeed = 742 com->lt_out.c_ispeed = com->lt_out.c_ospeed = comdefaultrate; 743 744 /* 745 * if we're open, change the running rate too 746 */ 747 tp = com->tp; 748 if (tp && (tp->t_state & TS_ISOPEN)) { 749 tp->t_termios.c_ispeed = 750 tp->t_termios.c_ospeed = comdefaultrate; 751 s = spltty(); 752 error = comparam(tp, &tp->t_termios); 753 splx(s); 754 } 755 return error; 756} 757 758SYSCTL_PROC(_machdep, OID_AUTO, conspeed, CTLTYPE_INT | CTLFLAG_RW, 759 0, 0, sysctl_machdep_comdefaultrate, "I", ""); 760 761/* 762 * Unload the driver and clear the table. 763 * XXX this is mostly wrong. 764 * XXX TODO: 765 * This is usually called when the card is ejected, but 766 * can be caused by a modunload of a controller driver. 767 * The idea is to reset the driver's view of the device 768 * and ensure that any driver entry points such as 769 * read and write do not hang. 770 */ 771int 772siodetach(dev) 773 device_t dev; 774{ 775 struct com_s *com; 776 int i; 777 778 com = (struct com_s *) device_get_softc(dev); 779 if (com == NULL) { 780 device_printf(dev, "NULL com in siounload\n"); 781 return (0); 782 } 783 com->gone = 1; 784 for (i = 0 ; i < 6; i++) 785 destroy_dev(com->devs[i]); 786 if (com->irqres) { 787 bus_teardown_intr(dev, com->irqres, com->cookie); 788 bus_release_resource(dev, SYS_RES_IRQ, 0, com->irqres); 789 } 790 if (com->ioportres) 791 bus_release_resource(dev, SYS_RES_IOPORT, 0, com->ioportres); 792 if (com->tp && (com->tp->t_state & TS_ISOPEN)) { 793 device_printf(dev, "still open, forcing close\n"); 794 (*linesw[com->tp->t_line].l_close)(com->tp, 0); 795 com->tp->t_gen++; 796 ttyclose(com->tp); 797 ttwakeup(com->tp); 798 ttwwakeup(com->tp); 799 } else { 800 if (com->ibuf != NULL) 801 free(com->ibuf, M_DEVBUF); 802#ifdef PC98 803 if (com->obuf1 != NULL) 804 free(com->obuf1, M_DEVBUF); 805#endif 806 device_set_softc(dev, NULL); 807 free(com, M_DEVBUF); 808 } 809 return (0); 810} 811 812int 813sioprobe(dev, xrid, rclk, noprobe) 814 device_t dev; 815 int xrid; 816 u_long rclk; 817 int noprobe; 818{ 819#if 0 820 static bool_t already_init; 821 device_t xdev; 822#endif 823 struct com_s *com; 824 u_int divisor; 825 bool_t failures[10]; 826 int fn; 827 device_t idev; 828 Port_t iobase; 829 intrmask_t irqmap[4]; 830 intrmask_t irqs; 831 u_char mcr_image; 832 int result; 833 u_long xirq; 834 u_int flags = device_get_flags(dev); 835 int rid; 836 struct resource *port; 837#ifdef PC98 838 int tmp; 839 struct siodev iod; 840#endif 841 842#ifdef PC98 843 iod.if_type = GET_IFTYPE(flags); 844 if ((iod.if_type < 0 || iod.if_type > COM_IF_END1) && 845 (iod.if_type < 0x10 || iod.if_type > COM_IF_END2)) 846 return ENXIO; 847#endif 848 849 rid = xrid; 850#ifdef PC98 851 if (IS_8251(iod.if_type)) { 852 port = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 853 0, ~0, 1, RF_ACTIVE); 854 } else if (iod.if_type == COM_IF_MODEM_CARD || 855 iod.if_type == COM_IF_RSA98III || 856 isa_get_vendorid(dev)) { 857 port = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 0, ~0, 858 if_16550a_type[iod.if_type & 0x0f].iatsz, RF_ACTIVE); 859 } else { 860 port = isa_alloc_resourcev(dev, SYS_RES_IOPORT, &rid, 861 if_16550a_type[iod.if_type & 0x0f].iat, 862 if_16550a_type[iod.if_type & 0x0f].iatsz, RF_ACTIVE); 863 } 864#else 865 port = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 866 0, ~0, IO_COMSIZE, RF_ACTIVE); 867#endif 868 if (!port) 869 return (ENXIO); 870#ifdef PC98 871 if (!IS_8251(iod.if_type)) { 872 if (isa_load_resourcev(port, 873 if_16550a_type[iod.if_type & 0x0f].iat, 874 if_16550a_type[iod.if_type & 0x0f].iatsz) != 0) { 875 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 876 return ENXIO; 877 } 878 } 879#endif 880 881 com = malloc(sizeof(*com), M_DEVBUF, M_NOWAIT | M_ZERO); 882 if (com == NULL) 883 return (ENOMEM); 884 device_set_softc(dev, com); 885 com->bst = rman_get_bustag(port); 886 com->bsh = rman_get_bushandle(port); 887#ifdef PC98 888 if (!IS_8251(iod.if_type) && rclk == 0) 889 rclk = if_16550a_type[iod.if_type & 0x0f].rclk; 890#else 891 if (rclk == 0) 892 rclk = DEFAULT_RCLK; 893#endif 894 com->rclk = rclk; 895 896 while (sio_inited != 2) 897 if (atomic_cmpset_int(&sio_inited, 0, 1)) { 898 mtx_init(&sio_lock, sio_driver_name, (comconsole != -1) ? 899 MTX_SPIN | MTX_QUIET : MTX_SPIN); 900 atomic_store_rel_int(&sio_inited, 2); 901 } 902 903#if 0 904 /* 905 * XXX this is broken - when we are first called, there are no 906 * previously configured IO ports. We could hard code 907 * 0x3f8, 0x2f8, 0x3e8, 0x2e8 etc but that's probably worse. 908 * This code has been doing nothing since the conversion since 909 * "count" is zero the first time around. 910 */ 911 if (!already_init) { 912 /* 913 * Turn off MCR_IENABLE for all likely serial ports. An unused 914 * port with its MCR_IENABLE gate open will inhibit interrupts 915 * from any used port that shares the interrupt vector. 916 * XXX the gate enable is elsewhere for some multiports. 917 */ 918 device_t *devs; 919 int count, i, xioport; 920#ifdef PC98 921 int xiftype; 922#endif 923 924 devclass_get_devices(sio_devclass, &devs, &count); 925#ifdef PC98 926 for (i = 0; i < count; i++) { 927 xdev = devs[i]; 928 xioport = bus_get_resource_start(xdev, SYS_RES_IOPORT, 0); 929 xiftype = GET_IFTYPE(device_get_flags(xdev)); 930 if (device_is_enabled(xdev) && xioport > 0) { 931 if (IS_8251(xiftype)) 932 outb((xioport & 0xff00) | PC98SIO_cmd_port(xiftype & 0x0f), 0xf2); 933 else 934 outb(xioport + if_16550a_type[xiftype & 0x0f].iat[com_mcr], 0); 935 } 936 } 937#else 938 for (i = 0; i < count; i++) { 939 xdev = devs[i]; 940 if (device_is_enabled(xdev) && 941 bus_get_resource(xdev, SYS_RES_IOPORT, 0, &xioport, 942 NULL) == 0) 943 outb(xioport + com_mcr, 0); 944 } 945#endif 946 free(devs, M_TEMP); 947 already_init = TRUE; 948 } 949#endif 950 951 if (COM_LLCONSOLE(flags)) { 952 printf("sio%d: reserved for low-level i/o\n", 953 device_get_unit(dev)); 954 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 955 device_set_softc(dev, NULL); 956 free(com, M_DEVBUF); 957 return (ENXIO); 958 } 959 960#ifdef PC98 961 DELAY(10); 962 963 /* 964 * If the port is i8251 UART (internal, B98_01) 965 */ 966 if (pc98_check_if_type(dev, &iod) == -1) { 967 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 968 device_set_softc(dev, NULL); 969 free(com, M_DEVBUF); 970 return (ENXIO); 971 } 972 if (iod.irq > 0) 973 bus_set_resource(dev, SYS_RES_IRQ, 0, iod.irq, 1); 974 if (IS_8251(iod.if_type)) { 975 outb(iod.cmd, 0); 976 DELAY(10); 977 outb(iod.cmd, 0); 978 DELAY(10); 979 outb(iod.cmd, 0); 980 DELAY(10); 981 outb(iod.cmd, CMD8251_RESET); 982 DELAY(1000); /* for a while...*/ 983 outb(iod.cmd, 0xf2); /* MODE (dummy) */ 984 DELAY(10); 985 outb(iod.cmd, 0x01); /* CMD (dummy) */ 986 DELAY(1000); /* for a while...*/ 987 if (( inb(iod.sts) & STS8251_TxEMP ) == 0 ) { 988 result = (ENXIO); 989 } 990 if (if_8251_type[iod.if_type & 0x0f].check_irq) { 991 COM_INT_DISABLE 992 tmp = ( inb( iod.ctrl ) & ~(IEN_Rx|IEN_TxEMP|IEN_Tx)); 993 outb( iod.ctrl, tmp|IEN_TxEMP ); 994 DELAY(10); 995 result = isa_irq_pending() ? 0 : ENXIO; 996 outb( iod.ctrl, tmp ); 997 COM_INT_ENABLE 998 } else { 999 /* 1000 * B98_01 doesn't activate TxEMP interrupt line 1001 * when being reset, so we can't check irq pending. 1002 */ 1003 result = 0; 1004 } 1005 if (epson_machine_id==0x20) { /* XXX */ 1006 result = 0; 1007 } 1008 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 1009 if (result) { 1010 device_set_softc(dev, NULL); 1011 free(com, M_DEVBUF); 1012 } 1013 return result; 1014 } 1015#endif /* PC98 */ 1016 /* 1017 * If the device is on a multiport card and has an AST/4 1018 * compatible interrupt control register, initialize this 1019 * register and prepare to leave MCR_IENABLE clear in the mcr. 1020 * Otherwise, prepare to set MCR_IENABLE in the mcr. 1021 * Point idev to the device struct giving the correct id_irq. 1022 * This is the struct for the master device if there is one. 1023 */ 1024 idev = dev; 1025 mcr_image = MCR_IENABLE; 1026#ifdef COM_MULTIPORT 1027 if (COM_ISMULTIPORT(flags)) { 1028#ifndef PC98 1029 Port_t xiobase; 1030 u_long io; 1031#endif 1032 1033 idev = devclass_get_device(sio_devclass, COM_MPMASTER(flags)); 1034 if (idev == NULL) { 1035 printf("sio%d: master device %d not configured\n", 1036 device_get_unit(dev), COM_MPMASTER(flags)); 1037 idev = dev; 1038 } 1039#ifndef PC98 1040 if (!COM_NOTAST4(flags)) { 1041 if (bus_get_resource(idev, SYS_RES_IOPORT, 0, &io, 1042 NULL) == 0) { 1043 xiobase = io; 1044 if (bus_get_resource(idev, SYS_RES_IRQ, 0, 1045 NULL, NULL) == 0) 1046 outb(xiobase + com_scr, 0x80); 1047 else 1048 outb(xiobase + com_scr, 0); 1049 } 1050 mcr_image = 0; 1051 } 1052#endif 1053 } 1054#endif /* COM_MULTIPORT */ 1055 if (bus_get_resource(idev, SYS_RES_IRQ, 0, NULL, NULL) != 0) 1056 mcr_image = 0; 1057 1058 bzero(failures, sizeof failures); 1059 iobase = rman_get_start(port); 1060 1061#ifdef PC98 1062 if (iod.if_type == COM_IF_RSA98III) { 1063 mcr_image = 0; 1064 1065 outb(iobase + rsa_msr, 0x04); 1066 outb(iobase + rsa_frr, 0x00); 1067 if ((inb(iobase + rsa_srr) & 0x36) != 0x36) { 1068 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 1069 device_set_softc(dev, NULL); 1070 free(com, M_DEVBUF); 1071 return (ENXIO); 1072 } 1073 outb(iobase + rsa_ier, 0x00); 1074 outb(iobase + rsa_frr, 0x00); 1075 outb(iobase + rsa_tivsr, 0x00); 1076 outb(iobase + rsa_tcr, 0x00); 1077 } 1078 1079 tmp = if_16550a_type[iod.if_type & 0x0f].irr_write; 1080 if (tmp != -1) { 1081 /* MC16550II */ 1082 int irqout; 1083 switch (isa_get_irq(idev)) { 1084 case 3: irqout = 4; break; 1085 case 5: irqout = 5; break; 1086 case 6: irqout = 6; break; 1087 case 12: irqout = 7; break; 1088 default: 1089 printf("sio%d: irq configuration error\n", 1090 device_get_unit(dev)); 1091 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 1092 device_set_softc(dev, NULL); 1093 free(com, M_DEVBUF); 1094 return (ENXIO); 1095 } 1096 outb((iobase & 0x00ff) | tmp, irqout); 1097 } 1098#endif 1099 1100 /* 1101 * We don't want to get actual interrupts, just masked ones. 1102 * Interrupts from this line should already be masked in the ICU, 1103 * but mask them in the processor as well in case there are some 1104 * (misconfigured) shared interrupts. 1105 */ 1106 mtx_lock_spin(&sio_lock); 1107/* EXTRA DELAY? */ 1108 1109 /* 1110 * Initialize the speed and the word size and wait long enough to 1111 * drain the maximum of 16 bytes of junk in device output queues. 1112 * The speed is undefined after a master reset and must be set 1113 * before relying on anything related to output. There may be 1114 * junk after a (very fast) soft reboot and (apparently) after 1115 * master reset. 1116 * XXX what about the UART bug avoided by waiting in comparam()? 1117 * We don't want to to wait long enough to drain at 2 bps. 1118 */ 1119 if (iobase == siocniobase) 1120 DELAY((16 + 1) * 1000000 / (comdefaultrate / 10)); 1121 else { 1122 sio_setreg(com, com_cfcr, CFCR_DLAB | CFCR_8BITS); 1123 divisor = siodivisor(rclk, SIO_TEST_SPEED); 1124 sio_setreg(com, com_dlbl, divisor & 0xff); 1125 sio_setreg(com, com_dlbh, divisor >> 8); 1126 sio_setreg(com, com_cfcr, CFCR_8BITS); 1127 DELAY((16 + 1) * 1000000 / (SIO_TEST_SPEED / 10)); 1128 } 1129 1130 /* 1131 * Enable the interrupt gate and disable device interupts. This 1132 * should leave the device driving the interrupt line low and 1133 * guarantee an edge trigger if an interrupt can be generated. 1134 */ 1135/* EXTRA DELAY? */ 1136 sio_setreg(com, com_mcr, mcr_image); 1137 sio_setreg(com, com_ier, 0); 1138 DELAY(1000); /* XXX */ 1139 irqmap[0] = isa_irq_pending(); 1140 1141 /* 1142 * Attempt to set loopback mode so that we can send a null byte 1143 * without annoying any external device. 1144 */ 1145/* EXTRA DELAY? */ 1146 sio_setreg(com, com_mcr, mcr_image | MCR_LOOPBACK); 1147 1148 /* 1149 * Attempt to generate an output interrupt. On 8250's, setting 1150 * IER_ETXRDY generates an interrupt independent of the current 1151 * setting and independent of whether the THR is empty. On 16450's, 1152 * setting IER_ETXRDY generates an interrupt independent of the 1153 * current setting. On 16550A's, setting IER_ETXRDY only 1154 * generates an interrupt when IER_ETXRDY is not already set. 1155 */ 1156 sio_setreg(com, com_ier, IER_ETXRDY); 1157#ifdef PC98 1158 if (iod.if_type == COM_IF_RSA98III) 1159 outb(iobase + rsa_ier, 0x04); 1160#endif 1161 1162 /* 1163 * On some 16x50 incompatibles, setting IER_ETXRDY doesn't generate 1164 * an interrupt. They'd better generate one for actually doing 1165 * output. Loopback may be broken on the same incompatibles but 1166 * it's unlikely to do more than allow the null byte out. 1167 */ 1168 sio_setreg(com, com_data, 0); 1169 DELAY((1 + 2) * 1000000 / (SIO_TEST_SPEED / 10)); 1170 1171 /* 1172 * Turn off loopback mode so that the interrupt gate works again 1173 * (MCR_IENABLE was hidden). This should leave the device driving 1174 * an interrupt line high. It doesn't matter if the interrupt 1175 * line oscillates while we are not looking at it, since interrupts 1176 * are disabled. 1177 */ 1178/* EXTRA DELAY? */ 1179 sio_setreg(com, com_mcr, mcr_image); 1180 1181 /* 1182 * Some pcmcia cards have the "TXRDY bug", so we check everyone 1183 * for IIR_TXRDY implementation ( Palido 321s, DC-1S... ) 1184 */ 1185 if (noprobe) { 1186 /* Reading IIR register twice */ 1187 for (fn = 0; fn < 2; fn ++) { 1188 DELAY(10000); 1189 failures[6] = sio_getreg(com, com_iir); 1190 } 1191 /* Check IIR_TXRDY clear ? */ 1192 result = 0; 1193 if (failures[6] & IIR_TXRDY) { 1194 /* Nop, Double check with clearing IER */ 1195 sio_setreg(com, com_ier, 0); 1196 if (sio_getreg(com, com_iir) & IIR_NOPEND) { 1197 /* Ok. we're familia this gang */ 1198 SET_FLAG(dev, COM_C_IIR_TXRDYBUG); 1199 } else { 1200 /* Unknown, Just omit this chip.. XXX */ 1201 result = ENXIO; 1202 sio_setreg(com, com_mcr, 0); 1203 } 1204 } else { 1205 /* OK. this is well-known guys */ 1206 CLR_FLAG(dev, COM_C_IIR_TXRDYBUG); 1207 } 1208 sio_setreg(com, com_ier, 0); 1209 sio_setreg(com, com_cfcr, CFCR_8BITS); 1210 mtx_unlock_spin(&sio_lock); 1211 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 1212 if (iobase == siocniobase) 1213 result = 0; 1214 if (result != 0) { 1215 device_set_softc(dev, NULL); 1216 free(com, M_DEVBUF); 1217 } 1218 return (result); 1219 } 1220 1221 /* 1222 * Check that 1223 * o the CFCR, IER and MCR in UART hold the values written to them 1224 * (the values happen to be all distinct - this is good for 1225 * avoiding false positive tests from bus echoes). 1226 * o an output interrupt is generated and its vector is correct. 1227 * o the interrupt goes away when the IIR in the UART is read. 1228 */ 1229/* EXTRA DELAY? */ 1230 failures[0] = sio_getreg(com, com_cfcr) - CFCR_8BITS; 1231 failures[1] = sio_getreg(com, com_ier) - IER_ETXRDY; 1232 failures[2] = sio_getreg(com, com_mcr) - mcr_image; 1233 DELAY(10000); /* Some internal modems need this time */ 1234 irqmap[1] = isa_irq_pending(); 1235 failures[4] = (sio_getreg(com, com_iir) & IIR_IMASK) - IIR_TXRDY; 1236#ifdef PC98 1237 if (iod.if_type == COM_IF_RSA98III) 1238 inb(iobase + rsa_srr); 1239#endif 1240 DELAY(1000); /* XXX */ 1241 irqmap[2] = isa_irq_pending(); 1242 failures[6] = (sio_getreg(com, com_iir) & IIR_IMASK) - IIR_NOPEND; 1243#ifdef PC98 1244 if (iod.if_type == COM_IF_RSA98III) 1245 inb(iobase + rsa_srr); 1246#endif 1247 1248 /* 1249 * Turn off all device interrupts and check that they go off properly. 1250 * Leave MCR_IENABLE alone. For ports without a master port, it gates 1251 * the OUT2 output of the UART to 1252 * the ICU input. Closing the gate would give a floating ICU input 1253 * (unless there is another device driving it) and spurious interrupts. 1254 * (On the system that this was first tested on, the input floats high 1255 * and gives a (masked) interrupt as soon as the gate is closed.) 1256 */ 1257 sio_setreg(com, com_ier, 0); 1258 sio_setreg(com, com_cfcr, CFCR_8BITS); /* dummy to avoid bus echo */ 1259 failures[7] = sio_getreg(com, com_ier); 1260#ifdef PC98 1261 if (iod.if_type == COM_IF_RSA98III) 1262 outb(iobase + rsa_ier, 0x00); 1263#endif 1264 DELAY(1000); /* XXX */ 1265 irqmap[3] = isa_irq_pending(); 1266 failures[9] = (sio_getreg(com, com_iir) & IIR_IMASK) - IIR_NOPEND; 1267#ifdef PC98 1268 if (iod.if_type == COM_IF_RSA98III) { 1269 inb(iobase + rsa_srr); 1270 outb(iobase + rsa_frr, 0x00); 1271 } 1272#endif 1273 1274 mtx_unlock_spin(&sio_lock); 1275 1276 irqs = irqmap[1] & ~irqmap[0]; 1277 if (bus_get_resource(idev, SYS_RES_IRQ, 0, &xirq, NULL) == 0 && 1278 ((1 << xirq) & irqs) == 0) { 1279 printf( 1280 "sio%d: configured irq %ld not in bitmap of probed irqs %#x\n", 1281 device_get_unit(dev), xirq, irqs); 1282 printf( 1283 "sio%d: port may not be enabled\n", 1284 device_get_unit(dev)); 1285 } 1286 if (bootverbose) 1287 printf("sio%d: irq maps: %#x %#x %#x %#x\n", 1288 device_get_unit(dev), 1289 irqmap[0], irqmap[1], irqmap[2], irqmap[3]); 1290 1291 result = 0; 1292 for (fn = 0; fn < sizeof failures; ++fn) 1293 if (failures[fn]) { 1294 sio_setreg(com, com_mcr, 0); 1295 result = ENXIO; 1296 if (bootverbose) { 1297 printf("sio%d: probe failed test(s):", 1298 device_get_unit(dev)); 1299 for (fn = 0; fn < sizeof failures; ++fn) 1300 if (failures[fn]) 1301 printf(" %d", fn); 1302 printf("\n"); 1303 } 1304 break; 1305 } 1306 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 1307 if (iobase == siocniobase) 1308 result = 0; 1309 if (result != 0) { 1310 device_set_softc(dev, NULL); 1311 free(com, M_DEVBUF); 1312 } 1313 return (result); 1314} 1315 1316#ifdef COM_ESP 1317static int 1318espattach(com, esp_port) 1319 struct com_s *com; 1320 Port_t esp_port; 1321{ 1322 u_char dips; 1323 u_char val; 1324 1325 /* 1326 * Check the ESP-specific I/O port to see if we're an ESP 1327 * card. If not, return failure immediately. 1328 */ 1329 if ((inb(esp_port) & 0xf3) == 0) { 1330 printf(" port 0x%x is not an ESP board?\n", esp_port); 1331 return (0); 1332 } 1333 1334 /* 1335 * We've got something that claims to be a Hayes ESP card. 1336 * Let's hope so. 1337 */ 1338 1339 /* Get the dip-switch configuration */ 1340#ifdef PC98 1341 outb(esp_port + ESP98_CMD1, ESP_GETDIPS); 1342 dips = inb(esp_port + ESP98_STATUS1); 1343#else 1344 outb(esp_port + ESP_CMD1, ESP_GETDIPS); 1345 dips = inb(esp_port + ESP_STATUS1); 1346#endif 1347 1348 /* 1349 * Bits 0,1 of dips say which COM port we are. 1350 */ 1351#ifdef PC98 1352 if ((rman_get_start(com->ioportres) & 0xff) == 1353 likely_com_ports[dips & 0x03]) 1354#else 1355 if (rman_get_start(com->ioportres) == likely_com_ports[dips & 0x03]) 1356#endif 1357 printf(" : ESP"); 1358 else { 1359 printf(" esp_port has com %d\n", dips & 0x03); 1360 return (0); 1361 } 1362 1363 /* 1364 * Check for ESP version 2.0 or later: bits 4,5,6 = 010. 1365 */ 1366#ifdef PC98 1367 outb(esp_port + ESP98_CMD1, ESP_GETTEST); 1368 val = inb(esp_port + ESP98_STATUS1); /* clear reg 1 */ 1369 val = inb(esp_port + ESP98_STATUS2); 1370#else 1371 outb(esp_port + ESP_CMD1, ESP_GETTEST); 1372 val = inb(esp_port + ESP_STATUS1); /* clear reg 1 */ 1373 val = inb(esp_port + ESP_STATUS2); 1374#endif 1375 if ((val & 0x70) < 0x20) { 1376 printf("-old (%o)", val & 0x70); 1377 return (0); 1378 } 1379 1380 /* 1381 * Check for ability to emulate 16550: bit 7 == 1 1382 */ 1383 if ((dips & 0x80) == 0) { 1384 printf(" slave"); 1385 return (0); 1386 } 1387 1388 /* 1389 * Okay, we seem to be a Hayes ESP card. Whee. 1390 */ 1391 com->esp = TRUE; 1392 com->esp_port = esp_port; 1393 return (1); 1394} 1395#endif /* COM_ESP */ 1396 1397int 1398sioattach(dev, xrid, rclk) 1399 device_t dev; 1400 int xrid; 1401 u_long rclk; 1402{ 1403 struct com_s *com; 1404#ifdef COM_ESP 1405 Port_t *espp; 1406#endif 1407 Port_t iobase; 1408 int unit; 1409 u_int flags; 1410 int rid; 1411 struct resource *port; 1412 int ret; 1413#ifdef PC98 1414 u_char *obuf; 1415 u_long obufsize; 1416 int if_type = GET_IFTYPE(device_get_flags(dev)); 1417#endif 1418 1419 rid = xrid; 1420#ifdef PC98 1421 if (IS_8251(if_type)) { 1422 port = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 1423 0, ~0, 1, RF_ACTIVE); 1424 } else if (if_type == COM_IF_MODEM_CARD || 1425 if_type == COM_IF_RSA98III || 1426 isa_get_vendorid(dev)) { 1427 port = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 0, ~0, 1428 if_16550a_type[if_type & 0x0f].iatsz, RF_ACTIVE); 1429 } else { 1430 port = isa_alloc_resourcev(dev, SYS_RES_IOPORT, &rid, 1431 if_16550a_type[if_type & 0x0f].iat, 1432 if_16550a_type[if_type & 0x0f].iatsz, RF_ACTIVE); 1433 } 1434#else 1435 port = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 1436 0, ~0, IO_COMSIZE, RF_ACTIVE); 1437#endif 1438 if (!port) 1439 return (ENXIO); 1440#ifdef PC98 1441 if (!IS_8251(if_type)) { 1442 if (isa_load_resourcev(port, 1443 if_16550a_type[if_type & 0x0f].iat, 1444 if_16550a_type[if_type & 0x0f].iatsz) != 0) { 1445 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 1446 return ENXIO; 1447 } 1448 } 1449#endif 1450 1451 iobase = rman_get_start(port); 1452 unit = device_get_unit(dev); 1453 com = device_get_softc(dev); 1454 flags = device_get_flags(dev); 1455 1456 if (unit >= sio_numunits) 1457 sio_numunits = unit + 1; 1458 1459#ifdef PC98 1460 obufsize = 256; 1461 if (if_type == COM_IF_RSA98III) 1462 obufsize = 2048; 1463 if ((obuf = malloc(obufsize * 2, M_DEVBUF, M_NOWAIT)) == NULL) { 1464 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 1465 return ENXIO; 1466 } 1467 bzero(obuf, obufsize * 2); 1468#endif 1469 1470 /* 1471 * sioprobe() has initialized the device registers as follows: 1472 * o cfcr = CFCR_8BITS. 1473 * It is most important that CFCR_DLAB is off, so that the 1474 * data port is not hidden when we enable interrupts. 1475 * o ier = 0. 1476 * Interrupts are only enabled when the line is open. 1477 * o mcr = MCR_IENABLE, or 0 if the port has AST/4 compatible 1478 * interrupt control register or the config specifies no irq. 1479 * Keeping MCR_DTR and MCR_RTS off might stop the external 1480 * device from sending before we are ready. 1481 */ 1482 bzero(com, sizeof *com); 1483 com->unit = unit; 1484 com->ioportres = port; 1485 com->bst = rman_get_bustag(port); 1486 com->bsh = rman_get_bushandle(port); 1487 com->cfcr_image = CFCR_8BITS; 1488 com->dtr_wait = 3 * hz; 1489 com->loses_outints = COM_LOSESOUTINTS(flags) != 0; 1490 com->no_irq = bus_get_resource(dev, SYS_RES_IRQ, 0, NULL, NULL) != 0; 1491 com->tx_fifo_size = 1; 1492#ifdef PC98 1493 com->obufsize = obufsize; 1494 com->obuf1 = obuf; 1495 com->obuf2 = obuf + obufsize; 1496#endif 1497 com->obufs[0].l_head = com->obuf1; 1498 com->obufs[1].l_head = com->obuf2; 1499 1500#ifdef PC98 1501 com->pc98_if_type = if_type; 1502 1503 if (IS_8251(if_type)) { 1504 pc98_set_ioport(com); 1505 1506 if (if_type == COM_IF_INTERNAL && pc98_check_8251fifo()) { 1507 com->pc98_8251fifo = 1; 1508 com->pc98_8251fifo_enable = 0; 1509 } 1510 } else { 1511 bus_addr_t *iat = if_16550a_type[if_type & 0x0f].iat; 1512 1513 com->data_port = iobase + iat[com_data]; 1514 com->int_id_port = iobase + iat[com_iir]; 1515 com->modem_ctl_port = iobase + iat[com_mcr]; 1516 com->mcr_image = inb(com->modem_ctl_port); 1517 com->line_status_port = iobase + iat[com_lsr]; 1518 com->modem_status_port = iobase + iat[com_msr]; 1519 com->intr_ctl_port = iobase + iat[com_ier]; 1520 } 1521#else /* not PC98 */ 1522 com->data_port = iobase + com_data; 1523 com->int_id_port = iobase + com_iir; 1524 com->modem_ctl_port = iobase + com_mcr; 1525 com->mcr_image = inb(com->modem_ctl_port); 1526 com->line_status_port = iobase + com_lsr; 1527 com->modem_status_port = iobase + com_msr; 1528 com->intr_ctl_port = iobase + com_ier; 1529#endif 1530 1531#ifdef PC98 1532 if (!IS_8251(if_type) && rclk == 0) 1533 rclk = if_16550a_type[if_type & 0x0f].rclk; 1534#else 1535 if (rclk == 0) 1536 rclk = DEFAULT_RCLK; 1537#endif 1538 com->rclk = rclk; 1539 1540 /* 1541 * We don't use all the flags from <sys/ttydefaults.h> since they 1542 * are only relevant for logins. It's important to have echo off 1543 * initially so that the line doesn't start blathering before the 1544 * echo flag can be turned off. 1545 */ 1546 com->it_in.c_iflag = 0; 1547 com->it_in.c_oflag = 0; 1548 com->it_in.c_cflag = TTYDEF_CFLAG; 1549 com->it_in.c_lflag = 0; 1550 if (unit == comconsole) { 1551#ifdef PC98 1552 if (IS_8251(com->pc98_if_type)) 1553 DELAY(100000); 1554#endif 1555 com->it_in.c_iflag = TTYDEF_IFLAG; 1556 com->it_in.c_oflag = TTYDEF_OFLAG; 1557 com->it_in.c_cflag = TTYDEF_CFLAG | CLOCAL; 1558 com->it_in.c_lflag = TTYDEF_LFLAG; 1559 com->lt_out.c_cflag = com->lt_in.c_cflag = CLOCAL; 1560 com->lt_out.c_ispeed = com->lt_out.c_ospeed = 1561 com->lt_in.c_ispeed = com->lt_in.c_ospeed = 1562 com->it_in.c_ispeed = com->it_in.c_ospeed = comdefaultrate; 1563 } else 1564 com->it_in.c_ispeed = com->it_in.c_ospeed = TTYDEF_SPEED; 1565 if (siosetwater(com, com->it_in.c_ispeed) != 0) { 1566 mtx_unlock_spin(&sio_lock); 1567 /* 1568 * Leave i/o resources allocated if this is a `cn'-level 1569 * console, so that other devices can't snarf them. 1570 */ 1571 if (iobase != siocniobase) 1572 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 1573 return (ENOMEM); 1574 } 1575 mtx_unlock_spin(&sio_lock); 1576 termioschars(&com->it_in); 1577 com->it_out = com->it_in; 1578 1579 /* attempt to determine UART type */ 1580 printf("sio%d: type", unit); 1581 1582 1583#ifndef PC98 1584#ifdef COM_MULTIPORT 1585 if (!COM_ISMULTIPORT(flags) && !COM_IIR_TXRDYBUG(flags)) 1586#else 1587 if (!COM_IIR_TXRDYBUG(flags)) 1588#endif 1589 { 1590 u_char scr; 1591 u_char scr1; 1592 u_char scr2; 1593 1594 scr = sio_getreg(com, com_scr); 1595 sio_setreg(com, com_scr, 0xa5); 1596 scr1 = sio_getreg(com, com_scr); 1597 sio_setreg(com, com_scr, 0x5a); 1598 scr2 = sio_getreg(com, com_scr); 1599 sio_setreg(com, com_scr, scr); 1600 if (scr1 != 0xa5 || scr2 != 0x5a) { 1601 printf(" 8250 or not responding"); 1602 goto determined_type; 1603 } 1604 } 1605#endif /* !PC98 */ 1606#ifdef PC98 1607 if (IS_8251(com->pc98_if_type)) { 1608 if (com->pc98_8251fifo && !COM_NOFIFO(flags)) 1609 com->tx_fifo_size = 16; 1610 com_int_TxRx_disable( com ); 1611 com_cflag_and_speed_set( com, com->it_in.c_cflag, comdefaultrate ); 1612 com_tiocm_bic( com, TIOCM_DTR|TIOCM_RTS|TIOCM_LE ); 1613 com_send_break_off( com ); 1614 1615 if (com->pc98_if_type == COM_IF_INTERNAL) { 1616 printf(" (internal%s%s)", 1617 com->pc98_8251fifo ? " fifo" : "", 1618 PC98SIO_baud_rate_port(com->pc98_if_type) != -1 ? 1619 " v-fast" : ""); 1620 } else { 1621 printf(" 8251%s", if_8251_type[com->pc98_if_type & 0x0f].name); 1622 } 1623 } else { 1624#endif /* PC98 */ 1625 sio_setreg(com, com_fifo, FIFO_ENABLE | FIFO_RX_HIGH); 1626 DELAY(100); 1627 com->st16650a = 0; 1628 switch (inb(com->int_id_port) & IIR_FIFO_MASK) { 1629 case FIFO_RX_LOW: 1630 printf(" 16450"); 1631 break; 1632 case FIFO_RX_MEDL: 1633 printf(" 16450?"); 1634 break; 1635 case FIFO_RX_MEDH: 1636 printf(" 16550?"); 1637 break; 1638 case FIFO_RX_HIGH: 1639 if (COM_NOFIFO(flags)) { 1640 printf(" 16550A fifo disabled"); 1641 } else { 1642 com->hasfifo = TRUE; 1643#ifdef PC98 1644 com->tx_fifo_size = 0; /* XXX flag conflicts. */ 1645 printf(" 16550A"); 1646#else 1647 if (COM_ST16650A(flags)) { 1648 com->st16650a = 1; 1649 com->tx_fifo_size = 32; 1650 printf(" ST16650A"); 1651 } else { 1652 com->tx_fifo_size = COM_FIFOSIZE(flags); 1653 printf(" 16550A"); 1654 } 1655#endif 1656 } 1657#ifdef PC98 1658 if (com->pc98_if_type == COM_IF_RSA98III) { 1659 com->tx_fifo_size = 2048; 1660 com->rsabase = iobase; 1661 outb(com->rsabase + rsa_ier, 0x00); 1662 outb(com->rsabase + rsa_frr, 0x00); 1663 } 1664#endif 1665 1666#ifdef COM_ESP 1667#ifdef PC98 1668 if (com->pc98_if_type == COM_IF_ESP98) 1669#endif 1670 for (espp = likely_esp_ports; *espp != 0; espp++) 1671 if (espattach(com, *espp)) { 1672 com->tx_fifo_size = 1024; 1673 break; 1674 } 1675#endif 1676 if (!com->st16650a) { 1677 if (!com->tx_fifo_size) 1678 com->tx_fifo_size = 16; 1679 else 1680 printf(" lookalike with %d bytes FIFO", 1681 com->tx_fifo_size); 1682 } 1683 1684 break; 1685 } 1686 1687#ifdef PC98 1688 if (com->pc98_if_type == COM_IF_RSB3000) { 1689 /* Set RSB-2000/3000 Extended Buffer mode. */ 1690 u_char lcr; 1691 lcr = sio_getreg(com, com_cfcr); 1692 sio_setreg(com, com_cfcr, lcr | CFCR_DLAB); 1693 sio_setreg(com, com_emr, EMR_EXBUFF | EMR_EFMODE); 1694 sio_setreg(com, com_cfcr, lcr); 1695 } 1696#endif 1697 1698#ifdef COM_ESP 1699 if (com->esp) { 1700 /* 1701 * Set 16550 compatibility mode. 1702 * We don't use the ESP_MODE_SCALE bit to increase the 1703 * fifo trigger levels because we can't handle large 1704 * bursts of input. 1705 * XXX flow control should be set in comparam(), not here. 1706 */ 1707#ifdef PC98 1708 outb(com->esp_port + ESP98_CMD1, ESP_SETMODE); 1709 outb(com->esp_port + ESP98_CMD2, ESP_MODE_RTS | ESP_MODE_FIFO); 1710#else 1711 outb(com->esp_port + ESP_CMD1, ESP_SETMODE); 1712 outb(com->esp_port + ESP_CMD2, ESP_MODE_RTS | ESP_MODE_FIFO); 1713#endif 1714 1715 /* Set RTS/CTS flow control. */ 1716#ifdef PC98 1717 outb(com->esp_port + ESP98_CMD1, ESP_SETFLOWTYPE); 1718 outb(com->esp_port + ESP98_CMD2, ESP_FLOW_RTS); 1719 outb(com->esp_port + ESP98_CMD2, ESP_FLOW_CTS); 1720#else 1721 outb(com->esp_port + ESP_CMD1, ESP_SETFLOWTYPE); 1722 outb(com->esp_port + ESP_CMD2, ESP_FLOW_RTS); 1723 outb(com->esp_port + ESP_CMD2, ESP_FLOW_CTS); 1724#endif 1725 1726 /* Set flow-control levels. */ 1727#ifdef PC98 1728 outb(com->esp_port + ESP98_CMD1, ESP_SETRXFLOW); 1729 outb(com->esp_port + ESP98_CMD2, HIBYTE(768)); 1730 outb(com->esp_port + ESP98_CMD2, LOBYTE(768)); 1731 outb(com->esp_port + ESP98_CMD2, HIBYTE(512)); 1732 outb(com->esp_port + ESP98_CMD2, LOBYTE(512)); 1733#else 1734 outb(com->esp_port + ESP_CMD1, ESP_SETRXFLOW); 1735 outb(com->esp_port + ESP_CMD2, HIBYTE(768)); 1736 outb(com->esp_port + ESP_CMD2, LOBYTE(768)); 1737 outb(com->esp_port + ESP_CMD2, HIBYTE(512)); 1738 outb(com->esp_port + ESP_CMD2, LOBYTE(512)); 1739#endif 1740 1741#ifdef PC98 1742 /* Set UART clock prescaler. */ 1743 outb(com->esp_port + ESP98_CMD1, ESP_SETCLOCK); 1744 outb(com->esp_port + ESP98_CMD2, 2); /* 4 times */ 1745#endif 1746 } 1747#endif /* COM_ESP */ 1748 sio_setreg(com, com_fifo, 0); 1749#ifdef PC98 1750 printf("%s", if_16550a_type[com->pc98_if_type & 0x0f].name); 1751#else 1752determined_type: ; 1753#endif 1754 1755#ifdef COM_MULTIPORT 1756 if (COM_ISMULTIPORT(flags)) { 1757 device_t masterdev; 1758 1759 com->multiport = TRUE; 1760 printf(" (multiport"); 1761 if (unit == COM_MPMASTER(flags)) 1762 printf(" master"); 1763 printf(")"); 1764 masterdev = devclass_get_device(sio_devclass, 1765 COM_MPMASTER(flags)); 1766 com->no_irq = (masterdev == NULL || bus_get_resource(masterdev, 1767 SYS_RES_IRQ, 0, NULL, NULL) != 0); 1768 } 1769#endif /* COM_MULTIPORT */ 1770#ifdef PC98 1771 } 1772#endif 1773 if (unit == comconsole) 1774 printf(", console"); 1775 if (COM_IIR_TXRDYBUG(flags)) 1776 printf(" with a bogus IIR_TXRDY register"); 1777 printf("\n"); 1778 1779 if (sio_fast_ih == NULL) { 1780 swi_add(&tty_ithd, "tty:sio", siopoll, NULL, SWI_TTY, 0, 1781 &sio_fast_ih); 1782 swi_add(&clk_ithd, "tty:sio", siopoll, NULL, SWI_TTY, 0, 1783 &sio_slow_ih); 1784 } 1785 com->devs[0] = make_dev(&sio_cdevsw, unit, 1786 UID_ROOT, GID_WHEEL, 0600, "ttyd%r", unit); 1787 com->devs[1] = make_dev(&sio_cdevsw, unit | CONTROL_INIT_STATE, 1788 UID_ROOT, GID_WHEEL, 0600, "ttyid%r", unit); 1789 com->devs[2] = make_dev(&sio_cdevsw, unit | CONTROL_LOCK_STATE, 1790 UID_ROOT, GID_WHEEL, 0600, "ttyld%r", unit); 1791 com->devs[3] = make_dev(&sio_cdevsw, unit | CALLOUT_MASK, 1792 UID_UUCP, GID_DIALER, 0660, "cuaa%r", unit); 1793 com->devs[4] = make_dev(&sio_cdevsw, 1794 unit | CALLOUT_MASK | CONTROL_INIT_STATE, 1795 UID_UUCP, GID_DIALER, 0660, "cuaia%r", unit); 1796 com->devs[5] = make_dev(&sio_cdevsw, 1797 unit | CALLOUT_MASK | CONTROL_LOCK_STATE, 1798 UID_UUCP, GID_DIALER, 0660, "cuala%r", unit); 1799 com->flags = flags; 1800 com->pps.ppscap = PPS_CAPTUREASSERT | PPS_CAPTURECLEAR; 1801 pps_init(&com->pps); 1802 1803 rid = 0; 1804 com->irqres = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0ul, ~0ul, 1, 1805 RF_ACTIVE); 1806 if (com->irqres) { 1807 ret = BUS_SETUP_INTR(device_get_parent(dev), dev, com->irqres, 1808 INTR_TYPE_TTY | INTR_FAST, 1809 siointr, com, &com->cookie); 1810 if (ret) { 1811 ret = BUS_SETUP_INTR(device_get_parent(dev), dev, 1812 com->irqres, INTR_TYPE_TTY, 1813 siointr, com, &com->cookie); 1814 if (ret == 0) 1815 device_printf(dev, "unable to activate interrupt in fast mode - using normal mode\n"); 1816 } 1817 if (ret) 1818 device_printf(dev, "could not activate interrupt\n"); 1819#if defined(DDB) && (defined(BREAK_TO_DEBUGGER) || \ 1820 defined(ALT_BREAK_TO_DEBUGGER)) 1821 /* 1822 * Enable interrupts for early break-to-debugger support 1823 * on the console. 1824 */ 1825 if (ret == 0 && unit == comconsole) 1826 outb(siocniobase + com_ier, IER_ERXRDY | IER_ERLS | 1827 IER_EMSC); 1828#endif 1829 } 1830 1831 return (0); 1832} 1833 1834static int 1835sioopen(dev, flag, mode, td) 1836 dev_t dev; 1837 int flag; 1838 int mode; 1839 struct thread *td; 1840{ 1841 struct com_s *com; 1842 int error; 1843 int mynor; 1844 int s; 1845 struct tty *tp; 1846 int unit; 1847 1848 mynor = minor(dev); 1849 unit = MINOR_TO_UNIT(mynor); 1850 com = com_addr(unit); 1851 if (com == NULL) 1852 return (ENXIO); 1853 if (com->gone) 1854 return (ENXIO); 1855 if (mynor & CONTROL_MASK) 1856 return (0); 1857 tp = dev->si_tty = com->tp = ttymalloc(com->tp); 1858 s = spltty(); 1859 /* 1860 * We jump to this label after all non-interrupted sleeps to pick 1861 * up any changes of the device state. 1862 */ 1863open_top: 1864 while (com->state & CS_DTR_OFF) { 1865 error = tsleep(&com->dtr_wait, TTIPRI | PCATCH, "siodtr", 0); 1866 if (com_addr(unit) == NULL) 1867 return (ENXIO); 1868 if (error != 0 || com->gone) 1869 goto out; 1870 } 1871 if (tp->t_state & TS_ISOPEN) { 1872 /* 1873 * The device is open, so everything has been initialized. 1874 * Handle conflicts. 1875 */ 1876 if (mynor & CALLOUT_MASK) { 1877 if (!com->active_out) { 1878 error = EBUSY; 1879 goto out; 1880 } 1881 } else { 1882 if (com->active_out) { 1883 if (flag & O_NONBLOCK) { 1884 error = EBUSY; 1885 goto out; 1886 } 1887 error = tsleep(&com->active_out, 1888 TTIPRI | PCATCH, "siobi", 0); 1889 if (com_addr(unit) == NULL) 1890 return (ENXIO); 1891 if (error != 0 || com->gone) 1892 goto out; 1893 goto open_top; 1894 } 1895 } 1896 if (tp->t_state & TS_XCLUDE && 1897 suser_td(td)) { 1898 error = EBUSY; 1899 goto out; 1900 } 1901 } else { 1902 /* 1903 * The device isn't open, so there are no conflicts. 1904 * Initialize it. Initialization is done twice in many 1905 * cases: to preempt sleeping callin opens if we are 1906 * callout, and to complete a callin open after DCD rises. 1907 */ 1908 tp->t_oproc = comstart; 1909 tp->t_param = comparam; 1910 tp->t_stop = comstop; 1911 tp->t_dev = dev; 1912 tp->t_termios = mynor & CALLOUT_MASK 1913 ? com->it_out : com->it_in; 1914#ifdef PC98 1915 if (!IS_8251(com->pc98_if_type)) 1916#endif 1917 (void)commctl(com, TIOCM_DTR | TIOCM_RTS, DMSET); 1918 com->poll = com->no_irq; 1919 com->poll_output = com->loses_outints; 1920 ++com->wopeners; 1921 error = comparam(tp, &tp->t_termios); 1922 --com->wopeners; 1923 if (error != 0) 1924 goto out; 1925#ifdef PC98 1926 if (IS_8251(com->pc98_if_type)) { 1927 com_tiocm_bis(com, TIOCM_DTR|TIOCM_RTS); 1928 pc98_msrint_start(dev); 1929 if (com->pc98_8251fifo) { 1930 com->pc98_8251fifo_enable = 1; 1931 outb(I8251F_fcr, CTRL8251F_ENABLE | 1932 CTRL8251F_XMT_RST | CTRL8251F_RCV_RST); 1933 } 1934 } 1935#endif 1936 /* 1937 * XXX we should goto open_top if comparam() slept. 1938 */ 1939 if (com->hasfifo) { 1940 /* 1941 * (Re)enable and drain fifos. 1942 * 1943 * Certain SMC chips cause problems if the fifos 1944 * are enabled while input is ready. Turn off the 1945 * fifo if necessary to clear the input. We test 1946 * the input ready bit after enabling the fifos 1947 * since we've already enabled them in comparam() 1948 * and to handle races between enabling and fresh 1949 * input. 1950 */ 1951 while (TRUE) { 1952 sio_setreg(com, com_fifo, 1953 FIFO_RCV_RST | FIFO_XMT_RST 1954 | com->fifo_image); 1955#ifdef PC98 1956 if (com->pc98_if_type == COM_IF_RSA98III) 1957 outb(com->rsabase + rsa_frr , 0x00); 1958#endif 1959 /* 1960 * XXX the delays are for superstitious 1961 * historical reasons. It must be less than 1962 * the character time at the maximum 1963 * supported speed (87 usec at 115200 bps 1964 * 8N1). Otherwise we might loop endlessly 1965 * if data is streaming in. We used to use 1966 * delays of 100. That usually worked 1967 * because DELAY(100) used to usually delay 1968 * for about 85 usec instead of 100. 1969 */ 1970 DELAY(50); 1971#ifdef PC98 1972 if (com->pc98_if_type == COM_IF_RSA98III ? 1973 !(inb(com->rsabase + rsa_srr) & 0x08) : 1974 !(inb(com->line_status_port) & LSR_RXRDY)) 1975 break; 1976#else 1977 if (!(inb(com->line_status_port) & LSR_RXRDY)) 1978 break; 1979#endif 1980 sio_setreg(com, com_fifo, 0); 1981 DELAY(50); 1982 (void) inb(com->data_port); 1983 } 1984 } 1985 1986 mtx_lock_spin(&sio_lock); 1987#ifdef PC98 1988 if (IS_8251(com->pc98_if_type)) { 1989 com_tiocm_bis(com, TIOCM_LE); 1990 com->pc98_prev_modem_status = pc98_get_modem_status(com); 1991 com_int_Rx_enable(com); 1992 } else { 1993#endif 1994 (void) inb(com->line_status_port); 1995 (void) inb(com->data_port); 1996 com->prev_modem_status = com->last_modem_status 1997 = inb(com->modem_status_port); 1998 if (COM_IIR_TXRDYBUG(com->flags)) { 1999 outb(com->intr_ctl_port, IER_ERXRDY | IER_ERLS 2000 | IER_EMSC); 2001 } else { 2002 outb(com->intr_ctl_port, IER_ERXRDY | IER_ETXRDY 2003 | IER_ERLS | IER_EMSC); 2004 } 2005#ifdef PC98 2006 if (com->pc98_if_type == COM_IF_RSA98III) { 2007 outb(com->rsabase + rsa_ier, 0x1d); 2008 outb(com->intr_ctl_port, IER_ERLS | IER_EMSC); 2009 } 2010#endif 2011#ifdef PC98 2012 } 2013#endif 2014 mtx_unlock_spin(&sio_lock); 2015 /* 2016 * Handle initial DCD. Callout devices get a fake initial 2017 * DCD (trapdoor DCD). If we are callout, then any sleeping 2018 * callin opens get woken up and resume sleeping on "siobi" 2019 * instead of "siodcd". 2020 */ 2021 /* 2022 * XXX `mynor & CALLOUT_MASK' should be 2023 * `tp->t_cflag & (SOFT_CARRIER | TRAPDOOR_CARRIER) where 2024 * TRAPDOOR_CARRIER is the default initial state for callout 2025 * devices and SOFT_CARRIER is like CLOCAL except it hides 2026 * the true carrier. 2027 */ 2028#ifdef PC98 2029 if ((IS_8251(com->pc98_if_type) && 2030 (pc98_get_modem_status(com) & TIOCM_CAR)) || 2031 (!IS_8251(com->pc98_if_type) && 2032 (com->prev_modem_status & MSR_DCD)) || 2033 mynor & CALLOUT_MASK) 2034 (*linesw[tp->t_line].l_modem)(tp, 1); 2035#else 2036 if (com->prev_modem_status & MSR_DCD || mynor & CALLOUT_MASK) 2037 (*linesw[tp->t_line].l_modem)(tp, 1); 2038#endif 2039 } 2040 /* 2041 * Wait for DCD if necessary. 2042 */ 2043 if (!(tp->t_state & TS_CARR_ON) && !(mynor & CALLOUT_MASK) 2044 && !(tp->t_cflag & CLOCAL) && !(flag & O_NONBLOCK)) { 2045 ++com->wopeners; 2046 error = tsleep(TSA_CARR_ON(tp), TTIPRI | PCATCH, "siodcd", 0); 2047 if (com_addr(unit) == NULL) 2048 return (ENXIO); 2049 --com->wopeners; 2050 if (error != 0 || com->gone) 2051 goto out; 2052 goto open_top; 2053 } 2054 error = (*linesw[tp->t_line].l_open)(dev, tp); 2055 disc_optim(tp, &tp->t_termios, com); 2056 if (tp->t_state & TS_ISOPEN && mynor & CALLOUT_MASK) 2057 com->active_out = TRUE; 2058 siosettimeout(); 2059out: 2060 splx(s); 2061 if (!(tp->t_state & TS_ISOPEN) && com->wopeners == 0) 2062 comhardclose(com); 2063 return (error); 2064} 2065 2066static int 2067sioclose(dev, flag, mode, td) 2068 dev_t dev; 2069 int flag; 2070 int mode; 2071 struct thread *td; 2072{ 2073 struct com_s *com; 2074 int mynor; 2075 int s; 2076 struct tty *tp; 2077 2078 mynor = minor(dev); 2079 if (mynor & CONTROL_MASK) 2080 return (0); 2081 com = com_addr(MINOR_TO_UNIT(mynor)); 2082 if (com == NULL) 2083 return (ENODEV); 2084 tp = com->tp; 2085 s = spltty(); 2086 (*linesw[tp->t_line].l_close)(tp, flag); 2087#ifdef PC98 2088 com->modem_checking = 0; 2089#endif 2090 disc_optim(tp, &tp->t_termios, com); 2091 comstop(tp, FREAD | FWRITE); 2092 comhardclose(com); 2093 ttyclose(tp); 2094 siosettimeout(); 2095 splx(s); 2096 if (com->gone) { 2097 printf("sio%d: gone\n", com->unit); 2098 s = spltty(); 2099 if (com->ibuf != NULL) 2100 free(com->ibuf, M_DEVBUF); 2101 bzero(tp, sizeof *tp); 2102 splx(s); 2103 } 2104 return (0); 2105} 2106 2107static void 2108comhardclose(com) 2109 struct com_s *com; 2110{ 2111 int s; 2112 struct tty *tp; 2113 int unit; 2114 2115 unit = com->unit; 2116 s = spltty(); 2117 com->poll = FALSE; 2118 com->poll_output = FALSE; 2119 com->do_timestamp = FALSE; 2120 com->do_dcd_timestamp = FALSE; 2121 com->pps.ppsparam.mode = 0; 2122#ifdef PC98 2123 if (IS_8251(com->pc98_if_type)) 2124 com_send_break_off(com); 2125 else 2126#endif 2127 sio_setreg(com, com_cfcr, com->cfcr_image &= ~CFCR_SBREAK); 2128 tp = com->tp; 2129 2130#if defined(DDB) && (defined(BREAK_TO_DEBUGGER) || \ 2131 defined(ALT_BREAK_TO_DEBUGGER)) 2132 /* 2133 * Leave interrupts enabled and don't clear DTR if this is the 2134 * console. This allows us to detect break-to-debugger events 2135 * while the console device is closed. 2136 */ 2137 if (com->unit != comconsole) 2138#endif 2139 { 2140#ifdef PC98 2141 int tmp; 2142 if (IS_8251(com->pc98_if_type)) 2143 com_int_TxRx_disable(com); 2144 else 2145 sio_setreg(com, com_ier, 0); 2146 if (com->pc98_if_type == COM_IF_RSA98III) 2147 outb(com->rsabase + rsa_ier, 0x00); 2148 if (IS_8251(com->pc98_if_type)) 2149 tmp = pc98_get_modem_status(com) & TIOCM_CAR; 2150 else 2151 tmp = com->prev_modem_status & MSR_DCD; 2152#else 2153 sio_setreg(com, com_ier, 0); 2154#endif 2155 if (tp->t_cflag & HUPCL 2156 /* 2157 * XXX we will miss any carrier drop between here and the 2158 * next open. Perhaps we should watch DCD even when the 2159 * port is closed; it is not sufficient to check it at 2160 * the next open because it might go up and down while 2161 * we're not watching. 2162 */ 2163 || (!com->active_out 2164#ifdef PC98 2165 && !(tmp) 2166#else 2167 && !(com->prev_modem_status & MSR_DCD) 2168#endif 2169 && !(com->it_in.c_cflag & CLOCAL)) 2170 || !(tp->t_state & TS_ISOPEN)) { 2171#ifdef PC98 2172 if (IS_8251(com->pc98_if_type)) 2173 com_tiocm_bic(com, TIOCM_DTR|TIOCM_RTS|TIOCM_LE); 2174 else 2175#endif 2176 (void)commctl(com, TIOCM_DTR, DMBIC); 2177 if (com->dtr_wait != 0 && !(com->state & CS_DTR_OFF)) { 2178 timeout(siodtrwakeup, com, com->dtr_wait); 2179 com->state |= CS_DTR_OFF; 2180 } 2181 } 2182#ifdef PC98 2183 else { 2184 if (IS_8251(com->pc98_if_type)) 2185 com_tiocm_bic(com, TIOCM_LE); 2186 } 2187#endif 2188 } 2189#ifdef PC98 2190 if (com->pc98_8251fifo) { 2191 if (com->pc98_8251fifo_enable) 2192 outb(I8251F_fcr, CTRL8251F_XMT_RST | CTRL8251F_RCV_RST); 2193 com->pc98_8251fifo_enable = 0; 2194 } 2195#endif 2196 if (com->hasfifo) { 2197 /* 2198 * Disable fifos so that they are off after controlled 2199 * reboots. Some BIOSes fail to detect 16550s when the 2200 * fifos are enabled. 2201 */ 2202 sio_setreg(com, com_fifo, 0); 2203 } 2204 com->active_out = FALSE; 2205 wakeup(&com->active_out); 2206 wakeup(TSA_CARR_ON(tp)); /* restart any wopeners */ 2207 splx(s); 2208} 2209 2210static int 2211sioread(dev, uio, flag) 2212 dev_t dev; 2213 struct uio *uio; 2214 int flag; 2215{ 2216 int mynor; 2217 struct com_s *com; 2218 2219 mynor = minor(dev); 2220 if (mynor & CONTROL_MASK) 2221 return (ENODEV); 2222 com = com_addr(MINOR_TO_UNIT(mynor)); 2223 if (com == NULL || com->gone) 2224 return (ENODEV); 2225 return ((*linesw[com->tp->t_line].l_read)(com->tp, uio, flag)); 2226} 2227 2228static int 2229siowrite(dev, uio, flag) 2230 dev_t dev; 2231 struct uio *uio; 2232 int flag; 2233{ 2234 int mynor; 2235 struct com_s *com; 2236 int unit; 2237 2238 mynor = minor(dev); 2239 if (mynor & CONTROL_MASK) 2240 return (ENODEV); 2241 2242 unit = MINOR_TO_UNIT(mynor); 2243 com = com_addr(unit); 2244 if (com == NULL || com->gone) 2245 return (ENODEV); 2246 /* 2247 * (XXX) We disallow virtual consoles if the physical console is 2248 * a serial port. This is in case there is a display attached that 2249 * is not the console. In that situation we don't need/want the X 2250 * server taking over the console. 2251 */ 2252 if (constty != NULL && unit == comconsole) 2253 constty = NULL; 2254 return ((*linesw[com->tp->t_line].l_write)(com->tp, uio, flag)); 2255} 2256 2257static void 2258siobusycheck(chan) 2259 void *chan; 2260{ 2261 struct com_s *com; 2262 int s; 2263 2264 com = (struct com_s *)chan; 2265 2266 /* 2267 * Clear TS_BUSY if low-level output is complete. 2268 * spl locking is sufficient because siointr1() does not set CS_BUSY. 2269 * If siointr1() clears CS_BUSY after we look at it, then we'll get 2270 * called again. Reading the line status port outside of siointr1() 2271 * is safe because CS_BUSY is clear so there are no output interrupts 2272 * to lose. 2273 */ 2274 s = spltty(); 2275 if (com->state & CS_BUSY) 2276 com->extra_state &= ~CSE_BUSYCHECK; /* False alarm. */ 2277#ifdef PC98 2278 else if ((IS_8251(com->pc98_if_type) && 2279 ((com->pc98_8251fifo_enable && 2280 (inb(I8251F_lsr) & (STS8251F_TxRDY | STS8251F_TxEMP)) 2281 == (STS8251F_TxRDY | STS8251F_TxEMP)) || 2282 (!com->pc98_8251fifo_enable && 2283 (inb(com->sts_port) & (STS8251_TxRDY | STS8251_TxEMP)) 2284 == (STS8251_TxRDY | STS8251_TxEMP)))) || 2285 ((inb(com->line_status_port) & (LSR_TSRE | LSR_TXRDY)) 2286 == (LSR_TSRE | LSR_TXRDY))) { 2287#else 2288 else if ((inb(com->line_status_port) & (LSR_TSRE | LSR_TXRDY)) 2289 == (LSR_TSRE | LSR_TXRDY)) { 2290#endif 2291 com->tp->t_state &= ~TS_BUSY; 2292 ttwwakeup(com->tp); 2293 com->extra_state &= ~CSE_BUSYCHECK; 2294 } else 2295 timeout(siobusycheck, com, hz / 100); 2296 splx(s); 2297} 2298 2299static u_int 2300siodivisor(rclk, speed) 2301 u_long rclk; 2302 speed_t speed; 2303{ 2304 long actual_speed; 2305 u_int divisor; 2306 int error; 2307 2308 if (speed == 0 || speed > (ULONG_MAX - 1) / 8) 2309 return (0); 2310 divisor = (rclk / (8UL * speed) + 1) / 2; 2311 if (divisor == 0 || divisor >= 65536) 2312 return (0); 2313 actual_speed = rclk / (16UL * divisor); 2314 2315 /* 10 times error in percent: */ 2316 error = ((actual_speed - (long)speed) * 2000 / (long)speed + 1) / 2; 2317 2318 /* 3.0% maximum error tolerance: */ 2319 if (error < -30 || error > 30) 2320 return (0); 2321 2322 return (divisor); 2323} 2324 2325static void 2326siodtrwakeup(chan) 2327 void *chan; 2328{ 2329 struct com_s *com; 2330 2331 com = (struct com_s *)chan; 2332 com->state &= ~CS_DTR_OFF; 2333 wakeup(&com->dtr_wait); 2334} 2335 2336/* 2337 * Call this function with the sio_lock mutex held. It will return with the 2338 * lock still held. 2339 */ 2340static void 2341sioinput(com) 2342 struct com_s *com; 2343{ 2344 u_char *buf; 2345 int incc; 2346 u_char line_status; 2347 int recv_data; 2348 struct tty *tp; 2349 2350 buf = com->ibuf; 2351 tp = com->tp; 2352 if (!(tp->t_state & TS_ISOPEN) || !(tp->t_cflag & CREAD)) { 2353 com_events -= (com->iptr - com->ibuf); 2354 com->iptr = com->ibuf; 2355 return; 2356 } 2357 if (tp->t_state & TS_CAN_BYPASS_L_RINT) { 2358 /* 2359 * Avoid the grotesquely inefficient lineswitch routine 2360 * (ttyinput) in "raw" mode. It usually takes about 450 2361 * instructions (that's without canonical processing or echo!). 2362 * slinput is reasonably fast (usually 40 instructions plus 2363 * call overhead). 2364 */ 2365 do { 2366 /* 2367 * This may look odd, but it is using save-and-enable 2368 * semantics instead of the save-and-disable semantics 2369 * that are used everywhere else. 2370 */ 2371 mtx_unlock_spin(&sio_lock); 2372 incc = com->iptr - buf; 2373 if (tp->t_rawq.c_cc + incc > tp->t_ihiwat 2374 && (com->state & CS_RTS_IFLOW 2375 || tp->t_iflag & IXOFF) 2376 && !(tp->t_state & TS_TBLOCK)) 2377 ttyblock(tp); 2378 com->delta_error_counts[CE_TTY_BUF_OVERFLOW] 2379 += b_to_q((char *)buf, incc, &tp->t_rawq); 2380 buf += incc; 2381 tk_nin += incc; 2382 tk_rawcc += incc; 2383 tp->t_rawcc += incc; 2384 ttwakeup(tp); 2385 if (tp->t_state & TS_TTSTOP 2386 && (tp->t_iflag & IXANY 2387 || tp->t_cc[VSTART] == tp->t_cc[VSTOP])) { 2388 tp->t_state &= ~TS_TTSTOP; 2389 tp->t_lflag &= ~FLUSHO; 2390 comstart(tp); 2391 } 2392 mtx_lock_spin(&sio_lock); 2393 } while (buf < com->iptr); 2394 } else { 2395 do { 2396 /* 2397 * This may look odd, but it is using save-and-enable 2398 * semantics instead of the save-and-disable semantics 2399 * that are used everywhere else. 2400 */ 2401 mtx_unlock_spin(&sio_lock); 2402 line_status = buf[com->ierroff]; 2403 recv_data = *buf++; 2404 if (line_status 2405 & (LSR_BI | LSR_FE | LSR_OE | LSR_PE)) { 2406 if (line_status & LSR_BI) 2407 recv_data |= TTY_BI; 2408 if (line_status & LSR_FE) 2409 recv_data |= TTY_FE; 2410 if (line_status & LSR_OE) 2411 recv_data |= TTY_OE; 2412 if (line_status & LSR_PE) 2413 recv_data |= TTY_PE; 2414 } 2415 (*linesw[tp->t_line].l_rint)(recv_data, tp); 2416 mtx_lock_spin(&sio_lock); 2417 } while (buf < com->iptr); 2418 } 2419 com_events -= (com->iptr - com->ibuf); 2420 com->iptr = com->ibuf; 2421 2422 /* 2423 * There is now room for another low-level buffer full of input, 2424 * so enable RTS if it is now disabled and there is room in the 2425 * high-level buffer. 2426 */ 2427#ifdef PC98 2428 if (IS_8251(com->pc98_if_type)) { 2429 if ((com->state & CS_RTS_IFLOW) && 2430 !(com_tiocm_get(com) & TIOCM_RTS) && 2431 !(tp->t_state & TS_TBLOCK)) 2432 com_tiocm_bis(com, TIOCM_RTS); 2433 } else { 2434 if ((com->state & CS_RTS_IFLOW) && 2435 !(com->mcr_image & MCR_RTS) && 2436 !(tp->t_state & TS_TBLOCK)) 2437 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS); 2438 } 2439#else 2440 if ((com->state & CS_RTS_IFLOW) && !(com->mcr_image & MCR_RTS) && 2441 !(tp->t_state & TS_TBLOCK)) 2442 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS); 2443#endif 2444} 2445 2446void 2447siointr(arg) 2448 void *arg; 2449{ 2450 struct com_s *com; 2451#ifdef PC98 2452 u_char rsa_buf_status; 2453#endif 2454 2455#ifndef COM_MULTIPORT 2456 com = (struct com_s *)arg; 2457 2458 mtx_lock_spin(&sio_lock); 2459 siointr1(com); 2460 mtx_unlock_spin(&sio_lock); 2461#else /* COM_MULTIPORT */ 2462 bool_t possibly_more_intrs; 2463 int unit; 2464 2465 /* 2466 * Loop until there is no activity on any port. This is necessary 2467 * to get an interrupt edge more than to avoid another interrupt. 2468 * If the IRQ signal is just an OR of the IRQ signals from several 2469 * devices, then the edge from one may be lost because another is 2470 * on. 2471 */ 2472 mtx_lock_spin(&sio_lock); 2473 do { 2474 possibly_more_intrs = FALSE; 2475 for (unit = 0; unit < sio_numunits; ++unit) { 2476 com = com_addr(unit); 2477 /* 2478 * XXX COM_LOCK(); 2479 * would it work here, or be counter-productive? 2480 */ 2481#ifdef PC98 2482 if (com != NULL 2483 && !com->gone 2484 && IS_8251(com->pc98_if_type)) { 2485 siointr1(com); 2486 } else if (com != NULL 2487 && !com->gone 2488 && com->pc98_if_type == COM_IF_RSA98III) { 2489 rsa_buf_status = 2490 inb(com->rsabase + rsa_srr) & 0xc9; 2491 if ((rsa_buf_status & 0xc8) 2492 || !(rsa_buf_status & 0x01)) { 2493 siointr1(com); 2494 if (rsa_buf_status != 2495 (inb(com->rsabase + rsa_srr) & 0xc9)) 2496 possibly_more_intrs = TRUE; 2497 } 2498 } else 2499#endif 2500 if (com != NULL 2501 && !com->gone 2502 && (inb(com->int_id_port) & IIR_IMASK) 2503 != IIR_NOPEND) { 2504 siointr1(com); 2505 possibly_more_intrs = TRUE; 2506 } 2507 /* XXX COM_UNLOCK(); */ 2508 } 2509 } while (possibly_more_intrs); 2510 mtx_unlock_spin(&sio_lock); 2511#endif /* COM_MULTIPORT */ 2512} 2513 2514static void 2515siointr1(com) 2516 struct com_s *com; 2517{ 2518 u_char line_status; 2519 u_char modem_status; 2520 u_char *ioptr; 2521 u_char recv_data; 2522 u_char int_ctl; 2523 u_char int_ctl_new; 2524 struct timecounter *tc; 2525 u_int count; 2526 2527#ifdef PC98 2528 u_char tmp = 0; 2529 u_char rsa_buf_status = 0; 2530 int rsa_tx_fifo_size = 0; 2531#endif /* PC98 */ 2532 2533 int_ctl = inb(com->intr_ctl_port); 2534 int_ctl_new = int_ctl; 2535 2536 while (!com->gone) { 2537#ifdef PC98 2538status_read:; 2539 if (IS_8251(com->pc98_if_type)) { 2540 if (com->pc98_8251fifo_enable) 2541 tmp = inb(I8251F_lsr); 2542 else 2543 tmp = inb(com->sts_port); 2544more_intr: 2545 line_status = 0; 2546 if (com->pc98_8251fifo_enable) { 2547 if (tmp & STS8251F_TxRDY) line_status |= LSR_TXRDY; 2548 if (tmp & STS8251F_RxRDY) line_status |= LSR_RXRDY; 2549 if (tmp & STS8251F_TxEMP) line_status |= LSR_TSRE; 2550 if (tmp & STS8251F_PE) line_status |= LSR_PE; 2551 if (tmp & STS8251F_OE) line_status |= LSR_OE; 2552 if (tmp & STS8251F_BD_SD) line_status |= LSR_BI; 2553 } else { 2554 if (tmp & STS8251_TxRDY) line_status |= LSR_TXRDY; 2555 if (tmp & STS8251_RxRDY) line_status |= LSR_RXRDY; 2556 if (tmp & STS8251_TxEMP) line_status |= LSR_TSRE; 2557 if (tmp & STS8251_PE) line_status |= LSR_PE; 2558 if (tmp & STS8251_OE) line_status |= LSR_OE; 2559 if (tmp & STS8251_FE) line_status |= LSR_FE; 2560 if (tmp & STS8251_BD_SD) line_status |= LSR_BI; 2561 } 2562 } else { 2563#endif /* PC98 */ 2564 if (com->pps.ppsparam.mode & PPS_CAPTUREBOTH) { 2565 modem_status = inb(com->modem_status_port); 2566 if ((modem_status ^ com->last_modem_status) & MSR_DCD) { 2567 tc = timecounter; 2568 count = tc->tc_get_timecount(tc); 2569 pps_event(&com->pps, tc, count, 2570 (modem_status & MSR_DCD) ? 2571 PPS_CAPTUREASSERT : PPS_CAPTURECLEAR); 2572 } 2573 } 2574 line_status = inb(com->line_status_port); 2575#ifdef PC98 2576 } 2577 if (com->pc98_if_type == COM_IF_RSA98III) 2578 rsa_buf_status = inb(com->rsabase + rsa_srr); 2579#endif /* PC98 */ 2580 2581 /* input event? (check first to help avoid overruns) */ 2582#ifndef PC98 2583 while (line_status & LSR_RCV_MASK) { 2584#else 2585 while ((line_status & LSR_RCV_MASK) 2586 || (com->pc98_if_type == COM_IF_RSA98III 2587 && (rsa_buf_status & 0x08))) { 2588#endif /* PC98 */ 2589 /* break/unnattached error bits or real input? */ 2590#ifdef PC98 2591 if (IS_8251(com->pc98_if_type)) { 2592 if (com->pc98_8251fifo_enable) { 2593 recv_data = inb(I8251F_data); 2594 if (tmp & (STS8251F_PE | STS8251F_OE | 2595 STS8251F_BD_SD)) { 2596 pc98_i8251_or_cmd(com, CMD8251_ER); 2597 recv_data = 0; 2598 } 2599 } else { 2600 recv_data = inb(com->data_port); 2601 if (tmp & (STS8251_PE | STS8251_OE | 2602 STS8251_FE | STS8251_BD_SD)) { 2603 pc98_i8251_or_cmd(com, CMD8251_ER); 2604 recv_data = 0; 2605 } 2606 } 2607 } else if (com->pc98_if_type == COM_IF_RSA98III) { 2608 if (!(rsa_buf_status & 0x08)) 2609 recv_data = 0; 2610 else 2611 recv_data = inb(com->data_port); 2612 } else 2613#endif 2614 if (!(line_status & LSR_RXRDY)) 2615 recv_data = 0; 2616 else 2617 recv_data = inb(com->data_port); 2618#if defined(DDB) && defined(ALT_BREAK_TO_DEBUGGER) 2619 /* 2620 * Solaris implements a new BREAK which is initiated 2621 * by a character sequence CR ~ ^b which is similar 2622 * to a familiar pattern used on Sun servers by the 2623 * Remote Console. 2624 */ 2625#define KEY_CRTLB 2 /* ^B */ 2626#define KEY_CR 13 /* CR '\r' */ 2627#define KEY_TILDE 126 /* ~ */ 2628 2629 if (com->unit == comconsole) { 2630 static int brk_state1 = 0, brk_state2 = 0; 2631 if (recv_data == KEY_CR) { 2632 brk_state1 = recv_data; 2633 brk_state2 = 0; 2634 } else if (brk_state1 == KEY_CR && (recv_data == KEY_TILDE || recv_data == KEY_CRTLB)) { 2635 if (recv_data == KEY_TILDE) 2636 brk_state2 = recv_data; 2637 else if (brk_state2 == KEY_TILDE && recv_data == KEY_CRTLB) { 2638 breakpoint(); 2639 brk_state1 = brk_state2 = 0; 2640 goto cont; 2641 } else 2642 brk_state2 = 0; 2643 } else 2644 brk_state1 = 0; 2645 } 2646#endif 2647 if (line_status & (LSR_BI | LSR_FE | LSR_PE)) { 2648 /* 2649 * Don't store BI if IGNBRK or FE/PE if IGNPAR. 2650 * Otherwise, push the work to a higher level 2651 * (to handle PARMRK) if we're bypassing. 2652 * Otherwise, convert BI/FE and PE+INPCK to 0. 2653 * 2654 * This makes bypassing work right in the 2655 * usual "raw" case (IGNBRK set, and IGNPAR 2656 * and INPCK clear). 2657 * 2658 * Note: BI together with FE/PE means just BI. 2659 */ 2660 if (line_status & LSR_BI) { 2661#if defined(DDB) && defined(BREAK_TO_DEBUGGER) 2662 if (com->unit == comconsole) { 2663 breakpoint(); 2664 goto cont; 2665 } 2666#endif 2667 if (com->tp == NULL 2668 || com->tp->t_iflag & IGNBRK) 2669 goto cont; 2670 } else { 2671 if (com->tp == NULL 2672 || com->tp->t_iflag & IGNPAR) 2673 goto cont; 2674 } 2675 if (com->tp->t_state & TS_CAN_BYPASS_L_RINT 2676 && (line_status & (LSR_BI | LSR_FE) 2677 || com->tp->t_iflag & INPCK)) 2678 recv_data = 0; 2679 } 2680 ++com->bytes_in; 2681 if (com->hotchar != 0 && recv_data == com->hotchar) 2682 swi_sched(sio_fast_ih, 0); 2683 ioptr = com->iptr; 2684 if (ioptr >= com->ibufend) 2685 CE_RECORD(com, CE_INTERRUPT_BUF_OVERFLOW); 2686 else { 2687 if (com->do_timestamp) 2688 microtime(&com->timestamp); 2689 ++com_events; 2690 swi_sched(sio_slow_ih, SWI_DELAY); 2691#if 0 /* for testing input latency vs efficiency */ 2692if (com->iptr - com->ibuf == 8) 2693 swi_sched(sio_fast_ih, 0); 2694#endif 2695 ioptr[0] = recv_data; 2696 ioptr[com->ierroff] = line_status; 2697 com->iptr = ++ioptr; 2698 if (ioptr == com->ihighwater 2699 && com->state & CS_RTS_IFLOW) 2700#ifdef PC98 2701 IS_8251(com->pc98_if_type) ? 2702 com_tiocm_bic(com, TIOCM_RTS) : 2703#endif 2704 outb(com->modem_ctl_port, 2705 com->mcr_image &= ~MCR_RTS); 2706 if (line_status & LSR_OE) 2707 CE_RECORD(com, CE_OVERRUN); 2708 } 2709cont: 2710 /* 2711 * "& 0x7F" is to avoid the gcc-1.40 generating a slow 2712 * jump from the top of the loop to here 2713 */ 2714#ifdef PC98 2715 if (IS_8251(com->pc98_if_type)) 2716 goto status_read; 2717 else 2718#endif 2719 line_status = inb(com->line_status_port) & 0x7F; 2720#ifdef PC98 2721 if (com->pc98_if_type == COM_IF_RSA98III) 2722 rsa_buf_status = inb(com->rsabase + rsa_srr); 2723#endif /* PC98 */ 2724 } 2725 2726 /* modem status change? (always check before doing output) */ 2727#ifdef PC98 2728 if (!IS_8251(com->pc98_if_type)) { 2729#endif 2730 modem_status = inb(com->modem_status_port); 2731 if (modem_status != com->last_modem_status) { 2732 if (com->do_dcd_timestamp 2733 && !(com->last_modem_status & MSR_DCD) 2734 && modem_status & MSR_DCD) 2735 microtime(&com->dcd_timestamp); 2736 2737 /* 2738 * Schedule high level to handle DCD changes. Note 2739 * that we don't use the delta bits anywhere. Some 2740 * UARTs mess them up, and it's easy to remember the 2741 * previous bits and calculate the delta. 2742 */ 2743 com->last_modem_status = modem_status; 2744 if (!(com->state & CS_CHECKMSR)) { 2745 com_events += LOTS_OF_EVENTS; 2746 com->state |= CS_CHECKMSR; 2747 swi_sched(sio_fast_ih, 0); 2748 } 2749 2750 /* handle CTS change immediately for crisp flow ctl */ 2751 if (com->state & CS_CTS_OFLOW) { 2752 if (modem_status & MSR_CTS) 2753 com->state |= CS_ODEVREADY; 2754 else 2755 com->state &= ~CS_ODEVREADY; 2756 } 2757 } 2758#ifdef PC98 2759 } 2760#endif 2761 2762 /* output queued and everything ready? */ 2763#ifndef PC98 2764 if (line_status & LSR_TXRDY 2765 && com->state >= (CS_BUSY | CS_TTGO | CS_ODEVREADY)) { 2766#else 2767 if (((com->pc98_if_type == COM_IF_RSA98III) 2768 ? (rsa_buf_status & 0x02) 2769 : (line_status & LSR_TXRDY)) 2770 && com->state >= (CS_BUSY | CS_TTGO | CS_ODEVREADY)) { 2771#endif 2772#ifdef PC98 2773 Port_t tmp_data_port; 2774 2775 if (IS_8251(com->pc98_if_type) && 2776 com->pc98_8251fifo_enable) 2777 tmp_data_port = I8251F_data; 2778 else 2779 tmp_data_port = com->data_port; 2780#endif 2781 2782 ioptr = com->obufq.l_head; 2783 if (com->tx_fifo_size > 1) { 2784 u_int ocount; 2785 2786 ocount = com->obufq.l_tail - ioptr; 2787#ifdef PC98 2788 if (com->pc98_if_type == COM_IF_RSA98III) { 2789 rsa_buf_status = inb(com->rsabase + rsa_srr); 2790 rsa_tx_fifo_size = 1024; 2791 if (!(rsa_buf_status & 0x01)) 2792 rsa_tx_fifo_size = 2048; 2793 if (ocount > rsa_tx_fifo_size) 2794 ocount = rsa_tx_fifo_size; 2795 } else 2796#endif 2797 if (ocount > com->tx_fifo_size) 2798 ocount = com->tx_fifo_size; 2799 com->bytes_out += ocount; 2800 do 2801#ifdef PC98 2802 outb(tmp_data_port, *ioptr++); 2803#else 2804 outb(com->data_port, *ioptr++); 2805#endif 2806 while (--ocount != 0); 2807 } else { 2808#ifdef PC98 2809 outb(tmp_data_port, *ioptr++); 2810#else 2811 outb(com->data_port, *ioptr++); 2812#endif 2813 ++com->bytes_out; 2814 } 2815#ifdef PC98 2816 if (IS_8251(com->pc98_if_type)) 2817 if (!(pc98_check_i8251_interrupt(com) & IEN_TxFLAG)) 2818 com_int_Tx_enable(com); 2819#endif 2820 com->obufq.l_head = ioptr; 2821 if (COM_IIR_TXRDYBUG(com->flags)) { 2822 int_ctl_new = int_ctl | IER_ETXRDY; 2823 } 2824 if (ioptr >= com->obufq.l_tail) { 2825 struct lbq *qp; 2826 2827 qp = com->obufq.l_next; 2828 qp->l_queued = FALSE; 2829 qp = qp->l_next; 2830 if (qp != NULL) { 2831 com->obufq.l_head = qp->l_head; 2832 com->obufq.l_tail = qp->l_tail; 2833 com->obufq.l_next = qp; 2834 } else { 2835 /* output just completed */ 2836 if (COM_IIR_TXRDYBUG(com->flags)) { 2837 int_ctl_new = int_ctl & ~IER_ETXRDY; 2838 } 2839 com->state &= ~CS_BUSY; 2840#if defined(PC98) 2841 if (IS_8251(com->pc98_if_type) && 2842 pc98_check_i8251_interrupt(com) & IEN_TxFLAG) 2843 com_int_Tx_disable(com); 2844#endif 2845 } 2846 if (!(com->state & CS_ODONE)) { 2847 com_events += LOTS_OF_EVENTS; 2848 com->state |= CS_ODONE; 2849 /* handle at high level ASAP */ 2850 swi_sched(sio_fast_ih, 0); 2851 } 2852 } 2853 if (COM_IIR_TXRDYBUG(com->flags) && (int_ctl != int_ctl_new)) { 2854#ifdef PC98 2855 if (com->pc98_if_type == COM_IF_RSA98III) { 2856 int_ctl_new &= ~(IER_ETXRDY | IER_ERXRDY); 2857 outb(com->intr_ctl_port, int_ctl_new); 2858 outb(com->rsabase + rsa_ier, 0x1d); 2859 } else 2860#endif 2861 outb(com->intr_ctl_port, int_ctl_new); 2862 } 2863 } 2864#ifdef PC98 2865 else if (line_status & LSR_TXRDY) { 2866 if (IS_8251(com->pc98_if_type)) 2867 if (pc98_check_i8251_interrupt(com) & IEN_TxFLAG) 2868 com_int_Tx_disable(com); 2869 } 2870 if (IS_8251(com->pc98_if_type)) { 2871 if (com->pc98_8251fifo_enable) { 2872 if ((tmp = inb(I8251F_lsr)) & STS8251F_RxRDY) 2873 goto more_intr; 2874 } else { 2875 if ((tmp = inb(com->sts_port)) & STS8251_RxRDY) 2876 goto more_intr; 2877 } 2878 } 2879#endif 2880 2881 /* finished? */ 2882#ifndef COM_MULTIPORT 2883#ifdef PC98 2884 if (IS_8251(com->pc98_if_type)) 2885 return; 2886#endif 2887 if ((inb(com->int_id_port) & IIR_IMASK) == IIR_NOPEND) 2888#endif /* COM_MULTIPORT */ 2889 return; 2890 } 2891} 2892 2893static int 2894sioioctl(dev, cmd, data, flag, td) 2895 dev_t dev; 2896 u_long cmd; 2897 caddr_t data; 2898 int flag; 2899 struct thread *td; 2900{ 2901 struct com_s *com; 2902 int error; 2903 int mynor; 2904 int s; 2905 struct tty *tp; 2906#if defined(COMPAT_43) || defined(COMPAT_SUNOS) 2907 u_long oldcmd; 2908 struct termios term; 2909#endif 2910 2911 mynor = minor(dev); 2912 com = com_addr(MINOR_TO_UNIT(mynor)); 2913 if (com == NULL || com->gone) 2914 return (ENODEV); 2915 if (mynor & CONTROL_MASK) { 2916 struct termios *ct; 2917 2918 switch (mynor & CONTROL_MASK) { 2919 case CONTROL_INIT_STATE: 2920 ct = mynor & CALLOUT_MASK ? &com->it_out : &com->it_in; 2921 break; 2922 case CONTROL_LOCK_STATE: 2923 ct = mynor & CALLOUT_MASK ? &com->lt_out : &com->lt_in; 2924 break; 2925 default: 2926 return (ENODEV); /* /dev/nodev */ 2927 } 2928 switch (cmd) { 2929 case TIOCSETA: 2930 error = suser_td(td); 2931 if (error != 0) 2932 return (error); 2933 *ct = *(struct termios *)data; 2934 return (0); 2935 case TIOCGETA: 2936 *(struct termios *)data = *ct; 2937 return (0); 2938 case TIOCGETD: 2939 *(int *)data = TTYDISC; 2940 return (0); 2941 case TIOCGWINSZ: 2942 bzero(data, sizeof(struct winsize)); 2943 return (0); 2944 default: 2945 return (ENOTTY); 2946 } 2947 } 2948 tp = com->tp; 2949#if defined(COMPAT_43) || defined(COMPAT_SUNOS) 2950 term = tp->t_termios; 2951 oldcmd = cmd; 2952 error = ttsetcompat(tp, &cmd, data, &term); 2953 if (error != 0) 2954 return (error); 2955 if (cmd != oldcmd) 2956 data = (caddr_t)&term; 2957#endif 2958 if (cmd == TIOCSETA || cmd == TIOCSETAW || cmd == TIOCSETAF) { 2959 int cc; 2960 struct termios *dt = (struct termios *)data; 2961 struct termios *lt = mynor & CALLOUT_MASK 2962 ? &com->lt_out : &com->lt_in; 2963 2964 dt->c_iflag = (tp->t_iflag & lt->c_iflag) 2965 | (dt->c_iflag & ~lt->c_iflag); 2966 dt->c_oflag = (tp->t_oflag & lt->c_oflag) 2967 | (dt->c_oflag & ~lt->c_oflag); 2968 dt->c_cflag = (tp->t_cflag & lt->c_cflag) 2969 | (dt->c_cflag & ~lt->c_cflag); 2970 dt->c_lflag = (tp->t_lflag & lt->c_lflag) 2971 | (dt->c_lflag & ~lt->c_lflag); 2972 for (cc = 0; cc < NCCS; ++cc) 2973 if (lt->c_cc[cc] != 0) 2974 dt->c_cc[cc] = tp->t_cc[cc]; 2975 if (lt->c_ispeed != 0) 2976 dt->c_ispeed = tp->t_ispeed; 2977 if (lt->c_ospeed != 0) 2978 dt->c_ospeed = tp->t_ospeed; 2979 } 2980 error = (*linesw[tp->t_line].l_ioctl)(tp, cmd, data, flag, td); 2981 if (error != ENOIOCTL) 2982 return (error); 2983 s = spltty(); 2984 error = ttioctl(tp, cmd, data, flag); 2985 disc_optim(tp, &tp->t_termios, com); 2986 if (error != ENOIOCTL) { 2987 splx(s); 2988 return (error); 2989 } 2990#ifdef PC98 2991 if (IS_8251(com->pc98_if_type)) { 2992 switch (cmd) { 2993 case TIOCSBRK: 2994 com_send_break_on(com); 2995 break; 2996 case TIOCCBRK: 2997 com_send_break_off(com); 2998 break; 2999 case TIOCSDTR: 3000 com_tiocm_bis(com, TIOCM_DTR | TIOCM_RTS); 3001 break; 3002 case TIOCCDTR: 3003 com_tiocm_bic(com, TIOCM_DTR); 3004 break; 3005 /* 3006 * XXX should disallow changing MCR_RTS if CS_RTS_IFLOW is set. The 3007 * changes get undone on the next call to comparam(). 3008 */ 3009 case TIOCMSET: 3010 com_tiocm_set(com, *(int *)data); 3011 break; 3012 case TIOCMBIS: 3013 com_tiocm_bis(com, *(int *)data); 3014 break; 3015 case TIOCMBIC: 3016 com_tiocm_bic(com, *(int *)data); 3017 break; 3018 case TIOCMGET: 3019 *(int *)data = com_tiocm_get(com); 3020 break; 3021 case TIOCMSDTRWAIT: 3022 /* must be root since the wait applies to following logins */ 3023 error = suser_td(td); 3024 if (error != 0) { 3025 splx(s); 3026 return (error); 3027 } 3028 com->dtr_wait = *(int *)data * hz / 100; 3029 break; 3030 case TIOCMGDTRWAIT: 3031 *(int *)data = com->dtr_wait * 100 / hz; 3032 break; 3033 case TIOCTIMESTAMP: 3034 com->do_timestamp = TRUE; 3035 *(struct timeval *)data = com->timestamp; 3036 break; 3037 case TIOCDCDTIMESTAMP: 3038 com->do_dcd_timestamp = TRUE; 3039 *(struct timeval *)data = com->dcd_timestamp; 3040 break; 3041 default: 3042 splx(s); 3043 error = pps_ioctl(cmd, data, &com->pps); 3044 if (error == ENODEV) 3045 error = ENOTTY; 3046 return (error); 3047 } 3048 } else { 3049#endif 3050 switch (cmd) { 3051 case TIOCSBRK: 3052 sio_setreg(com, com_cfcr, com->cfcr_image |= CFCR_SBREAK); 3053 break; 3054 case TIOCCBRK: 3055 sio_setreg(com, com_cfcr, com->cfcr_image &= ~CFCR_SBREAK); 3056 break; 3057 case TIOCSDTR: 3058 (void)commctl(com, TIOCM_DTR, DMBIS); 3059 break; 3060 case TIOCCDTR: 3061 (void)commctl(com, TIOCM_DTR, DMBIC); 3062 break; 3063 /* 3064 * XXX should disallow changing MCR_RTS if CS_RTS_IFLOW is set. The 3065 * changes get undone on the next call to comparam(). 3066 */ 3067 case TIOCMSET: 3068 (void)commctl(com, *(int *)data, DMSET); 3069 break; 3070 case TIOCMBIS: 3071 (void)commctl(com, *(int *)data, DMBIS); 3072 break; 3073 case TIOCMBIC: 3074 (void)commctl(com, *(int *)data, DMBIC); 3075 break; 3076 case TIOCMGET: 3077 *(int *)data = commctl(com, 0, DMGET); 3078 break; 3079 case TIOCMSDTRWAIT: 3080 /* must be root since the wait applies to following logins */ 3081 error = suser_td(td); 3082 if (error != 0) { 3083 splx(s); 3084 return (error); 3085 } 3086 com->dtr_wait = *(int *)data * hz / 100; 3087 break; 3088 case TIOCMGDTRWAIT: 3089 *(int *)data = com->dtr_wait * 100 / hz; 3090 break; 3091 case TIOCTIMESTAMP: 3092 com->do_timestamp = TRUE; 3093 *(struct timeval *)data = com->timestamp; 3094 break; 3095 case TIOCDCDTIMESTAMP: 3096 com->do_dcd_timestamp = TRUE; 3097 *(struct timeval *)data = com->dcd_timestamp; 3098 break; 3099 default: 3100 splx(s); 3101 error = pps_ioctl(cmd, data, &com->pps); 3102 if (error == ENODEV) 3103 error = ENOTTY; 3104 return (error); 3105 } 3106#ifdef PC98 3107 } 3108#endif 3109 splx(s); 3110 return (0); 3111} 3112 3113/* software interrupt handler for SWI_TTY */ 3114static void 3115siopoll(void *dummy) 3116{ 3117 int unit; 3118 3119 if (com_events == 0) 3120 return; 3121repeat: 3122 for (unit = 0; unit < sio_numunits; ++unit) { 3123 struct com_s *com; 3124 int incc; 3125 struct tty *tp; 3126 3127 com = com_addr(unit); 3128 if (com == NULL) 3129 continue; 3130 tp = com->tp; 3131 if (tp == NULL || com->gone) { 3132 /* 3133 * Discard any events related to never-opened or 3134 * going-away devices. 3135 */ 3136 mtx_lock_spin(&sio_lock); 3137 incc = com->iptr - com->ibuf; 3138 com->iptr = com->ibuf; 3139 if (com->state & CS_CHECKMSR) { 3140 incc += LOTS_OF_EVENTS; 3141 com->state &= ~CS_CHECKMSR; 3142 } 3143 com_events -= incc; 3144 mtx_unlock_spin(&sio_lock); 3145 continue; 3146 } 3147 if (com->iptr != com->ibuf) { 3148 mtx_lock_spin(&sio_lock); 3149 sioinput(com); 3150 mtx_unlock_spin(&sio_lock); 3151 } 3152 if (com->state & CS_CHECKMSR) { 3153 u_char delta_modem_status; 3154 3155#ifdef PC98 3156 if (!IS_8251(com->pc98_if_type)) { 3157#endif 3158 mtx_lock_spin(&sio_lock); 3159 delta_modem_status = com->last_modem_status 3160 ^ com->prev_modem_status; 3161 com->prev_modem_status = com->last_modem_status; 3162 com_events -= LOTS_OF_EVENTS; 3163 com->state &= ~CS_CHECKMSR; 3164 mtx_unlock_spin(&sio_lock); 3165 if (delta_modem_status & MSR_DCD) 3166 (*linesw[tp->t_line].l_modem) 3167 (tp, com->prev_modem_status & MSR_DCD); 3168#ifdef PC98 3169 } 3170#endif 3171 } 3172 if (com->state & CS_ODONE) { 3173 mtx_lock_spin(&sio_lock); 3174 com_events -= LOTS_OF_EVENTS; 3175 com->state &= ~CS_ODONE; 3176 mtx_unlock_spin(&sio_lock); 3177 if (!(com->state & CS_BUSY) 3178 && !(com->extra_state & CSE_BUSYCHECK)) { 3179 timeout(siobusycheck, com, hz / 100); 3180 com->extra_state |= CSE_BUSYCHECK; 3181 } 3182 (*linesw[tp->t_line].l_start)(tp); 3183 } 3184 if (com_events == 0) 3185 break; 3186 } 3187 if (com_events >= LOTS_OF_EVENTS) 3188 goto repeat; 3189} 3190 3191static int 3192comparam(tp, t) 3193 struct tty *tp; 3194 struct termios *t; 3195{ 3196 u_int cfcr; 3197 int cflag; 3198 struct com_s *com; 3199 u_int divisor; 3200 u_char dlbh; 3201 u_char dlbl; 3202 int s; 3203 int unit; 3204#ifdef PC98 3205 u_char param = 0; 3206#endif 3207 3208 unit = DEV_TO_UNIT(tp->t_dev); 3209 com = com_addr(unit); 3210 if (com == NULL) 3211 return (ENODEV); 3212 3213#ifdef PC98 3214 cfcr = 0; 3215 3216 if (IS_8251(com->pc98_if_type)) { 3217 if (pc98_ttspeedtab(com, t->c_ospeed, &divisor) != 0) 3218 return (EINVAL); 3219 } else { 3220#endif 3221 /* do historical conversions */ 3222 if (t->c_ispeed == 0) 3223 t->c_ispeed = t->c_ospeed; 3224 3225 /* check requested parameters */ 3226 if (t->c_ospeed == 0) 3227 divisor = 0; 3228 else { 3229 if (t->c_ispeed != t->c_ospeed) 3230 return (EINVAL); 3231 divisor = siodivisor(com->rclk, t->c_ispeed); 3232 if (divisor == 0) 3233 return (EINVAL); 3234 } 3235#ifdef PC98 3236 } 3237#endif 3238 3239 /* parameters are OK, convert them to the com struct and the device */ 3240 s = spltty(); 3241#ifdef PC98 3242 if (IS_8251(com->pc98_if_type)) { 3243 if (divisor == 0) 3244 com_tiocm_bic(com, TIOCM_DTR|TIOCM_RTS|TIOCM_LE); 3245 else 3246 com_tiocm_bis(com, TIOCM_DTR|TIOCM_RTS|TIOCM_LE); 3247 } else 3248#endif 3249 if (divisor == 0) 3250 (void)commctl(com, TIOCM_DTR, DMBIC); /* hang up line */ 3251 else 3252 (void)commctl(com, TIOCM_DTR, DMBIS); 3253 cflag = t->c_cflag; 3254#ifdef PC98 3255 if (!IS_8251(com->pc98_if_type)) { 3256#endif 3257 switch (cflag & CSIZE) { 3258 case CS5: 3259 cfcr = CFCR_5BITS; 3260 break; 3261 case CS6: 3262 cfcr = CFCR_6BITS; 3263 break; 3264 case CS7: 3265 cfcr = CFCR_7BITS; 3266 break; 3267 default: 3268 cfcr = CFCR_8BITS; 3269 break; 3270 } 3271 if (cflag & PARENB) { 3272 cfcr |= CFCR_PENAB; 3273 if (!(cflag & PARODD)) 3274 cfcr |= CFCR_PEVEN; 3275 } 3276 if (cflag & CSTOPB) 3277 cfcr |= CFCR_STOPB; 3278 3279 if (com->hasfifo && divisor != 0) { 3280 /* 3281 * Use a fifo trigger level low enough so that the input 3282 * latency from the fifo is less than about 16 msec and 3283 * the total latency is less than about 30 msec. These 3284 * latencies are reasonable for humans. Serial comms 3285 * protocols shouldn't expect anything better since modem 3286 * latencies are larger. 3287 * 3288 * We have to set the FIFO trigger point such that we 3289 * don't overflow it accidently if a serial interrupt 3290 * is delayed. At high speeds, FIFO_RX_HIGH does not 3291 * leave enough slots free. 3292 */ 3293 com->fifo_image = t->c_ospeed <= 4800 3294 ? FIFO_ENABLE : FIFO_ENABLE | FIFO_RX_MEDH; 3295#ifdef COM_ESP 3296 /* 3297 * The Hayes ESP card needs the fifo DMA mode bit set 3298 * in compatibility mode. If not, it will interrupt 3299 * for each character received. 3300 */ 3301 if (com->esp) 3302 com->fifo_image |= FIFO_DMA_MODE; 3303#endif 3304 sio_setreg(com, com_fifo, com->fifo_image); 3305 } 3306#ifdef PC98 3307 } 3308#endif 3309 3310 /* 3311 * This returns with interrupts disabled so that we can complete 3312 * the speed change atomically. Keeping interrupts disabled is 3313 * especially important while com_data is hidden. 3314 */ 3315 (void) siosetwater(com, t->c_ispeed); 3316 3317#ifdef PC98 3318 if (IS_8251(com->pc98_if_type)) 3319 com_cflag_and_speed_set(com, cflag, t->c_ospeed); 3320 else { 3321#endif 3322 if (divisor != 0) { 3323 sio_setreg(com, com_cfcr, cfcr | CFCR_DLAB); 3324 /* 3325 * Only set the divisor registers if they would change, 3326 * since on some 16550 incompatibles (UMC8669F), setting 3327 * them while input is arriving them loses sync until 3328 * data stops arriving. 3329 */ 3330 dlbl = divisor & 0xFF; 3331 if (sio_getreg(com, com_dlbl) != dlbl) 3332 sio_setreg(com, com_dlbl, dlbl); 3333 dlbh = divisor >> 8; 3334 if (sio_getreg(com, com_dlbh) != dlbh) 3335 sio_setreg(com, com_dlbh, dlbh); 3336 } 3337 3338 sio_setreg(com, com_cfcr, com->cfcr_image = cfcr); 3339#ifdef PC98 3340 } 3341#endif 3342 3343 if (!(tp->t_state & TS_TTSTOP)) 3344 com->state |= CS_TTGO; 3345 3346 if (cflag & CRTS_IFLOW) { 3347#ifndef PC98 3348 if (com->st16650a) { 3349 sio_setreg(com, com_cfcr, 0xbf); 3350 sio_setreg(com, com_fifo, 3351 sio_getreg(com, com_fifo) | 0x40); 3352 } 3353#endif 3354 com->state |= CS_RTS_IFLOW; 3355 /* 3356 * If CS_RTS_IFLOW just changed from off to on, the change 3357 * needs to be propagated to MCR_RTS. This isn't urgent, 3358 * so do it later by calling comstart() instead of repeating 3359 * a lot of code from comstart() here. 3360 */ 3361 } else if (com->state & CS_RTS_IFLOW) { 3362 com->state &= ~CS_RTS_IFLOW; 3363 /* 3364 * CS_RTS_IFLOW just changed from on to off. Force MCR_RTS 3365 * on here, since comstart() won't do it later. 3366 */ 3367#ifdef PC98 3368 if (IS_8251(com->pc98_if_type)) 3369 com_tiocm_bis(com, TIOCM_RTS); 3370 else 3371 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS); 3372#else 3373 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS); 3374 if (com->st16650a) { 3375 sio_setreg(com, com_cfcr, 0xbf); 3376 sio_setreg(com, com_fifo, 3377 sio_getreg(com, com_fifo) & ~0x40); 3378 } 3379#endif 3380 } 3381 3382 3383 /* 3384 * Set up state to handle output flow control. 3385 * XXX - worth handling MDMBUF (DCD) flow control at the lowest level? 3386 * Now has 10+ msec latency, while CTS flow has 50- usec latency. 3387 */ 3388 com->state |= CS_ODEVREADY; 3389 com->state &= ~CS_CTS_OFLOW; 3390#ifdef PC98 3391 if (com->pc98_if_type == COM_IF_RSA98III) { 3392 param = inb(com->rsabase + rsa_msr); 3393 outb(com->rsabase + rsa_msr, param & 0x14); 3394 } 3395#endif 3396 if (cflag & CCTS_OFLOW) { 3397 com->state |= CS_CTS_OFLOW; 3398#ifdef PC98 3399 if (IS_8251(com->pc98_if_type)) { 3400 if (!(pc98_get_modem_status(com) & TIOCM_CTS)) 3401 com->state &= ~CS_ODEVREADY; 3402 } else { 3403 if (com->pc98_if_type == COM_IF_RSA98III) { 3404 /* Set automatic flow control mode */ 3405 outb(com->rsabase + rsa_msr, param | 0x08); 3406 } else 3407#endif 3408 if (!(com->last_modem_status & MSR_CTS)) 3409 com->state &= ~CS_ODEVREADY; 3410#ifdef PC98 3411 } 3412#else 3413 if (com->st16650a) { 3414 sio_setreg(com, com_cfcr, 0xbf); 3415 sio_setreg(com, com_fifo, 3416 sio_getreg(com, com_fifo) | 0x80); 3417 } 3418 } else { 3419 if (com->st16650a) { 3420 sio_setreg(com, com_cfcr, 0xbf); 3421 sio_setreg(com, com_fifo, 3422 sio_getreg(com, com_fifo) & ~0x80); 3423 } 3424#endif 3425 } 3426 3427#ifdef PC98 3428 if (!IS_8251(com->pc98_if_type)) 3429#endif 3430 sio_setreg(com, com_cfcr, com->cfcr_image); 3431 3432 /* XXX shouldn't call functions while intrs are disabled. */ 3433 disc_optim(tp, t, com); 3434 /* 3435 * Recover from fiddling with CS_TTGO. We used to call siointr1() 3436 * unconditionally, but that defeated the careful discarding of 3437 * stale input in sioopen(). 3438 */ 3439 if (com->state >= (CS_BUSY | CS_TTGO)) 3440 siointr1(com); 3441 3442 mtx_unlock_spin(&sio_lock); 3443 splx(s); 3444 comstart(tp); 3445 if (com->ibufold != NULL) { 3446 free(com->ibufold, M_DEVBUF); 3447 com->ibufold = NULL; 3448 } 3449 return (0); 3450} 3451 3452/* 3453 * This function must be called with the sio_lock mutex released and will 3454 * return with it obtained. 3455 */ 3456static int 3457siosetwater(com, speed) 3458 struct com_s *com; 3459 speed_t speed; 3460{ 3461 int cp4ticks; 3462 u_char *ibuf; 3463 int ibufsize; 3464 struct tty *tp; 3465 3466 /* 3467 * Make the buffer size large enough to handle a softtty interrupt 3468 * latency of about 2 ticks without loss of throughput or data 3469 * (about 3 ticks if input flow control is not used or not honoured, 3470 * but a bit less for CS5-CS7 modes). 3471 */ 3472 cp4ticks = speed / 10 / hz * 4; 3473 for (ibufsize = 128; ibufsize < cp4ticks;) 3474 ibufsize <<= 1; 3475#ifdef PC98 3476 if (com->pc98_if_type == COM_IF_RSA98III) 3477 ibufsize = 2048; 3478#endif 3479 if (ibufsize == com->ibufsize) { 3480 mtx_lock_spin(&sio_lock); 3481 return (0); 3482 } 3483 3484 /* 3485 * Allocate input buffer. The extra factor of 2 in the size is 3486 * to allow for an error byte for each input byte. 3487 */ 3488 ibuf = malloc(2 * ibufsize, M_DEVBUF, M_NOWAIT); 3489 if (ibuf == NULL) { 3490 mtx_lock_spin(&sio_lock); 3491 return (ENOMEM); 3492 } 3493 3494 /* Initialize non-critical variables. */ 3495 com->ibufold = com->ibuf; 3496 com->ibufsize = ibufsize; 3497 tp = com->tp; 3498 if (tp != NULL) { 3499 tp->t_ififosize = 2 * ibufsize; 3500 tp->t_ispeedwat = (speed_t)-1; 3501 tp->t_ospeedwat = (speed_t)-1; 3502 } 3503 3504 /* 3505 * Read current input buffer, if any. Continue with interrupts 3506 * disabled. 3507 */ 3508 mtx_lock_spin(&sio_lock); 3509 if (com->iptr != com->ibuf) 3510 sioinput(com); 3511 3512 /*- 3513 * Initialize critical variables, including input buffer watermarks. 3514 * The external device is asked to stop sending when the buffer 3515 * exactly reaches high water, or when the high level requests it. 3516 * The high level is notified immediately (rather than at a later 3517 * clock tick) when this watermark is reached. 3518 * The buffer size is chosen so the watermark should almost never 3519 * be reached. 3520 * The low watermark is invisibly 0 since the buffer is always 3521 * emptied all at once. 3522 */ 3523 com->iptr = com->ibuf = ibuf; 3524 com->ibufend = ibuf + ibufsize; 3525 com->ierroff = ibufsize; 3526 com->ihighwater = ibuf + 3 * ibufsize / 4; 3527 return (0); 3528} 3529 3530static void 3531comstart(tp) 3532 struct tty *tp; 3533{ 3534 struct com_s *com; 3535 int s; 3536 int unit; 3537 3538 unit = DEV_TO_UNIT(tp->t_dev); 3539 com = com_addr(unit); 3540 if (com == NULL) 3541 return; 3542 s = spltty(); 3543 mtx_lock_spin(&sio_lock); 3544 if (tp->t_state & TS_TTSTOP) 3545 com->state &= ~CS_TTGO; 3546 else 3547 com->state |= CS_TTGO; 3548 if (tp->t_state & TS_TBLOCK) { 3549#ifdef PC98 3550 if (IS_8251(com->pc98_if_type)) { 3551 if ((com_tiocm_get(com) & TIOCM_RTS) && 3552 (com->state & CS_RTS_IFLOW)) 3553 com_tiocm_bic(com, TIOCM_RTS); 3554 } else { 3555 if ((com->mcr_image & MCR_RTS) && 3556 (com->state & CS_RTS_IFLOW)) 3557 outb(com->modem_ctl_port, com->mcr_image &= ~MCR_RTS); 3558 } 3559#else 3560 if (com->mcr_image & MCR_RTS && com->state & CS_RTS_IFLOW) 3561 outb(com->modem_ctl_port, com->mcr_image &= ~MCR_RTS); 3562#endif 3563 } else { 3564#ifdef PC98 3565 if (IS_8251(com->pc98_if_type)) { 3566 if (!(com_tiocm_get(com) & TIOCM_RTS) && 3567 com->iptr < com->ihighwater && 3568 com->state & CS_RTS_IFLOW) 3569 com_tiocm_bis(com, TIOCM_RTS); 3570 } else { 3571 if (!(com->mcr_image & MCR_RTS) && 3572 com->iptr < com->ihighwater && 3573 com->state & CS_RTS_IFLOW) 3574 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS); 3575 } 3576#else 3577 if (!(com->mcr_image & MCR_RTS) && com->iptr < com->ihighwater 3578 && com->state & CS_RTS_IFLOW) 3579 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS); 3580#endif 3581 } 3582 mtx_unlock_spin(&sio_lock); 3583 if (tp->t_state & (TS_TIMEOUT | TS_TTSTOP)) { 3584 ttwwakeup(tp); 3585 splx(s); 3586 return; 3587 } 3588 if (tp->t_outq.c_cc != 0) { 3589 struct lbq *qp; 3590 struct lbq *next; 3591 3592 if (!com->obufs[0].l_queued) { 3593 com->obufs[0].l_tail 3594 = com->obuf1 + q_to_b(&tp->t_outq, com->obuf1, 3595#ifdef PC98 3596 com->obufsize); 3597#else 3598 sizeof com->obuf1); 3599#endif 3600 com->obufs[0].l_next = NULL; 3601 com->obufs[0].l_queued = TRUE; 3602 mtx_lock_spin(&sio_lock); 3603 if (com->state & CS_BUSY) { 3604 qp = com->obufq.l_next; 3605 while ((next = qp->l_next) != NULL) 3606 qp = next; 3607 qp->l_next = &com->obufs[0]; 3608 } else { 3609 com->obufq.l_head = com->obufs[0].l_head; 3610 com->obufq.l_tail = com->obufs[0].l_tail; 3611 com->obufq.l_next = &com->obufs[0]; 3612 com->state |= CS_BUSY; 3613 } 3614 mtx_unlock_spin(&sio_lock); 3615 } 3616 if (tp->t_outq.c_cc != 0 && !com->obufs[1].l_queued) { 3617 com->obufs[1].l_tail 3618 = com->obuf2 + q_to_b(&tp->t_outq, com->obuf2, 3619#ifdef PC98 3620 com->obufsize); 3621#else 3622 sizeof com->obuf2); 3623#endif 3624 com->obufs[1].l_next = NULL; 3625 com->obufs[1].l_queued = TRUE; 3626 mtx_lock_spin(&sio_lock); 3627 if (com->state & CS_BUSY) { 3628 qp = com->obufq.l_next; 3629 while ((next = qp->l_next) != NULL) 3630 qp = next; 3631 qp->l_next = &com->obufs[1]; 3632 } else { 3633 com->obufq.l_head = com->obufs[1].l_head; 3634 com->obufq.l_tail = com->obufs[1].l_tail; 3635 com->obufq.l_next = &com->obufs[1]; 3636 com->state |= CS_BUSY; 3637 } 3638 mtx_unlock_spin(&sio_lock); 3639 } 3640 tp->t_state |= TS_BUSY; 3641 } 3642 mtx_lock_spin(&sio_lock); 3643 if (com->state >= (CS_BUSY | CS_TTGO)) 3644 siointr1(com); /* fake interrupt to start output */ 3645 mtx_unlock_spin(&sio_lock); 3646 ttwwakeup(tp); 3647 splx(s); 3648} 3649 3650static void 3651comstop(tp, rw) 3652 struct tty *tp; 3653 int rw; 3654{ 3655 struct com_s *com; 3656#ifdef PC98 3657 int rsa98_tmp = 0; 3658#endif 3659 3660 com = com_addr(DEV_TO_UNIT(tp->t_dev)); 3661 if (com == NULL || com->gone) 3662 return; 3663 mtx_lock_spin(&sio_lock); 3664 if (rw & FWRITE) { 3665#ifdef PC98 3666 if (!IS_8251(com->pc98_if_type)) { 3667#endif 3668 if (com->hasfifo) 3669#ifdef COM_ESP 3670 /* XXX avoid h/w bug. */ 3671 if (!com->esp) 3672#endif 3673 sio_setreg(com, com_fifo, 3674 FIFO_XMT_RST | com->fifo_image); 3675#ifdef PC98 3676 if (com->pc98_if_type == COM_IF_RSA98III) 3677 for (rsa98_tmp = 0; rsa98_tmp < 2048; rsa98_tmp++) 3678 sio_setreg(com, com_fifo, 3679 FIFO_XMT_RST | com->fifo_image); 3680 } 3681#endif 3682 com->obufs[0].l_queued = FALSE; 3683 com->obufs[1].l_queued = FALSE; 3684 if (com->state & CS_ODONE) 3685 com_events -= LOTS_OF_EVENTS; 3686 com->state &= ~(CS_ODONE | CS_BUSY); 3687 com->tp->t_state &= ~TS_BUSY; 3688 } 3689 if (rw & FREAD) { 3690#ifdef PC98 3691 if (!IS_8251(com->pc98_if_type)) { 3692 if (com->pc98_if_type == COM_IF_RSA98III) 3693 for (rsa98_tmp = 0; rsa98_tmp < 2048; rsa98_tmp++) 3694 sio_getreg(com, com_data); 3695#endif 3696 if (com->hasfifo) 3697#ifdef COM_ESP 3698 /* XXX avoid h/w bug. */ 3699 if (!com->esp) 3700#endif 3701 sio_setreg(com, com_fifo, 3702 FIFO_RCV_RST | com->fifo_image); 3703#ifdef PC98 3704 } 3705#endif 3706 com_events -= (com->iptr - com->ibuf); 3707 com->iptr = com->ibuf; 3708 } 3709 mtx_unlock_spin(&sio_lock); 3710 comstart(tp); 3711} 3712 3713static int 3714commctl(com, bits, how) 3715 struct com_s *com; 3716 int bits; 3717 int how; 3718{ 3719 int mcr; 3720 int msr; 3721 3722 if (how == DMGET) { 3723 bits = TIOCM_LE; /* XXX - always enabled while open */ 3724 mcr = com->mcr_image; 3725 if (mcr & MCR_DTR) 3726 bits |= TIOCM_DTR; 3727 if (mcr & MCR_RTS) 3728 bits |= TIOCM_RTS; 3729 msr = com->prev_modem_status; 3730 if (msr & MSR_CTS) 3731 bits |= TIOCM_CTS; 3732 if (msr & MSR_DCD) 3733 bits |= TIOCM_CD; 3734 if (msr & MSR_DSR) 3735 bits |= TIOCM_DSR; 3736 /* 3737 * XXX - MSR_RI is naturally volatile, and we make MSR_TERI 3738 * more volatile by reading the modem status a lot. Perhaps 3739 * we should latch both bits until the status is read here. 3740 */ 3741 if (msr & (MSR_RI | MSR_TERI)) 3742 bits |= TIOCM_RI; 3743 return (bits); 3744 } 3745 mcr = 0; 3746 if (bits & TIOCM_DTR) 3747 mcr |= MCR_DTR; 3748 if (bits & TIOCM_RTS) 3749 mcr |= MCR_RTS; 3750 if (com->gone) 3751 return(0); 3752 mtx_lock_spin(&sio_lock); 3753 switch (how) { 3754 case DMSET: 3755 outb(com->modem_ctl_port, 3756 com->mcr_image = mcr | (com->mcr_image & MCR_IENABLE)); 3757 break; 3758 case DMBIS: 3759 outb(com->modem_ctl_port, com->mcr_image |= mcr); 3760 break; 3761 case DMBIC: 3762 outb(com->modem_ctl_port, com->mcr_image &= ~mcr); 3763 break; 3764 } 3765 mtx_unlock_spin(&sio_lock); 3766 return (0); 3767} 3768 3769static void 3770siosettimeout() 3771{ 3772 struct com_s *com; 3773 bool_t someopen; 3774 int unit; 3775 3776 /* 3777 * Set our timeout period to 1 second if no polled devices are open. 3778 * Otherwise set it to max(1/200, 1/hz). 3779 * Enable timeouts iff some device is open. 3780 */ 3781 untimeout(comwakeup, (void *)NULL, sio_timeout_handle); 3782 sio_timeout = hz; 3783 someopen = FALSE; 3784 for (unit = 0; unit < sio_numunits; ++unit) { 3785 com = com_addr(unit); 3786 if (com != NULL && com->tp != NULL 3787 && com->tp->t_state & TS_ISOPEN && !com->gone) { 3788 someopen = TRUE; 3789 if (com->poll || com->poll_output) { 3790 sio_timeout = hz > 200 ? hz / 200 : 1; 3791 break; 3792 } 3793 } 3794 } 3795 if (someopen) { 3796 sio_timeouts_until_log = hz / sio_timeout; 3797 sio_timeout_handle = timeout(comwakeup, (void *)NULL, 3798 sio_timeout); 3799 } else { 3800 /* Flush error messages, if any. */ 3801 sio_timeouts_until_log = 1; 3802 comwakeup((void *)NULL); 3803 untimeout(comwakeup, (void *)NULL, sio_timeout_handle); 3804 } 3805} 3806 3807static void 3808comwakeup(chan) 3809 void *chan; 3810{ 3811 struct com_s *com; 3812 int unit; 3813 3814 sio_timeout_handle = timeout(comwakeup, (void *)NULL, sio_timeout); 3815 3816 /* 3817 * Recover from lost output interrupts. 3818 * Poll any lines that don't use interrupts. 3819 */ 3820 for (unit = 0; unit < sio_numunits; ++unit) { 3821 com = com_addr(unit); 3822 if (com != NULL && !com->gone 3823 && (com->state >= (CS_BUSY | CS_TTGO) || com->poll)) { 3824 mtx_lock_spin(&sio_lock); 3825 siointr1(com); 3826 mtx_unlock_spin(&sio_lock); 3827 } 3828 } 3829 3830 /* 3831 * Check for and log errors, but not too often. 3832 */ 3833 if (--sio_timeouts_until_log > 0) 3834 return; 3835 sio_timeouts_until_log = hz / sio_timeout; 3836 for (unit = 0; unit < sio_numunits; ++unit) { 3837 int errnum; 3838 3839 com = com_addr(unit); 3840 if (com == NULL) 3841 continue; 3842 if (com->gone) 3843 continue; 3844 for (errnum = 0; errnum < CE_NTYPES; ++errnum) { 3845 u_int delta; 3846 u_long total; 3847 3848 mtx_lock_spin(&sio_lock); 3849 delta = com->delta_error_counts[errnum]; 3850 com->delta_error_counts[errnum] = 0; 3851 mtx_unlock_spin(&sio_lock); 3852 if (delta == 0) 3853 continue; 3854 total = com->error_counts[errnum] += delta; 3855 log(LOG_ERR, "sio%d: %u more %s%s (total %lu)\n", 3856 unit, delta, error_desc[errnum], 3857 delta == 1 ? "" : "s", total); 3858 } 3859 } 3860} 3861 3862#ifdef PC98 3863/* commint is called when modem control line changes */ 3864static void 3865commint(dev_t dev) 3866{ 3867 register struct tty *tp; 3868 int stat,delta; 3869 struct com_s *com; 3870 int mynor,unit; 3871 3872 mynor = minor(dev); 3873 unit = MINOR_TO_UNIT(mynor); 3874 com = com_addr(unit); 3875 tp = com->tp; 3876 3877 stat = com_tiocm_get(com); 3878 delta = com_tiocm_get_delta(com); 3879 3880 if (com->state & CS_CTS_OFLOW) { 3881 if (stat & TIOCM_CTS) 3882 com->state |= CS_ODEVREADY; 3883 else 3884 com->state &= ~CS_ODEVREADY; 3885 } 3886 if ((delta & TIOCM_CAR) && (mynor & CALLOUT_MASK) == 0) { 3887 if (stat & TIOCM_CAR ) 3888 (void)(*linesw[tp->t_line].l_modem)(tp, 1); 3889 else if ((*linesw[tp->t_line].l_modem)(tp, 0) == 0) { 3890 /* negate DTR, RTS */ 3891 com_tiocm_bic(com, (tp->t_cflag & HUPCL) ? 3892 TIOCM_DTR|TIOCM_RTS|TIOCM_LE : TIOCM_LE ); 3893 /* disable IENABLE */ 3894 com_int_TxRx_disable( com ); 3895 } 3896 } 3897} 3898#endif 3899 3900static void 3901disc_optim(tp, t, com) 3902 struct tty *tp; 3903 struct termios *t; 3904 struct com_s *com; 3905{ 3906 if (!(t->c_iflag & (ICRNL | IGNCR | IMAXBEL | INLCR | ISTRIP | IXON)) 3907 && (!(t->c_iflag & BRKINT) || (t->c_iflag & IGNBRK)) 3908 && (!(t->c_iflag & PARMRK) 3909 || (t->c_iflag & (IGNPAR | IGNBRK)) == (IGNPAR | IGNBRK)) 3910 && !(t->c_lflag & (ECHO | ICANON | IEXTEN | ISIG | PENDIN)) 3911 && linesw[tp->t_line].l_rint == ttyinput) 3912 tp->t_state |= TS_CAN_BYPASS_L_RINT; 3913 else 3914 tp->t_state &= ~TS_CAN_BYPASS_L_RINT; 3915 com->hotchar = linesw[tp->t_line].l_hotchar; 3916} 3917 3918/* 3919 * Following are all routines needed for SIO to act as console 3920 */ 3921#include <sys/cons.h> 3922 3923struct siocnstate { 3924 u_char dlbl; 3925 u_char dlbh; 3926 u_char ier; 3927 u_char cfcr; 3928 u_char mcr; 3929}; 3930 3931#ifndef __alpha__ 3932static speed_t siocngetspeed(Port_t, u_long rclk); 3933#endif 3934static void siocnclose(struct siocnstate *sp, Port_t iobase); 3935static void siocnopen(struct siocnstate *sp, Port_t iobase, int speed); 3936static void siocntxwait(Port_t iobase); 3937 3938#ifdef __alpha__ 3939int siocnattach(int port, int speed); 3940int siogdbattach(int port, int speed); 3941int siogdbgetc(void); 3942void siogdbputc(int c); 3943#else 3944static cn_probe_t siocnprobe; 3945static cn_init_t siocninit; 3946static cn_term_t siocnterm; 3947#endif 3948static cn_checkc_t siocncheckc; 3949static cn_getc_t siocngetc; 3950static cn_putc_t siocnputc; 3951 3952#ifndef __alpha__ 3953CONS_DRIVER(sio, siocnprobe, siocninit, siocnterm, siocngetc, siocncheckc, 3954 siocnputc, NULL); 3955#endif 3956 3957/* To get the GDB related variables */ 3958#if DDB > 0 3959#include <ddb/ddb.h> 3960#endif 3961 3962static void 3963siocntxwait(iobase) 3964 Port_t iobase; 3965{ 3966 int timo; 3967 3968 /* 3969 * Wait for any pending transmission to finish. Required to avoid 3970 * the UART lockup bug when the speed is changed, and for normal 3971 * transmits. 3972 */ 3973 timo = 100000; 3974 while ((inb(iobase + com_lsr) & (LSR_TSRE | LSR_TXRDY)) 3975 != (LSR_TSRE | LSR_TXRDY) && --timo != 0) 3976 ; 3977} 3978 3979#ifndef __alpha__ 3980 3981/* 3982 * Read the serial port specified and try to figure out what speed 3983 * it's currently running at. We're assuming the serial port has 3984 * been initialized and is basicly idle. This routine is only intended 3985 * to be run at system startup. 3986 * 3987 * If the value read from the serial port doesn't make sense, return 0. 3988 */ 3989 3990static speed_t 3991siocngetspeed(iobase, rclk) 3992 Port_t iobase; 3993 u_long rclk; 3994{ 3995 u_int divisor; 3996 u_char dlbh; 3997 u_char dlbl; 3998 u_char cfcr; 3999 4000 cfcr = inb(iobase + com_cfcr); 4001 outb(iobase + com_cfcr, CFCR_DLAB | cfcr); 4002 4003 dlbl = inb(iobase + com_dlbl); 4004 dlbh = inb(iobase + com_dlbh); 4005 4006 outb(iobase + com_cfcr, cfcr); 4007 4008 divisor = dlbh << 8 | dlbl; 4009 4010 /* XXX there should be more sanity checking. */ 4011 if (divisor == 0) 4012 return (CONSPEED); 4013 return (rclk / (16UL * divisor)); 4014} 4015 4016#endif 4017 4018static void 4019siocnopen(sp, iobase, speed) 4020 struct siocnstate *sp; 4021 Port_t iobase; 4022 int speed; 4023{ 4024 u_int divisor; 4025 u_char dlbh; 4026 u_char dlbl; 4027 4028 /* 4029 * Save all the device control registers except the fifo register 4030 * and set our default ones (cs8 -parenb speed=comdefaultrate). 4031 * We can't save the fifo register since it is read-only. 4032 */ 4033 sp->ier = inb(iobase + com_ier); 4034 outb(iobase + com_ier, 0); /* spltty() doesn't stop siointr() */ 4035 siocntxwait(iobase); 4036 sp->cfcr = inb(iobase + com_cfcr); 4037 outb(iobase + com_cfcr, CFCR_DLAB | CFCR_8BITS); 4038 sp->dlbl = inb(iobase + com_dlbl); 4039 sp->dlbh = inb(iobase + com_dlbh); 4040 /* 4041 * Only set the divisor registers if they would change, since on 4042 * some 16550 incompatibles (Startech), setting them clears the 4043 * data input register. This also reduces the effects of the 4044 * UMC8669F bug. 4045 */ 4046 divisor = siodivisor(comdefaultrclk, speed); 4047 dlbl = divisor & 0xFF; 4048 if (sp->dlbl != dlbl) 4049 outb(iobase + com_dlbl, dlbl); 4050 dlbh = divisor >> 8; 4051 if (sp->dlbh != dlbh) 4052 outb(iobase + com_dlbh, dlbh); 4053 outb(iobase + com_cfcr, CFCR_8BITS); 4054 sp->mcr = inb(iobase + com_mcr); 4055 /* 4056 * We don't want interrupts, but must be careful not to "disable" 4057 * them by clearing the MCR_IENABLE bit, since that might cause 4058 * an interrupt by floating the IRQ line. 4059 */ 4060 outb(iobase + com_mcr, (sp->mcr & MCR_IENABLE) | MCR_DTR | MCR_RTS); 4061} 4062 4063static void 4064siocnclose(sp, iobase) 4065 struct siocnstate *sp; 4066 Port_t iobase; 4067{ 4068 /* 4069 * Restore the device control registers. 4070 */ 4071 siocntxwait(iobase); 4072 outb(iobase + com_cfcr, CFCR_DLAB | CFCR_8BITS); 4073 if (sp->dlbl != inb(iobase + com_dlbl)) 4074 outb(iobase + com_dlbl, sp->dlbl); 4075 if (sp->dlbh != inb(iobase + com_dlbh)) 4076 outb(iobase + com_dlbh, sp->dlbh); 4077 outb(iobase + com_cfcr, sp->cfcr); 4078 /* 4079 * XXX damp oscillations of MCR_DTR and MCR_RTS by not restoring them. 4080 */ 4081 outb(iobase + com_mcr, sp->mcr | MCR_DTR | MCR_RTS); 4082 outb(iobase + com_ier, sp->ier); 4083} 4084 4085#ifndef __alpha__ 4086 4087static void 4088siocnprobe(cp) 4089 struct consdev *cp; 4090{ 4091 speed_t boot_speed; 4092 u_char cfcr; 4093 u_int divisor; 4094 int s, unit; 4095 struct siocnstate sp; 4096 4097 /* 4098 * Find our first enabled console, if any. If it is a high-level 4099 * console device, then initialize it and return successfully. 4100 * If it is a low-level console device, then initialize it and 4101 * return unsuccessfully. It must be initialized in both cases 4102 * for early use by console drivers and debuggers. Initializing 4103 * the hardware is not necessary in all cases, since the i/o 4104 * routines initialize it on the fly, but it is necessary if 4105 * input might arrive while the hardware is switched back to an 4106 * uninitialized state. We can't handle multiple console devices 4107 * yet because our low-level routines don't take a device arg. 4108 * We trust the user to set the console flags properly so that we 4109 * don't need to probe. 4110 */ 4111 cp->cn_pri = CN_DEAD; 4112 4113 for (unit = 0; unit < 16; unit++) { /* XXX need to know how many */ 4114 int flags; 4115 int disabled; 4116 if (resource_int_value("sio", unit, "disabled", &disabled) == 0) { 4117 if (disabled) 4118 continue; 4119 } 4120 if (resource_int_value("sio", unit, "flags", &flags)) 4121 continue; 4122 if (COM_CONSOLE(flags) || COM_DEBUGGER(flags)) { 4123 int port; 4124 Port_t iobase; 4125 4126 if (resource_int_value("sio", unit, "port", &port)) 4127 continue; 4128 iobase = port; 4129 s = spltty(); 4130 if (boothowto & RB_SERIAL) { 4131 boot_speed = 4132 siocngetspeed(iobase, comdefaultrclk); 4133 if (boot_speed) 4134 comdefaultrate = boot_speed; 4135 } 4136 4137 /* 4138 * Initialize the divisor latch. We can't rely on 4139 * siocnopen() to do this the first time, since it 4140 * avoids writing to the latch if the latch appears 4141 * to have the correct value. Also, if we didn't 4142 * just read the speed from the hardware, then we 4143 * need to set the speed in hardware so that 4144 * switching it later is null. 4145 */ 4146 cfcr = inb(iobase + com_cfcr); 4147 outb(iobase + com_cfcr, CFCR_DLAB | cfcr); 4148 divisor = siodivisor(comdefaultrclk, comdefaultrate); 4149 outb(iobase + com_dlbl, divisor & 0xff); 4150 outb(iobase + com_dlbh, divisor >> 8); 4151 outb(iobase + com_cfcr, cfcr); 4152 4153 siocnopen(&sp, iobase, comdefaultrate); 4154 4155 splx(s); 4156 if (COM_CONSOLE(flags) && !COM_LLCONSOLE(flags)) { 4157 cp->cn_dev = makedev(CDEV_MAJOR, unit); 4158 cp->cn_pri = COM_FORCECONSOLE(flags) 4159 || boothowto & RB_SERIAL 4160 ? CN_REMOTE : CN_NORMAL; 4161 siocniobase = iobase; 4162 siocnunit = unit; 4163 } 4164 if (COM_DEBUGGER(flags)) { 4165 printf("sio%d: gdb debugging port\n", unit); 4166 siogdbiobase = iobase; 4167 siogdbunit = unit; 4168#if DDB > 0 4169 gdbdev = makedev(CDEV_MAJOR, unit); 4170 gdb_getc = siocngetc; 4171 gdb_putc = siocnputc; 4172#endif 4173 } 4174 } 4175 } 4176#ifdef __i386__ 4177#if DDB > 0 4178 /* 4179 * XXX Ugly Compatability. 4180 * If no gdb port has been specified, set it to be the console 4181 * as some configuration files don't specify the gdb port. 4182 */ 4183 if (gdbdev == NODEV && (boothowto & RB_GDB)) { 4184 printf("Warning: no GDB port specified. Defaulting to sio%d.\n", 4185 siocnunit); 4186 printf("Set flag 0x80 on desired GDB port in your\n"); 4187 printf("configuration file (currently sio only).\n"); 4188 siogdbiobase = siocniobase; 4189 siogdbunit = siocnunit; 4190 gdbdev = makedev(CDEV_MAJOR, siocnunit); 4191 gdb_getc = siocngetc; 4192 gdb_putc = siocnputc; 4193 } 4194#endif 4195#endif 4196} 4197 4198static void 4199siocninit(cp) 4200 struct consdev *cp; 4201{ 4202 comconsole = DEV_TO_UNIT(cp->cn_dev); 4203} 4204 4205static void 4206siocnterm(cp) 4207 struct consdev *cp; 4208{ 4209 comconsole = -1; 4210} 4211 4212#endif 4213 4214#ifdef __alpha__ 4215 4216CONS_DRIVER(sio, NULL, NULL, NULL, siocngetc, siocncheckc, siocnputc, NULL); 4217 4218int 4219siocnattach(port, speed) 4220 int port; 4221 int speed; 4222{ 4223 int s; 4224 u_char cfcr; 4225 u_int divisor; 4226 struct siocnstate sp; 4227 4228 siocniobase = port; 4229 comdefaultrate = speed; 4230 sio_consdev.cn_pri = CN_NORMAL; 4231 sio_consdev.cn_dev = makedev(CDEV_MAJOR, 0); 4232 4233 s = spltty(); 4234 4235 /* 4236 * Initialize the divisor latch. We can't rely on 4237 * siocnopen() to do this the first time, since it 4238 * avoids writing to the latch if the latch appears 4239 * to have the correct value. Also, if we didn't 4240 * just read the speed from the hardware, then we 4241 * need to set the speed in hardware so that 4242 * switching it later is null. 4243 */ 4244 cfcr = inb(siocniobase + com_cfcr); 4245 outb(siocniobase + com_cfcr, CFCR_DLAB | cfcr); 4246 divisor = siodivisor(comdefaultrclk, comdefaultrate); 4247 outb(siocniobase + com_dlbl, divisor & 0xff); 4248 outb(siocniobase + com_dlbh, divisor >> 8); 4249 outb(siocniobase + com_cfcr, cfcr); 4250 4251 siocnopen(&sp, siocniobase, comdefaultrate); 4252 splx(s); 4253 4254 cnadd(&sio_consdev); 4255 return (0); 4256} 4257 4258int 4259siogdbattach(port, speed) 4260 int port; 4261 int speed; 4262{ 4263 int s; 4264 u_char cfcr; 4265 u_int divisor; 4266 struct siocnstate sp; 4267 int unit = 1; /* XXX !!! */ 4268 4269 siogdbiobase = port; 4270 gdbdefaultrate = speed; 4271 4272 printf("sio%d: gdb debugging port\n", unit); 4273 siogdbunit = unit; 4274#if DDB > 0 4275 gdbdev = makedev(CDEV_MAJOR, unit); 4276 gdb_getc = siocngetc; 4277 gdb_putc = siocnputc; 4278#endif 4279 4280 s = spltty(); 4281 4282 /* 4283 * Initialize the divisor latch. We can't rely on 4284 * siocnopen() to do this the first time, since it 4285 * avoids writing to the latch if the latch appears 4286 * to have the correct value. Also, if we didn't 4287 * just read the speed from the hardware, then we 4288 * need to set the speed in hardware so that 4289 * switching it later is null. 4290 */ 4291 cfcr = inb(siogdbiobase + com_cfcr); 4292 outb(siogdbiobase + com_cfcr, CFCR_DLAB | cfcr); 4293 divisor = siodivisor(comdefaultrclk, gdbdefaultrate); 4294 outb(siogdbiobase + com_dlbl, divisor & 0xff); 4295 outb(siogdbiobase + com_dlbh, divisor >> 8); 4296 outb(siogdbiobase + com_cfcr, cfcr); 4297 4298 siocnopen(&sp, siogdbiobase, gdbdefaultrate); 4299 splx(s); 4300 4301 return (0); 4302} 4303 4304#endif 4305 4306static int 4307siocncheckc(dev) 4308 dev_t dev; 4309{ 4310 int c; 4311 Port_t iobase; 4312 int s; 4313 struct siocnstate sp; 4314 4315 if (minor(dev) == siogdbunit) 4316 iobase = siogdbiobase; 4317 else 4318 iobase = siocniobase; 4319 s = spltty(); 4320 siocnopen(&sp, iobase, comdefaultrate); 4321 if (inb(iobase + com_lsr) & LSR_RXRDY) 4322 c = inb(iobase + com_data); 4323 else 4324 c = -1; 4325 siocnclose(&sp, iobase); 4326 splx(s); 4327 return (c); 4328} 4329 4330 4331int 4332siocngetc(dev) 4333 dev_t dev; 4334{ 4335 int c; 4336 Port_t iobase; 4337 int s; 4338 struct siocnstate sp; 4339 4340 if (minor(dev) == siogdbunit) 4341 iobase = siogdbiobase; 4342 else 4343 iobase = siocniobase; 4344 s = spltty(); 4345 siocnopen(&sp, iobase, comdefaultrate); 4346 while (!(inb(iobase + com_lsr) & LSR_RXRDY)) 4347 ; 4348 c = inb(iobase + com_data); 4349 siocnclose(&sp, iobase); 4350 splx(s); 4351 return (c); 4352} 4353 4354void 4355siocnputc(dev, c) 4356 dev_t dev; 4357 int c; 4358{ 4359 int need_unlock; 4360 int s; 4361 struct siocnstate sp; 4362 Port_t iobase; 4363 4364 if (minor(dev) == siogdbunit) 4365 iobase = siogdbiobase; 4366 else 4367 iobase = siocniobase; 4368 s = spltty(); 4369 need_unlock = 0; 4370 if (sio_inited == 2 && !mtx_owned(&sio_lock)) { 4371 mtx_lock_spin(&sio_lock); 4372 need_unlock = 1; 4373 } 4374 siocnopen(&sp, iobase, comdefaultrate); 4375 siocntxwait(iobase); 4376 outb(iobase + com_data, c); 4377 siocnclose(&sp, iobase); 4378 if (need_unlock) 4379 mtx_unlock_spin(&sio_lock); 4380 splx(s); 4381} 4382 4383#ifdef __alpha__ 4384int 4385siogdbgetc() 4386{ 4387 int c; 4388 Port_t iobase; 4389 int s; 4390 struct siocnstate sp; 4391 4392 iobase = siogdbiobase; 4393 s = spltty(); 4394 siocnopen(&sp, iobase, gdbdefaultrate); 4395 while (!(inb(iobase + com_lsr) & LSR_RXRDY)) 4396 ; 4397 c = inb(iobase + com_data); 4398 siocnclose(&sp, iobase); 4399 splx(s); 4400 return (c); 4401} 4402 4403void 4404siogdbputc(c) 4405 int c; 4406{ 4407 int s; 4408 struct siocnstate sp; 4409 4410 s = spltty(); 4411 siocnopen(&sp, siogdbiobase, gdbdefaultrate); 4412 siocntxwait(siogdbiobase); 4413 outb(siogdbiobase + com_data, c); 4414 siocnclose(&sp, siogdbiobase); 4415 splx(s); 4416} 4417#endif 4418 4419#ifdef PC98 4420/* 4421 * pc98 local function 4422 */ 4423 4424static void 4425com_tiocm_set(struct com_s *com, int msr) 4426{ 4427 int s; 4428 int tmp = 0; 4429 int mask = CMD8251_TxEN|CMD8251_RxEN|CMD8251_DTR|CMD8251_RTS; 4430 4431 s=spltty(); 4432 com->pc98_prev_modem_status = ( msr & (TIOCM_LE|TIOCM_DTR|TIOCM_RTS) ) 4433 | ( com->pc98_prev_modem_status & ~(TIOCM_LE|TIOCM_DTR|TIOCM_RTS) ); 4434 tmp |= (CMD8251_TxEN|CMD8251_RxEN); 4435 if ( msr & TIOCM_DTR ) tmp |= CMD8251_DTR; 4436 if ( msr & TIOCM_RTS ) tmp |= CMD8251_RTS; 4437 pc98_i8251_clear_or_cmd( com, mask, tmp ); 4438 splx(s); 4439} 4440 4441static void 4442com_tiocm_bis(struct com_s *com, int msr) 4443{ 4444 int s; 4445 int tmp = 0; 4446 4447 s=spltty(); 4448 com->pc98_prev_modem_status |= ( msr & (TIOCM_LE|TIOCM_DTR|TIOCM_RTS) ); 4449 tmp |= CMD8251_TxEN|CMD8251_RxEN; 4450 if ( msr & TIOCM_DTR ) tmp |= CMD8251_DTR; 4451 if ( msr & TIOCM_RTS ) tmp |= CMD8251_RTS; 4452 4453 pc98_i8251_or_cmd( com, tmp ); 4454 splx(s); 4455} 4456 4457static void 4458com_tiocm_bic(struct com_s *com, int msr) 4459{ 4460 int s; 4461 int tmp = msr; 4462 4463 s=spltty(); 4464 com->pc98_prev_modem_status &= ~( msr & (TIOCM_LE|TIOCM_DTR|TIOCM_RTS) ); 4465 if ( msr & TIOCM_DTR ) tmp |= CMD8251_DTR; 4466 if ( msr & TIOCM_RTS ) tmp |= CMD8251_RTS; 4467 4468 pc98_i8251_clear_cmd( com, tmp ); 4469 splx(s); 4470} 4471 4472static int 4473com_tiocm_get(struct com_s *com) 4474{ 4475 return( com->pc98_prev_modem_status ); 4476} 4477 4478static int 4479com_tiocm_get_delta(struct com_s *com) 4480{ 4481 int tmp; 4482 4483 tmp = com->pc98_modem_delta; 4484 com->pc98_modem_delta = 0; 4485 return( tmp ); 4486} 4487 4488/* convert to TIOCM_?? ( ioctl.h ) */ 4489static int 4490pc98_get_modem_status(struct com_s *com) 4491{ 4492 register int msr; 4493 4494 msr = com->pc98_prev_modem_status 4495 & ~(TIOCM_CAR|TIOCM_RI|TIOCM_DSR|TIOCM_CTS); 4496 if (com->pc98_8251fifo_enable) { 4497 int stat2; 4498 4499 stat2 = inb(I8251F_msr); 4500 if ( stat2 & CICSCDF_CD ) msr |= TIOCM_CAR; 4501 if ( stat2 & CICSCDF_CI ) msr |= TIOCM_RI; 4502 if ( stat2 & CICSCDF_DR ) msr |= TIOCM_DSR; 4503 if ( stat2 & CICSCDF_CS ) msr |= TIOCM_CTS; 4504#if COM_CARRIER_DETECT_EMULATE 4505 if ( msr & (TIOCM_DSR|TIOCM_CTS) ) { 4506 msr |= TIOCM_CAR; 4507 } 4508#endif 4509 } else { 4510 int stat, stat2; 4511 4512 stat = inb(com->sts_port); 4513 stat2 = inb(com->in_modem_port); 4514 if ( !(stat2 & CICSCD_CD) ) msr |= TIOCM_CAR; 4515 if ( !(stat2 & CICSCD_CI) ) msr |= TIOCM_RI; 4516 if ( stat & STS8251_DSR ) msr |= TIOCM_DSR; 4517 if ( !(stat2 & CICSCD_CS) ) msr |= TIOCM_CTS; 4518#if COM_CARRIER_DETECT_EMULATE 4519 if ( msr & (TIOCM_DSR|TIOCM_CTS) ) { 4520 msr |= TIOCM_CAR; 4521 } 4522#endif 4523 } 4524 return(msr); 4525} 4526 4527static void 4528pc98_check_msr(void* chan) 4529{ 4530 int msr, delta; 4531 int s; 4532 register struct tty *tp; 4533 struct com_s *com; 4534 int mynor; 4535 int unit; 4536 dev_t dev; 4537 4538 dev=(dev_t)chan; 4539 mynor = minor(dev); 4540 unit = MINOR_TO_UNIT(mynor); 4541 com = com_addr(unit); 4542 tp = com->tp; 4543 4544 s = spltty(); 4545 msr = pc98_get_modem_status(com); 4546 /* make change flag */ 4547 delta = msr ^ com->pc98_prev_modem_status; 4548 if ( delta & TIOCM_CAR ) { 4549 if ( com->modem_car_chg_timer ) { 4550 if ( -- com->modem_car_chg_timer ) 4551 msr ^= TIOCM_CAR; 4552 } else { 4553 if ((com->modem_car_chg_timer = (msr & TIOCM_CAR) ? 4554 DCD_ON_RECOGNITION : DCD_OFF_TOLERANCE) != 0) 4555 msr ^= TIOCM_CAR; 4556 } 4557 } else 4558 com->modem_car_chg_timer = 0; 4559 delta = ( msr ^ com->pc98_prev_modem_status ) & 4560 (TIOCM_CAR|TIOCM_RI|TIOCM_DSR|TIOCM_CTS); 4561 com->pc98_prev_modem_status = msr; 4562 delta = ( com->pc98_modem_delta |= delta ); 4563 splx(s); 4564 if ( com->modem_checking || (tp->t_state & (TS_ISOPEN)) ) { 4565 if ( delta ) { 4566 commint(dev); 4567 } 4568 timeout(pc98_check_msr, (caddr_t)dev, 4569 PC98_CHECK_MODEM_INTERVAL); 4570 } else { 4571 com->modem_checking = 0; 4572 } 4573} 4574 4575static void 4576pc98_msrint_start(dev_t dev) 4577{ 4578 struct com_s *com; 4579 int mynor; 4580 int unit; 4581 int s = spltty(); 4582 4583 mynor = minor(dev); 4584 unit = MINOR_TO_UNIT(mynor); 4585 com = com_addr(unit); 4586 /* modem control line check routine envoke interval is 1/10 sec */ 4587 if ( com->modem_checking == 0 ) { 4588 com->pc98_prev_modem_status = pc98_get_modem_status(com); 4589 com->pc98_modem_delta = 0; 4590 timeout(pc98_check_msr, (caddr_t)dev, 4591 PC98_CHECK_MODEM_INTERVAL); 4592 com->modem_checking = 1; 4593 } 4594 splx(s); 4595} 4596 4597static void 4598pc98_disable_i8251_interrupt(struct com_s *com, int mod) 4599{ 4600 /* disable interrupt */ 4601 register int tmp; 4602 4603 mod |= ~(IEN_Tx|IEN_TxEMP|IEN_Rx); 4604 COM_INT_DISABLE 4605 tmp = inb( com->intr_ctrl_port ) & ~(IEN_Tx|IEN_TxEMP|IEN_Rx); 4606 outb( com->intr_ctrl_port, (com->intr_enable&=~mod) | tmp ); 4607 COM_INT_ENABLE 4608} 4609 4610static void 4611pc98_enable_i8251_interrupt(struct com_s *com, int mod) 4612{ 4613 register int tmp; 4614 4615 COM_INT_DISABLE 4616 tmp = inb( com->intr_ctrl_port ) & ~(IEN_Tx|IEN_TxEMP|IEN_Rx); 4617 outb( com->intr_ctrl_port, (com->intr_enable|=mod) | tmp ); 4618 COM_INT_ENABLE 4619} 4620 4621static int 4622pc98_check_i8251_interrupt(struct com_s *com) 4623{ 4624 return ( com->intr_enable & 0x07 ); 4625} 4626 4627static void 4628pc98_i8251_clear_cmd(struct com_s *com, int x) 4629{ 4630 int tmp; 4631 4632 COM_INT_DISABLE 4633 tmp = com->pc98_prev_siocmd & ~(x); 4634 if (com->pc98_8251fifo_enable) 4635 outb(I8251F_fcr, 0); 4636 outb(com->cmd_port, tmp); 4637 com->pc98_prev_siocmd = tmp & ~(CMD8251_ER|CMD8251_RESET|CMD8251_EH); 4638 if (com->pc98_8251fifo_enable) 4639 outb(I8251F_fcr, CTRL8251F_ENABLE); 4640 COM_INT_ENABLE 4641} 4642 4643static void 4644pc98_i8251_or_cmd(struct com_s *com, int x) 4645{ 4646 int tmp; 4647 4648 COM_INT_DISABLE 4649 if (com->pc98_8251fifo_enable) 4650 outb(I8251F_fcr, 0); 4651 tmp = com->pc98_prev_siocmd | (x); 4652 outb(com->cmd_port, tmp); 4653 com->pc98_prev_siocmd = tmp & ~(CMD8251_ER|CMD8251_RESET|CMD8251_EH); 4654 if (com->pc98_8251fifo_enable) 4655 outb(I8251F_fcr, CTRL8251F_ENABLE); 4656 COM_INT_ENABLE 4657} 4658 4659static void 4660pc98_i8251_set_cmd(struct com_s *com, int x) 4661{ 4662 int tmp; 4663 4664 COM_INT_DISABLE 4665 if (com->pc98_8251fifo_enable) 4666 outb(I8251F_fcr, 0); 4667 tmp = (x); 4668 outb(com->cmd_port, tmp); 4669 com->pc98_prev_siocmd = tmp & ~(CMD8251_ER|CMD8251_RESET|CMD8251_EH); 4670 if (com->pc98_8251fifo_enable) 4671 outb(I8251F_fcr, CTRL8251F_ENABLE); 4672 COM_INT_ENABLE 4673} 4674 4675static void 4676pc98_i8251_clear_or_cmd(struct com_s *com, int clr, int x) 4677{ 4678 int tmp; 4679 COM_INT_DISABLE 4680 if (com->pc98_8251fifo_enable) 4681 outb(I8251F_fcr, 0); 4682 tmp = com->pc98_prev_siocmd & ~(clr); 4683 tmp |= (x); 4684 outb(com->cmd_port, tmp); 4685 com->pc98_prev_siocmd = tmp & ~(CMD8251_ER|CMD8251_RESET|CMD8251_EH); 4686 if (com->pc98_8251fifo_enable) 4687 outb(I8251F_fcr, CTRL8251F_ENABLE); 4688 COM_INT_ENABLE 4689} 4690 4691static int 4692pc98_i8251_get_cmd(struct com_s *com) 4693{ 4694 return com->pc98_prev_siocmd; 4695} 4696 4697static int 4698pc98_i8251_get_mod(struct com_s *com) 4699{ 4700 return com->pc98_prev_siomod; 4701} 4702 4703static void 4704pc98_i8251_reset(struct com_s *com, int mode, int command) 4705{ 4706 if (com->pc98_8251fifo_enable) 4707 outb(I8251F_fcr, 0); 4708 outb(com->cmd_port, 0); /* dummy */ 4709 DELAY(2); 4710 outb(com->cmd_port, 0); /* dummy */ 4711 DELAY(2); 4712 outb(com->cmd_port, 0); /* dummy */ 4713 DELAY(2); 4714 outb(com->cmd_port, CMD8251_RESET); /* internal reset */ 4715 DELAY(2); 4716 outb(com->cmd_port, mode ); /* mode register */ 4717 com->pc98_prev_siomod = mode; 4718 DELAY(2); 4719 pc98_i8251_set_cmd( com, (command|CMD8251_ER) ); 4720 DELAY(10); 4721 if (com->pc98_8251fifo_enable) 4722 outb(I8251F_fcr, CTRL8251F_ENABLE | 4723 CTRL8251F_XMT_RST | CTRL8251F_RCV_RST); 4724} 4725 4726static void 4727pc98_check_sysclock(void) 4728{ 4729 /* get system clock from port */ 4730 if ( pc98_machine_type & M_8M ) { 4731 /* 8 MHz system & H98 */ 4732 sysclock = 8; 4733 } else { 4734 /* 5 MHz system */ 4735 sysclock = 5; 4736 } 4737} 4738 4739static void 4740com_cflag_and_speed_set( struct com_s *com, int cflag, int speed) 4741{ 4742 int cfcr=0; 4743 int previnterrupt; 4744 u_int count; 4745 4746 if (pc98_ttspeedtab(com, speed, &count) != 0) 4747 return; 4748 4749 previnterrupt = pc98_check_i8251_interrupt(com); 4750 pc98_disable_i8251_interrupt( com, IEN_Tx|IEN_TxEMP|IEN_Rx ); 4751 4752 switch ( cflag&CSIZE ) { 4753 case CS5: 4754 cfcr = MOD8251_5BITS; break; 4755 case CS6: 4756 cfcr = MOD8251_6BITS; break; 4757 case CS7: 4758 cfcr = MOD8251_7BITS; break; 4759 case CS8: 4760 cfcr = MOD8251_8BITS; break; 4761 } 4762 if ( cflag&PARENB ) { 4763 if ( cflag&PARODD ) 4764 cfcr |= MOD8251_PODD; 4765 else 4766 cfcr |= MOD8251_PEVEN; 4767 } else 4768 cfcr |= MOD8251_PDISAB; 4769 4770 if ( cflag&CSTOPB ) 4771 cfcr |= MOD8251_STOP2; 4772 else 4773 cfcr |= MOD8251_STOP1; 4774 4775 if ( count & 0x10000 ) 4776 cfcr |= MOD8251_CLKX1; 4777 else 4778 cfcr |= MOD8251_CLKX16; 4779 4780 if (epson_machine_id != 0x20) { /* XXX */ 4781 int tmp; 4782 while (!((tmp = inb(com->sts_port)) & STS8251_TxEMP)) 4783 ; 4784 } 4785 /* set baud rate from ospeed */ 4786 pc98_set_baud_rate( com, count ); 4787 4788 if ( cfcr != pc98_i8251_get_mod(com) ) 4789 pc98_i8251_reset(com, cfcr, pc98_i8251_get_cmd(com) ); 4790 4791 pc98_enable_i8251_interrupt( com, previnterrupt ); 4792} 4793 4794static int 4795pc98_ttspeedtab(struct com_s *com, int speed, u_int *divisor) 4796{ 4797 int if_type, effect_sp, count = -1, mod; 4798 4799 if_type = com->pc98_if_type & 0x0f; 4800 4801 switch (com->pc98_if_type) { 4802 case COM_IF_INTERNAL: 4803 if (PC98SIO_baud_rate_port(if_type) != -1) { 4804 count = ttspeedtab(speed, if_8251_type[if_type].speedtab); 4805 if (count > 0) { 4806 count |= COM1_EXT_CLOCK; 4807 break; 4808 } 4809 } 4810 4811 /* for *1CLK asynchronous! mode, TEFUTEFU */ 4812 mod = (sysclock == 5) ? 2457600 : 1996800; 4813 effect_sp = ttspeedtab( speed, pc98speedtab ); 4814 if ( effect_sp < 0 ) /* XXX */ 4815 effect_sp = ttspeedtab( (speed - 1), pc98speedtab ); 4816 if ( effect_sp <= 0 ) 4817 return effect_sp; 4818 if ( effect_sp == speed ) 4819 mod /= 16; 4820 if ( mod % effect_sp ) 4821 return(-1); 4822 count = mod / effect_sp; 4823 if ( count > 65535 ) 4824 return(-1); 4825 if ( effect_sp != speed ) 4826 count |= 0x10000; 4827 break; 4828 case COM_IF_PC9861K_1: 4829 case COM_IF_PC9861K_2: 4830 count = 1; 4831 break; 4832 case COM_IF_IND_SS_1: 4833 case COM_IF_IND_SS_2: 4834 case COM_IF_PIO9032B_1: 4835 case COM_IF_PIO9032B_2: 4836 count = ttspeedtab( speed, if_8251_type[if_type].speedtab ); 4837 break; 4838 case COM_IF_B98_01_1: 4839 case COM_IF_B98_01_2: 4840 count = ttspeedtab( speed, if_8251_type[if_type].speedtab ); 4841#ifdef B98_01_OLD 4842 if (count == 0 || count == 1) { 4843 count += 4; 4844 count |= 0x20000; /* x1 mode for 76800 and 153600 */ 4845 } 4846#endif 4847 break; 4848 } 4849 4850 if (count < 0) 4851 return count; 4852 4853 *divisor = (u_int) count; 4854 return 0; 4855} 4856 4857static void 4858pc98_set_baud_rate( struct com_s *com, u_int count ) 4859{ 4860 int if_type, io, s; 4861 4862 if_type = com->pc98_if_type & 0x0f; 4863 io = rman_get_start(com->ioportres) & 0xff00; 4864 4865 switch (com->pc98_if_type) { 4866 case COM_IF_INTERNAL: 4867 if (PC98SIO_baud_rate_port(if_type) != -1) { 4868 if (count & COM1_EXT_CLOCK) { 4869 outb((Port_t)PC98SIO_baud_rate_port(if_type), count & 0xff); 4870 break; 4871 } else { 4872 outb((Port_t)PC98SIO_baud_rate_port(if_type), 0x09); 4873 } 4874 } 4875 4876 if (count == 0) 4877 return; 4878 4879 /* set i8253 */ 4880 s = splclock(); 4881 if (count != 3) 4882 outb( 0x77, 0xb6 ); 4883 else 4884 outb( 0x77, 0xb4 ); 4885 outb( 0x5f, 0); 4886 outb( 0x75, count & 0xff ); 4887 outb( 0x5f, 0); 4888 outb( 0x75, (count >> 8) & 0xff ); 4889 splx(s); 4890 break; 4891 case COM_IF_IND_SS_1: 4892 case COM_IF_IND_SS_2: 4893 outb(io | PC98SIO_intr_ctrl_port(if_type), 0); 4894 outb(io | PC98SIO_baud_rate_port(if_type), 0); 4895 outb(io | PC98SIO_baud_rate_port(if_type), 0xc0); 4896 outb(io | PC98SIO_baud_rate_port(if_type), (count >> 8) | 0x80); 4897 outb(io | PC98SIO_baud_rate_port(if_type), count & 0xff); 4898 break; 4899 case COM_IF_PIO9032B_1: 4900 case COM_IF_PIO9032B_2: 4901 outb(io | PC98SIO_baud_rate_port(if_type), count); 4902 break; 4903 case COM_IF_B98_01_1: 4904 case COM_IF_B98_01_2: 4905 outb(io | PC98SIO_baud_rate_port(if_type), count & 0x0f); 4906#ifdef B98_01_OLD 4907 /* 4908 * Some old B98_01 board should be controlled 4909 * in different way, but this hasn't been tested yet. 4910 */ 4911 outb(io | PC98SIO_func_port(if_type), 4912 (count & 0x20000) ? 0xf0 : 0xf2); 4913#endif 4914 break; 4915 } 4916} 4917static int 4918pc98_check_if_type(device_t dev, struct siodev *iod) 4919{ 4920 int irr, io, if_type, tmp; 4921 static short irq_tab[2][8] = { 4922 { 3, 5, 6, 9, 10, 12, 13, -1}, 4923 { 3, 10, 12, 13, 5, 6, 9, -1} 4924 }; 4925 4926 if_type = iod->if_type & 0x0f; 4927 iod->irq = 0; 4928 io = isa_get_port(dev) & 0xff00; 4929 4930 if (IS_8251(iod->if_type)) { 4931 if (PC98SIO_func_port(if_type) != -1) { 4932 outb(io | PC98SIO_func_port(if_type), 0xf2); 4933 tmp = ttspeedtab(9600, if_8251_type[if_type].speedtab); 4934 if (tmp != -1 && PC98SIO_baud_rate_port(if_type) != -1) 4935 outb(io | PC98SIO_baud_rate_port(if_type), tmp); 4936 } 4937 4938 iod->cmd = io | PC98SIO_cmd_port(if_type); 4939 iod->sts = io | PC98SIO_sts_port(if_type); 4940 iod->mod = io | PC98SIO_in_modem_port(if_type); 4941 iod->ctrl = io | PC98SIO_intr_ctrl_port(if_type); 4942 4943 if (iod->if_type == COM_IF_INTERNAL) { 4944 iod->irq = 4; 4945 4946 if (pc98_check_8251vfast()) { 4947 PC98SIO_baud_rate_port(if_type) = I8251F_div; 4948 if_8251_type[if_type].speedtab = pc98fast_speedtab; 4949 } 4950 } else { 4951 tmp = inb( iod->mod ) & if_8251_type[if_type].irr_mask; 4952 if ((isa_get_port(dev) & 0xff) == IO_COM2) 4953 iod->irq = irq_tab[0][tmp]; 4954 else 4955 iod->irq = irq_tab[1][tmp]; 4956 } 4957 } else { 4958 irr = if_16550a_type[if_type].irr_read; 4959#ifdef COM_MULTIPORT 4960 if (!COM_ISMULTIPORT(device_get_flags(dev)) || 4961 device_get_unit(dev) == COM_MPMASTER(device_get_flags(dev))) 4962#endif 4963 if (irr != -1) { 4964 tmp = inb(io | irr); 4965 if (isa_get_port(dev) & 0x01) /* XXX depend on RSB-384 */ 4966 iod->irq = irq_tab[1][tmp >> 3]; 4967 else 4968 iod->irq = irq_tab[0][tmp & 0x07]; 4969 } 4970 } 4971 if ( iod->irq == -1 ) return -1; 4972 4973 return 0; 4974} 4975static void 4976pc98_set_ioport(struct com_s *com) 4977{ 4978 int if_type = com->pc98_if_type & 0x0f; 4979 Port_t io = rman_get_start(com->ioportres) & 0xff00; 4980 4981 pc98_check_sysclock(); 4982 com->data_port = io | PC98SIO_data_port(if_type); 4983 com->cmd_port = io | PC98SIO_cmd_port(if_type); 4984 com->sts_port = io | PC98SIO_sts_port(if_type); 4985 com->in_modem_port = io | PC98SIO_in_modem_port(if_type); 4986 com->intr_ctrl_port = io | PC98SIO_intr_ctrl_port(if_type); 4987} 4988static int 4989pc98_check_8251vfast(void) 4990{ 4991 int i; 4992 4993 outb(I8251F_div, 0x8c); 4994 DELAY(10); 4995 for (i = 0; i < 100; i++) { 4996 if ((inb(I8251F_div) & 0x80) != 0) { 4997 i = 0; 4998 break; 4999 } 5000 DELAY(1); 5001 } 5002 outb(I8251F_div, 0); 5003 DELAY(10); 5004 for (; i < 100; i++) { 5005 if ((inb(I8251F_div) & 0x80) == 0) 5006 return 1; 5007 DELAY(1); 5008 } 5009 5010 return 0; 5011} 5012static int 5013pc98_check_8251fifo(void) 5014{ 5015 u_char tmp1, tmp2; 5016 5017 tmp1 = inb(I8251F_iir); 5018 DELAY(10); 5019 tmp2 = inb(I8251F_iir); 5020 if (((tmp1 ^ tmp2) & 0x40) != 0 && ((tmp1 | tmp2) & 0x20) == 0) 5021 return 1; 5022 5023 return 0; 5024} 5025#endif /* PC98 defined */ 5026