sio.c revision 60472
1/*- 2 * Copyright (c) 1991 The Regents of the University of California. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by the University of 16 * California, Berkeley and its contributors. 17 * 4. Neither the name of the University nor the names of its contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 25 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 31 * SUCH DAMAGE. 32 * 33 * $FreeBSD: head/sys/pc98/cbus/sio.c 60472 2000-05-12 12:38:25Z nyan $ 34 * from: @(#)com.c 7.5 (Berkeley) 5/16/91 35 * from: i386/isa sio.c,v 1.234 36 */ 37 38#include "opt_comconsole.h" 39#include "opt_compat.h" 40#include "opt_ddb.h" 41#include "opt_sio.h" 42#include "card.h" 43#include "pci.h" 44#include "sio.h" 45 46/* 47 * Serial driver, based on 386BSD-0.1 com driver. 48 * Mostly rewritten to use pseudo-DMA. 49 * Works for National Semiconductor NS8250-NS16550AF UARTs. 50 * COM driver, based on HP dca driver. 51 * 52 * Changes for PC-Card integration: 53 * - Added PC-Card driver table and handlers 54 */ 55/*=============================================================== 56 * 386BSD(98),FreeBSD-1.1x(98) com driver. 57 * ----- 58 * modified for PC9801 by M.Ishii 59 * Kyoto University Microcomputer Club (KMC) 60 * Chou "TEFUTEFU" Hirotomi 61 * Kyoto Univ. the faculty of medicine 62 *=============================================================== 63 * FreeBSD-2.0.1(98) sio driver. 64 * ----- 65 * modified for pc98 Internal i8251 and MICRO CORE MC16550II 66 * T.Koike(hfc01340@niftyserve.or.jp) 67 * implement kernel device configuration 68 * aizu@orient.center.nitech.ac.jp 69 * 70 * Notes. 71 * ----- 72 * PC98 localization based on 386BSD(98) com driver. Using its PC98 local 73 * functions. 74 * This driver is under debugging,has bugs. 75 * 76 * 1) config 77 * options COM_MULTIPORT #if using MC16550II 78 * device sio0 at nec? port 0x30 tty irq 4 #internal 79 * device sio1 at nec? port 0xd2 tty irq 5 flags 0x101 #mc1 80 * device sio2 at nec? port 0x8d2 tty flags 0x101 #mc2 81 * # ~~~~~iobase ~~multi port flag 82 * # ~ master device is sio1 83 * 2) device 84 * cd /dev; MAKEDEV ttyd0 ttyd1 .. 85 * 3) /etc/rc.serial 86 * 57600bps is too fast for sio0(internal8251) 87 * my ex. 88 * #set default speed 9600 89 * modem() 90 * : 91 * stty </dev/ttyid$i crtscts 9600 92 * : # ~~~~ default speed(can change after init.) 93 * modem 0 1 2 94 * 4) COMCONSOLE 95 * not changed. 96 * 5) PC9861K,PIO9032B,B98_01 97 * not tested. 98 */ 99/* 100 * modified for AIWA B98-01 101 * by T.Hatanou <hatanou@yasuda.comm.waseda.ac.jp> last update: 15 Sep.1995 102 * 103 * How to configure... 104 * # options COM_MULTIPORT # support for MICROCORE MC16550II 105 * ... comment-out this line, which will conflict with B98_01. 106 * options "B98_01" # support for AIWA B98-01 107 * device sio1 at nec? port 0x00d1 tty irq ? 108 * device sio2 at nec? port 0x00d5 tty irq ? 109 * ... you can leave these lines `irq ?', irq will be autodetected. 110 */ 111/* 112 * Modified by Y.Takahashi of Kogakuin University. 113 */ 114/* 115 * modified for 8251(FIFO) by Seigo TANIMURA <tanimura@FreeBSD.org> 116 */ 117 118#ifdef PC98 119#define COM_IF_INTERNAL 0x00 120#define COM_IF_PC9861K_1 0x01 121#define COM_IF_PC9861K_2 0x02 122#define COM_IF_IND_SS_1 0x03 123#define COM_IF_IND_SS_2 0x04 124#define COM_IF_PIO9032B_1 0x05 125#define COM_IF_PIO9032B_2 0x06 126#define COM_IF_B98_01_1 0x07 127#define COM_IF_B98_01_2 0x08 128#define COM_IF_END1 COM_IF_B98_01_2 129#define COM_IF_RSA98 0x10 /* same as COM_IF_NS16550 */ 130#define COM_IF_NS16550 0x11 131#define COM_IF_SECOND_CCU 0x12 /* same as COM_IF_NS16550 */ 132#define COM_IF_MC16550II 0x13 133#define COM_IF_MCRS98 0x14 /* same as COM_IF_MC16550II */ 134#define COM_IF_RSB3000 0x15 135#define COM_IF_RSB384 0x16 136#define COM_IF_MODEM_CARD 0x17 /* same as COM_IF_NS16550 */ 137#define COM_IF_RSA98III 0x18 138#define COM_IF_ESP98 0x19 139#define COM_IF_END2 COM_IF_ESP98 140#endif /* PC98 */ 141 142#include <sys/param.h> 143#include <sys/systm.h> 144#include <sys/reboot.h> 145#include <sys/malloc.h> 146#include <sys/tty.h> 147#include <sys/proc.h> 148#include <sys/module.h> 149#include <sys/conf.h> 150#include <sys/dkstat.h> 151#include <sys/fcntl.h> 152#include <sys/interrupt.h> 153#include <sys/kernel.h> 154#include <sys/syslog.h> 155#include <sys/sysctl.h> 156#include <sys/bus.h> 157#include <machine/bus.h> 158#include <sys/rman.h> 159#include <sys/timetc.h> 160#include <sys/timepps.h> 161 162#ifdef PC98 163#include <pc98/pc98/pc98.h> 164#include <pc98/pc98/pc98_machdep.h> 165#include <i386/isa/ic/i8251.h> 166#else 167#include <isa/isareg.h> 168#endif 169#include <isa/isavar.h> 170#if NPCI > 0 171#include <pci/pcireg.h> 172#include <pci/pcivar.h> 173#endif 174#include <machine/lock.h> 175 176#include <machine/clock.h> 177#include <machine/ipl.h> 178#ifndef SMP 179#include <machine/lock.h> 180#endif 181#include <machine/resource.h> 182 183#include <isa/sioreg.h> 184 185#ifdef COM_ESP 186#include <i386/isa/ic/esp.h> 187#endif 188#include <i386/isa/ic/ns16550.h> 189#ifdef PC98 190#include <i386/isa/ic/rsa.h> 191#endif 192 193#ifndef __i386__ 194#define disable_intr() 195#define enable_intr() 196#endif 197 198#ifdef SMP 199#define disable_intr() COM_DISABLE_INTR() 200#define enable_intr() COM_ENABLE_INTR() 201#endif /* SMP */ 202 203#define LOTS_OF_EVENTS 64 /* helps separate urgent events from input */ 204 205#define CALLOUT_MASK 0x80 206#define CONTROL_MASK 0x60 207#define CONTROL_INIT_STATE 0x20 208#define CONTROL_LOCK_STATE 0x40 209#define DEV_TO_UNIT(dev) (MINOR_TO_UNIT(minor(dev))) 210#define MINOR_MAGIC_MASK (CALLOUT_MASK | CONTROL_MASK) 211#define MINOR_TO_UNIT(mynor) ((mynor) & ~MINOR_MAGIC_MASK) 212 213#ifdef COM_MULTIPORT 214/* checks in flags for multiport and which is multiport "master chip" 215 * for a given card 216 */ 217#define COM_ISMULTIPORT(flags) ((flags) & 0x01) 218#define COM_MPMASTER(flags) (((flags) >> 8) & 0x0ff) 219#define COM_NOTAST4(flags) ((flags) & 0x04) 220#endif /* COM_MULTIPORT */ 221 222#define COM_CONSOLE(flags) ((flags) & 0x10) 223#define COM_FORCECONSOLE(flags) ((flags) & 0x20) 224#define COM_LLCONSOLE(flags) ((flags) & 0x40) 225#define COM_DEBUGGER(flags) ((flags) & 0x80) 226#define COM_LOSESOUTINTS(flags) ((flags) & 0x08) 227#define COM_NOFIFO(flags) ((flags) & 0x02) 228#define COM_ST16650A(flags) ((flags) & 0x20000) 229#define COM_C_NOPROBE (0x40000) 230#define COM_NOPROBE(flags) ((flags) & COM_C_NOPROBE) 231#define COM_C_IIR_TXRDYBUG (0x80000) 232#define COM_IIR_TXRDYBUG(flags) ((flags) & COM_C_IIR_TXRDYBUG) 233#define COM_FIFOSIZE(flags) (((flags) & 0xff000000) >> 24) 234 235#ifdef PC98 236#define com_emr com_msr /* Extension mode register for RSB-2000/3000 */ 237#endif 238#define com_scr 7 /* scratch register for 16450-16550 (R/W) */ 239 240#define sio_getreg(com, off) \ 241 (bus_space_read_1((com)->bst, (com)->bsh, (off))) 242#define sio_setreg(com, off, value) \ 243 (bus_space_write_1((com)->bst, (com)->bsh, (off), (value))) 244 245/* 246 * com state bits. 247 * (CS_BUSY | CS_TTGO) and (CS_BUSY | CS_TTGO | CS_ODEVREADY) must be higher 248 * than the other bits so that they can be tested as a group without masking 249 * off the low bits. 250 * 251 * The following com and tty flags correspond closely: 252 * CS_BUSY = TS_BUSY (maintained by comstart(), siopoll() and 253 * comstop()) 254 * CS_TTGO = ~TS_TTSTOP (maintained by comparam() and comstart()) 255 * CS_CTS_OFLOW = CCTS_OFLOW (maintained by comparam()) 256 * CS_RTS_IFLOW = CRTS_IFLOW (maintained by comparam()) 257 * TS_FLUSH is not used. 258 * XXX I think TIOCSETA doesn't clear TS_TTSTOP when it clears IXON. 259 * XXX CS_*FLOW should be CF_*FLOW in com->flags (control flags not state). 260 */ 261#define CS_BUSY 0x80 /* output in progress */ 262#define CS_TTGO 0x40 /* output not stopped by XOFF */ 263#define CS_ODEVREADY 0x20 /* external device h/w ready (CTS) */ 264#define CS_CHECKMSR 1 /* check of MSR scheduled */ 265#define CS_CTS_OFLOW 2 /* use CTS output flow control */ 266#define CS_DTR_OFF 0x10 /* DTR held off */ 267#define CS_ODONE 4 /* output completed */ 268#define CS_RTS_IFLOW 8 /* use RTS input flow control */ 269#define CSE_BUSYCHECK 1 /* siobusycheck() scheduled */ 270 271static char const * const error_desc[] = { 272#define CE_OVERRUN 0 273 "silo overflow", 274#define CE_INTERRUPT_BUF_OVERFLOW 1 275 "interrupt-level buffer overflow", 276#define CE_TTY_BUF_OVERFLOW 2 277 "tty-level buffer overflow", 278}; 279 280#define CE_NTYPES 3 281#define CE_RECORD(com, errnum) (++(com)->delta_error_counts[errnum]) 282 283/* types. XXX - should be elsewhere */ 284typedef u_int Port_t; /* hardware port */ 285typedef u_char bool_t; /* boolean */ 286 287/* queue of linear buffers */ 288struct lbq { 289 u_char *l_head; /* next char to process */ 290 u_char *l_tail; /* one past the last char to process */ 291 struct lbq *l_next; /* next in queue */ 292 bool_t l_queued; /* nonzero if queued */ 293}; 294 295/* com device structure */ 296struct com_s { 297 u_int flags; /* Copy isa device flags */ 298 u_char state; /* miscellaneous flag bits */ 299 bool_t active_out; /* nonzero if the callout device is open */ 300 u_char cfcr_image; /* copy of value written to CFCR */ 301#ifdef COM_ESP 302 bool_t esp; /* is this unit a hayes esp board? */ 303#endif 304 u_char extra_state; /* more flag bits, separate for order trick */ 305 u_char fifo_image; /* copy of value written to FIFO */ 306 bool_t hasfifo; /* nonzero for 16550 UARTs */ 307 bool_t st16650a; /* Is a Startech 16650A or RTS/CTS compat */ 308 bool_t loses_outints; /* nonzero if device loses output interrupts */ 309 u_char mcr_image; /* copy of value written to MCR */ 310#ifdef COM_MULTIPORT 311 bool_t multiport; /* is this unit part of a multiport device? */ 312#endif /* COM_MULTIPORT */ 313 bool_t no_irq; /* nonzero if irq is not attached */ 314 bool_t gone; /* hardware disappeared */ 315 bool_t poll; /* nonzero if polling is required */ 316 bool_t poll_output; /* nonzero if polling for output is required */ 317 int unit; /* unit number */ 318 int dtr_wait; /* time to hold DTR down on close (* 1/hz) */ 319 u_int tx_fifo_size; 320 u_int wopeners; /* # processes waiting for DCD in open() */ 321 322 /* 323 * The high level of the driver never reads status registers directly 324 * because there would be too many side effects to handle conveniently. 325 * Instead, it reads copies of the registers stored here by the 326 * interrupt handler. 327 */ 328 u_char last_modem_status; /* last MSR read by intr handler */ 329 u_char prev_modem_status; /* last MSR handled by high level */ 330 331 u_char hotchar; /* ldisc-specific char to be handled ASAP */ 332 u_char *ibuf; /* start of input buffer */ 333 u_char *ibufend; /* end of input buffer */ 334 u_char *ibufold; /* old input buffer, to be freed */ 335 u_char *ihighwater; /* threshold in input buffer */ 336 u_char *iptr; /* next free spot in input buffer */ 337 int ibufsize; /* size of ibuf (not include error bytes) */ 338 int ierroff; /* offset of error bytes in ibuf */ 339 340 struct lbq obufq; /* head of queue of output buffers */ 341 struct lbq obufs[2]; /* output buffers */ 342 343 bus_space_tag_t bst; 344 bus_space_handle_t bsh; 345 346#ifdef PC98 347 Port_t cmd_port; 348 Port_t sts_port; 349 Port_t in_modem_port; 350 Port_t intr_ctrl_port; 351 Port_t rsabase; /* iobase address of a I/O-DATA RSA board */ 352 int intr_enable; 353 int pc98_prev_modem_status; 354 int pc98_modem_delta; 355 int modem_car_chg_timer; 356 int pc98_prev_siocmd; 357 int pc98_prev_siomod; 358 int modem_checking; 359 int pc98_if_type; 360 361 bool_t pc98_8251fifo; 362 bool_t pc98_8251fifo_enable; 363#endif /* PC98 */ 364 Port_t data_port; /* i/o ports */ 365#ifdef COM_ESP 366 Port_t esp_port; 367#endif 368 Port_t int_id_port; 369 Port_t modem_ctl_port; 370 Port_t line_status_port; 371 Port_t modem_status_port; 372 Port_t intr_ctl_port; /* Ports of IIR register */ 373 374 struct tty *tp; /* cross reference */ 375 376 /* Initial state. */ 377 struct termios it_in; /* should be in struct tty */ 378 struct termios it_out; 379 380 /* Lock state. */ 381 struct termios lt_in; /* should be in struct tty */ 382 struct termios lt_out; 383 384 bool_t do_timestamp; 385 bool_t do_dcd_timestamp; 386 struct timeval timestamp; 387 struct timeval dcd_timestamp; 388 struct pps_state pps; 389 390 u_long bytes_in; /* statistics */ 391 u_long bytes_out; 392 u_int delta_error_counts[CE_NTYPES]; 393 u_long error_counts[CE_NTYPES]; 394 395 struct resource *irqres; 396 struct resource *ioportres; 397 void *cookie; 398 399 /* 400 * Data area for output buffers. Someday we should build the output 401 * buffer queue without copying data. 402 */ 403#ifdef PC98 404 int obufsize; 405 u_char *obuf1; 406 u_char *obuf2; 407#else 408 u_char obuf1[256]; 409 u_char obuf2[256]; 410#endif 411}; 412 413#ifdef COM_ESP 414static int espattach __P((struct com_s *com, Port_t esp_port)); 415#endif 416static int sioattach __P((device_t dev, int rid)); 417static int sio_isa_attach __P((device_t dev)); 418 419static timeout_t siobusycheck; 420static timeout_t siodtrwakeup; 421static void comhardclose __P((struct com_s *com)); 422static void sioinput __P((struct com_s *com)); 423static void siointr1 __P((struct com_s *com)); 424static void siointr __P((void *arg)); 425static int commctl __P((struct com_s *com, int bits, int how)); 426static int comparam __P((struct tty *tp, struct termios *t)); 427static swihand_t siopoll; 428static int sioprobe __P((device_t dev, int xrid)); 429static int sio_isa_probe __P((device_t dev)); 430static void siosettimeout __P((void)); 431static int siosetwater __P((struct com_s *com, speed_t speed)); 432static void comstart __P((struct tty *tp)); 433static void comstop __P((struct tty *tp, int rw)); 434static timeout_t comwakeup; 435static void disc_optim __P((struct tty *tp, struct termios *t, 436 struct com_s *com)); 437 438#if NCARD > 0 439static int sio_pccard_attach __P((device_t dev)); 440static int sio_pccard_detach __P((device_t dev)); 441static int sio_pccard_probe __P((device_t dev)); 442#endif /* NCARD > 0 */ 443 444#if NPCI > 0 445static int sio_pci_attach __P((device_t dev)); 446static void sio_pci_kludge_unit __P((device_t dev)); 447static int sio_pci_probe __P((device_t dev)); 448#endif /* NPCI > 0 */ 449 450static char driver_name[] = "sio"; 451 452/* table and macro for fast conversion from a unit number to its com struct */ 453static devclass_t sio_devclass; 454#define com_addr(unit) ((struct com_s *) \ 455 devclass_get_softc(sio_devclass, unit)) 456 457static device_method_t sio_isa_methods[] = { 458 /* Device interface */ 459 DEVMETHOD(device_probe, sio_isa_probe), 460 DEVMETHOD(device_attach, sio_isa_attach), 461 462 { 0, 0 } 463}; 464 465static driver_t sio_isa_driver = { 466 driver_name, 467 sio_isa_methods, 468 sizeof(struct com_s), 469}; 470 471#if NCARD > 0 472static device_method_t sio_pccard_methods[] = { 473 /* Device interface */ 474 DEVMETHOD(device_probe, sio_pccard_probe), 475 DEVMETHOD(device_attach, sio_pccard_attach), 476 DEVMETHOD(device_detach, sio_pccard_detach), 477 478 { 0, 0 } 479}; 480 481static driver_t sio_pccard_driver = { 482 driver_name, 483 sio_pccard_methods, 484 sizeof(struct com_s), 485}; 486#endif /* NCARD > 0 */ 487 488#if NPCI > 0 489static device_method_t sio_pci_methods[] = { 490 /* Device interface */ 491 DEVMETHOD(device_probe, sio_pci_probe), 492 DEVMETHOD(device_attach, sio_pci_attach), 493 494 { 0, 0 } 495}; 496 497static driver_t sio_pci_driver = { 498 driver_name, 499 sio_pci_methods, 500 sizeof(struct com_s), 501}; 502#endif /* NPCI > 0 */ 503 504static d_open_t sioopen; 505static d_close_t sioclose; 506static d_read_t sioread; 507static d_write_t siowrite; 508static d_ioctl_t sioioctl; 509 510#define CDEV_MAJOR 28 511static struct cdevsw sio_cdevsw = { 512 /* open */ sioopen, 513 /* close */ sioclose, 514 /* read */ sioread, 515 /* write */ siowrite, 516 /* ioctl */ sioioctl, 517 /* poll */ ttypoll, 518 /* mmap */ nommap, 519 /* strategy */ nostrategy, 520 /* name */ driver_name, 521 /* maj */ CDEV_MAJOR, 522 /* dump */ nodump, 523 /* psize */ nopsize, 524 /* flags */ D_TTY, 525 /* bmaj */ -1 526}; 527 528int comconsole = -1; 529static volatile speed_t comdefaultrate = CONSPEED; 530#ifdef __alpha__ 531static volatile speed_t gdbdefaultrate = CONSPEED; 532#endif 533static u_int com_events; /* input chars + weighted output completions */ 534static Port_t siocniobase; 535static int siocnunit; 536static Port_t siogdbiobase; 537static int siogdbunit = -1; 538static bool_t sio_registered; 539static int sio_timeout; 540static int sio_timeouts_until_log; 541static struct callout_handle sio_timeout_handle 542 = CALLOUT_HANDLE_INITIALIZER(&sio_timeout_handle); 543static int sio_numunits; 544 545#ifdef PC98 546struct siodev { 547 short if_type; 548 short irq; 549 Port_t cmd, sts, ctrl, mod; 550}; 551static int sysclock; 552 553#define COM_INT_DISABLE {int previpri; previpri=spltty(); 554#define COM_INT_ENABLE splx(previpri);} 555#define IEN_TxFLAG IEN_Tx 556 557#define COM_CARRIER_DETECT_EMULATE 0 558#define PC98_CHECK_MODEM_INTERVAL (hz/10) 559#define DCD_OFF_TOLERANCE 2 560#define DCD_ON_RECOGNITION 2 561#define GET_IFTYPE(flags) ((flags >> 24) & 0x1f) 562#define SET_IFTYPE(type) (type << 24) 563#define IS_8251(if_type) (!(if_type & 0x10)) 564#define COM1_EXT_CLOCK 0x40000 565 566static void commint __P((dev_t dev)); 567static void com_tiocm_set __P((struct com_s *com, int msr)); 568static void com_tiocm_bis __P((struct com_s *com, int msr)); 569static void com_tiocm_bic __P((struct com_s *com, int msr)); 570static int com_tiocm_get __P((struct com_s *com)); 571static int com_tiocm_get_delta __P((struct com_s *com)); 572static void pc98_msrint_start __P((dev_t dev)); 573static void com_cflag_and_speed_set __P((struct com_s *com, int cflag, int speed)); 574static int pc98_ttspeedtab __P((struct com_s *com, int speed)); 575static int pc98_get_modem_status __P((struct com_s *com)); 576static timeout_t pc98_check_msr; 577static void pc98_set_baud_rate __P((struct com_s *com, int count)); 578static void pc98_i8251_reset __P((struct com_s *com, int mode, int command)); 579static void pc98_disable_i8251_interrupt __P((struct com_s *com, int mod)); 580static void pc98_enable_i8251_interrupt __P((struct com_s *com, int mod)); 581static int pc98_check_i8251_interrupt __P((struct com_s *com)); 582static int pc98_i8251_get_cmd __P((struct com_s *com)); 583static int pc98_i8251_get_mod __P((struct com_s *com)); 584static void pc98_i8251_set_cmd __P((struct com_s *com, int x)); 585static void pc98_i8251_or_cmd __P((struct com_s *com, int x)); 586static void pc98_i8251_clear_cmd __P((struct com_s *com, int x)); 587static void pc98_i8251_clear_or_cmd __P((struct com_s *com, int clr, int x)); 588static int pc98_check_if_type __P((device_t dev, struct siodev *iod)); 589static int pc98_check_8251vfast __P((void)); 590static int pc98_check_8251fifo __P((void)); 591static void pc98_check_sysclock __P((void)); 592static void pc98_set_ioport __P((struct com_s *com)); 593 594#define com_int_Tx_disable(com) \ 595 pc98_disable_i8251_interrupt(com,IEN_Tx|IEN_TxEMP) 596#define com_int_Tx_enable(com) \ 597 pc98_enable_i8251_interrupt(com,IEN_TxFLAG) 598#define com_int_Rx_disable(com) \ 599 pc98_disable_i8251_interrupt(com,IEN_Rx) 600#define com_int_Rx_enable(com) \ 601 pc98_enable_i8251_interrupt(com,IEN_Rx) 602#define com_int_TxRx_disable(com) \ 603 pc98_disable_i8251_interrupt(com,IEN_Tx|IEN_TxEMP|IEN_Rx) 604#define com_int_TxRx_enable(com) \ 605 pc98_enable_i8251_interrupt(com,IEN_TxFLAG|IEN_Rx) 606#define com_send_break_on(com) \ 607 pc98_i8251_or_cmd(com,CMD8251_SBRK) 608#define com_send_break_off(com) \ 609 pc98_i8251_clear_cmd(com,CMD8251_SBRK) 610 611static struct speedtab pc98speedtab[] = { /* internal RS232C interface */ 612 { 0, 0, }, 613 { 50, 50, }, 614 { 75, 75, }, 615 { 150, 150, }, 616 { 200, 200, }, 617 { 300, 300, }, 618 { 600, 600, }, 619 { 1200, 1200, }, 620 { 2400, 2400, }, 621 { 4800, 4800, }, 622 { 9600, 9600, }, 623 { 19200, 19200, }, 624 { 38400, 38400, }, 625 { 51200, 51200, }, 626 { 76800, 76800, }, 627 { 20800, 20800, }, 628 { 31200, 31200, }, 629 { 41600, 41600, }, 630 { 62400, 62400, }, 631 { -1, -1 } 632}; 633static struct speedtab pc98fast_speedtab[] = { 634 { 9600, 0x80 | COMBRD(9600), }, 635 { 19200, 0x80 | COMBRD(19200), }, 636 { 38400, 0x80 | COMBRD(38400), }, 637 { 57600, 0x80 | COMBRD(57600), }, 638 { 115200, 0x80 | COMBRD(115200), }, 639 { -1, -1 } 640}; 641static struct speedtab comspeedtab_pio9032b[] = { 642 { 300, 6, }, 643 { 600, 5, }, 644 { 1200, 4, }, 645 { 2400, 3, }, 646 { 4800, 2, }, 647 { 9600, 1, }, 648 { 19200, 0, }, 649 { 38400, 7, }, 650 { -1, -1 } 651}; 652static struct speedtab comspeedtab_b98_01[] = { 653 { 75, 11, }, 654 { 150, 10, }, 655 { 300, 9, }, 656 { 600, 8, }, 657 { 1200, 7, }, 658 { 2400, 6, }, 659 { 4800, 5, }, 660 { 9600, 4, }, 661 { 19200, 3, }, 662 { 38400, 2, }, 663 { 76800, 1, }, 664 { 153600, 0, }, 665 { -1, -1 } 666}; 667static struct speedtab comspeedtab_mc16550[] = { 668 { 300, 1536, }, 669 { 600, 768, }, 670 { 1200, 384, }, 671 { 2400, 192, }, 672 { 4800, 96, }, 673 { 9600, 48, }, 674 { 19200, 24, }, 675 { 38400, 12, }, 676 { 57600, 8, }, 677 { 115200, 4, }, 678 { 153600, 3, }, 679 { 230400, 2, }, 680 { 460800, 1, }, 681 { -1, -1 } 682}; 683static struct speedtab comspeedtab_rsb384[] = { 684 { 300, 3840, }, 685 { 600, 1920, }, 686 { 1200, 960, }, 687 { 2400, 480, }, 688 { 4800, 240, }, 689 { 9600, 120, }, 690 { 19200, 60, }, 691 { 38400, 30, }, 692 { 57600, 20, }, 693 { 115200, 10, }, 694 { 128000, 9, }, 695 { 144000, 8, }, 696 { 192000, 6, }, 697 { 230400, 5, }, 698 { 288000, 4, }, 699 { 384000, 3, }, 700 { 576000, 2, }, 701 { 1152000, 1, }, 702 { -1, -1 } 703}; 704static struct speedtab comspeedtab_rsa[] = { 705 { 0, 0 }, 706 { 50, COMBRD_RSA(50) }, 707 { 75, COMBRD_RSA(75) }, 708 { 110, COMBRD_RSA(110) }, 709 { 134, COMBRD_RSA(134) }, 710 { 150, COMBRD_RSA(150) }, 711 { 200, COMBRD_RSA(200) }, 712 { 300, COMBRD_RSA(300) }, 713 { 600, COMBRD_RSA(600) }, 714 { 1200, COMBRD_RSA(1200) }, 715 { 1800, COMBRD_RSA(1800) }, 716 { 2400, COMBRD_RSA(2400) }, 717 { 4800, COMBRD_RSA(4800) }, 718 { 9600, COMBRD_RSA(9600) }, 719 { 19200, COMBRD_RSA(19200) }, 720 { 38400, COMBRD_RSA(38400) }, 721 { 57600, COMBRD_RSA(57600) }, 722 { 115200, COMBRD_RSA(115200) }, 723 { 230400, COMBRD_RSA(230400) }, 724 { 460800, COMBRD_RSA(460800) }, 725 { 921600, COMBRD_RSA(921600) }, 726 { -1, -1 } 727}; 728#endif /* PC98 */ 729 730static struct speedtab comspeedtab[] = { 731 { 0, 0 }, 732 { 50, COMBRD(50) }, 733 { 75, COMBRD(75) }, 734 { 110, COMBRD(110) }, 735 { 134, COMBRD(134) }, 736 { 150, COMBRD(150) }, 737 { 200, COMBRD(200) }, 738 { 300, COMBRD(300) }, 739 { 600, COMBRD(600) }, 740 { 1200, COMBRD(1200) }, 741 { 1800, COMBRD(1800) }, 742 { 2400, COMBRD(2400) }, 743 { 4800, COMBRD(4800) }, 744 { 9600, COMBRD(9600) }, 745 { 19200, COMBRD(19200) }, 746 { 38400, COMBRD(38400) }, 747 { 57600, COMBRD(57600) }, 748 { 115200, COMBRD(115200) }, 749 { -1, -1 } 750}; 751 752#ifdef PC98 753struct { 754 char *name; 755 short port_table[7]; 756 short irr_mask; 757 struct speedtab *speedtab; 758 short check_irq; 759} if_8251_type[] = { 760 /* COM_IF_INTERNAL */ 761 { " (internal)", {0x30, 0x32, 0x32, 0x33, 0x35, -1, -1}, 762 -1, pc98speedtab, 1 }, 763 /* COM_IF_PC9861K_1 */ 764 { " (PC9861K)", {0xb1, 0xb3, 0xb3, 0xb0, 0xb0, -1, -1}, 765 3, NULL, 1 }, 766 /* COM_IF_PC9861K_2 */ 767 { " (PC9861K)", {0xb9, 0xbb, 0xbb, 0xb2, 0xb2, -1, -1}, 768 3, NULL, 1 }, 769 /* COM_IF_IND_SS_1 */ 770 { " (IND-SS)", {0xb1, 0xb3, 0xb3, 0xb0, 0xb0, 0xb3, -1}, 771 3, comspeedtab_mc16550, 1 }, 772 /* COM_IF_IND_SS_2 */ 773 { " (IND-SS)", {0xb9, 0xbb, 0xbb, 0xb2, 0xb2, 0xbb, -1}, 774 3, comspeedtab_mc16550, 1 }, 775 /* COM_IF_PIO9032B_1 */ 776 { " (PIO9032B)", {0xb1, 0xb3, 0xb3, 0xb0, 0xb0, 0xb8, -1}, 777 7, comspeedtab_pio9032b, 1 }, 778 /* COM_IF_PIO9032B_2 */ 779 { " (PIO9032B)", {0xb9, 0xbb, 0xbb, 0xb2, 0xb2, 0xba, -1}, 780 7, comspeedtab_pio9032b, 1 }, 781 /* COM_IF_B98_01_1 */ 782 { " (B98-01)", {0xb1, 0xb3, 0xb3, 0xb0, 0xb0, 0xd1, 0xd3}, 783 7, comspeedtab_b98_01, 0 }, 784 /* COM_IF_B98_01_2 */ 785 { " (B98-01)", {0xb9, 0xbb, 0xbb, 0xb2, 0xb2, 0xd5, 0xd7}, 786 7, comspeedtab_b98_01, 0 }, 787}; 788#define PC98SIO_data_port(type) (if_8251_type[type].port_table[0]) 789#define PC98SIO_cmd_port(type) (if_8251_type[type].port_table[1]) 790#define PC98SIO_sts_port(type) (if_8251_type[type].port_table[2]) 791#define PC98SIO_in_modem_port(type) (if_8251_type[type].port_table[3]) 792#define PC98SIO_intr_ctrl_port(type) (if_8251_type[type].port_table[4]) 793#define PC98SIO_baud_rate_port(type) (if_8251_type[type].port_table[5]) 794#define PC98SIO_func_port(type) (if_8251_type[type].port_table[6]) 795 796#define I8251F_data 0x130 797#define I8251F_lsr 0x132 798#define I8251F_msr 0x134 799#define I8251F_iir 0x136 800#define I8251F_fcr 0x138 801#define I8251F_div 0x13a 802 803 804static bus_addr_t port_table_0[] = 805 {0x000, 0x001, 0x002, 0x003, 0x004, 0x005, 0x006, 0x007}; 806static bus_addr_t port_table_1[] = 807 {0x000, 0x002, 0x004, 0x006, 0x008, 0x00a, 0x00c, 0x00e}; 808static bus_addr_t port_table_8[] = 809 {0x000, 0x100, 0x200, 0x300, 0x400, 0x500, 0x600, 0x700}; 810static bus_addr_t port_table_rsa[] = 811 {0x008, 0x009, 0x00a, 0x00b, 0x00c, 0x00d, 0x00e, 0x00f}; 812 813struct { 814 char *name; 815 short irr_read; 816 short irr_write; 817 bus_addr_t *port_table; 818 struct speedtab *speedtab; 819} if_16550a_type[] = { 820 /* COM_IF_RSA98 */ 821 { " (RSA-98)", -1, -1, port_table_0, comspeedtab }, 822 /* COM_IF_NS16550 */ 823 { "", -1, -1, port_table_0, comspeedtab }, 824 /* COM_IF_SECOND_CCU */ 825 { "", -1, -1, port_table_0, comspeedtab }, 826 /* COM_IF_MC16550II */ 827 { " (MC16550II)", -1, 0x1000, port_table_8, comspeedtab_mc16550 }, 828 /* COM_IF_MCRS98 */ 829 { " (MC-RS98)", -1, 0x1000, port_table_8, comspeedtab_mc16550 }, 830 /* COM_IF_RSB3000 */ 831 { " (RSB-3000)", 0xbf, -1, port_table_1, comspeedtab_rsb384 }, 832 /* COM_IF_RSB384 */ 833 { " (RSB-384)", 0xbf, -1, port_table_1, comspeedtab_rsb384 }, 834 /* COM_IF_MODEM_CARD */ 835 { "", -1, -1, port_table_0, comspeedtab }, 836 /* COM_IF_RSA98III */ 837 { " (RSA-98III)", -1, -1, port_table_rsa, comspeedtab_rsa }, 838 /* COM_IF_ESP98 */ 839 { " (ESP98)", -1, -1, port_table_1, comspeedtab_mc16550 }, 840}; 841#endif /* PC98 */ 842 843#ifdef COM_ESP 844#ifdef PC98 845 846/* XXX configure this properly. */ 847static Port_t likely_com_ports[] = { 0, 0xb0, 0xb1, 0 }; 848static Port_t likely_esp_ports[] = { 0xc0d0, 0 }; 849 850#define ESP98_CMD1 (ESP_CMD1 * 0x100) 851#define ESP98_CMD2 (ESP_CMD2 * 0x100) 852#define ESP98_STATUS1 (ESP_STATUS1 * 0x100) 853#define ESP98_STATUS2 (ESP_STATUS2 * 0x100) 854 855#else /* PC98 */ 856 857/* XXX configure this properly. */ 858static Port_t likely_com_ports[] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8, }; 859static Port_t likely_esp_ports[] = { 0x140, 0x180, 0x280, 0 }; 860 861#endif /* PC98 */ 862#endif 863 864/* 865 * handle sysctl read/write requests for console speed 866 * 867 * In addition to setting comdefaultrate for I/O through /dev/console, 868 * also set the initial and lock values for the /dev/ttyXX device 869 * if there is one associated with the console. Finally, if the /dev/tty 870 * device has already been open, change the speed on the open running port 871 * itself. 872 */ 873 874static int 875sysctl_machdep_comdefaultrate SYSCTL_HANDLER_ARGS 876{ 877 int error, s; 878 speed_t newspeed; 879 struct com_s *com; 880 struct tty *tp; 881 882 newspeed = comdefaultrate; 883 884 error = sysctl_handle_opaque(oidp, &newspeed, sizeof newspeed, req); 885 if (error || !req->newptr) 886 return (error); 887 888 comdefaultrate = newspeed; 889 890 if (comconsole < 0) /* serial console not selected? */ 891 return (0); 892 893 com = com_addr(comconsole); 894 if (com == NULL) 895 return (ENXIO); 896 897 /* 898 * set the initial and lock rates for /dev/ttydXX and /dev/cuaXX 899 * (note, the lock rates really are boolean -- if non-zero, disallow 900 * speed changes) 901 */ 902 com->it_in.c_ispeed = com->it_in.c_ospeed = 903 com->lt_in.c_ispeed = com->lt_in.c_ospeed = 904 com->it_out.c_ispeed = com->it_out.c_ospeed = 905 com->lt_out.c_ispeed = com->lt_out.c_ospeed = comdefaultrate; 906 907 /* 908 * if we're open, change the running rate too 909 */ 910 tp = com->tp; 911 if (tp && (tp->t_state & TS_ISOPEN)) { 912 tp->t_termios.c_ispeed = 913 tp->t_termios.c_ospeed = comdefaultrate; 914 s = spltty(); 915 error = comparam(tp, &tp->t_termios); 916 splx(s); 917 } 918 return error; 919} 920 921SYSCTL_PROC(_machdep, OID_AUTO, conspeed, CTLTYPE_INT | CTLFLAG_RW, 922 0, 0, sysctl_machdep_comdefaultrate, "I", ""); 923 924#define SET_FLAG(dev, bit) device_set_flags(dev, device_get_flags(dev) | (bit)) 925#define CLR_FLAG(dev, bit) device_set_flags(dev, device_get_flags(dev) & ~(bit)) 926 927#if NCARD > 0 928static int 929sio_pccard_probe(dev) 930 device_t dev; 931{ 932 /* Do not probe IRQ - pccard doesn't turn on the interrupt line */ 933 /* until bus_setup_intr */ 934 SET_FLAG(dev, COM_C_NOPROBE); 935 936 return (sioprobe(dev, 0)); 937} 938 939static int 940sio_pccard_attach(dev) 941 device_t dev; 942{ 943 return (sioattach(dev, 0)); 944} 945 946/* 947 * sio_detach - unload the driver and clear the table. 948 * XXX TODO: 949 * This is usually called when the card is ejected, but 950 * can be caused by a modunload of a controller driver. 951 * The idea is to reset the driver's view of the device 952 * and ensure that any driver entry points such as 953 * read and write do not hang. 954 */ 955static int 956sio_pccard_detach(dev) 957 device_t dev; 958{ 959 struct com_s *com; 960 961 com = (struct com_s *) device_get_softc(dev); 962 if (com == NULL) { 963 device_printf(dev, "NULL com in siounload\n"); 964 return (0); 965 } 966 com->gone = 1; 967 if (com->irqres) { 968 bus_teardown_intr(dev, com->irqres, com->cookie); 969 bus_release_resource(dev, SYS_RES_IRQ, 0, com->irqres); 970 } 971 if (com->ioportres) 972 bus_release_resource(dev, SYS_RES_IOPORT, 0, com->ioportres); 973 if (com->tp && (com->tp->t_state & TS_ISOPEN)) { 974 device_printf(dev, "still open, forcing close\n"); 975 com->tp->t_gen++; 976 ttyclose(com->tp); 977 ttwakeup(com->tp); 978 ttwwakeup(com->tp); 979 } else { 980 if (com->ibuf != NULL) 981 free(com->ibuf, M_DEVBUF); 982 } 983 device_printf(dev, "unloaded\n"); 984 return (0); 985} 986#endif /* NCARD > 0 */ 987 988#if NPCI > 0 989struct pci_ids { 990 u_int32_t type; 991 const char *desc; 992 int rid; 993}; 994 995static struct pci_ids pci_ids[] = { 996 { 0x100812b9, "3COM PCI FaxModem", 0x10 }, 997 { 0x048011c1, "ActionTec 56k FAX PCI Modem", 0x14 }, 998 { 0x00000000, NULL, 0 } 999}; 1000 1001static int 1002sio_pci_attach(dev) 1003 device_t dev; 1004{ 1005 u_int32_t type; 1006 struct pci_ids *id; 1007 1008 type = pci_get_devid(dev); 1009 id = pci_ids; 1010 while (id->type && id->type != type) 1011 id++; 1012 if (id->desc == NULL) 1013 return (ENXIO); 1014 sio_pci_kludge_unit(dev); 1015 return (sioattach(dev, id->rid)); 1016} 1017 1018/* 1019 * Don't cut and paste this to other drivers. It is a horrible kludge 1020 * which will fail to work and also be unnecessary in future versions. 1021 */ 1022static void 1023sio_pci_kludge_unit(dev) 1024 device_t dev; 1025{ 1026 devclass_t dc; 1027 int err; 1028 int start; 1029 int unit; 1030 1031 unit = 0; 1032 start = 0; 1033 while (resource_int_value("sio", unit, "port", &start) == 0 && 1034 start > 0) 1035 unit++; 1036 if (device_get_unit(dev) < unit) { 1037 dc = device_get_devclass(dev); 1038 while (devclass_get_device(dc, unit)) 1039 unit++; 1040 device_printf(dev, "moving to sio%d\n", unit); 1041 err = device_set_unit(dev, unit); /* EVIL DO NOT COPY */ 1042 if (err) 1043 device_printf(dev, "error moving device %d\n", err); 1044 } 1045} 1046 1047static int 1048sio_pci_probe(dev) 1049 device_t dev; 1050{ 1051 u_int32_t type; 1052 struct pci_ids *id; 1053 1054 type = pci_get_devid(dev); 1055 id = pci_ids; 1056 while (id->type && id->type != type) 1057 id++; 1058 if (id->desc == NULL) 1059 return (ENXIO); 1060 device_set_desc(dev, id->desc); 1061 return (sioprobe(dev, id->rid)); 1062} 1063#endif /* NPCI > 0 */ 1064 1065static struct isa_pnp_id sio_ids[] = { 1066 {0x0005d041, "Standard PC COM port"}, /* PNP0500 */ 1067 {0x0105d041, "16550A-compatible COM port"}, /* PNP0501 */ 1068 {0x0205d041, "Multiport serial device (non-intelligent 16550)"}, /* PNP0502 */ 1069 {0x1005d041, "Generic IRDA-compatible device"}, /* PNP0510 */ 1070 {0x1105d041, "Generic IRDA-compatible device"}, /* PNP0511 */ 1071 /* Devices that do not have a compatid */ 1072 {0x7602a904, NULL}, /* AEI0276 - 56K v.90 Fax Modem (LKT) */ 1073 {0x00007905, NULL}, /* AKY0000 - 56K Plug&Play Modem */ 1074 {0x01405407, NULL}, /* AZT4001 - AZT3000 PnP SOUND DEVICE, MODEM */ 1075 {0x56039008, NULL}, /* BDP0356 - Best Data 56x2 */ 1076 {0x36339008, NULL}, /* BDP3336 - Best Data Prods. 336F */ 1077 {0x0014490a, NULL}, /* BRI1400 - Boca 33.6 PnP */ 1078 {0x0015490a, NULL}, /* BRI1500 - Internal Fax Data */ 1079 {0x0034490a, NULL}, /* BRI3400 - Internal ACF Modem */ 1080 {0x00b4490a, NULL}, /* BRIB400 - Boca 56k PnP */ 1081 {0x0030320d, NULL}, /* CIR3000 - Cirrus Logic V43 */ 1082 {0x0100440e, NULL}, /* CRD0001 - Cardinal MVP288IV ? */ 1083 {0x1200c31e, NULL}, /* GVC0012 - VF1128HV-R9 (win modem?) */ 1084 {0x0303c31e, NULL}, /* GVC0303 - MaxTech 33.6 PnP D/F/V */ 1085 {0x0505c31e, NULL}, /* GVC0505 - GVC 56k Faxmodem */ 1086 {0x0050c31e, NULL}, /* GVC5000 - some GVC modem */ 1087 {0x3800f91e, NULL}, /* GWY0038 - Telepath with v.90 */ 1088 {0x9062f91e, NULL}, /* GWY6290 - Telepath with x2 Technology */ 1089 {0x0000f435, NULL}, /* MOT0000 - Motorola ModemSURFR 33.6 Intern */ 1090 {0x5015f435, NULL}, /* MOT1550 - Motorola ModemSURFR 56K Modem */ 1091 {0xf015f435, NULL}, /* MOT15F0 - Motorola VoiceSURFR 56K Modem */ 1092 {0x6045f435, NULL}, /* MOT4560 - Motorola ? */ 1093 {0x61e7a338, NULL}, /* NECE761 - 33.6Modem */ 1094 {0x39804f3f, NULL}, /* OZO8039 - Zoom 56k flex */ 1095 {0x3024a341, NULL}, /* PMC2430 - Pace 56 Voice Internal Modem */ 1096 {0x1000eb49, NULL}, /* ROK0010 - Rockwell ? */ 1097 {0x5002734a, NULL}, /* RSS0250 - 5614Jx3(G) Internal Modem */ 1098 {0xc100ad4d, NULL}, /* SMM00C1 - Leopard 56k PnP */ 1099 {0x9012b04e, NULL}, /* SUP1290 - Supra ? */ 1100 {0x1013b04e, NULL}, /* SUP1310 - SupraExpress 336i PnP */ 1101 {0x8013b04e, NULL}, /* SUP1380 - SupraExpress 288i PnP Voice */ 1102 {0x8113b04e, NULL}, /* SUP1381 - SupraExpress 336i PnP Voice */ 1103 {0x5016b04e, NULL}, /* SUP1650 - Supra 336i Sp Intl */ 1104 {0x7420b04e, NULL}, /* SUP2070 - Supra ? */ 1105 {0x8020b04e, NULL}, /* SUP2080 - Supra ? */ 1106 {0x8420b04e, NULL}, /* SUP2084 - SupraExpress 56i PnP */ 1107 {0x7121b04e, NULL}, /* SUP2171 - SupraExpress 56i Sp? */ 1108 {0x8024b04e, NULL}, /* SUP2480 - Supra ? */ 1109 {0x01007256, NULL}, /* USR0001 - U.S. Robotics Inc., Sportster W */ 1110 {0x02007256, NULL}, /* USR0002 - U.S. Robotics Inc. Sportster 33. */ 1111 {0x04007256, NULL}, /* USR0004 - USR Sportster 14.4k */ 1112 {0x06007256, NULL}, /* USR0006 - USR Sportster 33.6k */ 1113 {0x11007256, NULL}, /* USR0011 - USR ? */ 1114 {0x01017256, NULL}, /* USR0101 - USR ? */ 1115 {0x30207256, NULL}, /* USR2030 - U.S.Robotics Inc. Sportster 560 */ 1116 {0x50207256, NULL}, /* USR2050 - U.S.Robotics Inc. Sportster 33. */ 1117 {0x70207256, NULL}, /* USR2070 - U.S.Robotics Inc. Sportster 560 */ 1118 {0x30307256, NULL}, /* USR3030 - U.S. Robotics 56K FAX INT */ 1119 {0x31307256, NULL}, /* USR3031 - U.S. Robotics 56K FAX INT */ 1120 {0x50307256, NULL}, /* USR3050 - U.S. Robotics 56K FAX INT */ 1121 {0x70307256, NULL}, /* USR3070 - U.S. Robotics 56K Voice INT */ 1122 {0x90307256, NULL}, /* USR3090 - USR ? */ 1123 {0x90917256, NULL}, /* USR9190 - USR 56k Voice INT */ 1124 {0x0300695c, NULL}, /* WCI0003 - Fax/Voice/Modem/Speakphone/Asvd */ 1125 {0x61f7896a, NULL}, /* ZTIF761 - Zoom ComStar 33.6 */ 1126#ifdef PC98 1127 {0x0100e4a5, "RSA-98III"}, 1128#endif 1129 {0} 1130}; 1131 1132 1133 1134static int 1135sio_isa_probe(dev) 1136 device_t dev; 1137{ 1138#ifdef PC98 1139 int logical_id; 1140#endif 1141 /* Check isapnp ids */ 1142 if (ISA_PNP_PROBE(device_get_parent(dev), dev, sio_ids) == ENXIO) 1143 return (ENXIO); 1144#ifdef PC98 1145 logical_id = isa_get_logicalid(dev); 1146 if (logical_id == 0x0100e4a5) /* RSA-98III */ 1147 device_set_flags(dev, SET_IFTYPE(COM_IF_RSA98III)); 1148#endif 1149 return (sioprobe(dev, 0)); 1150} 1151 1152static int 1153sioprobe(dev, xrid) 1154 device_t dev; 1155 int xrid; 1156{ 1157#if 0 1158 static bool_t already_init; 1159 device_t xdev; 1160#endif 1161 struct com_s *com; 1162 bool_t failures[10]; 1163 int fn; 1164 device_t idev; 1165 Port_t iobase; 1166 intrmask_t irqmap[4]; 1167 intrmask_t irqs; 1168 u_char mcr_image; 1169 int result; 1170 u_long xirq; 1171 u_int flags = device_get_flags(dev); 1172 int rid; 1173 struct resource *port; 1174#ifdef PC98 1175 int tmp; 1176 struct siodev iod; 1177#endif 1178 1179#ifdef PC98 1180 iod.if_type = GET_IFTYPE(flags); 1181 if ((iod.if_type < 0 || iod.if_type > COM_IF_END1) && 1182 (iod.if_type < 0x10 || iod.if_type > COM_IF_END2)) 1183 return ENXIO; 1184#endif 1185 1186 rid = xrid; 1187#ifdef PC98 1188 if (IS_8251(iod.if_type)) { 1189 port = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 1190 0, ~0, 1, RF_ACTIVE); 1191 } else if (isa_get_vendorid(dev)) { 1192 port = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 1193 0, ~0, IO_COMSIZE, RF_ACTIVE); 1194 } else { 1195 port = isa_alloc_resourcev(dev, SYS_RES_IOPORT, &rid, 1196 if_16550a_type[iod.if_type & 0x0f].port_table, 1197 IO_COMSIZE, RF_ACTIVE); 1198 } 1199#else 1200 port = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 1201 0, ~0, IO_COMSIZE, RF_ACTIVE); 1202#endif 1203 if (!port) 1204 return (ENXIO); 1205#ifdef PC98 1206 if (!IS_8251(iod.if_type)) { 1207 if (isa_load_resourcev(port, 1208 if_16550a_type[iod.if_type & 0x0f].port_table, 1209 IO_COMSIZE) != 0) { 1210 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 1211 return ENXIO; 1212 } 1213 } 1214#endif 1215 1216 com = device_get_softc(dev); 1217 com->bst = rman_get_bustag(port); 1218 com->bsh = rman_get_bushandle(port); 1219 1220#if 0 1221 /* 1222 * XXX this is broken - when we are first called, there are no 1223 * previously configured IO ports. We could hard code 1224 * 0x3f8, 0x2f8, 0x3e8, 0x2e8 etc but that's probably worse. 1225 * This code has been doing nothing since the conversion since 1226 * "count" is zero the first time around. 1227 */ 1228 if (!already_init) { 1229 /* 1230 * Turn off MCR_IENABLE for all likely serial ports. An unused 1231 * port with its MCR_IENABLE gate open will inhibit interrupts 1232 * from any used port that shares the interrupt vector. 1233 * XXX the gate enable is elsewhere for some multiports. 1234 */ 1235 device_t *devs; 1236 int count, i, xioport; 1237#ifdef PC98 1238 int xiftype; 1239#endif 1240 1241 devclass_get_devices(sio_devclass, &devs, &count); 1242#ifdef PC98 1243 for (i = 0; i < count; i++) { 1244 xdev = devs[i]; 1245 xioport = bus_get_resource_start(xdev, SYS_RES_IOPORT, 0); 1246 xiftype = GET_IFTYPE(device_get_flags(xdev)); 1247 if (device_is_enabled(xdev) && xioport > 0) { 1248 if (IS_8251(xiftype)) 1249 outb((xioport & 0xff00) | PC98SIO_cmd_port(xiftype & 0x0f), 0xf2); 1250 else 1251 outb(xioport + if_16550a_type[xiftype & 0x0f].port_table[com_mcr], 0); 1252 } 1253 } 1254#else 1255 for (i = 0; i < count; i++) { 1256 xdev = devs[i]; 1257 if (device_is_enabled(xdev) && 1258 bus_get_resource(xdev, SYS_RES_IOPORT, 0, &xioport, 1259 NULL) == 0) 1260 outb(xioport + com_mcr, 0); 1261 } 1262#endif 1263 free(devs, M_TEMP); 1264 already_init = TRUE; 1265 } 1266#endif 1267 1268 if (COM_LLCONSOLE(flags)) { 1269 printf("sio%d: reserved for low-level i/o\n", 1270 device_get_unit(dev)); 1271 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 1272 return (ENXIO); 1273 } 1274 1275#ifdef PC98 1276 DELAY(10); 1277 1278 /* 1279 * If the port is i8251 UART (internal, B98_01) 1280 */ 1281 if (pc98_check_if_type(dev, &iod) == -1) { 1282 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 1283 return (ENXIO); 1284 } 1285 if (iod.irq > 0) 1286 bus_set_resource(dev, SYS_RES_IRQ, 0, iod.irq, 1); 1287 if (IS_8251(iod.if_type)) { 1288 outb(iod.cmd, 0); 1289 DELAY(10); 1290 outb(iod.cmd, 0); 1291 DELAY(10); 1292 outb(iod.cmd, 0); 1293 DELAY(10); 1294 outb(iod.cmd, CMD8251_RESET); 1295 DELAY(1000); /* for a while...*/ 1296 outb(iod.cmd, 0xf2); /* MODE (dummy) */ 1297 DELAY(10); 1298 outb(iod.cmd, 0x01); /* CMD (dummy) */ 1299 DELAY(1000); /* for a while...*/ 1300 if (( inb(iod.sts) & STS8251_TxEMP ) == 0 ) { 1301 result = (ENXIO); 1302 } 1303 if (if_8251_type[iod.if_type & 0x0f].check_irq) { 1304 COM_INT_DISABLE 1305 tmp = ( inb( iod.ctrl ) & ~(IEN_Rx|IEN_TxEMP|IEN_Tx)); 1306 outb( iod.ctrl, tmp|IEN_TxEMP ); 1307 DELAY(10); 1308 result = isa_irq_pending() ? 0 : ENXIO; 1309 outb( iod.ctrl, tmp ); 1310 COM_INT_ENABLE 1311 } else { 1312 /* 1313 * B98_01 doesn't activate TxEMP interrupt line 1314 * when being reset, so we can't check irq pending. 1315 */ 1316 result = 0; 1317 } 1318 if (epson_machine_id==0x20) { /* XXX */ 1319 result = 0; 1320 } 1321 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 1322 return result; 1323 } 1324#endif /* PC98 */ 1325 /* 1326 * If the device is on a multiport card and has an AST/4 1327 * compatible interrupt control register, initialize this 1328 * register and prepare to leave MCR_IENABLE clear in the mcr. 1329 * Otherwise, prepare to set MCR_IENABLE in the mcr. 1330 * Point idev to the device struct giving the correct id_irq. 1331 * This is the struct for the master device if there is one. 1332 */ 1333 idev = dev; 1334 mcr_image = MCR_IENABLE; 1335#ifdef COM_MULTIPORT 1336 if (COM_ISMULTIPORT(flags)) { 1337#ifndef PC98 1338 Port_t xiobase; 1339 u_long io; 1340#endif 1341 1342 idev = devclass_get_device(sio_devclass, COM_MPMASTER(flags)); 1343 if (idev == NULL) { 1344 printf("sio%d: master device %d not configured\n", 1345 device_get_unit(dev), COM_MPMASTER(flags)); 1346 idev = dev; 1347 } 1348#ifndef PC98 1349 if (!COM_NOTAST4(flags)) { 1350 if (bus_get_resource(idev, SYS_RES_IOPORT, 0, &io, 1351 NULL) == 0) { 1352 xiobase = io; 1353 if (bus_get_resource(idev, SYS_RES_IRQ, 0, 1354 NULL, NULL) == 0) 1355 outb(xiobase + com_scr, 0x80); 1356 else 1357 outb(xiobase + com_scr, 0); 1358 } 1359 mcr_image = 0; 1360 } 1361#endif 1362 } 1363#endif /* COM_MULTIPORT */ 1364 if (bus_get_resource(idev, SYS_RES_IRQ, 0, NULL, NULL) != 0) 1365 mcr_image = 0; 1366 1367 bzero(failures, sizeof failures); 1368 iobase = rman_get_start(port); 1369 1370#ifdef PC98 1371 if (iod.if_type == COM_IF_RSA98III) { 1372 mcr_image = 0; 1373 1374 outb(iobase + rsa_msr, 0x04); 1375 outb(iobase + rsa_frr, 0x00); 1376 if ((inb(iobase + rsa_srr) & 0x36) != 0x36) { 1377 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 1378 return (ENXIO); 1379 } 1380 outb(iobase + rsa_ier, 0x00); 1381 outb(iobase + rsa_frr, 0x00); 1382 outb(iobase + rsa_tivsr, 0x00); 1383 outb(iobase + rsa_tcr, 0x00); 1384 } 1385 1386 tmp = if_16550a_type[iod.if_type & 0x0f].irr_write; 1387 if (tmp != -1) { 1388 /* MC16550II */ 1389 int irqout; 1390 switch (isa_get_irq(idev)) { 1391 case 3: irqout = 4; break; 1392 case 5: irqout = 5; break; 1393 case 6: irqout = 6; break; 1394 case 12: irqout = 7; break; 1395 default: 1396 printf("sio%d: irq configuration error\n", 1397 device_get_unit(dev)); 1398 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 1399 return (ENXIO); 1400 } 1401 outb((iobase & 0x00ff) | tmp, irqout); 1402 } 1403#endif 1404 1405 /* 1406 * We don't want to get actual interrupts, just masked ones. 1407 * Interrupts from this line should already be masked in the ICU, 1408 * but mask them in the processor as well in case there are some 1409 * (misconfigured) shared interrupts. 1410 */ 1411 disable_intr(); 1412/* EXTRA DELAY? */ 1413 1414 /* 1415 * Initialize the speed and the word size and wait long enough to 1416 * drain the maximum of 16 bytes of junk in device output queues. 1417 * The speed is undefined after a master reset and must be set 1418 * before relying on anything related to output. There may be 1419 * junk after a (very fast) soft reboot and (apparently) after 1420 * master reset. 1421 * XXX what about the UART bug avoided by waiting in comparam()? 1422 * We don't want to to wait long enough to drain at 2 bps. 1423 */ 1424 if (iobase == siocniobase) 1425 DELAY((16 + 1) * 1000000 / (comdefaultrate / 10)); 1426 else { 1427#ifdef PC98 1428 tmp = ttspeedtab(SIO_TEST_SPEED, 1429 if_16550a_type[iod.if_type & 0x0f].speedtab); 1430 sio_setreg(com, com_cfcr, CFCR_DLAB | CFCR_8BITS); 1431 sio_setreg(com, com_dlbl, tmp & 0xff); 1432 sio_setreg(com, com_dlbh, (tmp >> 8) & 0xff); 1433 sio_setreg(com, com_cfcr, CFCR_8BITS); 1434#else 1435 sio_setreg(com, com_cfcr, CFCR_DLAB | CFCR_8BITS); 1436 sio_setreg(com, com_dlbl, COMBRD(SIO_TEST_SPEED) & 0xff); 1437 sio_setreg(com, com_dlbh, (u_int) COMBRD(SIO_TEST_SPEED) >> 8); 1438 sio_setreg(com, com_cfcr, CFCR_8BITS); 1439#endif 1440 DELAY((16 + 1) * 1000000 / (SIO_TEST_SPEED / 10)); 1441 } 1442 1443 /* 1444 * Enable the interrupt gate and disable device interupts. This 1445 * should leave the device driving the interrupt line low and 1446 * guarantee an edge trigger if an interrupt can be generated. 1447 */ 1448/* EXTRA DELAY? */ 1449 sio_setreg(com, com_mcr, mcr_image); 1450 sio_setreg(com, com_ier, 0); 1451 DELAY(1000); /* XXX */ 1452 irqmap[0] = isa_irq_pending(); 1453 1454 /* 1455 * Attempt to set loopback mode so that we can send a null byte 1456 * without annoying any external device. 1457 */ 1458/* EXTRA DELAY? */ 1459 sio_setreg(com, com_mcr, mcr_image | MCR_LOOPBACK); 1460 1461 /* 1462 * Attempt to generate an output interrupt. On 8250's, setting 1463 * IER_ETXRDY generates an interrupt independent of the current 1464 * setting and independent of whether the THR is empty. On 16450's, 1465 * setting IER_ETXRDY generates an interrupt independent of the 1466 * current setting. On 16550A's, setting IER_ETXRDY only 1467 * generates an interrupt when IER_ETXRDY is not already set. 1468 */ 1469 sio_setreg(com, com_ier, IER_ETXRDY); 1470#ifdef PC98 1471 if (iod.if_type == COM_IF_RSA98III) 1472 outb(iobase + rsa_ier, 0x04); 1473#endif 1474 1475 /* 1476 * On some 16x50 incompatibles, setting IER_ETXRDY doesn't generate 1477 * an interrupt. They'd better generate one for actually doing 1478 * output. Loopback may be broken on the same incompatibles but 1479 * it's unlikely to do more than allow the null byte out. 1480 */ 1481 sio_setreg(com, com_data, 0); 1482 DELAY((1 + 2) * 1000000 / (SIO_TEST_SPEED / 10)); 1483 1484 /* 1485 * Turn off loopback mode so that the interrupt gate works again 1486 * (MCR_IENABLE was hidden). This should leave the device driving 1487 * an interrupt line high. It doesn't matter if the interrupt 1488 * line oscillates while we are not looking at it, since interrupts 1489 * are disabled. 1490 */ 1491/* EXTRA DELAY? */ 1492 sio_setreg(com, com_mcr, mcr_image); 1493 1494 /* 1495 * Some pcmcia cards have the "TXRDY bug", so we check everyone 1496 * for IIR_TXRDY implementation ( Palido 321s, DC-1S... ) 1497 */ 1498 if (COM_NOPROBE(flags)) { 1499 /* Reading IIR register twice */ 1500 for (fn = 0; fn < 2; fn ++) { 1501 DELAY(10000); 1502 failures[6] = sio_getreg(com, com_iir); 1503 } 1504 /* Check IIR_TXRDY clear ? */ 1505 result = 0; 1506 if (failures[6] & IIR_TXRDY) { 1507 /* Nop, Double check with clearing IER */ 1508 sio_setreg(com, com_ier, 0); 1509 if (sio_getreg(com, com_iir) & IIR_NOPEND) { 1510 /* Ok. we're familia this gang */ 1511 SET_FLAG(dev, COM_C_IIR_TXRDYBUG); 1512 } else { 1513 /* Unknown, Just omit this chip.. XXX */ 1514 result = ENXIO; 1515 } 1516 } else { 1517 /* OK. this is well-known guys */ 1518 CLR_FLAG(dev, COM_C_IIR_TXRDYBUG); 1519 } 1520 sio_setreg(com, com_cfcr, CFCR_8BITS); 1521 enable_intr(); 1522 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 1523 return (iobase == siocniobase ? 0 : result); 1524 } 1525 1526 /* 1527 * Check that 1528 * o the CFCR, IER and MCR in UART hold the values written to them 1529 * (the values happen to be all distinct - this is good for 1530 * avoiding false positive tests from bus echoes). 1531 * o an output interrupt is generated and its vector is correct. 1532 * o the interrupt goes away when the IIR in the UART is read. 1533 */ 1534/* EXTRA DELAY? */ 1535 failures[0] = sio_getreg(com, com_cfcr) - CFCR_8BITS; 1536 failures[1] = sio_getreg(com, com_ier) - IER_ETXRDY; 1537 failures[2] = sio_getreg(com, com_mcr) - mcr_image; 1538 DELAY(10000); /* Some internal modems need this time */ 1539 irqmap[1] = isa_irq_pending(); 1540 failures[4] = (sio_getreg(com, com_iir) & IIR_IMASK) - IIR_TXRDY; 1541#ifdef PC98 1542 if (iod.if_type == COM_IF_RSA98III) 1543 inb(iobase + rsa_srr); 1544#endif 1545 DELAY(1000); /* XXX */ 1546 irqmap[2] = isa_irq_pending(); 1547 failures[6] = (sio_getreg(com, com_iir) & IIR_IMASK) - IIR_NOPEND; 1548#ifdef PC98 1549 if (iod.if_type == COM_IF_RSA98III) 1550 inb(iobase + rsa_srr); 1551#endif 1552 1553 /* 1554 * Turn off all device interrupts and check that they go off properly. 1555 * Leave MCR_IENABLE alone. For ports without a master port, it gates 1556 * the OUT2 output of the UART to 1557 * the ICU input. Closing the gate would give a floating ICU input 1558 * (unless there is another device driving it) and spurious interrupts. 1559 * (On the system that this was first tested on, the input floats high 1560 * and gives a (masked) interrupt as soon as the gate is closed.) 1561 */ 1562 sio_setreg(com, com_ier, 0); 1563 sio_setreg(com, com_cfcr, CFCR_8BITS); /* dummy to avoid bus echo */ 1564 failures[7] = sio_getreg(com, com_ier); 1565#ifdef PC98 1566 if (iod.if_type == COM_IF_RSA98III) 1567 outb(iobase + rsa_ier, 0x00); 1568#endif 1569 DELAY(1000); /* XXX */ 1570 irqmap[3] = isa_irq_pending(); 1571 failures[9] = (sio_getreg(com, com_iir) & IIR_IMASK) - IIR_NOPEND; 1572#ifdef PC98 1573 if (iod.if_type == COM_IF_RSA98III) { 1574 inb(iobase + rsa_srr); 1575 outb(iobase + rsa_frr, 0x00); 1576 } 1577#endif 1578 1579 enable_intr(); 1580 1581 irqs = irqmap[1] & ~irqmap[0]; 1582 if (bus_get_resource(idev, SYS_RES_IRQ, 0, &xirq, NULL) == 0 && 1583 ((1 << xirq) & irqs) == 0) 1584 printf( 1585 "sio%d: configured irq %ld not in bitmap of probed irqs %#x\n", 1586 device_get_unit(dev), xirq, irqs); 1587 if (bootverbose) 1588 printf("sio%d: irq maps: %#x %#x %#x %#x\n", 1589 device_get_unit(dev), 1590 irqmap[0], irqmap[1], irqmap[2], irqmap[3]); 1591 1592 result = 0; 1593 for (fn = 0; fn < sizeof failures; ++fn) 1594 if (failures[fn]) { 1595 sio_setreg(com, com_mcr, 0); 1596 result = ENXIO; 1597 if (bootverbose) { 1598 printf("sio%d: probe failed test(s):", 1599 device_get_unit(dev)); 1600 for (fn = 0; fn < sizeof failures; ++fn) 1601 if (failures[fn]) 1602 printf(" %d", fn); 1603 printf("\n"); 1604 } 1605 break; 1606 } 1607 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 1608 return (iobase == siocniobase ? 0 : result); 1609} 1610 1611#ifdef COM_ESP 1612static int 1613espattach(com, esp_port) 1614 struct com_s *com; 1615 Port_t esp_port; 1616{ 1617 u_char dips; 1618 u_char val; 1619 1620 /* 1621 * Check the ESP-specific I/O port to see if we're an ESP 1622 * card. If not, return failure immediately. 1623 */ 1624 if ((inb(esp_port) & 0xf3) == 0) { 1625 printf(" port 0x%x is not an ESP board?\n", esp_port); 1626 return (0); 1627 } 1628 1629 /* 1630 * We've got something that claims to be a Hayes ESP card. 1631 * Let's hope so. 1632 */ 1633 1634 /* Get the dip-switch configuration */ 1635#ifdef PC98 1636 outb(esp_port + ESP98_CMD1, ESP_GETDIPS); 1637 dips = inb(esp_port + ESP98_STATUS1); 1638#else 1639 outb(esp_port + ESP_CMD1, ESP_GETDIPS); 1640 dips = inb(esp_port + ESP_STATUS1); 1641#endif 1642 1643 /* 1644 * Bits 0,1 of dips say which COM port we are. 1645 */ 1646#ifdef PC98 1647 if ((rman_get_start(com->ioportres) & 0xff) == 1648 likely_com_ports[dips & 0x03]) 1649#else 1650 if (rman_get_start(com->ioportres) == likely_com_ports[dips & 0x03]) 1651#endif 1652 printf(" : ESP"); 1653 else { 1654 printf(" esp_port has com %d\n", dips & 0x03); 1655 return (0); 1656 } 1657 1658 /* 1659 * Check for ESP version 2.0 or later: bits 4,5,6 = 010. 1660 */ 1661#ifdef PC98 1662 outb(esp_port + ESP98_CMD1, ESP_GETTEST); 1663 val = inb(esp_port + ESP98_STATUS1); /* clear reg 1 */ 1664 val = inb(esp_port + ESP98_STATUS2); 1665#else 1666 outb(esp_port + ESP_CMD1, ESP_GETTEST); 1667 val = inb(esp_port + ESP_STATUS1); /* clear reg 1 */ 1668 val = inb(esp_port + ESP_STATUS2); 1669#endif 1670 if ((val & 0x70) < 0x20) { 1671 printf("-old (%o)", val & 0x70); 1672 return (0); 1673 } 1674 1675 /* 1676 * Check for ability to emulate 16550: bit 7 == 1 1677 */ 1678 if ((dips & 0x80) == 0) { 1679 printf(" slave"); 1680 return (0); 1681 } 1682 1683 /* 1684 * Okay, we seem to be a Hayes ESP card. Whee. 1685 */ 1686 com->esp = TRUE; 1687 com->esp_port = esp_port; 1688 return (1); 1689} 1690#endif /* COM_ESP */ 1691 1692static int 1693sio_isa_attach(dev) 1694 device_t dev; 1695{ 1696 return (sioattach(dev, 0)); 1697} 1698 1699static int 1700sioattach(dev, xrid) 1701 device_t dev; 1702 int xrid; 1703{ 1704 struct com_s *com; 1705#ifdef COM_ESP 1706 Port_t *espp; 1707#endif 1708 Port_t iobase; 1709 int unit; 1710 u_int flags; 1711 int rid; 1712 struct resource *port; 1713 int ret; 1714#ifdef PC98 1715 u_char *obuf; 1716 u_long obufsize; 1717 int if_type = GET_IFTYPE(device_get_flags(dev)); 1718#endif 1719 1720 rid = xrid; 1721#ifdef PC98 1722 if (IS_8251(if_type)) { 1723 port = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 1724 0, ~0, 1, RF_ACTIVE); 1725 } else if (isa_get_vendorid(dev)) { 1726 port = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 1727 0, ~0, IO_COMSIZE, RF_ACTIVE); 1728 } else { 1729 port = isa_alloc_resourcev(dev, SYS_RES_IOPORT, &rid, 1730 if_16550a_type[if_type & 0x0f].port_table, 1731 IO_COMSIZE, RF_ACTIVE); 1732 } 1733#else 1734 port = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 1735 0, ~0, IO_COMSIZE, RF_ACTIVE); 1736#endif 1737 if (!port) 1738 return (ENXIO); 1739#ifdef PC98 1740 if (!IS_8251(if_type)) { 1741 if (isa_load_resourcev(port, 1742 if_16550a_type[if_type & 0x0f].port_table, 1743 IO_COMSIZE) != 0) { 1744 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 1745 return ENXIO; 1746 } 1747 } 1748#endif 1749 1750 iobase = rman_get_start(port); 1751 unit = device_get_unit(dev); 1752 com = device_get_softc(dev); 1753 flags = device_get_flags(dev); 1754 1755 if (unit >= sio_numunits) 1756 sio_numunits = unit + 1; 1757 1758#ifdef PC98 1759 obufsize = 256; 1760 if (if_type == COM_IF_RSA98III) 1761 obufsize = 2048; 1762 if ((obuf = malloc(obufsize * 2, M_DEVBUF, M_NOWAIT)) == NULL) { 1763 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 1764 return ENXIO; 1765 } 1766 bzero(obuf, obufsize * 2); 1767#endif 1768 1769 /* 1770 * sioprobe() has initialized the device registers as follows: 1771 * o cfcr = CFCR_8BITS. 1772 * It is most important that CFCR_DLAB is off, so that the 1773 * data port is not hidden when we enable interrupts. 1774 * o ier = 0. 1775 * Interrupts are only enabled when the line is open. 1776 * o mcr = MCR_IENABLE, or 0 if the port has AST/4 compatible 1777 * interrupt control register or the config specifies no irq. 1778 * Keeping MCR_DTR and MCR_RTS off might stop the external 1779 * device from sending before we are ready. 1780 */ 1781 bzero(com, sizeof *com); 1782 com->unit = unit; 1783 com->ioportres = port; 1784 com->bst = rman_get_bustag(port); 1785 com->bsh = rman_get_bushandle(port); 1786 com->cfcr_image = CFCR_8BITS; 1787 com->dtr_wait = 3 * hz; 1788 com->loses_outints = COM_LOSESOUTINTS(flags) != 0; 1789 com->no_irq = bus_get_resource(dev, SYS_RES_IRQ, 0, NULL, NULL) != 0; 1790 com->tx_fifo_size = 1; 1791#ifdef PC98 1792 com->obufsize = obufsize; 1793 com->obuf1 = obuf; 1794 com->obuf2 = obuf + obufsize; 1795#endif 1796 com->obufs[0].l_head = com->obuf1; 1797 com->obufs[1].l_head = com->obuf2; 1798 1799#ifdef PC98 1800 com->pc98_if_type = if_type; 1801 1802 if (IS_8251(if_type)) { 1803 pc98_set_ioport(com); 1804 1805 if (if_type == COM_IF_INTERNAL && pc98_check_8251fifo()) { 1806 com->pc98_8251fifo = 1; 1807 com->pc98_8251fifo_enable = 0; 1808 } 1809 } else { 1810 bus_addr_t *iat = if_16550a_type[if_type & 0x0f].port_table; 1811 1812 com->data_port = iobase + iat[com_data]; 1813 com->int_id_port = iobase + iat[com_iir]; 1814 com->modem_ctl_port = iobase + iat[com_mcr]; 1815 com->mcr_image = inb(com->modem_ctl_port); 1816 com->line_status_port = iobase + iat[com_lsr]; 1817 com->modem_status_port = iobase + iat[com_msr]; 1818 com->intr_ctl_port = iobase + iat[com_ier]; 1819 } 1820#else /* not PC98 */ 1821 com->data_port = iobase + com_data; 1822 com->int_id_port = iobase + com_iir; 1823 com->modem_ctl_port = iobase + com_mcr; 1824 com->mcr_image = inb(com->modem_ctl_port); 1825 com->line_status_port = iobase + com_lsr; 1826 com->modem_status_port = iobase + com_msr; 1827 com->intr_ctl_port = iobase + com_ier; 1828#endif 1829 1830 /* 1831 * We don't use all the flags from <sys/ttydefaults.h> since they 1832 * are only relevant for logins. It's important to have echo off 1833 * initially so that the line doesn't start blathering before the 1834 * echo flag can be turned off. 1835 */ 1836 com->it_in.c_iflag = 0; 1837 com->it_in.c_oflag = 0; 1838 com->it_in.c_cflag = TTYDEF_CFLAG; 1839 com->it_in.c_lflag = 0; 1840 if (unit == comconsole) { 1841#ifdef PC98 1842 if (IS_8251(com->pc98_if_type)) 1843 DELAY(100000); 1844#endif 1845 com->it_in.c_iflag = TTYDEF_IFLAG; 1846 com->it_in.c_oflag = TTYDEF_OFLAG; 1847 com->it_in.c_cflag = TTYDEF_CFLAG | CLOCAL; 1848 com->it_in.c_lflag = TTYDEF_LFLAG; 1849 com->lt_out.c_cflag = com->lt_in.c_cflag = CLOCAL; 1850 com->lt_out.c_ispeed = com->lt_out.c_ospeed = 1851 com->lt_in.c_ispeed = com->lt_in.c_ospeed = 1852 com->it_in.c_ispeed = com->it_in.c_ospeed = comdefaultrate; 1853 } else 1854 com->it_in.c_ispeed = com->it_in.c_ospeed = TTYDEF_SPEED; 1855 if (siosetwater(com, com->it_in.c_ispeed) != 0) { 1856 enable_intr(); 1857 /* 1858 * Leave i/o resources allocated if this is a `cn'-level 1859 * console, so that other devices can't snarf them. 1860 */ 1861 if (iobase != siocniobase) 1862 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 1863 return (ENOMEM); 1864 } 1865 enable_intr(); 1866 termioschars(&com->it_in); 1867 com->it_out = com->it_in; 1868 1869 /* attempt to determine UART type */ 1870 printf("sio%d: type", unit); 1871 1872 1873#ifndef PC98 1874#ifdef COM_MULTIPORT 1875 if (!COM_ISMULTIPORT(flags) && !COM_IIR_TXRDYBUG(flags)) 1876#else 1877 if (!COM_IIR_TXRDYBUG(flags)) 1878#endif 1879 { 1880 u_char scr; 1881 u_char scr1; 1882 u_char scr2; 1883 1884 scr = sio_getreg(com, com_scr); 1885 sio_setreg(com, com_scr, 0xa5); 1886 scr1 = sio_getreg(com, com_scr); 1887 sio_setreg(com, com_scr, 0x5a); 1888 scr2 = sio_getreg(com, com_scr); 1889 sio_setreg(com, com_scr, scr); 1890 if (scr1 != 0xa5 || scr2 != 0x5a) { 1891 printf(" 8250"); 1892 goto determined_type; 1893 } 1894 } 1895#endif /* !PC98 */ 1896#ifdef PC98 1897 if (IS_8251(com->pc98_if_type)) { 1898 if (com->pc98_8251fifo && !COM_NOFIFO(flags)) 1899 com->tx_fifo_size = 16; 1900 com_int_TxRx_disable( com ); 1901 com_cflag_and_speed_set( com, com->it_in.c_cflag, comdefaultrate ); 1902 com_tiocm_bic( com, TIOCM_DTR|TIOCM_RTS|TIOCM_LE ); 1903 com_send_break_off( com ); 1904 1905 if (com->pc98_if_type == COM_IF_INTERNAL) { 1906 printf(" (internal%s%s)", 1907 com->pc98_8251fifo ? " fifo" : "", 1908 PC98SIO_baud_rate_port(com->pc98_if_type) != -1 ? 1909 " v-fast" : ""); 1910 } else { 1911 printf(" 8251%s", if_8251_type[com->pc98_if_type & 0x0f].name); 1912 } 1913 } else { 1914#endif /* PC98 */ 1915 sio_setreg(com, com_fifo, FIFO_ENABLE | FIFO_RX_HIGH); 1916 DELAY(100); 1917 com->st16650a = 0; 1918 switch (inb(com->int_id_port) & IIR_FIFO_MASK) { 1919 case FIFO_RX_LOW: 1920 printf(" 16450"); 1921 break; 1922 case FIFO_RX_MEDL: 1923 printf(" 16450?"); 1924 break; 1925 case FIFO_RX_MEDH: 1926 printf(" 16550?"); 1927 break; 1928 case FIFO_RX_HIGH: 1929 if (COM_NOFIFO(flags)) { 1930 printf(" 16550A fifo disabled"); 1931 } else { 1932 com->hasfifo = TRUE; 1933#ifdef PC98 1934 com->tx_fifo_size = 0; /* XXX flag conflicts. */ 1935 printf(" 16550A"); 1936#else 1937 if (COM_ST16650A(flags)) { 1938 com->st16650a = 1; 1939 com->tx_fifo_size = 32; 1940 printf(" ST16650A"); 1941 } else { 1942 com->tx_fifo_size = COM_FIFOSIZE(flags); 1943 printf(" 16550A"); 1944 } 1945#endif 1946 } 1947#ifdef PC98 1948 if (com->pc98_if_type == COM_IF_RSA98III) { 1949 com->tx_fifo_size = 2048; 1950 com->rsabase = iobase; 1951 outb(com->rsabase + rsa_ier, 0x00); 1952 outb(com->rsabase + rsa_frr, 0x00); 1953 } 1954#endif 1955 1956#ifdef COM_ESP 1957#ifdef PC98 1958 if (com->pc98_if_type == COM_IF_ESP98) 1959#endif 1960 for (espp = likely_esp_ports; *espp != 0; espp++) 1961 if (espattach(com, *espp)) { 1962 com->tx_fifo_size = 1024; 1963 break; 1964 } 1965#endif 1966 if (!com->st16650a) { 1967 if (!com->tx_fifo_size) 1968 com->tx_fifo_size = 16; 1969 else 1970 printf(" lookalike with %d bytes FIFO", 1971 com->tx_fifo_size); 1972 } 1973 1974 break; 1975 } 1976 1977#ifdef PC98 1978 if (com->pc98_if_type == COM_IF_RSB3000) { 1979 /* Set RSB-2000/3000 Extended Buffer mode. */ 1980 u_char lcr; 1981 lcr = sio_getreg(com, com_cfcr); 1982 sio_setreg(com, com_cfcr, lcr | CFCR_DLAB); 1983 sio_setreg(com, com_emr, EMR_EXBUFF | EMR_EFMODE); 1984 sio_setreg(com, com_cfcr, lcr); 1985 } 1986#endif 1987 1988#ifdef COM_ESP 1989 if (com->esp) { 1990 /* 1991 * Set 16550 compatibility mode. 1992 * We don't use the ESP_MODE_SCALE bit to increase the 1993 * fifo trigger levels because we can't handle large 1994 * bursts of input. 1995 * XXX flow control should be set in comparam(), not here. 1996 */ 1997#ifdef PC98 1998 outb(com->esp_port + ESP98_CMD1, ESP_SETMODE); 1999 outb(com->esp_port + ESP98_CMD2, ESP_MODE_RTS | ESP_MODE_FIFO); 2000#else 2001 outb(com->esp_port + ESP_CMD1, ESP_SETMODE); 2002 outb(com->esp_port + ESP_CMD2, ESP_MODE_RTS | ESP_MODE_FIFO); 2003#endif 2004 2005 /* Set RTS/CTS flow control. */ 2006#ifdef PC98 2007 outb(com->esp_port + ESP98_CMD1, ESP_SETFLOWTYPE); 2008 outb(com->esp_port + ESP98_CMD2, ESP_FLOW_RTS); 2009 outb(com->esp_port + ESP98_CMD2, ESP_FLOW_CTS); 2010#else 2011 outb(com->esp_port + ESP_CMD1, ESP_SETFLOWTYPE); 2012 outb(com->esp_port + ESP_CMD2, ESP_FLOW_RTS); 2013 outb(com->esp_port + ESP_CMD2, ESP_FLOW_CTS); 2014#endif 2015 2016 /* Set flow-control levels. */ 2017#ifdef PC98 2018 outb(com->esp_port + ESP98_CMD1, ESP_SETRXFLOW); 2019 outb(com->esp_port + ESP98_CMD2, HIBYTE(768)); 2020 outb(com->esp_port + ESP98_CMD2, LOBYTE(768)); 2021 outb(com->esp_port + ESP98_CMD2, HIBYTE(512)); 2022 outb(com->esp_port + ESP98_CMD2, LOBYTE(512)); 2023#else 2024 outb(com->esp_port + ESP_CMD1, ESP_SETRXFLOW); 2025 outb(com->esp_port + ESP_CMD2, HIBYTE(768)); 2026 outb(com->esp_port + ESP_CMD2, LOBYTE(768)); 2027 outb(com->esp_port + ESP_CMD2, HIBYTE(512)); 2028 outb(com->esp_port + ESP_CMD2, LOBYTE(512)); 2029#endif 2030 2031#ifdef PC98 2032 /* Set UART clock prescaler. */ 2033 outb(com->esp_port + ESP98_CMD1, ESP_SETCLOCK); 2034 outb(com->esp_port + ESP98_CMD2, 2); /* 4 times */ 2035#endif 2036 } 2037#endif /* COM_ESP */ 2038 sio_setreg(com, com_fifo, 0); 2039#ifdef PC98 2040 printf("%s", if_16550a_type[com->pc98_if_type & 0x0f].name); 2041#else 2042determined_type: ; 2043#endif 2044 2045#ifdef COM_MULTIPORT 2046 if (COM_ISMULTIPORT(flags)) { 2047 device_t masterdev; 2048 2049 com->multiport = TRUE; 2050 printf(" (multiport"); 2051 if (unit == COM_MPMASTER(flags)) 2052 printf(" master"); 2053 printf(")"); 2054 masterdev = devclass_get_device(sio_devclass, 2055 COM_MPMASTER(flags)); 2056 com->no_irq = (masterdev == NULL || bus_get_resource(masterdev, 2057 SYS_RES_IRQ, 0, NULL, NULL) != 0); 2058 } 2059#endif /* COM_MULTIPORT */ 2060#ifdef PC98 2061 } 2062#endif 2063 if (unit == comconsole) 2064 printf(", console"); 2065 if (COM_IIR_TXRDYBUG(flags)) 2066 printf(" with a bogus IIR_TXRDY register"); 2067 printf("\n"); 2068 2069 if (!sio_registered) { 2070 register_swi(SWI_TTY, siopoll); 2071 sio_registered = TRUE; 2072 } 2073 make_dev(&sio_cdevsw, unit, 2074 UID_ROOT, GID_WHEEL, 0600, "ttyd%r", unit); 2075 make_dev(&sio_cdevsw, unit | CONTROL_INIT_STATE, 2076 UID_ROOT, GID_WHEEL, 0600, "ttyid%r", unit); 2077 make_dev(&sio_cdevsw, unit | CONTROL_LOCK_STATE, 2078 UID_ROOT, GID_WHEEL, 0600, "ttyld%r", unit); 2079 make_dev(&sio_cdevsw, unit | CALLOUT_MASK, 2080 UID_UUCP, GID_DIALER, 0660, "cuaa%r", unit); 2081 make_dev(&sio_cdevsw, unit | CALLOUT_MASK | CONTROL_INIT_STATE, 2082 UID_UUCP, GID_DIALER, 0660, "cuaia%r", unit); 2083 make_dev(&sio_cdevsw, unit | CALLOUT_MASK | CONTROL_LOCK_STATE, 2084 UID_UUCP, GID_DIALER, 0660, "cuala%r", unit); 2085 com->flags = flags; 2086 com->pps.ppscap = PPS_CAPTUREASSERT | PPS_CAPTURECLEAR; 2087 pps_init(&com->pps); 2088 2089 rid = 0; 2090 com->irqres = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0ul, ~0ul, 1, 2091 RF_ACTIVE); 2092 if (com->irqres) { 2093 ret = BUS_SETUP_INTR(device_get_parent(dev), dev, com->irqres, 2094 INTR_TYPE_TTY | INTR_TYPE_FAST, 2095 siointr, com, &com->cookie); 2096 if (ret) { 2097 ret = BUS_SETUP_INTR(device_get_parent(dev), dev, 2098 com->irqres, INTR_TYPE_TTY, 2099 siointr, com, &com->cookie); 2100 if (ret == 0) 2101 device_printf(dev, "unable to activate interrupt in fast mode - using normal mode"); 2102 } 2103 if (ret) 2104 device_printf(dev, "could not activate interrupt\n"); 2105 } 2106 2107 return (0); 2108} 2109 2110static int 2111sioopen(dev, flag, mode, p) 2112 dev_t dev; 2113 int flag; 2114 int mode; 2115 struct proc *p; 2116{ 2117 struct com_s *com; 2118 int error; 2119 int mynor; 2120 int s; 2121 struct tty *tp; 2122 int unit; 2123 2124 mynor = minor(dev); 2125 unit = MINOR_TO_UNIT(mynor); 2126 com = com_addr(unit); 2127 if (com == NULL) 2128 return (ENXIO); 2129 if (com->gone) 2130 return (ENXIO); 2131 if (mynor & CONTROL_MASK) 2132 return (0); 2133 tp = dev->si_tty = com->tp = ttymalloc(com->tp); 2134 s = spltty(); 2135 /* 2136 * We jump to this label after all non-interrupted sleeps to pick 2137 * up any changes of the device state. 2138 */ 2139open_top: 2140 while (com->state & CS_DTR_OFF) { 2141 error = tsleep(&com->dtr_wait, TTIPRI | PCATCH, "siodtr", 0); 2142 if (com_addr(unit) == NULL) 2143 return (ENXIO); 2144 if (error != 0 || com->gone) 2145 goto out; 2146 } 2147 if (tp->t_state & TS_ISOPEN) { 2148 /* 2149 * The device is open, so everything has been initialized. 2150 * Handle conflicts. 2151 */ 2152 if (mynor & CALLOUT_MASK) { 2153 if (!com->active_out) { 2154 error = EBUSY; 2155 goto out; 2156 } 2157 } else { 2158 if (com->active_out) { 2159 if (flag & O_NONBLOCK) { 2160 error = EBUSY; 2161 goto out; 2162 } 2163 error = tsleep(&com->active_out, 2164 TTIPRI | PCATCH, "siobi", 0); 2165 if (com_addr(unit) == NULL) 2166 return (ENXIO); 2167 if (error != 0 || com->gone) 2168 goto out; 2169 goto open_top; 2170 } 2171 } 2172 if (tp->t_state & TS_XCLUDE && 2173 suser(p)) { 2174 error = EBUSY; 2175 goto out; 2176 } 2177 } else { 2178 /* 2179 * The device isn't open, so there are no conflicts. 2180 * Initialize it. Initialization is done twice in many 2181 * cases: to preempt sleeping callin opens if we are 2182 * callout, and to complete a callin open after DCD rises. 2183 */ 2184 tp->t_oproc = comstart; 2185 tp->t_param = comparam; 2186 tp->t_stop = comstop; 2187 tp->t_dev = dev; 2188 tp->t_termios = mynor & CALLOUT_MASK 2189 ? com->it_out : com->it_in; 2190#ifdef PC98 2191 if (!IS_8251(com->pc98_if_type)) 2192#endif 2193 (void)commctl(com, TIOCM_DTR | TIOCM_RTS, DMSET); 2194 com->poll = com->no_irq; 2195 com->poll_output = com->loses_outints; 2196 ++com->wopeners; 2197 error = comparam(tp, &tp->t_termios); 2198 --com->wopeners; 2199 if (error != 0) 2200 goto out; 2201#ifdef PC98 2202 if (IS_8251(com->pc98_if_type)) { 2203 com_tiocm_bis(com, TIOCM_DTR|TIOCM_RTS); 2204 pc98_msrint_start(dev); 2205 if (com->pc98_8251fifo) { 2206 com->pc98_8251fifo_enable = 1; 2207 outb(I8251F_fcr, CTRL8251F_ENABLE | 2208 CTRL8251F_XMT_RST | CTRL8251F_RCV_RST); 2209 } 2210 } 2211#endif 2212 /* 2213 * XXX we should goto open_top if comparam() slept. 2214 */ 2215 if (com->hasfifo) { 2216 /* 2217 * (Re)enable and drain fifos. 2218 * 2219 * Certain SMC chips cause problems if the fifos 2220 * are enabled while input is ready. Turn off the 2221 * fifo if necessary to clear the input. We test 2222 * the input ready bit after enabling the fifos 2223 * since we've already enabled them in comparam() 2224 * and to handle races between enabling and fresh 2225 * input. 2226 */ 2227 while (TRUE) { 2228 sio_setreg(com, com_fifo, 2229 FIFO_RCV_RST | FIFO_XMT_RST 2230 | com->fifo_image); 2231#ifdef PC98 2232 if (com->pc98_if_type == COM_IF_RSA98III) 2233 outb(com->rsabase + rsa_frr , 0x00); 2234#endif 2235 /* 2236 * XXX the delays are for superstitious 2237 * historical reasons. It must be less than 2238 * the character time at the maximum 2239 * supported speed (87 usec at 115200 bps 2240 * 8N1). Otherwise we might loop endlessly 2241 * if data is streaming in. We used to use 2242 * delays of 100. That usually worked 2243 * because DELAY(100) used to usually delay 2244 * for about 85 usec instead of 100. 2245 */ 2246 DELAY(50); 2247#ifdef PC98 2248 if (com->pc98_if_type == COM_IF_RSA98III ? 2249 !(inb(com->rsabase + rsa_srr) & 0x08) : 2250 !(inb(com->line_status_port) & LSR_RXRDY)) 2251 break; 2252#else 2253 if (!(inb(com->line_status_port) & LSR_RXRDY)) 2254 break; 2255#endif 2256 sio_setreg(com, com_fifo, 0); 2257 DELAY(50); 2258 (void) inb(com->data_port); 2259 } 2260 } 2261 2262 disable_intr(); 2263#ifdef PC98 2264 if (IS_8251(com->pc98_if_type)) { 2265 com_tiocm_bis(com, TIOCM_LE); 2266 com->pc98_prev_modem_status = pc98_get_modem_status(com); 2267 com_int_Rx_enable(com); 2268 } else { 2269#endif 2270 (void) inb(com->line_status_port); 2271 (void) inb(com->data_port); 2272 com->prev_modem_status = com->last_modem_status 2273 = inb(com->modem_status_port); 2274 if (COM_IIR_TXRDYBUG(com->flags)) { 2275 outb(com->intr_ctl_port, IER_ERXRDY | IER_ERLS 2276 | IER_EMSC); 2277 } else { 2278 outb(com->intr_ctl_port, IER_ERXRDY | IER_ETXRDY 2279 | IER_ERLS | IER_EMSC); 2280 } 2281#ifdef PC98 2282 if (com->pc98_if_type == COM_IF_RSA98III) { 2283 outb(com->rsabase + rsa_ier, 0x1d); 2284 outb(com->intr_ctl_port, IER_ERLS | IER_EMSC); 2285 } 2286#endif 2287#ifdef PC98 2288 } 2289#endif 2290 enable_intr(); 2291 /* 2292 * Handle initial DCD. Callout devices get a fake initial 2293 * DCD (trapdoor DCD). If we are callout, then any sleeping 2294 * callin opens get woken up and resume sleeping on "siobi" 2295 * instead of "siodcd". 2296 */ 2297 /* 2298 * XXX `mynor & CALLOUT_MASK' should be 2299 * `tp->t_cflag & (SOFT_CARRIER | TRAPDOOR_CARRIER) where 2300 * TRAPDOOR_CARRIER is the default initial state for callout 2301 * devices and SOFT_CARRIER is like CLOCAL except it hides 2302 * the true carrier. 2303 */ 2304#ifdef PC98 2305 if ((IS_8251(com->pc98_if_type) && 2306 (pc98_get_modem_status(com) & TIOCM_CAR)) || 2307 (!IS_8251(com->pc98_if_type) && 2308 (com->prev_modem_status & MSR_DCD)) || 2309 mynor & CALLOUT_MASK) 2310 (*linesw[tp->t_line].l_modem)(tp, 1); 2311#else 2312 if (com->prev_modem_status & MSR_DCD || mynor & CALLOUT_MASK) 2313 (*linesw[tp->t_line].l_modem)(tp, 1); 2314#endif 2315 } 2316 /* 2317 * Wait for DCD if necessary. 2318 */ 2319 if (!(tp->t_state & TS_CARR_ON) && !(mynor & CALLOUT_MASK) 2320 && !(tp->t_cflag & CLOCAL) && !(flag & O_NONBLOCK)) { 2321 ++com->wopeners; 2322 error = tsleep(TSA_CARR_ON(tp), TTIPRI | PCATCH, "siodcd", 0); 2323 if (com_addr(unit) == NULL) 2324 return (ENXIO); 2325 --com->wopeners; 2326 if (error != 0 || com->gone) 2327 goto out; 2328 goto open_top; 2329 } 2330 error = (*linesw[tp->t_line].l_open)(dev, tp); 2331 disc_optim(tp, &tp->t_termios, com); 2332 if (tp->t_state & TS_ISOPEN && mynor & CALLOUT_MASK) 2333 com->active_out = TRUE; 2334 siosettimeout(); 2335out: 2336 splx(s); 2337 if (!(tp->t_state & TS_ISOPEN) && com->wopeners == 0) 2338 comhardclose(com); 2339 return (error); 2340} 2341 2342static int 2343sioclose(dev, flag, mode, p) 2344 dev_t dev; 2345 int flag; 2346 int mode; 2347 struct proc *p; 2348{ 2349 struct com_s *com; 2350 int mynor; 2351 int s; 2352 struct tty *tp; 2353 2354 mynor = minor(dev); 2355 if (mynor & CONTROL_MASK) 2356 return (0); 2357 com = com_addr(MINOR_TO_UNIT(mynor)); 2358 if (com == NULL) 2359 return (ENODEV); 2360 tp = com->tp; 2361 s = spltty(); 2362 (*linesw[tp->t_line].l_close)(tp, flag); 2363#ifdef PC98 2364 com->modem_checking = 0; 2365#endif 2366 disc_optim(tp, &tp->t_termios, com); 2367 comstop(tp, FREAD | FWRITE); 2368 comhardclose(com); 2369 ttyclose(tp); 2370 siosettimeout(); 2371 splx(s); 2372 if (com->gone) { 2373 printf("sio%d: gone\n", com->unit); 2374 s = spltty(); 2375 if (com->ibuf != NULL) 2376 free(com->ibuf, M_DEVBUF); 2377 bzero(tp, sizeof *tp); 2378 splx(s); 2379 } 2380 return (0); 2381} 2382 2383static void 2384comhardclose(com) 2385 struct com_s *com; 2386{ 2387 int s; 2388 struct tty *tp; 2389 int unit; 2390 2391 unit = com->unit; 2392 s = spltty(); 2393 com->poll = FALSE; 2394 com->poll_output = FALSE; 2395 com->do_timestamp = FALSE; 2396 com->do_dcd_timestamp = FALSE; 2397 com->pps.ppsparam.mode = 0; 2398#ifdef PC98 2399 if (IS_8251(com->pc98_if_type)) 2400 com_send_break_off(com); 2401 else 2402#endif 2403 sio_setreg(com, com_cfcr, com->cfcr_image &= ~CFCR_SBREAK); 2404 { 2405#ifdef PC98 2406 int tmp; 2407 if (IS_8251(com->pc98_if_type)) 2408 com_int_TxRx_disable(com); 2409 else 2410 sio_setreg(com, com_ier, 0); 2411 if (com->pc98_if_type == COM_IF_RSA98III) 2412 outb(com->rsabase + rsa_ier, 0x00); 2413#else 2414 sio_setreg(com, com_ier, 0); 2415#endif 2416 tp = com->tp; 2417#ifdef PC98 2418 if (IS_8251(com->pc98_if_type)) 2419 tmp = pc98_get_modem_status(com) & TIOCM_CAR; 2420 else 2421 tmp = com->prev_modem_status & MSR_DCD; 2422#endif 2423 if (tp->t_cflag & HUPCL 2424 /* 2425 * XXX we will miss any carrier drop between here and the 2426 * next open. Perhaps we should watch DCD even when the 2427 * port is closed; it is not sufficient to check it at 2428 * the next open because it might go up and down while 2429 * we're not watching. 2430 */ 2431 || (!com->active_out 2432#ifdef PC98 2433 && !(tmp) 2434#else 2435 && !(com->prev_modem_status & MSR_DCD) 2436#endif 2437 && !(com->it_in.c_cflag & CLOCAL)) 2438 || !(tp->t_state & TS_ISOPEN)) { 2439#ifdef PC98 2440 if (IS_8251(com->pc98_if_type)) 2441 com_tiocm_bic(com, TIOCM_DTR|TIOCM_RTS|TIOCM_LE); 2442 else 2443#endif 2444 (void)commctl(com, TIOCM_DTR, DMBIC); 2445 if (com->dtr_wait != 0 && !(com->state & CS_DTR_OFF)) { 2446 timeout(siodtrwakeup, com, com->dtr_wait); 2447 com->state |= CS_DTR_OFF; 2448 } 2449 } 2450#ifdef PC98 2451 else { 2452 if (IS_8251(com->pc98_if_type)) 2453 com_tiocm_bic(com, TIOCM_LE); 2454 } 2455#endif 2456 } 2457#ifdef PC98 2458 if (com->pc98_8251fifo) { 2459 if (com->pc98_8251fifo_enable) 2460 outb(I8251F_fcr, CTRL8251F_XMT_RST | CTRL8251F_RCV_RST); 2461 com->pc98_8251fifo_enable = 0; 2462 } 2463#endif 2464 if (com->hasfifo) { 2465 /* 2466 * Disable fifos so that they are off after controlled 2467 * reboots. Some BIOSes fail to detect 16550s when the 2468 * fifos are enabled. 2469 */ 2470 sio_setreg(com, com_fifo, 0); 2471 } 2472 com->active_out = FALSE; 2473 wakeup(&com->active_out); 2474 wakeup(TSA_CARR_ON(tp)); /* restart any wopeners */ 2475 splx(s); 2476} 2477 2478static int 2479sioread(dev, uio, flag) 2480 dev_t dev; 2481 struct uio *uio; 2482 int flag; 2483{ 2484 int mynor; 2485 struct com_s *com; 2486 2487 mynor = minor(dev); 2488 if (mynor & CONTROL_MASK) 2489 return (ENODEV); 2490 com = com_addr(MINOR_TO_UNIT(mynor)); 2491 if (com == NULL || com->gone) 2492 return (ENODEV); 2493 return ((*linesw[com->tp->t_line].l_read)(com->tp, uio, flag)); 2494} 2495 2496static int 2497siowrite(dev, uio, flag) 2498 dev_t dev; 2499 struct uio *uio; 2500 int flag; 2501{ 2502 int mynor; 2503 struct com_s *com; 2504 int unit; 2505 2506 mynor = minor(dev); 2507 if (mynor & CONTROL_MASK) 2508 return (ENODEV); 2509 2510 unit = MINOR_TO_UNIT(mynor); 2511 com = com_addr(unit); 2512 if (com == NULL || com->gone) 2513 return (ENODEV); 2514 /* 2515 * (XXX) We disallow virtual consoles if the physical console is 2516 * a serial port. This is in case there is a display attached that 2517 * is not the console. In that situation we don't need/want the X 2518 * server taking over the console. 2519 */ 2520 if (constty != NULL && unit == comconsole) 2521 constty = NULL; 2522 return ((*linesw[com->tp->t_line].l_write)(com->tp, uio, flag)); 2523} 2524 2525static void 2526siobusycheck(chan) 2527 void *chan; 2528{ 2529 struct com_s *com; 2530 int s; 2531 2532 com = (struct com_s *)chan; 2533 2534 /* 2535 * Clear TS_BUSY if low-level output is complete. 2536 * spl locking is sufficient because siointr1() does not set CS_BUSY. 2537 * If siointr1() clears CS_BUSY after we look at it, then we'll get 2538 * called again. Reading the line status port outside of siointr1() 2539 * is safe because CS_BUSY is clear so there are no output interrupts 2540 * to lose. 2541 */ 2542 s = spltty(); 2543 if (com->state & CS_BUSY) 2544 com->extra_state &= ~CSE_BUSYCHECK; /* False alarm. */ 2545#ifdef PC98 2546 else if ((IS_8251(com->pc98_if_type) && 2547 ((com->pc98_8251fifo_enable && 2548 (inb(I8251F_lsr) & (STS8251F_TxRDY | STS8251F_TxEMP)) 2549 == (STS8251F_TxRDY | STS8251F_TxEMP)) || 2550 (!com->pc98_8251fifo_enable && 2551 (inb(com->sts_port) & (STS8251_TxRDY | STS8251_TxEMP)) 2552 == (STS8251_TxRDY | STS8251_TxEMP)))) || 2553 ((inb(com->line_status_port) & (LSR_TSRE | LSR_TXRDY)) 2554 == (LSR_TSRE | LSR_TXRDY))) { 2555#else 2556 else if ((inb(com->line_status_port) & (LSR_TSRE | LSR_TXRDY)) 2557 == (LSR_TSRE | LSR_TXRDY)) { 2558#endif 2559 com->tp->t_state &= ~TS_BUSY; 2560 ttwwakeup(com->tp); 2561 com->extra_state &= ~CSE_BUSYCHECK; 2562 } else 2563 timeout(siobusycheck, com, hz / 100); 2564 splx(s); 2565} 2566 2567static void 2568siodtrwakeup(chan) 2569 void *chan; 2570{ 2571 struct com_s *com; 2572 2573 com = (struct com_s *)chan; 2574 com->state &= ~CS_DTR_OFF; 2575 wakeup(&com->dtr_wait); 2576} 2577 2578static void 2579sioinput(com) 2580 struct com_s *com; 2581{ 2582 u_char *buf; 2583 int incc; 2584 u_char line_status; 2585 int recv_data; 2586 struct tty *tp; 2587 2588 buf = com->ibuf; 2589 tp = com->tp; 2590 if (!(tp->t_state & TS_ISOPEN) || !(tp->t_cflag & CREAD)) { 2591 com_events -= (com->iptr - com->ibuf); 2592 com->iptr = com->ibuf; 2593 return; 2594 } 2595 if (tp->t_state & TS_CAN_BYPASS_L_RINT) { 2596 /* 2597 * Avoid the grotesquely inefficient lineswitch routine 2598 * (ttyinput) in "raw" mode. It usually takes about 450 2599 * instructions (that's without canonical processing or echo!). 2600 * slinput is reasonably fast (usually 40 instructions plus 2601 * call overhead). 2602 */ 2603 do { 2604 enable_intr(); 2605 incc = com->iptr - buf; 2606 if (tp->t_rawq.c_cc + incc > tp->t_ihiwat 2607 && (com->state & CS_RTS_IFLOW 2608 || tp->t_iflag & IXOFF) 2609 && !(tp->t_state & TS_TBLOCK)) 2610 ttyblock(tp); 2611 com->delta_error_counts[CE_TTY_BUF_OVERFLOW] 2612 += b_to_q((char *)buf, incc, &tp->t_rawq); 2613 buf += incc; 2614 tk_nin += incc; 2615 tk_rawcc += incc; 2616 tp->t_rawcc += incc; 2617 ttwakeup(tp); 2618 if (tp->t_state & TS_TTSTOP 2619 && (tp->t_iflag & IXANY 2620 || tp->t_cc[VSTART] == tp->t_cc[VSTOP])) { 2621 tp->t_state &= ~TS_TTSTOP; 2622 tp->t_lflag &= ~FLUSHO; 2623 comstart(tp); 2624 } 2625 disable_intr(); 2626 } while (buf < com->iptr); 2627 } else { 2628 do { 2629 enable_intr(); 2630 line_status = buf[com->ierroff]; 2631 recv_data = *buf++; 2632 if (line_status 2633 & (LSR_BI | LSR_FE | LSR_OE | LSR_PE)) { 2634 if (line_status & LSR_BI) 2635 recv_data |= TTY_BI; 2636 if (line_status & LSR_FE) 2637 recv_data |= TTY_FE; 2638 if (line_status & LSR_OE) 2639 recv_data |= TTY_OE; 2640 if (line_status & LSR_PE) 2641 recv_data |= TTY_PE; 2642 } 2643 (*linesw[tp->t_line].l_rint)(recv_data, tp); 2644 disable_intr(); 2645 } while (buf < com->iptr); 2646 } 2647 com_events -= (com->iptr - com->ibuf); 2648 com->iptr = com->ibuf; 2649 2650 /* 2651 * There is now room for another low-level buffer full of input, 2652 * so enable RTS if it is now disabled and there is room in the 2653 * high-level buffer. 2654 */ 2655#ifdef PC98 2656 if (IS_8251(com->pc98_if_type)) { 2657 if ((com->state & CS_RTS_IFLOW) && 2658 !(com_tiocm_get(com) & TIOCM_RTS) && 2659 !(tp->t_state & TS_TBLOCK)) 2660 com_tiocm_bis(com, TIOCM_RTS); 2661 } else { 2662 if ((com->state & CS_RTS_IFLOW) && 2663 !(com->mcr_image & MCR_RTS) && 2664 !(tp->t_state & TS_TBLOCK)) 2665 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS); 2666 } 2667#else 2668 if ((com->state & CS_RTS_IFLOW) && !(com->mcr_image & MCR_RTS) && 2669 !(tp->t_state & TS_TBLOCK)) 2670 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS); 2671#endif 2672} 2673 2674void 2675siointr(arg) 2676 void *arg; 2677{ 2678#ifndef COM_MULTIPORT 2679 COM_LOCK(); 2680 siointr1((struct com_s *) arg); 2681 COM_UNLOCK(); 2682#else /* COM_MULTIPORT */ 2683 bool_t possibly_more_intrs; 2684 int unit; 2685 struct com_s *com; 2686#ifdef PC98 2687 u_char rsa_buf_status; 2688#endif 2689 2690 /* 2691 * Loop until there is no activity on any port. This is necessary 2692 * to get an interrupt edge more than to avoid another interrupt. 2693 * If the IRQ signal is just an OR of the IRQ signals from several 2694 * devices, then the edge from one may be lost because another is 2695 * on. 2696 */ 2697 COM_LOCK(); 2698 do { 2699 possibly_more_intrs = FALSE; 2700 for (unit = 0; unit < sio_numunits; ++unit) { 2701 com = com_addr(unit); 2702 /* 2703 * XXX COM_LOCK(); 2704 * would it work here, or be counter-productive? 2705 */ 2706#ifdef PC98 2707 if (com != NULL 2708 && !com->gone 2709 && IS_8251(com->pc98_if_type)) { 2710 siointr1(com); 2711 } else if (com != NULL 2712 && !com->gone 2713 && com->pc98_if_type == COM_IF_RSA98III) { 2714 rsa_buf_status = 2715 inb(com->rsabase + rsa_srr) & 0xc9; 2716 if ((rsa_buf_status & 0xc8) 2717 || !(rsa_buf_status & 0x01)) { 2718 siointr1(com); 2719 if (rsa_buf_status != 2720 (inb(com->rsabase + rsa_srr) & 0xc9)) 2721 possibly_more_intrs = TRUE; 2722 } 2723 } else 2724#endif 2725 if (com != NULL 2726 && !com->gone 2727 && (inb(com->int_id_port) & IIR_IMASK) 2728 != IIR_NOPEND) { 2729 siointr1(com); 2730 possibly_more_intrs = TRUE; 2731 } 2732 /* XXX COM_UNLOCK(); */ 2733 } 2734 } while (possibly_more_intrs); 2735 COM_UNLOCK(); 2736#endif /* COM_MULTIPORT */ 2737} 2738 2739static void 2740siointr1(com) 2741 struct com_s *com; 2742{ 2743 u_char line_status; 2744 u_char modem_status; 2745 u_char *ioptr; 2746 u_char recv_data; 2747 u_char int_ctl; 2748 u_char int_ctl_new; 2749 struct timecounter *tc; 2750 u_int count; 2751 2752#ifdef PC98 2753 u_char tmp = 0; 2754 u_char rsa_buf_status = 0; 2755 int rsa_tx_fifo_size = 0; 2756#endif /* PC98 */ 2757 2758 int_ctl = inb(com->intr_ctl_port); 2759 int_ctl_new = int_ctl; 2760 2761 while (!com->gone) { 2762#ifdef PC98 2763status_read:; 2764 if (IS_8251(com->pc98_if_type)) { 2765 if (com->pc98_8251fifo_enable) 2766 tmp = inb(I8251F_lsr); 2767 else 2768 tmp = inb(com->sts_port); 2769more_intr: 2770 line_status = 0; 2771 if (com->pc98_8251fifo_enable) { 2772 if (tmp & STS8251F_TxRDY) line_status |= LSR_TXRDY; 2773 if (tmp & STS8251F_RxRDY) line_status |= LSR_RXRDY; 2774 if (tmp & STS8251F_TxEMP) line_status |= LSR_TSRE; 2775 if (tmp & STS8251F_PE) line_status |= LSR_PE; 2776 if (tmp & STS8251F_OE) line_status |= LSR_OE; 2777 if (tmp & STS8251F_BD_SD) line_status |= LSR_BI; 2778 } else { 2779 if (tmp & STS8251_TxRDY) line_status |= LSR_TXRDY; 2780 if (tmp & STS8251_RxRDY) line_status |= LSR_RXRDY; 2781 if (tmp & STS8251_TxEMP) line_status |= LSR_TSRE; 2782 if (tmp & STS8251_PE) line_status |= LSR_PE; 2783 if (tmp & STS8251_OE) line_status |= LSR_OE; 2784 if (tmp & STS8251_FE) line_status |= LSR_FE; 2785 if (tmp & STS8251_BD_SD) line_status |= LSR_BI; 2786 } 2787 } else { 2788#endif /* PC98 */ 2789 if (com->pps.ppsparam.mode & PPS_CAPTUREBOTH) { 2790 modem_status = inb(com->modem_status_port); 2791 if ((modem_status ^ com->last_modem_status) & MSR_DCD) { 2792 tc = timecounter; 2793 count = tc->tc_get_timecount(tc); 2794 pps_event(&com->pps, tc, count, 2795 (modem_status & MSR_DCD) ? 2796 PPS_CAPTUREASSERT : PPS_CAPTURECLEAR); 2797 } 2798 } 2799 line_status = inb(com->line_status_port); 2800#ifdef PC98 2801 } 2802 if (com->pc98_if_type == COM_IF_RSA98III) 2803 rsa_buf_status = inb(com->rsabase + rsa_srr); 2804#endif /* PC98 */ 2805 2806 /* input event? (check first to help avoid overruns) */ 2807#ifndef PC98 2808 while (line_status & LSR_RCV_MASK) { 2809#else 2810 while ((line_status & LSR_RCV_MASK) 2811 || (com->pc98_if_type == COM_IF_RSA98III 2812 && (rsa_buf_status & 0x08))) { 2813#endif /* PC98 */ 2814 /* break/unnattached error bits or real input? */ 2815#ifdef PC98 2816 if (IS_8251(com->pc98_if_type)) { 2817 if (com->pc98_8251fifo_enable) { 2818 recv_data = inb(I8251F_data); 2819 if (tmp & (STS8251F_PE | STS8251F_OE | 2820 STS8251F_BD_SD)) { 2821 pc98_i8251_or_cmd(com, CMD8251_ER); 2822 recv_data = 0; 2823 } 2824 } else { 2825 recv_data = inb(com->data_port); 2826 if (tmp & (STS8251_PE | STS8251_OE | 2827 STS8251_FE | STS8251_BD_SD)) { 2828 pc98_i8251_or_cmd(com, CMD8251_ER); 2829 recv_data = 0; 2830 } 2831 } 2832 } else if (com->pc98_if_type == COM_IF_RSA98III) { 2833 if (!(rsa_buf_status & 0x08)) 2834 recv_data = 0; 2835 else 2836 recv_data = inb(com->data_port); 2837 } else 2838#endif 2839 if (!(line_status & LSR_RXRDY)) 2840 recv_data = 0; 2841 else 2842 recv_data = inb(com->data_port); 2843 if (line_status & (LSR_BI | LSR_FE | LSR_PE)) { 2844 /* 2845 * Don't store BI if IGNBRK or FE/PE if IGNPAR. 2846 * Otherwise, push the work to a higher level 2847 * (to handle PARMRK) if we're bypassing. 2848 * Otherwise, convert BI/FE and PE+INPCK to 0. 2849 * 2850 * This makes bypassing work right in the 2851 * usual "raw" case (IGNBRK set, and IGNPAR 2852 * and INPCK clear). 2853 * 2854 * Note: BI together with FE/PE means just BI. 2855 */ 2856 if (line_status & LSR_BI) { 2857#if defined(DDB) && defined(BREAK_TO_DEBUGGER) 2858 if (com->unit == comconsole) { 2859 breakpoint(); 2860 goto cont; 2861 } 2862#endif 2863 if (com->tp == NULL 2864 || com->tp->t_iflag & IGNBRK) 2865 goto cont; 2866 } else { 2867 if (com->tp == NULL 2868 || com->tp->t_iflag & IGNPAR) 2869 goto cont; 2870 } 2871 if (com->tp->t_state & TS_CAN_BYPASS_L_RINT 2872 && (line_status & (LSR_BI | LSR_FE) 2873 || com->tp->t_iflag & INPCK)) 2874 recv_data = 0; 2875 } 2876 ++com->bytes_in; 2877 if (com->hotchar != 0 && recv_data == com->hotchar) 2878 setsofttty(); 2879 ioptr = com->iptr; 2880 if (ioptr >= com->ibufend) 2881 CE_RECORD(com, CE_INTERRUPT_BUF_OVERFLOW); 2882 else { 2883 if (com->do_timestamp) 2884 microtime(&com->timestamp); 2885 ++com_events; 2886 schedsofttty(); 2887#if 0 /* for testing input latency vs efficiency */ 2888if (com->iptr - com->ibuf == 8) 2889 setsofttty(); 2890#endif 2891 ioptr[0] = recv_data; 2892 ioptr[com->ierroff] = line_status; 2893 com->iptr = ++ioptr; 2894 if (ioptr == com->ihighwater 2895 && com->state & CS_RTS_IFLOW) 2896#ifdef PC98 2897 IS_8251(com->pc98_if_type) ? 2898 com_tiocm_bic(com, TIOCM_RTS) : 2899#endif 2900 outb(com->modem_ctl_port, 2901 com->mcr_image &= ~MCR_RTS); 2902 if (line_status & LSR_OE) 2903 CE_RECORD(com, CE_OVERRUN); 2904 } 2905cont: 2906 /* 2907 * "& 0x7F" is to avoid the gcc-1.40 generating a slow 2908 * jump from the top of the loop to here 2909 */ 2910#ifdef PC98 2911 if (IS_8251(com->pc98_if_type)) 2912 goto status_read; 2913 else 2914#endif 2915 line_status = inb(com->line_status_port) & 0x7F; 2916#ifdef PC98 2917 if (com->pc98_if_type == COM_IF_RSA98III) 2918 rsa_buf_status = inb(com->rsabase + rsa_srr); 2919#endif /* PC98 */ 2920 } 2921 2922 /* modem status change? (always check before doing output) */ 2923#ifdef PC98 2924 if (!IS_8251(com->pc98_if_type)) { 2925#endif 2926 modem_status = inb(com->modem_status_port); 2927 if (modem_status != com->last_modem_status) { 2928 if (com->do_dcd_timestamp 2929 && !(com->last_modem_status & MSR_DCD) 2930 && modem_status & MSR_DCD) 2931 microtime(&com->dcd_timestamp); 2932 2933 /* 2934 * Schedule high level to handle DCD changes. Note 2935 * that we don't use the delta bits anywhere. Some 2936 * UARTs mess them up, and it's easy to remember the 2937 * previous bits and calculate the delta. 2938 */ 2939 com->last_modem_status = modem_status; 2940 if (!(com->state & CS_CHECKMSR)) { 2941 com_events += LOTS_OF_EVENTS; 2942 com->state |= CS_CHECKMSR; 2943 setsofttty(); 2944 } 2945 2946 /* handle CTS change immediately for crisp flow ctl */ 2947 if (com->state & CS_CTS_OFLOW) { 2948 if (modem_status & MSR_CTS) 2949 com->state |= CS_ODEVREADY; 2950 else 2951 com->state &= ~CS_ODEVREADY; 2952 } 2953 } 2954#ifdef PC98 2955 } 2956#endif 2957 2958 /* output queued and everything ready? */ 2959#ifndef PC98 2960 if (line_status & LSR_TXRDY 2961 && com->state >= (CS_BUSY | CS_TTGO | CS_ODEVREADY)) { 2962#else 2963 if (((com->pc98_if_type == COM_IF_RSA98III) 2964 ? (rsa_buf_status & 0x02) 2965 : (line_status & LSR_TXRDY)) 2966 && com->state >= (CS_BUSY | CS_TTGO | CS_ODEVREADY)) { 2967#endif 2968#ifdef PC98 2969 Port_t tmp_data_port; 2970 2971 if (IS_8251(com->pc98_if_type) && 2972 com->pc98_8251fifo_enable) 2973 tmp_data_port = I8251F_data; 2974 else 2975 tmp_data_port = com->data_port; 2976#endif 2977 2978 ioptr = com->obufq.l_head; 2979 if (com->tx_fifo_size > 1) { 2980 u_int ocount; 2981 2982 ocount = com->obufq.l_tail - ioptr; 2983#ifdef PC98 2984 if (com->pc98_if_type == COM_IF_RSA98III) { 2985 rsa_buf_status = inb(com->rsabase + rsa_srr); 2986 rsa_tx_fifo_size = 1024; 2987 if (!(rsa_buf_status & 0x01)) 2988 rsa_tx_fifo_size = 2048; 2989 if (ocount > rsa_tx_fifo_size) 2990 ocount = rsa_tx_fifo_size; 2991 } else 2992#endif 2993 if (ocount > com->tx_fifo_size) 2994 ocount = com->tx_fifo_size; 2995 com->bytes_out += ocount; 2996 do 2997#ifdef PC98 2998 outb(tmp_data_port, *ioptr++); 2999#else 3000 outb(com->data_port, *ioptr++); 3001#endif 3002 while (--ocount != 0); 3003 } else { 3004#ifdef PC98 3005 outb(tmp_data_port, *ioptr++); 3006#else 3007 outb(com->data_port, *ioptr++); 3008#endif 3009 ++com->bytes_out; 3010 } 3011#ifdef PC98 3012 if (IS_8251(com->pc98_if_type)) 3013 if (!(pc98_check_i8251_interrupt(com) & IEN_TxFLAG)) 3014 com_int_Tx_enable(com); 3015#endif 3016 com->obufq.l_head = ioptr; 3017 if (COM_IIR_TXRDYBUG(com->flags)) { 3018 int_ctl_new = int_ctl | IER_ETXRDY; 3019 } 3020 if (ioptr >= com->obufq.l_tail) { 3021 struct lbq *qp; 3022 3023 qp = com->obufq.l_next; 3024 qp->l_queued = FALSE; 3025 qp = qp->l_next; 3026 if (qp != NULL) { 3027 com->obufq.l_head = qp->l_head; 3028 com->obufq.l_tail = qp->l_tail; 3029 com->obufq.l_next = qp; 3030 } else { 3031 /* output just completed */ 3032 if (COM_IIR_TXRDYBUG(com->flags)) { 3033 int_ctl_new = int_ctl & ~IER_ETXRDY; 3034 } 3035 com->state &= ~CS_BUSY; 3036#if defined(PC98) 3037 if (IS_8251(com->pc98_if_type) && 3038 pc98_check_i8251_interrupt(com) & IEN_TxFLAG) 3039 com_int_Tx_disable(com); 3040#endif 3041 } 3042 if (!(com->state & CS_ODONE)) { 3043 com_events += LOTS_OF_EVENTS; 3044 com->state |= CS_ODONE; 3045 setsofttty(); /* handle at high level ASAP */ 3046 } 3047 } 3048 if (COM_IIR_TXRDYBUG(com->flags) && (int_ctl != int_ctl_new)) { 3049#ifdef PC98 3050 if (com->pc98_if_type == COM_IF_RSA98III) { 3051 int_ctl_new &= ~(IER_ETXRDY | IER_ERXRDY); 3052 outb(com->intr_ctl_port, int_ctl_new); 3053 outb(com->rsabase + rsa_ier, 0x1d); 3054 } else 3055#endif 3056 outb(com->intr_ctl_port, int_ctl_new); 3057 } 3058 } 3059#ifdef PC98 3060 else if (line_status & LSR_TXRDY) { 3061 if (IS_8251(com->pc98_if_type)) 3062 if (pc98_check_i8251_interrupt(com) & IEN_TxFLAG) 3063 com_int_Tx_disable(com); 3064 } 3065 if (IS_8251(com->pc98_if_type)) { 3066 if (com->pc98_8251fifo_enable) { 3067 if ((tmp = inb(I8251F_lsr)) & STS8251F_RxRDY) 3068 goto more_intr; 3069 } else { 3070 if ((tmp = inb(com->sts_port)) & STS8251_RxRDY) 3071 goto more_intr; 3072 } 3073 } 3074#endif 3075 3076 /* finished? */ 3077#ifndef COM_MULTIPORT 3078#ifdef PC98 3079 if (IS_8251(com->pc98_if_type)) 3080 return; 3081#endif 3082 if ((inb(com->int_id_port) & IIR_IMASK) == IIR_NOPEND) 3083#endif /* COM_MULTIPORT */ 3084 return; 3085 } 3086} 3087 3088static int 3089sioioctl(dev, cmd, data, flag, p) 3090 dev_t dev; 3091 u_long cmd; 3092 caddr_t data; 3093 int flag; 3094 struct proc *p; 3095{ 3096 struct com_s *com; 3097 int error; 3098 int mynor; 3099 int s; 3100 struct tty *tp; 3101#if defined(COMPAT_43) || defined(COMPAT_SUNOS) 3102 u_long oldcmd; 3103 struct termios term; 3104#endif 3105 3106 mynor = minor(dev); 3107 com = com_addr(MINOR_TO_UNIT(mynor)); 3108 if (com == NULL || com->gone) 3109 return (ENODEV); 3110 if (mynor & CONTROL_MASK) { 3111 struct termios *ct; 3112 3113 switch (mynor & CONTROL_MASK) { 3114 case CONTROL_INIT_STATE: 3115 ct = mynor & CALLOUT_MASK ? &com->it_out : &com->it_in; 3116 break; 3117 case CONTROL_LOCK_STATE: 3118 ct = mynor & CALLOUT_MASK ? &com->lt_out : &com->lt_in; 3119 break; 3120 default: 3121 return (ENODEV); /* /dev/nodev */ 3122 } 3123 switch (cmd) { 3124 case TIOCSETA: 3125 error = suser(p); 3126 if (error != 0) 3127 return (error); 3128 *ct = *(struct termios *)data; 3129 return (0); 3130 case TIOCGETA: 3131 *(struct termios *)data = *ct; 3132 return (0); 3133 case TIOCGETD: 3134 *(int *)data = TTYDISC; 3135 return (0); 3136 case TIOCGWINSZ: 3137 bzero(data, sizeof(struct winsize)); 3138 return (0); 3139 default: 3140 return (ENOTTY); 3141 } 3142 } 3143 tp = com->tp; 3144#if defined(COMPAT_43) || defined(COMPAT_SUNOS) 3145 term = tp->t_termios; 3146 oldcmd = cmd; 3147 error = ttsetcompat(tp, &cmd, data, &term); 3148 if (error != 0) 3149 return (error); 3150 if (cmd != oldcmd) 3151 data = (caddr_t)&term; 3152#endif 3153 if (cmd == TIOCSETA || cmd == TIOCSETAW || cmd == TIOCSETAF) { 3154 int cc; 3155 struct termios *dt = (struct termios *)data; 3156 struct termios *lt = mynor & CALLOUT_MASK 3157 ? &com->lt_out : &com->lt_in; 3158 3159 dt->c_iflag = (tp->t_iflag & lt->c_iflag) 3160 | (dt->c_iflag & ~lt->c_iflag); 3161 dt->c_oflag = (tp->t_oflag & lt->c_oflag) 3162 | (dt->c_oflag & ~lt->c_oflag); 3163 dt->c_cflag = (tp->t_cflag & lt->c_cflag) 3164 | (dt->c_cflag & ~lt->c_cflag); 3165 dt->c_lflag = (tp->t_lflag & lt->c_lflag) 3166 | (dt->c_lflag & ~lt->c_lflag); 3167 for (cc = 0; cc < NCCS; ++cc) 3168 if (lt->c_cc[cc] != 0) 3169 dt->c_cc[cc] = tp->t_cc[cc]; 3170 if (lt->c_ispeed != 0) 3171 dt->c_ispeed = tp->t_ispeed; 3172 if (lt->c_ospeed != 0) 3173 dt->c_ospeed = tp->t_ospeed; 3174 } 3175 error = (*linesw[tp->t_line].l_ioctl)(tp, cmd, data, flag, p); 3176 if (error != ENOIOCTL) 3177 return (error); 3178 s = spltty(); 3179 error = ttioctl(tp, cmd, data, flag); 3180 disc_optim(tp, &tp->t_termios, com); 3181 if (error != ENOIOCTL) { 3182 splx(s); 3183 return (error); 3184 } 3185#ifdef PC98 3186 if (IS_8251(com->pc98_if_type)) { 3187 switch (cmd) { 3188 case TIOCSBRK: 3189 com_send_break_on(com); 3190 break; 3191 case TIOCCBRK: 3192 com_send_break_off(com); 3193 break; 3194 case TIOCSDTR: 3195 com_tiocm_bis(com, TIOCM_DTR | TIOCM_RTS); 3196 break; 3197 case TIOCCDTR: 3198 com_tiocm_bic(com, TIOCM_DTR); 3199 break; 3200 /* 3201 * XXX should disallow changing MCR_RTS if CS_RTS_IFLOW is set. The 3202 * changes get undone on the next call to comparam(). 3203 */ 3204 case TIOCMSET: 3205 com_tiocm_set(com, *(int *)data); 3206 break; 3207 case TIOCMBIS: 3208 com_tiocm_bis(com, *(int *)data); 3209 break; 3210 case TIOCMBIC: 3211 com_tiocm_bic(com, *(int *)data); 3212 break; 3213 case TIOCMGET: 3214 *(int *)data = com_tiocm_get(com); 3215 break; 3216 case TIOCMSDTRWAIT: 3217 /* must be root since the wait applies to following logins */ 3218 error = suser(p); 3219 if (error != 0) { 3220 splx(s); 3221 return (error); 3222 } 3223 com->dtr_wait = *(int *)data * hz / 100; 3224 break; 3225 case TIOCMGDTRWAIT: 3226 *(int *)data = com->dtr_wait * 100 / hz; 3227 break; 3228 case TIOCTIMESTAMP: 3229 com->do_timestamp = TRUE; 3230 *(struct timeval *)data = com->timestamp; 3231 break; 3232 case TIOCDCDTIMESTAMP: 3233 com->do_dcd_timestamp = TRUE; 3234 *(struct timeval *)data = com->dcd_timestamp; 3235 break; 3236 default: 3237 splx(s); 3238 error = pps_ioctl(cmd, data, &com->pps); 3239 if (error == ENODEV) 3240 error = ENOTTY; 3241 return (error); 3242 } 3243 } else { 3244#endif 3245 switch (cmd) { 3246 case TIOCSBRK: 3247 sio_setreg(com, com_cfcr, com->cfcr_image |= CFCR_SBREAK); 3248 break; 3249 case TIOCCBRK: 3250 sio_setreg(com, com_cfcr, com->cfcr_image &= ~CFCR_SBREAK); 3251 break; 3252 case TIOCSDTR: 3253 (void)commctl(com, TIOCM_DTR, DMBIS); 3254 break; 3255 case TIOCCDTR: 3256 (void)commctl(com, TIOCM_DTR, DMBIC); 3257 break; 3258 /* 3259 * XXX should disallow changing MCR_RTS if CS_RTS_IFLOW is set. The 3260 * changes get undone on the next call to comparam(). 3261 */ 3262 case TIOCMSET: 3263 (void)commctl(com, *(int *)data, DMSET); 3264 break; 3265 case TIOCMBIS: 3266 (void)commctl(com, *(int *)data, DMBIS); 3267 break; 3268 case TIOCMBIC: 3269 (void)commctl(com, *(int *)data, DMBIC); 3270 break; 3271 case TIOCMGET: 3272 *(int *)data = commctl(com, 0, DMGET); 3273 break; 3274 case TIOCMSDTRWAIT: 3275 /* must be root since the wait applies to following logins */ 3276 error = suser(p); 3277 if (error != 0) { 3278 splx(s); 3279 return (error); 3280 } 3281 com->dtr_wait = *(int *)data * hz / 100; 3282 break; 3283 case TIOCMGDTRWAIT: 3284 *(int *)data = com->dtr_wait * 100 / hz; 3285 break; 3286 case TIOCTIMESTAMP: 3287 com->do_timestamp = TRUE; 3288 *(struct timeval *)data = com->timestamp; 3289 break; 3290 case TIOCDCDTIMESTAMP: 3291 com->do_dcd_timestamp = TRUE; 3292 *(struct timeval *)data = com->dcd_timestamp; 3293 break; 3294 default: 3295 splx(s); 3296 error = pps_ioctl(cmd, data, &com->pps); 3297 if (error == ENODEV) 3298 error = ENOTTY; 3299 return (error); 3300 } 3301#ifdef PC98 3302 } 3303#endif 3304 splx(s); 3305 return (0); 3306} 3307 3308static void 3309siopoll() 3310{ 3311 int unit; 3312 3313 if (com_events == 0) 3314 return; 3315repeat: 3316 for (unit = 0; unit < sio_numunits; ++unit) { 3317 struct com_s *com; 3318 int incc; 3319 struct tty *tp; 3320 3321 com = com_addr(unit); 3322 if (com == NULL) 3323 continue; 3324 tp = com->tp; 3325 if (tp == NULL || com->gone) { 3326 /* 3327 * Discard any events related to never-opened or 3328 * going-away devices. 3329 */ 3330 disable_intr(); 3331 incc = com->iptr - com->ibuf; 3332 com->iptr = com->ibuf; 3333 if (com->state & CS_CHECKMSR) { 3334 incc += LOTS_OF_EVENTS; 3335 com->state &= ~CS_CHECKMSR; 3336 } 3337 com_events -= incc; 3338 enable_intr(); 3339 continue; 3340 } 3341 if (com->iptr != com->ibuf) { 3342 disable_intr(); 3343 sioinput(com); 3344 enable_intr(); 3345 } 3346 if (com->state & CS_CHECKMSR) { 3347 u_char delta_modem_status; 3348 3349#ifdef PC98 3350 if (!IS_8251(com->pc98_if_type)) { 3351#endif 3352 disable_intr(); 3353 delta_modem_status = com->last_modem_status 3354 ^ com->prev_modem_status; 3355 com->prev_modem_status = com->last_modem_status; 3356 com_events -= LOTS_OF_EVENTS; 3357 com->state &= ~CS_CHECKMSR; 3358 enable_intr(); 3359 if (delta_modem_status & MSR_DCD) 3360 (*linesw[tp->t_line].l_modem) 3361 (tp, com->prev_modem_status & MSR_DCD); 3362#ifdef PC98 3363 } 3364#endif 3365 } 3366 if (com->state & CS_ODONE) { 3367 disable_intr(); 3368 com_events -= LOTS_OF_EVENTS; 3369 com->state &= ~CS_ODONE; 3370 enable_intr(); 3371 if (!(com->state & CS_BUSY) 3372 && !(com->extra_state & CSE_BUSYCHECK)) { 3373 timeout(siobusycheck, com, hz / 100); 3374 com->extra_state |= CSE_BUSYCHECK; 3375 } 3376 (*linesw[tp->t_line].l_start)(tp); 3377 } 3378 if (com_events == 0) 3379 break; 3380 } 3381 if (com_events >= LOTS_OF_EVENTS) 3382 goto repeat; 3383} 3384 3385static int 3386comparam(tp, t) 3387 struct tty *tp; 3388 struct termios *t; 3389{ 3390 u_int cfcr; 3391 int cflag; 3392 struct com_s *com; 3393 int divisor; 3394 u_char dlbh; 3395 u_char dlbl; 3396 int s; 3397 int unit; 3398#ifdef PC98 3399 u_char param = 0; 3400#endif 3401 3402#ifdef PC98 3403 unit = DEV_TO_UNIT(tp->t_dev); 3404 com = com_addr(unit); 3405 3406 cfcr = 0; 3407 if (IS_8251(com->pc98_if_type)) { 3408 divisor = pc98_ttspeedtab(com, t->c_ospeed); 3409 } else { 3410 /* do historical conversions */ 3411 if (t->c_ispeed == 0) 3412 t->c_ispeed = t->c_ospeed; 3413 3414 /* check requested parameters */ 3415 divisor = ttspeedtab(t->c_ospeed, 3416 if_16550a_type[com->pc98_if_type & 0x0f].speedtab); 3417 } 3418#else 3419 /* do historical conversions */ 3420 if (t->c_ispeed == 0) 3421 t->c_ispeed = t->c_ospeed; 3422 3423 /* check requested parameters */ 3424 divisor = ttspeedtab(t->c_ospeed, comspeedtab); 3425#endif 3426 if (divisor < 0 || (divisor > 0 && t->c_ispeed != t->c_ospeed)) 3427 return (EINVAL); 3428 3429#ifndef PC98 3430 /* parameters are OK, convert them to the com struct and the device */ 3431 unit = DEV_TO_UNIT(tp->t_dev); 3432 com = com_addr(unit); 3433 if (com == NULL) 3434 return (ENODEV); 3435#endif 3436 s = spltty(); 3437#ifdef PC98 3438 if (IS_8251(com->pc98_if_type)) { 3439 if (divisor == 0) 3440 com_tiocm_bic(com, TIOCM_DTR|TIOCM_RTS|TIOCM_LE); 3441 else 3442 com_tiocm_bis(com, TIOCM_DTR|TIOCM_RTS|TIOCM_LE); 3443 } else 3444#endif 3445 if (divisor == 0) 3446 (void)commctl(com, TIOCM_DTR, DMBIC); /* hang up line */ 3447 else 3448 (void)commctl(com, TIOCM_DTR, DMBIS); 3449 cflag = t->c_cflag; 3450#ifdef PC98 3451 if (!IS_8251(com->pc98_if_type)) { 3452#endif 3453 switch (cflag & CSIZE) { 3454 case CS5: 3455 cfcr = CFCR_5BITS; 3456 break; 3457 case CS6: 3458 cfcr = CFCR_6BITS; 3459 break; 3460 case CS7: 3461 cfcr = CFCR_7BITS; 3462 break; 3463 default: 3464 cfcr = CFCR_8BITS; 3465 break; 3466 } 3467 if (cflag & PARENB) { 3468 cfcr |= CFCR_PENAB; 3469 if (!(cflag & PARODD)) 3470 cfcr |= CFCR_PEVEN; 3471 } 3472 if (cflag & CSTOPB) 3473 cfcr |= CFCR_STOPB; 3474 3475 if (com->hasfifo && divisor != 0) { 3476 /* 3477 * Use a fifo trigger level low enough so that the input 3478 * latency from the fifo is less than about 16 msec and 3479 * the total latency is less than about 30 msec. These 3480 * latencies are reasonable for humans. Serial comms 3481 * protocols shouldn't expect anything better since modem 3482 * latencies are larger. 3483 */ 3484 com->fifo_image = t->c_ospeed <= 4800 3485 ? FIFO_ENABLE : FIFO_ENABLE | FIFO_RX_HIGH; 3486#ifdef COM_ESP 3487 /* 3488 * The Hayes ESP card needs the fifo DMA mode bit set 3489 * in compatibility mode. If not, it will interrupt 3490 * for each character received. 3491 */ 3492 if (com->esp) 3493 com->fifo_image |= FIFO_DMA_MODE; 3494#endif 3495 sio_setreg(com, com_fifo, com->fifo_image); 3496 } 3497#ifdef PC98 3498 } 3499#endif 3500 3501 /* 3502 * This returns with interrupts disabled so that we can complete 3503 * the speed change atomically. Keeping interrupts disabled is 3504 * especially important while com_data is hidden. 3505 */ 3506 (void) siosetwater(com, t->c_ispeed); 3507 3508#ifdef PC98 3509 if (IS_8251(com->pc98_if_type)) 3510 com_cflag_and_speed_set(com, cflag, t->c_ospeed); 3511 else { 3512#endif 3513 if (divisor != 0) { 3514 sio_setreg(com, com_cfcr, cfcr | CFCR_DLAB); 3515 /* 3516 * Only set the divisor registers if they would change, 3517 * since on some 16550 incompatibles (UMC8669F), setting 3518 * them while input is arriving them loses sync until 3519 * data stops arriving. 3520 */ 3521 dlbl = divisor & 0xFF; 3522 if (sio_getreg(com, com_dlbl) != dlbl) 3523 sio_setreg(com, com_dlbl, dlbl); 3524 dlbh = (u_int) divisor >> 8; 3525 if (sio_getreg(com, com_dlbh) != dlbh) 3526 sio_setreg(com, com_dlbh, dlbh); 3527 } 3528 3529 sio_setreg(com, com_cfcr, com->cfcr_image = cfcr); 3530#ifdef PC98 3531 } 3532#endif 3533 3534 if (!(tp->t_state & TS_TTSTOP)) 3535 com->state |= CS_TTGO; 3536 3537 if (cflag & CRTS_IFLOW) { 3538#ifndef PC98 3539 if (com->st16650a) { 3540 sio_setreg(com, com_cfcr, 0xbf); 3541 sio_setreg(com, com_fifo, 3542 sio_getreg(com, com_fifo) | 0x40); 3543 } 3544#endif 3545 com->state |= CS_RTS_IFLOW; 3546 /* 3547 * If CS_RTS_IFLOW just changed from off to on, the change 3548 * needs to be propagated to MCR_RTS. This isn't urgent, 3549 * so do it later by calling comstart() instead of repeating 3550 * a lot of code from comstart() here. 3551 */ 3552 } else if (com->state & CS_RTS_IFLOW) { 3553 com->state &= ~CS_RTS_IFLOW; 3554 /* 3555 * CS_RTS_IFLOW just changed from on to off. Force MCR_RTS 3556 * on here, since comstart() won't do it later. 3557 */ 3558#ifdef PC98 3559 if (IS_8251(com->pc98_if_type)) 3560 com_tiocm_bis(com, TIOCM_RTS); 3561 else 3562 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS); 3563#else 3564 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS); 3565 if (com->st16650a) { 3566 sio_setreg(com, com_cfcr, 0xbf); 3567 sio_setreg(com, com_fifo, 3568 sio_getreg(com, com_fifo) & ~0x40); 3569 } 3570#endif 3571 } 3572 3573 3574 /* 3575 * Set up state to handle output flow control. 3576 * XXX - worth handling MDMBUF (DCD) flow control at the lowest level? 3577 * Now has 10+ msec latency, while CTS flow has 50- usec latency. 3578 */ 3579 com->state |= CS_ODEVREADY; 3580 com->state &= ~CS_CTS_OFLOW; 3581#ifdef PC98 3582 if (com->pc98_if_type == COM_IF_RSA98III) { 3583 param = inb(com->rsabase + rsa_msr); 3584 outb(com->rsabase + rsa_msr, param & 0x14); 3585 } 3586#endif 3587 if (cflag & CCTS_OFLOW) { 3588 com->state |= CS_CTS_OFLOW; 3589#ifdef PC98 3590 if (IS_8251(com->pc98_if_type)) { 3591 if (!(pc98_get_modem_status(com) & TIOCM_CTS)) 3592 com->state &= ~CS_ODEVREADY; 3593 } else { 3594 if (com->pc98_if_type == COM_IF_RSA98III) { 3595 /* Set automatic flow control mode */ 3596 outb(com->rsabase + rsa_msr, param | 0x08); 3597 } else 3598#endif 3599 if (!(com->last_modem_status & MSR_CTS)) 3600 com->state &= ~CS_ODEVREADY; 3601#ifdef PC98 3602 } 3603#else 3604 if (com->st16650a) { 3605 sio_setreg(com, com_cfcr, 0xbf); 3606 sio_setreg(com, com_fifo, 3607 sio_getreg(com, com_fifo) | 0x80); 3608 } 3609 } else { 3610 if (com->st16650a) { 3611 sio_setreg(com, com_cfcr, 0xbf); 3612 sio_setreg(com, com_fifo, 3613 sio_getreg(com, com_fifo) & ~0x80); 3614 } 3615#endif 3616 } 3617 3618#ifdef PC98 3619 if (!IS_8251(com->pc98_if_type)) 3620#endif 3621 sio_setreg(com, com_cfcr, com->cfcr_image); 3622 3623 /* XXX shouldn't call functions while intrs are disabled. */ 3624 disc_optim(tp, t, com); 3625 /* 3626 * Recover from fiddling with CS_TTGO. We used to call siointr1() 3627 * unconditionally, but that defeated the careful discarding of 3628 * stale input in sioopen(). 3629 */ 3630 if (com->state >= (CS_BUSY | CS_TTGO)) 3631 siointr1(com); 3632 3633 enable_intr(); 3634 splx(s); 3635 comstart(tp); 3636 if (com->ibufold != NULL) { 3637 free(com->ibufold, M_DEVBUF); 3638 com->ibufold = NULL; 3639 } 3640 return (0); 3641} 3642 3643static int 3644siosetwater(com, speed) 3645 struct com_s *com; 3646 speed_t speed; 3647{ 3648 int cp4ticks; 3649 u_char *ibuf; 3650 int ibufsize; 3651 struct tty *tp; 3652 3653 /* 3654 * Make the buffer size large enough to handle a softtty interrupt 3655 * latency of about 2 ticks without loss of throughput or data 3656 * (about 3 ticks if input flow control is not used or not honoured, 3657 * but a bit less for CS5-CS7 modes). 3658 */ 3659 cp4ticks = speed / 10 / hz * 4; 3660 for (ibufsize = 128; ibufsize < cp4ticks;) 3661 ibufsize <<= 1; 3662#ifdef PC98 3663 if (com->pc98_if_type == COM_IF_RSA98III) 3664 ibufsize = 2048; 3665#endif 3666 if (ibufsize == com->ibufsize) { 3667 disable_intr(); 3668 return (0); 3669 } 3670 3671 /* 3672 * Allocate input buffer. The extra factor of 2 in the size is 3673 * to allow for an error byte for each input byte. 3674 */ 3675 ibuf = malloc(2 * ibufsize, M_DEVBUF, M_NOWAIT); 3676 if (ibuf == NULL) { 3677 disable_intr(); 3678 return (ENOMEM); 3679 } 3680 3681 /* Initialize non-critical variables. */ 3682 com->ibufold = com->ibuf; 3683 com->ibufsize = ibufsize; 3684 tp = com->tp; 3685 if (tp != NULL) { 3686 tp->t_ififosize = 2 * ibufsize; 3687 tp->t_ispeedwat = (speed_t)-1; 3688 tp->t_ospeedwat = (speed_t)-1; 3689 } 3690 3691 /* 3692 * Read current input buffer, if any. Continue with interrupts 3693 * disabled. 3694 */ 3695 disable_intr(); 3696 if (com->iptr != com->ibuf) 3697 sioinput(com); 3698 3699 /*- 3700 * Initialize critical variables, including input buffer watermarks. 3701 * The external device is asked to stop sending when the buffer 3702 * exactly reaches high water, or when the high level requests it. 3703 * The high level is notified immediately (rather than at a later 3704 * clock tick) when this watermark is reached. 3705 * The buffer size is chosen so the watermark should almost never 3706 * be reached. 3707 * The low watermark is invisibly 0 since the buffer is always 3708 * emptied all at once. 3709 */ 3710 com->iptr = com->ibuf = ibuf; 3711 com->ibufend = ibuf + ibufsize; 3712 com->ierroff = ibufsize; 3713 com->ihighwater = ibuf + 3 * ibufsize / 4; 3714 return (0); 3715} 3716 3717static void 3718comstart(tp) 3719 struct tty *tp; 3720{ 3721 struct com_s *com; 3722 int s; 3723 int unit; 3724 3725 unit = DEV_TO_UNIT(tp->t_dev); 3726 com = com_addr(unit); 3727 if (com == NULL) 3728 return; 3729 s = spltty(); 3730 disable_intr(); 3731 if (tp->t_state & TS_TTSTOP) 3732 com->state &= ~CS_TTGO; 3733 else 3734 com->state |= CS_TTGO; 3735 if (tp->t_state & TS_TBLOCK) { 3736#ifdef PC98 3737 if (IS_8251(com->pc98_if_type)) { 3738 if ((com_tiocm_get(com) & TIOCM_RTS) && 3739 (com->state & CS_RTS_IFLOW)) 3740 com_tiocm_bic(com, TIOCM_RTS); 3741 } else { 3742 if ((com->mcr_image & MCR_RTS) && 3743 (com->state & CS_RTS_IFLOW)) 3744 outb(com->modem_ctl_port, com->mcr_image &= ~MCR_RTS); 3745 } 3746#else 3747 if (com->mcr_image & MCR_RTS && com->state & CS_RTS_IFLOW) 3748 outb(com->modem_ctl_port, com->mcr_image &= ~MCR_RTS); 3749#endif 3750 } else { 3751#ifdef PC98 3752 if (IS_8251(com->pc98_if_type)) { 3753 if (!(com_tiocm_get(com) & TIOCM_RTS) && 3754 com->iptr < com->ihighwater && 3755 com->state & CS_RTS_IFLOW) 3756 com_tiocm_bis(com, TIOCM_RTS); 3757 } else { 3758 if (!(com->mcr_image & MCR_RTS) && 3759 com->iptr < com->ihighwater && 3760 com->state & CS_RTS_IFLOW) 3761 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS); 3762 } 3763#else 3764 if (!(com->mcr_image & MCR_RTS) && com->iptr < com->ihighwater 3765 && com->state & CS_RTS_IFLOW) 3766 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS); 3767#endif 3768 } 3769 enable_intr(); 3770 if (tp->t_state & (TS_TIMEOUT | TS_TTSTOP)) { 3771 ttwwakeup(tp); 3772 splx(s); 3773 return; 3774 } 3775 if (tp->t_outq.c_cc != 0) { 3776 struct lbq *qp; 3777 struct lbq *next; 3778 3779 if (!com->obufs[0].l_queued) { 3780 com->obufs[0].l_tail 3781 = com->obuf1 + q_to_b(&tp->t_outq, com->obuf1, 3782#ifdef PC98 3783 com->obufsize); 3784#else 3785 sizeof com->obuf1); 3786#endif 3787 com->obufs[0].l_next = NULL; 3788 com->obufs[0].l_queued = TRUE; 3789 disable_intr(); 3790 if (com->state & CS_BUSY) { 3791 qp = com->obufq.l_next; 3792 while ((next = qp->l_next) != NULL) 3793 qp = next; 3794 qp->l_next = &com->obufs[0]; 3795 } else { 3796 com->obufq.l_head = com->obufs[0].l_head; 3797 com->obufq.l_tail = com->obufs[0].l_tail; 3798 com->obufq.l_next = &com->obufs[0]; 3799 com->state |= CS_BUSY; 3800 } 3801 enable_intr(); 3802 } 3803 if (tp->t_outq.c_cc != 0 && !com->obufs[1].l_queued) { 3804 com->obufs[1].l_tail 3805 = com->obuf2 + q_to_b(&tp->t_outq, com->obuf2, 3806#ifdef PC98 3807 com->obufsize); 3808#else 3809 sizeof com->obuf2); 3810#endif 3811 com->obufs[1].l_next = NULL; 3812 com->obufs[1].l_queued = TRUE; 3813 disable_intr(); 3814 if (com->state & CS_BUSY) { 3815 qp = com->obufq.l_next; 3816 while ((next = qp->l_next) != NULL) 3817 qp = next; 3818 qp->l_next = &com->obufs[1]; 3819 } else { 3820 com->obufq.l_head = com->obufs[1].l_head; 3821 com->obufq.l_tail = com->obufs[1].l_tail; 3822 com->obufq.l_next = &com->obufs[1]; 3823 com->state |= CS_BUSY; 3824 } 3825 enable_intr(); 3826 } 3827 tp->t_state |= TS_BUSY; 3828 } 3829 disable_intr(); 3830 if (com->state >= (CS_BUSY | CS_TTGO)) 3831 siointr1(com); /* fake interrupt to start output */ 3832 enable_intr(); 3833 ttwwakeup(tp); 3834 splx(s); 3835} 3836 3837static void 3838comstop(tp, rw) 3839 struct tty *tp; 3840 int rw; 3841{ 3842 struct com_s *com; 3843#ifdef PC98 3844 int rsa98_tmp = 0; 3845#endif 3846 3847 com = com_addr(DEV_TO_UNIT(tp->t_dev)); 3848 if (com == NULL || com->gone) 3849 return; 3850 disable_intr(); 3851 if (rw & FWRITE) { 3852#ifdef PC98 3853 if (!IS_8251(com->pc98_if_type)) { 3854#endif 3855 if (com->hasfifo) 3856#ifdef COM_ESP 3857 /* XXX avoid h/w bug. */ 3858 if (!com->esp) 3859#endif 3860 sio_setreg(com, com_fifo, 3861 FIFO_XMT_RST | com->fifo_image); 3862#ifdef PC98 3863 if (com->pc98_if_type == COM_IF_RSA98III) 3864 for (rsa98_tmp = 0; rsa98_tmp < 2048; rsa98_tmp++) 3865 sio_setreg(com, com_fifo, 3866 FIFO_XMT_RST | com->fifo_image); 3867 } 3868#endif 3869 com->obufs[0].l_queued = FALSE; 3870 com->obufs[1].l_queued = FALSE; 3871 if (com->state & CS_ODONE) 3872 com_events -= LOTS_OF_EVENTS; 3873 com->state &= ~(CS_ODONE | CS_BUSY); 3874 com->tp->t_state &= ~TS_BUSY; 3875 } 3876 if (rw & FREAD) { 3877#ifdef PC98 3878 if (!IS_8251(com->pc98_if_type)) { 3879 if (com->pc98_if_type == COM_IF_RSA98III) 3880 for (rsa98_tmp = 0; rsa98_tmp < 2048; rsa98_tmp++) 3881 sio_getreg(com, com_data); 3882#endif 3883 if (com->hasfifo) 3884#ifdef COM_ESP 3885 /* XXX avoid h/w bug. */ 3886 if (!com->esp) 3887#endif 3888 sio_setreg(com, com_fifo, 3889 FIFO_RCV_RST | com->fifo_image); 3890#ifdef PC98 3891 } 3892#endif 3893 com_events -= (com->iptr - com->ibuf); 3894 com->iptr = com->ibuf; 3895 } 3896 enable_intr(); 3897 comstart(tp); 3898} 3899 3900static int 3901commctl(com, bits, how) 3902 struct com_s *com; 3903 int bits; 3904 int how; 3905{ 3906 int mcr; 3907 int msr; 3908 3909 if (how == DMGET) { 3910 bits = TIOCM_LE; /* XXX - always enabled while open */ 3911 mcr = com->mcr_image; 3912 if (mcr & MCR_DTR) 3913 bits |= TIOCM_DTR; 3914 if (mcr & MCR_RTS) 3915 bits |= TIOCM_RTS; 3916 msr = com->prev_modem_status; 3917 if (msr & MSR_CTS) 3918 bits |= TIOCM_CTS; 3919 if (msr & MSR_DCD) 3920 bits |= TIOCM_CD; 3921 if (msr & MSR_DSR) 3922 bits |= TIOCM_DSR; 3923 /* 3924 * XXX - MSR_RI is naturally volatile, and we make MSR_TERI 3925 * more volatile by reading the modem status a lot. Perhaps 3926 * we should latch both bits until the status is read here. 3927 */ 3928 if (msr & (MSR_RI | MSR_TERI)) 3929 bits |= TIOCM_RI; 3930 return (bits); 3931 } 3932 mcr = 0; 3933 if (bits & TIOCM_DTR) 3934 mcr |= MCR_DTR; 3935 if (bits & TIOCM_RTS) 3936 mcr |= MCR_RTS; 3937 if (com->gone) 3938 return(0); 3939 disable_intr(); 3940 switch (how) { 3941 case DMSET: 3942 outb(com->modem_ctl_port, 3943 com->mcr_image = mcr | (com->mcr_image & MCR_IENABLE)); 3944 break; 3945 case DMBIS: 3946 outb(com->modem_ctl_port, com->mcr_image |= mcr); 3947 break; 3948 case DMBIC: 3949 outb(com->modem_ctl_port, com->mcr_image &= ~mcr); 3950 break; 3951 } 3952 enable_intr(); 3953 return (0); 3954} 3955 3956static void 3957siosettimeout() 3958{ 3959 struct com_s *com; 3960 bool_t someopen; 3961 int unit; 3962 3963 /* 3964 * Set our timeout period to 1 second if no polled devices are open. 3965 * Otherwise set it to max(1/200, 1/hz). 3966 * Enable timeouts iff some device is open. 3967 */ 3968 untimeout(comwakeup, (void *)NULL, sio_timeout_handle); 3969 sio_timeout = hz; 3970 someopen = FALSE; 3971 for (unit = 0; unit < sio_numunits; ++unit) { 3972 com = com_addr(unit); 3973 if (com != NULL && com->tp != NULL 3974 && com->tp->t_state & TS_ISOPEN && !com->gone) { 3975 someopen = TRUE; 3976 if (com->poll || com->poll_output) { 3977 sio_timeout = hz > 200 ? hz / 200 : 1; 3978 break; 3979 } 3980 } 3981 } 3982 if (someopen) { 3983 sio_timeouts_until_log = hz / sio_timeout; 3984 sio_timeout_handle = timeout(comwakeup, (void *)NULL, 3985 sio_timeout); 3986 } else { 3987 /* Flush error messages, if any. */ 3988 sio_timeouts_until_log = 1; 3989 comwakeup((void *)NULL); 3990 untimeout(comwakeup, (void *)NULL, sio_timeout_handle); 3991 } 3992} 3993 3994static void 3995comwakeup(chan) 3996 void *chan; 3997{ 3998 struct com_s *com; 3999 int unit; 4000 4001 sio_timeout_handle = timeout(comwakeup, (void *)NULL, sio_timeout); 4002 4003 /* 4004 * Recover from lost output interrupts. 4005 * Poll any lines that don't use interrupts. 4006 */ 4007 for (unit = 0; unit < sio_numunits; ++unit) { 4008 com = com_addr(unit); 4009 if (com != NULL && !com->gone 4010 && (com->state >= (CS_BUSY | CS_TTGO) || com->poll)) { 4011 disable_intr(); 4012 siointr1(com); 4013 enable_intr(); 4014 } 4015 } 4016 4017 /* 4018 * Check for and log errors, but not too often. 4019 */ 4020 if (--sio_timeouts_until_log > 0) 4021 return; 4022 sio_timeouts_until_log = hz / sio_timeout; 4023 for (unit = 0; unit < sio_numunits; ++unit) { 4024 int errnum; 4025 4026 com = com_addr(unit); 4027 if (com == NULL) 4028 continue; 4029 if (com->gone) 4030 continue; 4031 for (errnum = 0; errnum < CE_NTYPES; ++errnum) { 4032 u_int delta; 4033 u_long total; 4034 4035 disable_intr(); 4036 delta = com->delta_error_counts[errnum]; 4037 com->delta_error_counts[errnum] = 0; 4038 enable_intr(); 4039 if (delta == 0) 4040 continue; 4041 total = com->error_counts[errnum] += delta; 4042 log(LOG_ERR, "sio%d: %u more %s%s (total %lu)\n", 4043 unit, delta, error_desc[errnum], 4044 delta == 1 ? "" : "s", total); 4045 } 4046 } 4047} 4048 4049#ifdef PC98 4050/* commint is called when modem control line changes */ 4051static void 4052commint(dev_t dev) 4053{ 4054 register struct tty *tp; 4055 int stat,delta; 4056 struct com_s *com; 4057 int mynor,unit; 4058 4059 mynor = minor(dev); 4060 unit = MINOR_TO_UNIT(mynor); 4061 com = com_addr(unit); 4062 tp = com->tp; 4063 4064 stat = com_tiocm_get(com); 4065 delta = com_tiocm_get_delta(com); 4066 4067 if (com->state & CS_CTS_OFLOW) { 4068 if (stat & TIOCM_CTS) 4069 com->state |= CS_ODEVREADY; 4070 else 4071 com->state &= ~CS_ODEVREADY; 4072 } 4073 if ((delta & TIOCM_CAR) && (mynor & CALLOUT_MASK) == 0) { 4074 if (stat & TIOCM_CAR ) 4075 (void)(*linesw[tp->t_line].l_modem)(tp, 1); 4076 else if ((*linesw[tp->t_line].l_modem)(tp, 0) == 0) { 4077 /* negate DTR, RTS */ 4078 com_tiocm_bic(com, (tp->t_cflag & HUPCL) ? 4079 TIOCM_DTR|TIOCM_RTS|TIOCM_LE : TIOCM_LE ); 4080 /* disable IENABLE */ 4081 com_int_TxRx_disable( com ); 4082 } 4083 } 4084} 4085#endif 4086 4087static void 4088disc_optim(tp, t, com) 4089 struct tty *tp; 4090 struct termios *t; 4091 struct com_s *com; 4092{ 4093 if (!(t->c_iflag & (ICRNL | IGNCR | IMAXBEL | INLCR | ISTRIP | IXON)) 4094 && (!(t->c_iflag & BRKINT) || (t->c_iflag & IGNBRK)) 4095 && (!(t->c_iflag & PARMRK) 4096 || (t->c_iflag & (IGNPAR | IGNBRK)) == (IGNPAR | IGNBRK)) 4097 && !(t->c_lflag & (ECHO | ICANON | IEXTEN | ISIG | PENDIN)) 4098 && linesw[tp->t_line].l_rint == ttyinput) 4099 tp->t_state |= TS_CAN_BYPASS_L_RINT; 4100 else 4101 tp->t_state &= ~TS_CAN_BYPASS_L_RINT; 4102 com->hotchar = linesw[tp->t_line].l_hotchar; 4103} 4104 4105/* 4106 * Following are all routines needed for SIO to act as console 4107 */ 4108#include <sys/cons.h> 4109 4110struct siocnstate { 4111 u_char dlbl; 4112 u_char dlbh; 4113 u_char ier; 4114 u_char cfcr; 4115 u_char mcr; 4116}; 4117 4118static speed_t siocngetspeed __P((Port_t, struct speedtab *)); 4119static void siocnclose __P((struct siocnstate *sp, Port_t iobase)); 4120static void siocnopen __P((struct siocnstate *sp, Port_t iobase, int speed)); 4121static void siocntxwait __P((Port_t iobase)); 4122 4123static cn_probe_t siocnprobe; 4124static cn_init_t siocninit; 4125static cn_checkc_t siocncheckc; 4126static cn_getc_t siocngetc; 4127static cn_putc_t siocnputc; 4128 4129#ifdef __i386__ 4130CONS_DRIVER(sio, siocnprobe, siocninit, NULL, siocngetc, siocncheckc, 4131 siocnputc, NULL); 4132#endif 4133 4134/* To get the GDB related variables */ 4135#if DDB > 0 4136#include <ddb/ddb.h> 4137#endif 4138 4139static void 4140siocntxwait(iobase) 4141 Port_t iobase; 4142{ 4143 int timo; 4144 4145 /* 4146 * Wait for any pending transmission to finish. Required to avoid 4147 * the UART lockup bug when the speed is changed, and for normal 4148 * transmits. 4149 */ 4150 timo = 100000; 4151 while ((inb(iobase + com_lsr) & (LSR_TSRE | LSR_TXRDY)) 4152 != (LSR_TSRE | LSR_TXRDY) && --timo != 0) 4153 ; 4154} 4155 4156/* 4157 * Read the serial port specified and try to figure out what speed 4158 * it's currently running at. We're assuming the serial port has 4159 * been initialized and is basicly idle. This routine is only intended 4160 * to be run at system startup. 4161 * 4162 * If the value read from the serial port doesn't make sense, return 0. 4163 */ 4164 4165static speed_t 4166siocngetspeed(iobase, table) 4167 Port_t iobase; 4168 struct speedtab *table; 4169{ 4170 int code; 4171 u_char dlbh; 4172 u_char dlbl; 4173 u_char cfcr; 4174 4175 cfcr = inb(iobase + com_cfcr); 4176 outb(iobase + com_cfcr, CFCR_DLAB | cfcr); 4177 4178 dlbl = inb(iobase + com_dlbl); 4179 dlbh = inb(iobase + com_dlbh); 4180 4181 outb(iobase + com_cfcr, cfcr); 4182 4183 code = dlbh << 8 | dlbl; 4184 4185 for (; table->sp_speed != -1; table++) 4186 if (table->sp_code == code) 4187 return (table->sp_speed); 4188 4189 return (0); /* didn't match anything sane */ 4190} 4191 4192static void 4193siocnopen(sp, iobase, speed) 4194 struct siocnstate *sp; 4195 Port_t iobase; 4196 int speed; 4197{ 4198 int divisor; 4199 u_char dlbh; 4200 u_char dlbl; 4201 4202 /* 4203 * Save all the device control registers except the fifo register 4204 * and set our default ones (cs8 -parenb speed=comdefaultrate). 4205 * We can't save the fifo register since it is read-only. 4206 */ 4207 sp->ier = inb(iobase + com_ier); 4208 outb(iobase + com_ier, 0); /* spltty() doesn't stop siointr() */ 4209 siocntxwait(iobase); 4210 sp->cfcr = inb(iobase + com_cfcr); 4211 outb(iobase + com_cfcr, CFCR_DLAB | CFCR_8BITS); 4212 sp->dlbl = inb(iobase + com_dlbl); 4213 sp->dlbh = inb(iobase + com_dlbh); 4214 /* 4215 * Only set the divisor registers if they would change, since on 4216 * some 16550 incompatibles (Startech), setting them clears the 4217 * data input register. This also reduces the effects of the 4218 * UMC8669F bug. 4219 */ 4220 divisor = ttspeedtab(speed, comspeedtab); 4221 dlbl = divisor & 0xFF; 4222 if (sp->dlbl != dlbl) 4223 outb(iobase + com_dlbl, dlbl); 4224 dlbh = (u_int) divisor >> 8; 4225 if (sp->dlbh != dlbh) 4226 outb(iobase + com_dlbh, dlbh); 4227 outb(iobase + com_cfcr, CFCR_8BITS); 4228 sp->mcr = inb(iobase + com_mcr); 4229 /* 4230 * We don't want interrupts, but must be careful not to "disable" 4231 * them by clearing the MCR_IENABLE bit, since that might cause 4232 * an interrupt by floating the IRQ line. 4233 */ 4234 outb(iobase + com_mcr, (sp->mcr & MCR_IENABLE) | MCR_DTR | MCR_RTS); 4235} 4236 4237static void 4238siocnclose(sp, iobase) 4239 struct siocnstate *sp; 4240 Port_t iobase; 4241{ 4242 /* 4243 * Restore the device control registers. 4244 */ 4245 siocntxwait(iobase); 4246 outb(iobase + com_cfcr, CFCR_DLAB | CFCR_8BITS); 4247 if (sp->dlbl != inb(iobase + com_dlbl)) 4248 outb(iobase + com_dlbl, sp->dlbl); 4249 if (sp->dlbh != inb(iobase + com_dlbh)) 4250 outb(iobase + com_dlbh, sp->dlbh); 4251 outb(iobase + com_cfcr, sp->cfcr); 4252 /* 4253 * XXX damp oscillations of MCR_DTR and MCR_RTS by not restoring them. 4254 */ 4255 outb(iobase + com_mcr, sp->mcr | MCR_DTR | MCR_RTS); 4256 outb(iobase + com_ier, sp->ier); 4257} 4258 4259static void 4260siocnprobe(cp) 4261 struct consdev *cp; 4262{ 4263 speed_t boot_speed; 4264 u_char cfcr; 4265 int s, unit; 4266 struct siocnstate sp; 4267 4268 /* 4269 * Find our first enabled console, if any. If it is a high-level 4270 * console device, then initialize it and return successfully. 4271 * If it is a low-level console device, then initialize it and 4272 * return unsuccessfully. It must be initialized in both cases 4273 * for early use by console drivers and debuggers. Initializing 4274 * the hardware is not necessary in all cases, since the i/o 4275 * routines initialize it on the fly, but it is necessary if 4276 * input might arrive while the hardware is switched back to an 4277 * uninitialized state. We can't handle multiple console devices 4278 * yet because our low-level routines don't take a device arg. 4279 * We trust the user to set the console flags properly so that we 4280 * don't need to probe. 4281 */ 4282 cp->cn_pri = CN_DEAD; 4283 4284 for (unit = 0; unit < 16; unit++) { /* XXX need to know how many */ 4285 int flags; 4286 int disabled; 4287 if (resource_int_value("sio", unit, "disabled", &disabled) == 0) { 4288 if (disabled) 4289 continue; 4290 } 4291 if (resource_int_value("sio", unit, "flags", &flags)) 4292 continue; 4293 if (COM_CONSOLE(flags) || COM_DEBUGGER(flags)) { 4294 int port; 4295 Port_t iobase; 4296 4297 if (resource_int_value("sio", unit, "port", &port)) 4298 continue; 4299 iobase = port; 4300 s = spltty(); 4301 if (boothowto & RB_SERIAL) { 4302 boot_speed = siocngetspeed(iobase, comspeedtab); 4303 if (boot_speed) 4304 comdefaultrate = boot_speed; 4305 } 4306 4307 /* 4308 * Initialize the divisor latch. We can't rely on 4309 * siocnopen() to do this the first time, since it 4310 * avoids writing to the latch if the latch appears 4311 * to have the correct value. Also, if we didn't 4312 * just read the speed from the hardware, then we 4313 * need to set the speed in hardware so that 4314 * switching it later is null. 4315 */ 4316 cfcr = inb(iobase + com_cfcr); 4317 outb(iobase + com_cfcr, CFCR_DLAB | cfcr); 4318 outb(iobase + com_dlbl, 4319 COMBRD(comdefaultrate) & 0xff); 4320 outb(iobase + com_dlbh, 4321 (u_int) COMBRD(comdefaultrate) >> 8); 4322 outb(iobase + com_cfcr, cfcr); 4323 4324 siocnopen(&sp, iobase, comdefaultrate); 4325 4326 splx(s); 4327 if (COM_CONSOLE(flags) && !COM_LLCONSOLE(flags)) { 4328 cp->cn_dev = makedev(CDEV_MAJOR, unit); 4329 cp->cn_pri = COM_FORCECONSOLE(flags) 4330 || boothowto & RB_SERIAL 4331 ? CN_REMOTE : CN_NORMAL; 4332 siocniobase = iobase; 4333 siocnunit = unit; 4334 } 4335 if (COM_DEBUGGER(flags)) { 4336 printf("sio%d: gdb debugging port\n", unit); 4337 siogdbiobase = iobase; 4338 siogdbunit = unit; 4339#if DDB > 0 4340 gdbdev = makedev(CDEV_MAJOR, unit); 4341 gdb_getc = siocngetc; 4342 gdb_putc = siocnputc; 4343#endif 4344 } 4345 } 4346 } 4347#ifdef __i386__ 4348#if DDB > 0 4349 /* 4350 * XXX Ugly Compatability. 4351 * If no gdb port has been specified, set it to be the console 4352 * as some configuration files don't specify the gdb port. 4353 */ 4354 if (gdbdev == NODEV && (boothowto & RB_GDB)) { 4355 printf("Warning: no GDB port specified. Defaulting to sio%d.\n", 4356 siocnunit); 4357 printf("Set flag 0x80 on desired GDB port in your\n"); 4358 printf("configuration file (currently sio only).\n"); 4359 siogdbiobase = siocniobase; 4360 siogdbunit = siocnunit; 4361 gdbdev = makedev(CDEV_MAJOR, siocnunit); 4362 gdb_getc = siocngetc; 4363 gdb_putc = siocnputc; 4364 } 4365#endif 4366#endif 4367} 4368 4369#ifdef __alpha__ 4370 4371CONS_DRIVER(sio, NULL, NULL, NULL, siocngetc, siocncheckc, siocnputc, NULL); 4372 4373int 4374siocnattach(port, speed) 4375 int port; 4376 int speed; 4377{ 4378 int s; 4379 u_char cfcr; 4380 struct siocnstate sp; 4381 4382 siocniobase = port; 4383 comdefaultrate = speed; 4384 sio_consdev.cn_pri = CN_NORMAL; 4385 sio_consdev.cn_dev = makedev(CDEV_MAJOR, 0); 4386 4387 s = spltty(); 4388 4389 /* 4390 * Initialize the divisor latch. We can't rely on 4391 * siocnopen() to do this the first time, since it 4392 * avoids writing to the latch if the latch appears 4393 * to have the correct value. Also, if we didn't 4394 * just read the speed from the hardware, then we 4395 * need to set the speed in hardware so that 4396 * switching it later is null. 4397 */ 4398 cfcr = inb(siocniobase + com_cfcr); 4399 outb(siocniobase + com_cfcr, CFCR_DLAB | cfcr); 4400 outb(siocniobase + com_dlbl, 4401 COMBRD(comdefaultrate) & 0xff); 4402 outb(siocniobase + com_dlbh, 4403 (u_int) COMBRD(comdefaultrate) >> 8); 4404 outb(siocniobase + com_cfcr, cfcr); 4405 4406 siocnopen(&sp, siocniobase, comdefaultrate); 4407 splx(s); 4408 4409 cn_tab = &sio_consdev; 4410 return (0); 4411} 4412 4413int 4414siogdbattach(port, speed) 4415 int port; 4416 int speed; 4417{ 4418 int s; 4419 u_char cfcr; 4420 struct siocnstate sp; 4421 4422 siogdbiobase = port; 4423 gdbdefaultrate = speed; 4424 4425 s = spltty(); 4426 4427 /* 4428 * Initialize the divisor latch. We can't rely on 4429 * siocnopen() to do this the first time, since it 4430 * avoids writing to the latch if the latch appears 4431 * to have the correct value. Also, if we didn't 4432 * just read the speed from the hardware, then we 4433 * need to set the speed in hardware so that 4434 * switching it later is null. 4435 */ 4436 cfcr = inb(siogdbiobase + com_cfcr); 4437 outb(siogdbiobase + com_cfcr, CFCR_DLAB | cfcr); 4438 outb(siogdbiobase + com_dlbl, 4439 COMBRD(gdbdefaultrate) & 0xff); 4440 outb(siogdbiobase + com_dlbh, 4441 (u_int) COMBRD(gdbdefaultrate) >> 8); 4442 outb(siogdbiobase + com_cfcr, cfcr); 4443 4444 siocnopen(&sp, siogdbiobase, gdbdefaultrate); 4445 splx(s); 4446 4447 return (0); 4448} 4449 4450#endif 4451 4452static void 4453siocninit(cp) 4454 struct consdev *cp; 4455{ 4456 comconsole = DEV_TO_UNIT(cp->cn_dev); 4457} 4458 4459static int 4460siocncheckc(dev) 4461 dev_t dev; 4462{ 4463 int c; 4464 Port_t iobase; 4465 int s; 4466 struct siocnstate sp; 4467 4468 if (minor(dev) == siogdbunit) 4469 iobase = siogdbiobase; 4470 else 4471 iobase = siocniobase; 4472 s = spltty(); 4473 siocnopen(&sp, iobase, comdefaultrate); 4474 if (inb(iobase + com_lsr) & LSR_RXRDY) 4475 c = inb(iobase + com_data); 4476 else 4477 c = -1; 4478 siocnclose(&sp, iobase); 4479 splx(s); 4480 return (c); 4481} 4482 4483 4484int 4485siocngetc(dev) 4486 dev_t dev; 4487{ 4488 int c; 4489 Port_t iobase; 4490 int s; 4491 struct siocnstate sp; 4492 4493 if (minor(dev) == siogdbunit) 4494 iobase = siogdbiobase; 4495 else 4496 iobase = siocniobase; 4497 s = spltty(); 4498 siocnopen(&sp, iobase, comdefaultrate); 4499 while (!(inb(iobase + com_lsr) & LSR_RXRDY)) 4500 ; 4501 c = inb(iobase + com_data); 4502 siocnclose(&sp, iobase); 4503 splx(s); 4504 return (c); 4505} 4506 4507void 4508siocnputc(dev, c) 4509 dev_t dev; 4510 int c; 4511{ 4512 int s; 4513 struct siocnstate sp; 4514 Port_t iobase; 4515 4516 if (minor(dev) == siogdbunit) 4517 iobase = siogdbiobase; 4518 else 4519 iobase = siocniobase; 4520 s = spltty(); 4521 siocnopen(&sp, iobase, comdefaultrate); 4522 siocntxwait(iobase); 4523 outb(iobase + com_data, c); 4524 siocnclose(&sp, iobase); 4525 splx(s); 4526} 4527 4528#ifdef __alpha__ 4529int 4530siogdbgetc() 4531{ 4532 int c; 4533 Port_t iobase; 4534 int s; 4535 struct siocnstate sp; 4536 4537 iobase = siogdbiobase; 4538 s = spltty(); 4539 siocnopen(&sp, iobase, gdbdefaultrate); 4540 while (!(inb(iobase + com_lsr) & LSR_RXRDY)) 4541 ; 4542 c = inb(iobase + com_data); 4543 siocnclose(&sp, iobase); 4544 splx(s); 4545 return (c); 4546} 4547 4548void 4549siogdbputc(c) 4550 int c; 4551{ 4552 int s; 4553 struct siocnstate sp; 4554 4555 s = spltty(); 4556 siocnopen(&sp, siogdbiobase, gdbdefaultrate); 4557 siocntxwait(siogdbiobase); 4558 outb(siogdbiobase + com_data, c); 4559 siocnclose(&sp, siogdbiobase); 4560 splx(s); 4561} 4562#endif 4563 4564DRIVER_MODULE(sio, isa, sio_isa_driver, sio_devclass, 0, 0); 4565#if NCARD > 0 4566DRIVER_MODULE(sio, pccard, sio_pccard_driver, sio_devclass, 0, 0); 4567#endif 4568#if NPCI > 0 4569DRIVER_MODULE(sio, pci, sio_pci_driver, sio_devclass, 0, 0); 4570#endif 4571 4572#ifdef PC98 4573/* 4574 * pc98 local function 4575 */ 4576 4577static void 4578com_tiocm_set(struct com_s *com, int msr) 4579{ 4580 int s; 4581 int tmp = 0; 4582 int mask = CMD8251_TxEN|CMD8251_RxEN|CMD8251_DTR|CMD8251_RTS; 4583 4584 s=spltty(); 4585 com->pc98_prev_modem_status = ( msr & (TIOCM_LE|TIOCM_DTR|TIOCM_RTS) ) 4586 | ( com->pc98_prev_modem_status & ~(TIOCM_LE|TIOCM_DTR|TIOCM_RTS) ); 4587 tmp |= (CMD8251_TxEN|CMD8251_RxEN); 4588 if ( msr & TIOCM_DTR ) tmp |= CMD8251_DTR; 4589 if ( msr & TIOCM_RTS ) tmp |= CMD8251_RTS; 4590 pc98_i8251_clear_or_cmd( com, mask, tmp ); 4591 splx(s); 4592} 4593 4594static void 4595com_tiocm_bis(struct com_s *com, int msr) 4596{ 4597 int s; 4598 int tmp = 0; 4599 4600 s=spltty(); 4601 com->pc98_prev_modem_status |= ( msr & (TIOCM_LE|TIOCM_DTR|TIOCM_RTS) ); 4602 tmp |= CMD8251_TxEN|CMD8251_RxEN; 4603 if ( msr & TIOCM_DTR ) tmp |= CMD8251_DTR; 4604 if ( msr & TIOCM_RTS ) tmp |= CMD8251_RTS; 4605 4606 pc98_i8251_or_cmd( com, tmp ); 4607 splx(s); 4608} 4609 4610static void 4611com_tiocm_bic(struct com_s *com, int msr) 4612{ 4613 int s; 4614 int tmp = msr; 4615 4616 s=spltty(); 4617 com->pc98_prev_modem_status &= ~( msr & (TIOCM_LE|TIOCM_DTR|TIOCM_RTS) ); 4618 if ( msr & TIOCM_DTR ) tmp |= CMD8251_DTR; 4619 if ( msr & TIOCM_RTS ) tmp |= CMD8251_RTS; 4620 4621 pc98_i8251_clear_cmd( com, tmp ); 4622 splx(s); 4623} 4624 4625static int 4626com_tiocm_get(struct com_s *com) 4627{ 4628 return( com->pc98_prev_modem_status ); 4629} 4630 4631static int 4632com_tiocm_get_delta(struct com_s *com) 4633{ 4634 int tmp; 4635 4636 tmp = com->pc98_modem_delta; 4637 com->pc98_modem_delta = 0; 4638 return( tmp ); 4639} 4640 4641/* convert to TIOCM_?? ( ioctl.h ) */ 4642static int 4643pc98_get_modem_status(struct com_s *com) 4644{ 4645 register int msr; 4646 4647 msr = com->pc98_prev_modem_status 4648 & ~(TIOCM_CAR|TIOCM_RI|TIOCM_DSR|TIOCM_CTS); 4649 if (com->pc98_8251fifo_enable) { 4650 int stat2; 4651 4652 stat2 = inb(I8251F_msr); 4653 if ( stat2 & CICSCDF_CD ) msr |= TIOCM_CAR; 4654 if ( stat2 & CICSCDF_CI ) msr |= TIOCM_RI; 4655 if ( stat2 & CICSCDF_DR ) msr |= TIOCM_DSR; 4656 if ( stat2 & CICSCDF_CS ) msr |= TIOCM_CTS; 4657#if COM_CARRIER_DETECT_EMULATE 4658 if ( msr & (TIOCM_DSR|TIOCM_CTS) ) { 4659 msr |= TIOCM_CAR; 4660 } 4661#endif 4662 } else { 4663 int stat, stat2; 4664 4665 stat = inb(com->sts_port); 4666 stat2 = inb(com->in_modem_port); 4667 if ( !(stat2 & CICSCD_CD) ) msr |= TIOCM_CAR; 4668 if ( !(stat2 & CICSCD_CI) ) msr |= TIOCM_RI; 4669 if ( stat & STS8251_DSR ) msr |= TIOCM_DSR; 4670 if ( !(stat2 & CICSCD_CS) ) msr |= TIOCM_CTS; 4671#if COM_CARRIER_DETECT_EMULATE 4672 if ( msr & (TIOCM_DSR|TIOCM_CTS) ) { 4673 msr |= TIOCM_CAR; 4674 } 4675#endif 4676 } 4677 return(msr); 4678} 4679 4680static void 4681pc98_check_msr(void* chan) 4682{ 4683 int msr, delta; 4684 int s; 4685 register struct tty *tp; 4686 struct com_s *com; 4687 int mynor; 4688 int unit; 4689 dev_t dev; 4690 4691 dev=(dev_t)chan; 4692 mynor = minor(dev); 4693 unit = MINOR_TO_UNIT(mynor); 4694 com = com_addr(unit); 4695 tp = com->tp; 4696 4697 s = spltty(); 4698 msr = pc98_get_modem_status(com); 4699 /* make change flag */ 4700 delta = msr ^ com->pc98_prev_modem_status; 4701 if ( delta & TIOCM_CAR ) { 4702 if ( com->modem_car_chg_timer ) { 4703 if ( -- com->modem_car_chg_timer ) 4704 msr ^= TIOCM_CAR; 4705 } else { 4706 if ((com->modem_car_chg_timer = (msr & TIOCM_CAR) ? 4707 DCD_ON_RECOGNITION : DCD_OFF_TOLERANCE) != 0) 4708 msr ^= TIOCM_CAR; 4709 } 4710 } else 4711 com->modem_car_chg_timer = 0; 4712 delta = ( msr ^ com->pc98_prev_modem_status ) & 4713 (TIOCM_CAR|TIOCM_RI|TIOCM_DSR|TIOCM_CTS); 4714 com->pc98_prev_modem_status = msr; 4715 delta = ( com->pc98_modem_delta |= delta ); 4716 splx(s); 4717 if ( com->modem_checking || (tp->t_state & (TS_ISOPEN)) ) { 4718 if ( delta ) { 4719 commint(dev); 4720 } 4721 timeout(pc98_check_msr, (caddr_t)dev, 4722 PC98_CHECK_MODEM_INTERVAL); 4723 } else { 4724 com->modem_checking = 0; 4725 } 4726} 4727 4728static void 4729pc98_msrint_start(dev_t dev) 4730{ 4731 struct com_s *com; 4732 int mynor; 4733 int unit; 4734 int s = spltty(); 4735 4736 mynor = minor(dev); 4737 unit = MINOR_TO_UNIT(mynor); 4738 com = com_addr(unit); 4739 /* modem control line check routine envoke interval is 1/10 sec */ 4740 if ( com->modem_checking == 0 ) { 4741 com->pc98_prev_modem_status = pc98_get_modem_status(com); 4742 com->pc98_modem_delta = 0; 4743 timeout(pc98_check_msr, (caddr_t)dev, 4744 PC98_CHECK_MODEM_INTERVAL); 4745 com->modem_checking = 1; 4746 } 4747 splx(s); 4748} 4749 4750static void 4751pc98_disable_i8251_interrupt(struct com_s *com, int mod) 4752{ 4753 /* disable interrupt */ 4754 register int tmp; 4755 4756 mod |= ~(IEN_Tx|IEN_TxEMP|IEN_Rx); 4757 COM_INT_DISABLE 4758 tmp = inb( com->intr_ctrl_port ) & ~(IEN_Tx|IEN_TxEMP|IEN_Rx); 4759 outb( com->intr_ctrl_port, (com->intr_enable&=~mod) | tmp ); 4760 COM_INT_ENABLE 4761} 4762 4763static void 4764pc98_enable_i8251_interrupt(struct com_s *com, int mod) 4765{ 4766 register int tmp; 4767 4768 COM_INT_DISABLE 4769 tmp = inb( com->intr_ctrl_port ) & ~(IEN_Tx|IEN_TxEMP|IEN_Rx); 4770 outb( com->intr_ctrl_port, (com->intr_enable|=mod) | tmp ); 4771 COM_INT_ENABLE 4772} 4773 4774static int 4775pc98_check_i8251_interrupt(struct com_s *com) 4776{ 4777 return ( com->intr_enable & 0x07 ); 4778} 4779 4780static void 4781pc98_i8251_clear_cmd(struct com_s *com, int x) 4782{ 4783 int tmp; 4784 4785 COM_INT_DISABLE 4786 tmp = com->pc98_prev_siocmd & ~(x); 4787 if (com->pc98_8251fifo_enable) 4788 outb(I8251F_fcr, 0); 4789 outb(com->cmd_port, tmp); 4790 com->pc98_prev_siocmd = tmp & ~(CMD8251_ER|CMD8251_RESET|CMD8251_EH); 4791 if (com->pc98_8251fifo_enable) 4792 outb(I8251F_fcr, CTRL8251F_ENABLE); 4793 COM_INT_ENABLE 4794} 4795 4796static void 4797pc98_i8251_or_cmd(struct com_s *com, int x) 4798{ 4799 int tmp; 4800 4801 COM_INT_DISABLE 4802 if (com->pc98_8251fifo_enable) 4803 outb(I8251F_fcr, 0); 4804 tmp = com->pc98_prev_siocmd | (x); 4805 outb(com->cmd_port, tmp); 4806 com->pc98_prev_siocmd = tmp & ~(CMD8251_ER|CMD8251_RESET|CMD8251_EH); 4807 if (com->pc98_8251fifo_enable) 4808 outb(I8251F_fcr, CTRL8251F_ENABLE); 4809 COM_INT_ENABLE 4810} 4811 4812static void 4813pc98_i8251_set_cmd(struct com_s *com, int x) 4814{ 4815 int tmp; 4816 4817 COM_INT_DISABLE 4818 if (com->pc98_8251fifo_enable) 4819 outb(I8251F_fcr, 0); 4820 tmp = (x); 4821 outb(com->cmd_port, tmp); 4822 com->pc98_prev_siocmd = tmp & ~(CMD8251_ER|CMD8251_RESET|CMD8251_EH); 4823 if (com->pc98_8251fifo_enable) 4824 outb(I8251F_fcr, CTRL8251F_ENABLE); 4825 COM_INT_ENABLE 4826} 4827 4828static void 4829pc98_i8251_clear_or_cmd(struct com_s *com, int clr, int x) 4830{ 4831 int tmp; 4832 COM_INT_DISABLE 4833 if (com->pc98_8251fifo_enable) 4834 outb(I8251F_fcr, 0); 4835 tmp = com->pc98_prev_siocmd & ~(clr); 4836 tmp |= (x); 4837 outb(com->cmd_port, tmp); 4838 com->pc98_prev_siocmd = tmp & ~(CMD8251_ER|CMD8251_RESET|CMD8251_EH); 4839 if (com->pc98_8251fifo_enable) 4840 outb(I8251F_fcr, CTRL8251F_ENABLE); 4841 COM_INT_ENABLE 4842} 4843 4844static int 4845pc98_i8251_get_cmd(struct com_s *com) 4846{ 4847 return com->pc98_prev_siocmd; 4848} 4849 4850static int 4851pc98_i8251_get_mod(struct com_s *com) 4852{ 4853 return com->pc98_prev_siomod; 4854} 4855 4856static void 4857pc98_i8251_reset(struct com_s *com, int mode, int command) 4858{ 4859 if (com->pc98_8251fifo_enable) 4860 outb(I8251F_fcr, 0); 4861 outb(com->cmd_port, 0); /* dummy */ 4862 DELAY(2); 4863 outb(com->cmd_port, 0); /* dummy */ 4864 DELAY(2); 4865 outb(com->cmd_port, 0); /* dummy */ 4866 DELAY(2); 4867 outb(com->cmd_port, CMD8251_RESET); /* internal reset */ 4868 DELAY(2); 4869 outb(com->cmd_port, mode ); /* mode register */ 4870 com->pc98_prev_siomod = mode; 4871 DELAY(2); 4872 pc98_i8251_set_cmd( com, (command|CMD8251_ER) ); 4873 DELAY(10); 4874 if (com->pc98_8251fifo_enable) 4875 outb(I8251F_fcr, CTRL8251F_ENABLE | 4876 CTRL8251F_XMT_RST | CTRL8251F_RCV_RST); 4877} 4878 4879static void 4880pc98_check_sysclock(void) 4881{ 4882 /* get system clock from port */ 4883 if ( pc98_machine_type & M_8M ) { 4884 /* 8 MHz system & H98 */ 4885 sysclock = 8; 4886 } else { 4887 /* 5 MHz system */ 4888 sysclock = 5; 4889 } 4890} 4891 4892static void 4893com_cflag_and_speed_set( struct com_s *com, int cflag, int speed) 4894{ 4895 int cfcr=0, count; 4896 int previnterrupt; 4897 4898 count = pc98_ttspeedtab( com, speed ); 4899 if ( count < 0 ) return; 4900 4901 previnterrupt = pc98_check_i8251_interrupt(com); 4902 pc98_disable_i8251_interrupt( com, IEN_Tx|IEN_TxEMP|IEN_Rx ); 4903 4904 switch ( cflag&CSIZE ) { 4905 case CS5: 4906 cfcr = MOD8251_5BITS; break; 4907 case CS6: 4908 cfcr = MOD8251_6BITS; break; 4909 case CS7: 4910 cfcr = MOD8251_7BITS; break; 4911 case CS8: 4912 cfcr = MOD8251_8BITS; break; 4913 } 4914 if ( cflag&PARENB ) { 4915 if ( cflag&PARODD ) 4916 cfcr |= MOD8251_PODD; 4917 else 4918 cfcr |= MOD8251_PEVEN; 4919 } else 4920 cfcr |= MOD8251_PDISAB; 4921 4922 if ( cflag&CSTOPB ) 4923 cfcr |= MOD8251_STOP2; 4924 else 4925 cfcr |= MOD8251_STOP1; 4926 4927 if ( count & 0x10000 ) 4928 cfcr |= MOD8251_CLKX1; 4929 else 4930 cfcr |= MOD8251_CLKX16; 4931 4932 if (epson_machine_id != 0x20) { /* XXX */ 4933 int tmp; 4934 while (!((tmp = inb(com->sts_port)) & STS8251_TxEMP)) 4935 ; 4936 } 4937 /* set baud rate from ospeed */ 4938 pc98_set_baud_rate( com, count ); 4939 4940 if ( cfcr != pc98_i8251_get_mod(com) ) 4941 pc98_i8251_reset(com, cfcr, pc98_i8251_get_cmd(com) ); 4942 4943 pc98_enable_i8251_interrupt( com, previnterrupt ); 4944} 4945 4946static int 4947pc98_ttspeedtab(struct com_s *com, int speed) 4948{ 4949 int if_type, effect_sp, count = -1, mod; 4950 4951 if_type = com->pc98_if_type & 0x0f; 4952 4953 switch (com->pc98_if_type) { 4954 case COM_IF_INTERNAL: 4955 if (PC98SIO_baud_rate_port(if_type) != -1) { 4956 count = ttspeedtab(speed, if_8251_type[if_type].speedtab); 4957 if (count > 0) { 4958 count |= COM1_EXT_CLOCK; 4959 break; 4960 } 4961 } 4962 4963 /* for *1CLK asynchronous! mode, TEFUTEFU */ 4964 mod = (sysclock == 5) ? 2457600 : 1996800; 4965 effect_sp = ttspeedtab( speed, pc98speedtab ); 4966 if ( effect_sp < 0 ) /* XXX */ 4967 effect_sp = ttspeedtab( (speed - 1), pc98speedtab ); 4968 if ( effect_sp <= 0 ) 4969 return effect_sp; 4970 if ( effect_sp == speed ) 4971 mod /= 16; 4972 if ( mod % effect_sp ) 4973 return(-1); 4974 count = mod / effect_sp; 4975 if ( count > 65535 ) 4976 return(-1); 4977 if ( effect_sp != speed ) 4978 count |= 0x10000; 4979 break; 4980 case COM_IF_PC9861K_1: 4981 case COM_IF_PC9861K_2: 4982 count = 1; 4983 break; 4984 case COM_IF_IND_SS_1: 4985 case COM_IF_IND_SS_2: 4986 case COM_IF_PIO9032B_1: 4987 case COM_IF_PIO9032B_2: 4988 if ( speed == 0 ) return 0; 4989 count = ttspeedtab( speed, if_8251_type[if_type].speedtab ); 4990 break; 4991 case COM_IF_B98_01_1: 4992 case COM_IF_B98_01_2: 4993 if ( speed == 0 ) return 0; 4994 count = ttspeedtab( speed, if_8251_type[if_type].speedtab ); 4995#ifdef B98_01_OLD 4996 if (count == 0 || count == 1) { 4997 count += 4; 4998 count |= 0x20000; /* x1 mode for 76800 and 153600 */ 4999 } 5000#endif 5001 break; 5002 } 5003 5004 return count; 5005} 5006 5007static void 5008pc98_set_baud_rate( struct com_s *com, int count ) 5009{ 5010 int if_type, io, s; 5011 5012 if_type = com->pc98_if_type & 0x0f; 5013 io = rman_get_start(com->ioportres) & 0xff00; 5014 5015 switch (com->pc98_if_type) { 5016 case COM_IF_INTERNAL: 5017 if (PC98SIO_baud_rate_port(if_type) != -1) { 5018 if (count & COM1_EXT_CLOCK) { 5019 outb((Port_t)PC98SIO_baud_rate_port(if_type), count & 0xff); 5020 break; 5021 } else { 5022 outb((Port_t)PC98SIO_baud_rate_port(if_type), 0x09); 5023 } 5024 } 5025 5026 if ( count < 0 ) { 5027 printf( "[ Illegal count : %d ]", count ); 5028 return; 5029 } else if ( count == 0 ) 5030 return; 5031 /* set i8253 */ 5032 s = splclock(); 5033 if (count != 3) 5034 outb( 0x77, 0xb6 ); 5035 else 5036 outb( 0x77, 0xb4 ); 5037 outb( 0x5f, 0); 5038 outb( 0x75, count & 0xff ); 5039 outb( 0x5f, 0); 5040 outb( 0x75, (count >> 8) & 0xff ); 5041 splx(s); 5042 break; 5043 case COM_IF_IND_SS_1: 5044 case COM_IF_IND_SS_2: 5045 outb(io | PC98SIO_intr_ctrl_port(if_type), 0); 5046 outb(io | PC98SIO_baud_rate_port(if_type), 0); 5047 outb(io | PC98SIO_baud_rate_port(if_type), 0xc0); 5048 outb(io | PC98SIO_baud_rate_port(if_type), (count >> 8) | 0x80); 5049 outb(io | PC98SIO_baud_rate_port(if_type), count & 0xff); 5050 break; 5051 case COM_IF_PIO9032B_1: 5052 case COM_IF_PIO9032B_2: 5053 outb(io | PC98SIO_baud_rate_port(if_type), count); 5054 break; 5055 case COM_IF_B98_01_1: 5056 case COM_IF_B98_01_2: 5057 outb(io | PC98SIO_baud_rate_port(if_type), count & 0x0f); 5058#ifdef B98_01_OLD 5059 /* 5060 * Some old B98_01 board should be controlled 5061 * in different way, but this hasn't been tested yet. 5062 */ 5063 outb(io | PC98SIO_func_port(if_type), 5064 (count & 0x20000) ? 0xf0 : 0xf2); 5065#endif 5066 break; 5067 } 5068} 5069static int 5070pc98_check_if_type(device_t dev, struct siodev *iod) 5071{ 5072 int irr, io, if_type, tmp; 5073 static short irq_tab[2][8] = { 5074 { 3, 5, 6, 9, 10, 12, 13, -1}, 5075 { 3, 10, 12, 13, 5, 6, 9, -1} 5076 }; 5077 5078 if_type = iod->if_type & 0x0f; 5079 iod->irq = 0; 5080 io = isa_get_port(dev) & 0xff00; 5081 5082 if (IS_8251(iod->if_type)) { 5083 if (PC98SIO_func_port(if_type) != -1) { 5084 outb(io | PC98SIO_func_port(if_type), 0xf2); 5085 tmp = ttspeedtab(9600, if_8251_type[if_type].speedtab); 5086 if (tmp != -1 && PC98SIO_baud_rate_port(if_type) != -1) 5087 outb(io | PC98SIO_baud_rate_port(if_type), tmp); 5088 } 5089 5090 iod->cmd = io | PC98SIO_cmd_port(if_type); 5091 iod->sts = io | PC98SIO_sts_port(if_type); 5092 iod->mod = io | PC98SIO_in_modem_port(if_type); 5093 iod->ctrl = io | PC98SIO_intr_ctrl_port(if_type); 5094 5095 if (iod->if_type == COM_IF_INTERNAL) { 5096 iod->irq = 4; 5097 5098 if (pc98_check_8251vfast()) { 5099 PC98SIO_baud_rate_port(if_type) = I8251F_div; 5100 if_8251_type[if_type].speedtab = pc98fast_speedtab; 5101 } 5102 } else { 5103 tmp = inb( iod->mod ) & if_8251_type[if_type].irr_mask; 5104 if ((isa_get_port(dev) & 0xff) == IO_COM2) 5105 iod->irq = irq_tab[0][tmp]; 5106 else 5107 iod->irq = irq_tab[1][tmp]; 5108 } 5109 } else { 5110 irr = if_16550a_type[if_type].irr_read; 5111#ifdef COM_MULTIPORT 5112 if (!COM_ISMULTIPORT(device_get_flags(dev)) || 5113 device_get_unit(dev) == COM_MPMASTER(device_get_flags(dev))) 5114#endif 5115 if (irr != -1) { 5116 tmp = inb(io | irr); 5117 if (isa_get_port(dev) & 0x01) /* XXX depend on RSB-384 */ 5118 iod->irq = irq_tab[1][tmp >> 3]; 5119 else 5120 iod->irq = irq_tab[0][tmp & 0x07]; 5121 } 5122 } 5123 if ( iod->irq == -1 ) return -1; 5124 5125 return 0; 5126} 5127static void 5128pc98_set_ioport(struct com_s *com) 5129{ 5130 int if_type = com->pc98_if_type & 0x0f; 5131 Port_t io = rman_get_start(com->ioportres) & 0xff00; 5132 5133 pc98_check_sysclock(); 5134 com->data_port = io | PC98SIO_data_port(if_type); 5135 com->cmd_port = io | PC98SIO_cmd_port(if_type); 5136 com->sts_port = io | PC98SIO_sts_port(if_type); 5137 com->in_modem_port = io | PC98SIO_in_modem_port(if_type); 5138 com->intr_ctrl_port = io | PC98SIO_intr_ctrl_port(if_type); 5139} 5140static int 5141pc98_check_8251vfast(void) 5142{ 5143 int i; 5144 5145 outb(I8251F_div, 0x8c); 5146 DELAY(10); 5147 for (i = 0; i < 100; i++) { 5148 if ((inb(I8251F_div) & 0x80) != 0) { 5149 i = 0; 5150 break; 5151 } 5152 DELAY(1); 5153 } 5154 outb(I8251F_div, 0); 5155 DELAY(10); 5156 for (; i < 100; i++) { 5157 if ((inb(I8251F_div) & 0x80) == 0) 5158 return 1; 5159 DELAY(1); 5160 } 5161 5162 return 0; 5163} 5164static int 5165pc98_check_8251fifo(void) 5166{ 5167 u_char tmp1, tmp2; 5168 5169 tmp1 = inb(I8251F_iir); 5170 DELAY(10); 5171 tmp2 = inb(I8251F_iir); 5172 if (((tmp1 ^ tmp2) & 0x40) != 0 && ((tmp1 | tmp2) & 0x20) == 0) 5173 return 1; 5174 5175 return 0; 5176} 5177#endif /* PC98 defined */ 5178