sio.c revision 58888
1/*- 2 * Copyright (c) 1991 The Regents of the University of California. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by the University of 16 * California, Berkeley and its contributors. 17 * 4. Neither the name of the University nor the names of its contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 25 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 31 * SUCH DAMAGE. 32 * 33 * $FreeBSD: head/sys/pc98/cbus/sio.c 58888 2000-04-01 11:27:31Z kato $ 34 * from: @(#)com.c 7.5 (Berkeley) 5/16/91 35 * from: i386/isa sio.c,v 1.234 36 */ 37 38#include "opt_comconsole.h" 39#include "opt_compat.h" 40#include "opt_ddb.h" 41#include "opt_sio.h" 42#include "card.h" 43#include "pci.h" 44#include "sio.h" 45 46/* 47 * Serial driver, based on 386BSD-0.1 com driver. 48 * Mostly rewritten to use pseudo-DMA. 49 * Works for National Semiconductor NS8250-NS16550AF UARTs. 50 * COM driver, based on HP dca driver. 51 * 52 * Changes for PC-Card integration: 53 * - Added PC-Card driver table and handlers 54 */ 55/*=============================================================== 56 * 386BSD(98),FreeBSD-1.1x(98) com driver. 57 * ----- 58 * modified for PC9801 by M.Ishii 59 * Kyoto University Microcomputer Club (KMC) 60 * Chou "TEFUTEFU" Hirotomi 61 * Kyoto Univ. the faculty of medicine 62 *=============================================================== 63 * FreeBSD-2.0.1(98) sio driver. 64 * ----- 65 * modified for pc98 Internal i8251 and MICRO CORE MC16550II 66 * T.Koike(hfc01340@niftyserve.or.jp) 67 * implement kernel device configuration 68 * aizu@orient.center.nitech.ac.jp 69 * 70 * Notes. 71 * ----- 72 * PC98 localization based on 386BSD(98) com driver. Using its PC98 local 73 * functions. 74 * This driver is under debugging,has bugs. 75 * 76 * 1) config 77 * options COM_MULTIPORT #if using MC16550II 78 * device sio0 at nec? port 0x30 tty irq 4 #internal 79 * device sio1 at nec? port 0xd2 tty irq 5 flags 0x101 #mc1 80 * device sio2 at nec? port 0x8d2 tty flags 0x101 #mc2 81 * # ~~~~~iobase ~~multi port flag 82 * # ~ master device is sio1 83 * 2) device 84 * cd /dev; MAKEDEV ttyd0 ttyd1 .. 85 * 3) /etc/rc.serial 86 * 57600bps is too fast for sio0(internal8251) 87 * my ex. 88 * #set default speed 9600 89 * modem() 90 * : 91 * stty </dev/ttyid$i crtscts 9600 92 * : # ~~~~ default speed(can change after init.) 93 * modem 0 1 2 94 * 4) COMCONSOLE 95 * not changed. 96 * 5) PC9861K,PIO9032B,B98_01 97 * not tested. 98 */ 99/* 100 * modified for AIWA B98-01 101 * by T.Hatanou <hatanou@yasuda.comm.waseda.ac.jp> last update: 15 Sep.1995 102 * 103 * How to configure... 104 * # options COM_MULTIPORT # support for MICROCORE MC16550II 105 * ... comment-out this line, which will conflict with B98_01. 106 * options "B98_01" # support for AIWA B98-01 107 * device sio1 at nec? port 0x00d1 tty irq ? 108 * device sio2 at nec? port 0x00d5 tty irq ? 109 * ... you can leave these lines `irq ?', irq will be autodetected. 110 */ 111/* 112 * Modified by Y.Takahashi of Kogakuin University. 113 */ 114/* 115 * modified for 8251(FIFO) by Seigo TANIMURA <tanimura@FreeBSD.org> 116 */ 117 118#ifdef PC98 119#define COM_IF_INTERNAL 0x00 120#define COM_IF_PC9861K_1 0x01 121#define COM_IF_PC9861K_2 0x02 122#define COM_IF_IND_SS_1 0x03 123#define COM_IF_IND_SS_2 0x04 124#define COM_IF_PIO9032B_1 0x05 125#define COM_IF_PIO9032B_2 0x06 126#define COM_IF_B98_01_1 0x07 127#define COM_IF_B98_01_2 0x08 128#define COM_IF_END1 COM_IF_B98_01_2 129#define COM_IF_RSA98 0x10 /* same as COM_IF_NS16550 */ 130#define COM_IF_NS16550 0x11 131#define COM_IF_SECOND_CCU 0x12 /* same as COM_IF_NS16550 */ 132#define COM_IF_MC16550II 0x13 133#define COM_IF_MCRS98 0x14 /* same as COM_IF_MC16550II */ 134#define COM_IF_RSB3000 0x15 135#define COM_IF_RSB384 0x16 136#define COM_IF_MODEM_CARD 0x17 /* same as COM_IF_NS16550 */ 137#define COM_IF_RSA98III 0x18 138#define COM_IF_ESP98 0x19 139#define COM_IF_END2 COM_IF_ESP98 140#endif /* PC98 */ 141 142#include <sys/param.h> 143#include <sys/systm.h> 144#include <sys/reboot.h> 145#include <sys/malloc.h> 146#include <sys/tty.h> 147#include <sys/proc.h> 148#include <sys/module.h> 149#include <sys/conf.h> 150#include <sys/dkstat.h> 151#include <sys/fcntl.h> 152#include <sys/interrupt.h> 153#include <sys/kernel.h> 154#include <sys/syslog.h> 155#include <sys/sysctl.h> 156#include <sys/bus.h> 157#include <machine/bus.h> 158#include <sys/rman.h> 159#include <sys/timetc.h> 160#include <sys/timepps.h> 161 162#ifdef PC98 163#include <pc98/pc98/pc98.h> 164#include <pc98/pc98/pc98_machdep.h> 165#include <i386/isa/ic/i8251.h> 166#else 167#include <isa/isareg.h> 168#endif 169#include <isa/isavar.h> 170#if NPCI > 0 171#include <pci/pcireg.h> 172#include <pci/pcivar.h> 173#endif 174#include <machine/lock.h> 175 176#include <machine/clock.h> 177#include <machine/ipl.h> 178#ifndef SMP 179#include <machine/lock.h> 180#endif 181#include <machine/resource.h> 182 183#include <isa/sioreg.h> 184 185#ifdef COM_ESP 186#include <i386/isa/ic/esp.h> 187#endif 188#include <i386/isa/ic/ns16550.h> 189#ifdef PC98 190#include <i386/isa/ic/rsa.h> 191#endif 192 193#ifndef __i386__ 194#define disable_intr() 195#define enable_intr() 196#endif 197 198#ifdef SMP 199#define disable_intr() COM_DISABLE_INTR() 200#define enable_intr() COM_ENABLE_INTR() 201#endif /* SMP */ 202 203#define LOTS_OF_EVENTS 64 /* helps separate urgent events from input */ 204 205#define CALLOUT_MASK 0x80 206#define CONTROL_MASK 0x60 207#define CONTROL_INIT_STATE 0x20 208#define CONTROL_LOCK_STATE 0x40 209#define DEV_TO_UNIT(dev) (MINOR_TO_UNIT(minor(dev))) 210#define MINOR_MAGIC_MASK (CALLOUT_MASK | CONTROL_MASK) 211#define MINOR_TO_UNIT(mynor) ((mynor) & ~MINOR_MAGIC_MASK) 212 213#ifdef COM_MULTIPORT 214/* checks in flags for multiport and which is multiport "master chip" 215 * for a given card 216 */ 217#define COM_ISMULTIPORT(flags) ((flags) & 0x01) 218#define COM_MPMASTER(flags) (((flags) >> 8) & 0x0ff) 219#define COM_NOTAST4(flags) ((flags) & 0x04) 220#endif /* COM_MULTIPORT */ 221 222#define COM_CONSOLE(flags) ((flags) & 0x10) 223#define COM_FORCECONSOLE(flags) ((flags) & 0x20) 224#define COM_LLCONSOLE(flags) ((flags) & 0x40) 225#define COM_DEBUGGER(flags) ((flags) & 0x80) 226#define COM_LOSESOUTINTS(flags) ((flags) & 0x08) 227#define COM_NOFIFO(flags) ((flags) & 0x02) 228#define COM_ST16650A(flags) ((flags) & 0x20000) 229#define COM_C_NOPROBE (0x40000) 230#define COM_NOPROBE(flags) ((flags) & COM_C_NOPROBE) 231#define COM_C_IIR_TXRDYBUG (0x80000) 232#define COM_IIR_TXRDYBUG(flags) ((flags) & COM_C_IIR_TXRDYBUG) 233#define COM_FIFOSIZE(flags) (((flags) & 0xff000000) >> 24) 234 235#ifdef PC98 236#define com_emr com_msr /* Extension mode register for RSB-2000/3000 */ 237#else 238#define com_scr 7 /* scratch register for 16450-16550 (R/W) */ 239#endif 240 241/* 242 * com state bits. 243 * (CS_BUSY | CS_TTGO) and (CS_BUSY | CS_TTGO | CS_ODEVREADY) must be higher 244 * than the other bits so that they can be tested as a group without masking 245 * off the low bits. 246 * 247 * The following com and tty flags correspond closely: 248 * CS_BUSY = TS_BUSY (maintained by comstart(), siopoll() and 249 * comstop()) 250 * CS_TTGO = ~TS_TTSTOP (maintained by comparam() and comstart()) 251 * CS_CTS_OFLOW = CCTS_OFLOW (maintained by comparam()) 252 * CS_RTS_IFLOW = CRTS_IFLOW (maintained by comparam()) 253 * TS_FLUSH is not used. 254 * XXX I think TIOCSETA doesn't clear TS_TTSTOP when it clears IXON. 255 * XXX CS_*FLOW should be CF_*FLOW in com->flags (control flags not state). 256 */ 257#define CS_BUSY 0x80 /* output in progress */ 258#define CS_TTGO 0x40 /* output not stopped by XOFF */ 259#define CS_ODEVREADY 0x20 /* external device h/w ready (CTS) */ 260#define CS_CHECKMSR 1 /* check of MSR scheduled */ 261#define CS_CTS_OFLOW 2 /* use CTS output flow control */ 262#define CS_DTR_OFF 0x10 /* DTR held off */ 263#define CS_ODONE 4 /* output completed */ 264#define CS_RTS_IFLOW 8 /* use RTS input flow control */ 265#define CSE_BUSYCHECK 1 /* siobusycheck() scheduled */ 266 267static char const * const error_desc[] = { 268#define CE_OVERRUN 0 269 "silo overflow", 270#define CE_INTERRUPT_BUF_OVERFLOW 1 271 "interrupt-level buffer overflow", 272#define CE_TTY_BUF_OVERFLOW 2 273 "tty-level buffer overflow", 274}; 275 276#define CE_NTYPES 3 277#define CE_RECORD(com, errnum) (++(com)->delta_error_counts[errnum]) 278 279/* types. XXX - should be elsewhere */ 280typedef u_int Port_t; /* hardware port */ 281typedef u_char bool_t; /* boolean */ 282 283/* queue of linear buffers */ 284struct lbq { 285 u_char *l_head; /* next char to process */ 286 u_char *l_tail; /* one past the last char to process */ 287 struct lbq *l_next; /* next in queue */ 288 bool_t l_queued; /* nonzero if queued */ 289}; 290 291/* com device structure */ 292struct com_s { 293 u_int flags; /* Copy isa device flags */ 294 u_char state; /* miscellaneous flag bits */ 295 bool_t active_out; /* nonzero if the callout device is open */ 296 u_char cfcr_image; /* copy of value written to CFCR */ 297#ifdef COM_ESP 298 bool_t esp; /* is this unit a hayes esp board? */ 299#endif 300 u_char extra_state; /* more flag bits, separate for order trick */ 301 u_char fifo_image; /* copy of value written to FIFO */ 302 bool_t hasfifo; /* nonzero for 16550 UARTs */ 303 bool_t st16650a; /* Is a Startech 16650A or RTS/CTS compat */ 304 bool_t loses_outints; /* nonzero if device loses output interrupts */ 305 u_char mcr_image; /* copy of value written to MCR */ 306#ifdef COM_MULTIPORT 307 bool_t multiport; /* is this unit part of a multiport device? */ 308#endif /* COM_MULTIPORT */ 309 bool_t no_irq; /* nonzero if irq is not attached */ 310 bool_t gone; /* hardware disappeared */ 311 bool_t poll; /* nonzero if polling is required */ 312 bool_t poll_output; /* nonzero if polling for output is required */ 313 int unit; /* unit number */ 314 int dtr_wait; /* time to hold DTR down on close (* 1/hz) */ 315 u_int tx_fifo_size; 316 u_int wopeners; /* # processes waiting for DCD in open() */ 317 318 /* 319 * The high level of the driver never reads status registers directly 320 * because there would be too many side effects to handle conveniently. 321 * Instead, it reads copies of the registers stored here by the 322 * interrupt handler. 323 */ 324 u_char last_modem_status; /* last MSR read by intr handler */ 325 u_char prev_modem_status; /* last MSR handled by high level */ 326 327 u_char hotchar; /* ldisc-specific char to be handled ASAP */ 328 u_char *ibuf; /* start of input buffer */ 329 u_char *ibufend; /* end of input buffer */ 330 u_char *ibufold; /* old input buffer, to be freed */ 331 u_char *ihighwater; /* threshold in input buffer */ 332 u_char *iptr; /* next free spot in input buffer */ 333 int ibufsize; /* size of ibuf (not include error bytes) */ 334 int ierroff; /* offset of error bytes in ibuf */ 335 336 struct lbq obufq; /* head of queue of output buffers */ 337 struct lbq obufs[2]; /* output buffers */ 338 339#ifdef PC98 340 Port_t cmd_port; 341 Port_t sts_port; 342 Port_t in_modem_port; 343 Port_t intr_ctrl_port; 344 int intr_enable; 345 int pc98_prev_modem_status; 346 int pc98_modem_delta; 347 int modem_car_chg_timer; 348 int pc98_prev_siocmd; 349 int pc98_prev_siomod; 350 int modem_checking; 351 int pc98_if_type; 352 353 bool_t pc98_8251fifo; 354 bool_t pc98_8251fifo_enable; 355#endif /* PC98 */ 356 Port_t data_port; /* i/o ports */ 357#ifdef COM_ESP 358 Port_t esp_port; 359#endif 360 Port_t int_id_port; 361 Port_t iobase; 362#ifdef PC98 363 Port_t rsabase; /* iobase address of a I/O-DATA RSA board */ 364#endif 365 Port_t modem_ctl_port; 366 Port_t line_status_port; 367 Port_t modem_status_port; 368 Port_t intr_ctl_port; /* Ports of IIR register */ 369 370 struct tty *tp; /* cross reference */ 371 372 /* Initial state. */ 373 struct termios it_in; /* should be in struct tty */ 374 struct termios it_out; 375 376 /* Lock state. */ 377 struct termios lt_in; /* should be in struct tty */ 378 struct termios lt_out; 379 380 bool_t do_timestamp; 381 bool_t do_dcd_timestamp; 382 struct timeval timestamp; 383 struct timeval dcd_timestamp; 384 struct pps_state pps; 385 386 u_long bytes_in; /* statistics */ 387 u_long bytes_out; 388 u_int delta_error_counts[CE_NTYPES]; 389 u_long error_counts[CE_NTYPES]; 390 391 struct resource *irqres; 392 struct resource *ioportres; 393 void *cookie; 394 395 /* 396 * Data area for output buffers. Someday we should build the output 397 * buffer queue without copying data. 398 */ 399#ifdef PC98 400 int obufsize; 401 u_char *obuf1; 402 u_char *obuf2; 403#else 404 u_char obuf1[256]; 405 u_char obuf2[256]; 406#endif 407}; 408 409#ifdef COM_ESP 410static int espattach __P((struct com_s *com, Port_t esp_port)); 411#endif 412static int sioattach __P((device_t dev, int rid)); 413static int sio_isa_attach __P((device_t dev)); 414 415static timeout_t siobusycheck; 416static timeout_t siodtrwakeup; 417static void comhardclose __P((struct com_s *com)); 418static void sioinput __P((struct com_s *com)); 419static void siointr1 __P((struct com_s *com)); 420static void siointr __P((void *arg)); 421static int commctl __P((struct com_s *com, int bits, int how)); 422static int comparam __P((struct tty *tp, struct termios *t)); 423static swihand_t siopoll; 424static int sioprobe __P((device_t dev, int xrid)); 425static int sio_isa_probe __P((device_t dev)); 426static void siosettimeout __P((void)); 427static int siosetwater __P((struct com_s *com, speed_t speed)); 428static void comstart __P((struct tty *tp)); 429static void comstop __P((struct tty *tp, int rw)); 430static timeout_t comwakeup; 431static void disc_optim __P((struct tty *tp, struct termios *t, 432 struct com_s *com)); 433 434#if NCARD > 0 435static int sio_pccard_attach __P((device_t dev)); 436static int sio_pccard_detach __P((device_t dev)); 437static int sio_pccard_probe __P((device_t dev)); 438#endif /* NCARD > 0 */ 439 440#if NPCI > 0 441static int sio_pci_attach __P((device_t dev)); 442static void sio_pci_kludge_unit __P((device_t dev)); 443static int sio_pci_probe __P((device_t dev)); 444#endif /* NPCI > 0 */ 445 446static char driver_name[] = "sio"; 447 448/* table and macro for fast conversion from a unit number to its com struct */ 449static devclass_t sio_devclass; 450#define com_addr(unit) ((struct com_s *) \ 451 devclass_get_softc(sio_devclass, unit)) 452 453static device_method_t sio_isa_methods[] = { 454 /* Device interface */ 455 DEVMETHOD(device_probe, sio_isa_probe), 456 DEVMETHOD(device_attach, sio_isa_attach), 457 458 { 0, 0 } 459}; 460 461static driver_t sio_isa_driver = { 462 driver_name, 463 sio_isa_methods, 464 sizeof(struct com_s), 465}; 466 467#if NCARD > 0 468static device_method_t sio_pccard_methods[] = { 469 /* Device interface */ 470 DEVMETHOD(device_probe, sio_pccard_probe), 471 DEVMETHOD(device_attach, sio_pccard_attach), 472 DEVMETHOD(device_detach, sio_pccard_detach), 473 474 { 0, 0 } 475}; 476 477static driver_t sio_pccard_driver = { 478 driver_name, 479 sio_pccard_methods, 480 sizeof(struct com_s), 481}; 482#endif /* NCARD > 0 */ 483 484#if NPCI > 0 485static device_method_t sio_pci_methods[] = { 486 /* Device interface */ 487 DEVMETHOD(device_probe, sio_pci_probe), 488 DEVMETHOD(device_attach, sio_pci_attach), 489 490 { 0, 0 } 491}; 492 493static driver_t sio_pci_driver = { 494 driver_name, 495 sio_pci_methods, 496 sizeof(struct com_s), 497}; 498#endif /* NPCI > 0 */ 499 500static d_open_t sioopen; 501static d_close_t sioclose; 502static d_read_t sioread; 503static d_write_t siowrite; 504static d_ioctl_t sioioctl; 505 506#define CDEV_MAJOR 28 507static struct cdevsw sio_cdevsw = { 508 /* open */ sioopen, 509 /* close */ sioclose, 510 /* read */ sioread, 511 /* write */ siowrite, 512 /* ioctl */ sioioctl, 513 /* poll */ ttypoll, 514 /* mmap */ nommap, 515 /* strategy */ nostrategy, 516 /* name */ driver_name, 517 /* maj */ CDEV_MAJOR, 518 /* dump */ nodump, 519 /* psize */ nopsize, 520 /* flags */ D_TTY, 521 /* bmaj */ -1 522}; 523 524int comconsole = -1; 525static volatile speed_t comdefaultrate = CONSPEED; 526#ifdef __alpha__ 527static volatile speed_t gdbdefaultrate = CONSPEED; 528#endif 529static u_int com_events; /* input chars + weighted output completions */ 530static Port_t siocniobase; 531static int siocnunit; 532static Port_t siogdbiobase; 533static int siogdbunit = -1; 534static bool_t sio_registered; 535static int sio_timeout; 536static int sio_timeouts_until_log; 537static struct callout_handle sio_timeout_handle 538 = CALLOUT_HANDLE_INITIALIZER(&sio_timeout_handle); 539static int sio_numunits; 540 541#ifdef PC98 542struct siodev { 543 short if_type; 544 short irq; 545 Port_t cmd, sts, ctrl, mod; 546}; 547static int sysclock; 548 549#define COM_INT_DISABLE {int previpri; previpri=spltty(); 550#define COM_INT_ENABLE splx(previpri);} 551#define IEN_TxFLAG IEN_Tx 552 553#define COM_CARRIER_DETECT_EMULATE 0 554#define PC98_CHECK_MODEM_INTERVAL (hz/10) 555#define DCD_OFF_TOLERANCE 2 556#define DCD_ON_RECOGNITION 2 557#define GET_IFTYPE(flags) ((flags >> 24) & 0x1f) 558#define IS_8251(if_type) (!(if_type & 0x10)) 559#define COM1_EXT_CLOCK 0x40000 560 561static void commint __P((dev_t dev)); 562static void com_tiocm_set __P((struct com_s *com, int msr)); 563static void com_tiocm_bis __P((struct com_s *com, int msr)); 564static void com_tiocm_bic __P((struct com_s *com, int msr)); 565static int com_tiocm_get __P((struct com_s *com)); 566static int com_tiocm_get_delta __P((struct com_s *com)); 567static void pc98_msrint_start __P((dev_t dev)); 568static void com_cflag_and_speed_set __P((struct com_s *com, int cflag, int speed)); 569static int pc98_ttspeedtab __P((struct com_s *com, int speed)); 570static int pc98_get_modem_status __P((struct com_s *com)); 571static timeout_t pc98_check_msr; 572static void pc98_set_baud_rate __P((struct com_s *com, int count)); 573static void pc98_i8251_reset __P((struct com_s *com, int mode, int command)); 574static void pc98_disable_i8251_interrupt __P((struct com_s *com, int mod)); 575static void pc98_enable_i8251_interrupt __P((struct com_s *com, int mod)); 576static int pc98_check_i8251_interrupt __P((struct com_s *com)); 577static int pc98_i8251_get_cmd __P((struct com_s *com)); 578static int pc98_i8251_get_mod __P((struct com_s *com)); 579static void pc98_i8251_set_cmd __P((struct com_s *com, int x)); 580static void pc98_i8251_or_cmd __P((struct com_s *com, int x)); 581static void pc98_i8251_clear_cmd __P((struct com_s *com, int x)); 582static void pc98_i8251_clear_or_cmd __P((struct com_s *com, int clr, int x)); 583static int pc98_check_if_type __P((device_t dev, struct siodev *iod)); 584static int pc98_check_8251vfast __P((void)); 585static int pc98_check_8251fifo __P((void)); 586static void pc98_check_sysclock __P((void)); 587static int pc98_set_ioport __P((struct com_s *com)); 588 589#define com_int_Tx_disable(com) \ 590 pc98_disable_i8251_interrupt(com,IEN_Tx|IEN_TxEMP) 591#define com_int_Tx_enable(com) \ 592 pc98_enable_i8251_interrupt(com,IEN_TxFLAG) 593#define com_int_Rx_disable(com) \ 594 pc98_disable_i8251_interrupt(com,IEN_Rx) 595#define com_int_Rx_enable(com) \ 596 pc98_enable_i8251_interrupt(com,IEN_Rx) 597#define com_int_TxRx_disable(com) \ 598 pc98_disable_i8251_interrupt(com,IEN_Tx|IEN_TxEMP|IEN_Rx) 599#define com_int_TxRx_enable(com) \ 600 pc98_enable_i8251_interrupt(com,IEN_TxFLAG|IEN_Rx) 601#define com_send_break_on(com) \ 602 pc98_i8251_or_cmd(com,CMD8251_SBRK) 603#define com_send_break_off(com) \ 604 pc98_i8251_clear_cmd(com,CMD8251_SBRK) 605 606static struct speedtab pc98speedtab[] = { /* internal RS232C interface */ 607 { 0, 0, }, 608 { 50, 50, }, 609 { 75, 75, }, 610 { 150, 150, }, 611 { 200, 200, }, 612 { 300, 300, }, 613 { 600, 600, }, 614 { 1200, 1200, }, 615 { 2400, 2400, }, 616 { 4800, 4800, }, 617 { 9600, 9600, }, 618 { 19200, 19200, }, 619 { 38400, 38400, }, 620 { 51200, 51200, }, 621 { 76800, 76800, }, 622 { 20800, 20800, }, 623 { 31200, 31200, }, 624 { 41600, 41600, }, 625 { 62400, 62400, }, 626 { -1, -1 } 627}; 628static struct speedtab pc98fast_speedtab[] = { 629 { 9600, 0x80 | COMBRD(9600), }, 630 { 19200, 0x80 | COMBRD(19200), }, 631 { 38400, 0x80 | COMBRD(38400), }, 632 { 57600, 0x80 | COMBRD(57600), }, 633 { 115200, 0x80 | COMBRD(115200), }, 634 { -1, -1 } 635}; 636static struct speedtab comspeedtab_pio9032b[] = { 637 { 300, 6, }, 638 { 600, 5, }, 639 { 1200, 4, }, 640 { 2400, 3, }, 641 { 4800, 2, }, 642 { 9600, 1, }, 643 { 19200, 0, }, 644 { 38400, 7, }, 645 { -1, -1 } 646}; 647static struct speedtab comspeedtab_b98_01[] = { 648 { 75, 11, }, 649 { 150, 10, }, 650 { 300, 9, }, 651 { 600, 8, }, 652 { 1200, 7, }, 653 { 2400, 6, }, 654 { 4800, 5, }, 655 { 9600, 4, }, 656 { 19200, 3, }, 657 { 38400, 2, }, 658 { 76800, 1, }, 659 { 153600, 0, }, 660 { -1, -1 } 661}; 662static struct speedtab comspeedtab_mc16550[] = { 663 { 300, 1536, }, 664 { 600, 768, }, 665 { 1200, 384, }, 666 { 2400, 192, }, 667 { 4800, 96, }, 668 { 9600, 48, }, 669 { 19200, 24, }, 670 { 38400, 12, }, 671 { 57600, 8, }, 672 { 115200, 4, }, 673 { 153600, 3, }, 674 { 230400, 2, }, 675 { 460800, 1, }, 676 { -1, -1 } 677}; 678static struct speedtab comspeedtab_rsb384[] = { 679 { 300, 3840, }, 680 { 600, 1920, }, 681 { 1200, 960, }, 682 { 2400, 480, }, 683 { 4800, 240, }, 684 { 9600, 120, }, 685 { 19200, 60, }, 686 { 38400, 30, }, 687 { 57600, 20, }, 688 { 115200, 10, }, 689 { 128000, 9, }, 690 { 144000, 8, }, 691 { 192000, 6, }, 692 { 230400, 5, }, 693 { 288000, 4, }, 694 { 384000, 3, }, 695 { 576000, 2, }, 696 { 1152000, 1, }, 697 { -1, -1 } 698}; 699static struct speedtab comspeedtab_rsa[] = { 700 { 0, 0 }, 701 { 50, COMBRD_RSA(50) }, 702 { 75, COMBRD_RSA(75) }, 703 { 110, COMBRD_RSA(110) }, 704 { 134, COMBRD_RSA(134) }, 705 { 150, COMBRD_RSA(150) }, 706 { 200, COMBRD_RSA(200) }, 707 { 300, COMBRD_RSA(300) }, 708 { 600, COMBRD_RSA(600) }, 709 { 1200, COMBRD_RSA(1200) }, 710 { 1800, COMBRD_RSA(1800) }, 711 { 2400, COMBRD_RSA(2400) }, 712 { 4800, COMBRD_RSA(4800) }, 713 { 9600, COMBRD_RSA(9600) }, 714 { 19200, COMBRD_RSA(19200) }, 715 { 38400, COMBRD_RSA(38400) }, 716 { 57600, COMBRD_RSA(57600) }, 717 { 115200, COMBRD_RSA(115200) }, 718 { 230400, COMBRD_RSA(230400) }, 719 { 460800, COMBRD_RSA(460800) }, 720 { 921600, COMBRD_RSA(921600) }, 721 { -1, -1 } 722}; 723#endif /* PC98 */ 724 725static struct speedtab comspeedtab[] = { 726 { 0, 0 }, 727 { 50, COMBRD(50) }, 728 { 75, COMBRD(75) }, 729 { 110, COMBRD(110) }, 730 { 134, COMBRD(134) }, 731 { 150, COMBRD(150) }, 732 { 200, COMBRD(200) }, 733 { 300, COMBRD(300) }, 734 { 600, COMBRD(600) }, 735 { 1200, COMBRD(1200) }, 736 { 1800, COMBRD(1800) }, 737 { 2400, COMBRD(2400) }, 738 { 4800, COMBRD(4800) }, 739 { 9600, COMBRD(9600) }, 740 { 19200, COMBRD(19200) }, 741 { 38400, COMBRD(38400) }, 742 { 57600, COMBRD(57600) }, 743 { 115200, COMBRD(115200) }, 744 { -1, -1 } 745}; 746 747#ifdef PC98 748struct { 749 char *name; 750 short port_table[7]; 751 short irr_mask; 752 struct speedtab *speedtab; 753 short check_irq; 754} if_8251_type[] = { 755 /* COM_IF_INTERNAL */ 756 { " (internal)", {0x30, 0x32, 0x32, 0x33, 0x35, -1, -1}, 757 -1, pc98speedtab, 1 }, 758 /* COM_IF_PC9861K_1 */ 759 { " (PC9861K)", {0xb1, 0xb3, 0xb3, 0xb0, 0xb0, -1, -1}, 760 3, NULL, 1 }, 761 /* COM_IF_PC9861K_2 */ 762 { " (PC9861K)", {0xb9, 0xbb, 0xbb, 0xb2, 0xb2, -1, -1}, 763 3, NULL, 1 }, 764 /* COM_IF_IND_SS_1 */ 765 { " (IND-SS)", {0xb1, 0xb3, 0xb3, 0xb0, 0xb0, 0xb3, -1}, 766 3, comspeedtab_mc16550, 1 }, 767 /* COM_IF_IND_SS_2 */ 768 { " (IND-SS)", {0xb9, 0xbb, 0xbb, 0xb2, 0xb2, 0xbb, -1}, 769 3, comspeedtab_mc16550, 1 }, 770 /* COM_IF_PIO9032B_1 */ 771 { " (PIO9032B)", {0xb1, 0xb3, 0xb3, 0xb0, 0xb0, 0xb8, -1}, 772 7, comspeedtab_pio9032b, 1 }, 773 /* COM_IF_PIO9032B_2 */ 774 { " (PIO9032B)", {0xb9, 0xbb, 0xbb, 0xb2, 0xb2, 0xba, -1}, 775 7, comspeedtab_pio9032b, 1 }, 776 /* COM_IF_B98_01_1 */ 777 { " (B98-01)", {0xb1, 0xb3, 0xb3, 0xb0, 0xb0, 0xd1, 0xd3}, 778 7, comspeedtab_b98_01, 0 }, 779 /* COM_IF_B98_01_2 */ 780 { " (B98-01)", {0xb9, 0xbb, 0xbb, 0xb2, 0xb2, 0xd5, 0xd7}, 781 7, comspeedtab_b98_01, 0 }, 782}; 783#define PC98SIO_data_port(type) (if_8251_type[type].port_table[0]) 784#define PC98SIO_cmd_port(type) (if_8251_type[type].port_table[1]) 785#define PC98SIO_sts_port(type) (if_8251_type[type].port_table[2]) 786#define PC98SIO_in_modem_port(type) (if_8251_type[type].port_table[3]) 787#define PC98SIO_intr_ctrl_port(type) (if_8251_type[type].port_table[4]) 788#define PC98SIO_baud_rate_port(type) (if_8251_type[type].port_table[5]) 789#define PC98SIO_func_port(type) (if_8251_type[type].port_table[6]) 790 791#define I8251F_data 0x130 792#define I8251F_lsr 0x132 793#define I8251F_msr 0x134 794#define I8251F_iir 0x136 795#define I8251F_fcr 0x138 796#define I8251F_div 0x13a 797 798 799struct { 800 char *name; 801 short irr_read; 802 short irr_write; 803 short port_shift; 804 short io_size; 805 struct speedtab *speedtab; 806} if_16550a_type[] = { 807 /* COM_IF_RSA98 */ 808 { " (RSA-98)", -1, -1, 0, IO_COMSIZE, comspeedtab }, 809 /* COM_IF_NS16550 */ 810 { "", -1, -1, 0, IO_COMSIZE, comspeedtab }, 811 /* COM_IF_SECOND_CCU */ 812 { "", -1, -1, 0, IO_COMSIZE, comspeedtab }, 813 /* COM_IF_MC16550II */ 814 { " (MC16550II)", -1, 0x1000, 8, 1, comspeedtab_mc16550 }, 815 /* COM_IF_MCRS98 */ 816 { " (MC-RS98)", -1, 0x1000, 8, 1, comspeedtab_mc16550 }, 817 /* COM_IF_RSB3000 */ 818 { " (RSB-3000)", 0xbf, -1, 1, 1, comspeedtab_rsb384 }, 819 /* COM_IF_RSB384 */ 820 { " (RSB-384)", 0xbf, -1, 1, 1, comspeedtab_rsb384 }, 821 /* COM_IF_MODEM_CARD */ 822 { "", -1, -1, 0, IO_COMSIZE, comspeedtab }, 823 /* COM_IF_RSA98III */ 824 { " (RSA-98III)", -1, -1, 0, 16, comspeedtab_rsa }, 825 /* COM_IF_ESP98 */ 826 { " (ESP98)", -1, -1, 1, 1, comspeedtab_mc16550 }, 827}; 828#endif /* PC98 */ 829 830#ifdef COM_ESP 831#ifdef PC98 832 833/* XXX configure this properly. */ 834static Port_t likely_com_ports[] = { 0, 0xb0, 0xb1, 0 }; 835static Port_t likely_esp_ports[] = { 0xc0d0, 0 }; 836 837#define ESP98_CMD1 (ESP_CMD1 * 0x100) 838#define ESP98_CMD2 (ESP_CMD2 * 0x100) 839#define ESP98_STATUS1 (ESP_STATUS1 * 0x100) 840#define ESP98_STATUS2 (ESP_STATUS2 * 0x100) 841 842#else /* PC98 */ 843 844/* XXX configure this properly. */ 845static Port_t likely_com_ports[] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8, }; 846static Port_t likely_esp_ports[] = { 0x140, 0x180, 0x280, 0 }; 847 848#endif /* PC98 */ 849#endif 850 851/* 852 * handle sysctl read/write requests for console speed 853 * 854 * In addition to setting comdefaultrate for I/O through /dev/console, 855 * also set the initial and lock values for the /dev/ttyXX device 856 * if there is one associated with the console. Finally, if the /dev/tty 857 * device has already been open, change the speed on the open running port 858 * itself. 859 */ 860 861static int 862sysctl_machdep_comdefaultrate SYSCTL_HANDLER_ARGS 863{ 864 int error, s; 865 speed_t newspeed; 866 struct com_s *com; 867 struct tty *tp; 868 869 newspeed = comdefaultrate; 870 871 error = sysctl_handle_opaque(oidp, &newspeed, sizeof newspeed, req); 872 if (error || !req->newptr) 873 return (error); 874 875 comdefaultrate = newspeed; 876 877 if (comconsole < 0) /* serial console not selected? */ 878 return (0); 879 880 com = com_addr(comconsole); 881 if (com == NULL) 882 return (ENXIO); 883 884 /* 885 * set the initial and lock rates for /dev/ttydXX and /dev/cuaXX 886 * (note, the lock rates really are boolean -- if non-zero, disallow 887 * speed changes) 888 */ 889 com->it_in.c_ispeed = com->it_in.c_ospeed = 890 com->lt_in.c_ispeed = com->lt_in.c_ospeed = 891 com->it_out.c_ispeed = com->it_out.c_ospeed = 892 com->lt_out.c_ispeed = com->lt_out.c_ospeed = comdefaultrate; 893 894 /* 895 * if we're open, change the running rate too 896 */ 897 tp = com->tp; 898 if (tp && (tp->t_state & TS_ISOPEN)) { 899 tp->t_termios.c_ispeed = 900 tp->t_termios.c_ospeed = comdefaultrate; 901 s = spltty(); 902 error = comparam(tp, &tp->t_termios); 903 splx(s); 904 } 905 return error; 906} 907 908SYSCTL_PROC(_machdep, OID_AUTO, conspeed, CTLTYPE_INT | CTLFLAG_RW, 909 0, 0, sysctl_machdep_comdefaultrate, "I", ""); 910 911#define SET_FLAG(dev, bit) device_set_flags(dev, device_get_flags(dev) | (bit)) 912#define CLR_FLAG(dev, bit) device_set_flags(dev, device_get_flags(dev) & ~(bit)) 913 914#if NCARD > 0 915static int 916sio_pccard_probe(dev) 917 device_t dev; 918{ 919 /* Do not probe IRQ - pccard doesn't turn on the interrupt line */ 920 /* until bus_setup_intr */ 921 SET_FLAG(dev, COM_C_NOPROBE); 922 923 return (sioprobe(dev, 0)); 924} 925 926static int 927sio_pccard_attach(dev) 928 device_t dev; 929{ 930 return (sioattach(dev, 0)); 931} 932 933/* 934 * sio_detach - unload the driver and clear the table. 935 * XXX TODO: 936 * This is usually called when the card is ejected, but 937 * can be caused by a modunload of a controller driver. 938 * The idea is to reset the driver's view of the device 939 * and ensure that any driver entry points such as 940 * read and write do not hang. 941 */ 942static int 943sio_pccard_detach(dev) 944 device_t dev; 945{ 946 struct com_s *com; 947 948 com = (struct com_s *) device_get_softc(dev); 949 if (com == NULL) { 950 device_printf(dev, "NULL com in siounload\n"); 951 return (0); 952 } 953 if (com->iobase == 0) { 954 device_printf(dev, "already unloaded!\n"); 955 return (0); 956 } 957 com->gone = 1; 958 if (com->irqres) { 959 bus_teardown_intr(dev, com->irqres, com->cookie); 960 bus_release_resource(dev, SYS_RES_IRQ, 0, com->irqres); 961 } 962 if (com->ioportres) 963 bus_release_resource(dev, SYS_RES_IOPORT, 0, com->ioportres); 964 if (com->tp && (com->tp->t_state & TS_ISOPEN)) { 965 device_printf(dev, "still open, forcing close\n"); 966 com->tp->t_gen++; 967 ttyclose(com->tp); 968 ttwakeup(com->tp); 969 ttwwakeup(com->tp); 970 } else { 971 if (com->ibuf != NULL) 972 free(com->ibuf, M_DEVBUF); 973 } 974 device_printf(dev, "unloaded\n"); 975 return (0); 976} 977#endif /* NCARD > 0 */ 978 979#if NPCI > 0 980struct pci_ids { 981 u_int32_t type; 982 const char *desc; 983 int rid; 984}; 985 986static struct pci_ids pci_ids[] = { 987 { 0x100812b9, "3COM PCI FaxModem", 0x10 }, 988 { 0x048011c1, "ActionTec 56k FAX PCI Modem", 0x14 }, 989 { 0x00000000, NULL, 0 } 990}; 991 992static int 993sio_pci_attach(dev) 994 device_t dev; 995{ 996 u_int32_t type; 997 struct pci_ids *id; 998 999 type = pci_get_devid(dev); 1000 id = pci_ids; 1001 while (id->type && id->type != type) 1002 id++; 1003 if (id->desc == NULL) 1004 return (ENXIO); 1005 sio_pci_kludge_unit(dev); 1006 return (sioattach(dev, id->rid)); 1007} 1008 1009/* 1010 * Don't cut and paste this to other drivers. It is a horrible kludge 1011 * which will fail to work and also be unnecessary in future versions. 1012 */ 1013static void 1014sio_pci_kludge_unit(dev) 1015 device_t dev; 1016{ 1017 devclass_t dc; 1018 int err; 1019 int start; 1020 int unit; 1021 1022 unit = 0; 1023 start = 0; 1024 while (resource_int_value("sio", unit, "port", &start) == 0 && 1025 start > 0) 1026 unit++; 1027 if (device_get_unit(dev) < unit) { 1028 dc = device_get_devclass(dev); 1029 while (devclass_get_device(dc, unit)) 1030 unit++; 1031 device_printf(dev, "moving to sio%d\n", unit); 1032 err = device_set_unit(dev, unit); /* EVIL DO NOT COPY */ 1033 if (err) 1034 device_printf(dev, "error moving device %d\n", err); 1035 } 1036} 1037 1038static int 1039sio_pci_probe(dev) 1040 device_t dev; 1041{ 1042 u_int32_t type; 1043 struct pci_ids *id; 1044 1045 type = pci_get_devid(dev); 1046 id = pci_ids; 1047 while (id->type && id->type != type) 1048 id++; 1049 if (id->desc == NULL) 1050 return (ENXIO); 1051 device_set_desc(dev, id->desc); 1052 return (sioprobe(dev, id->rid)); 1053} 1054#endif /* NPCI > 0 */ 1055 1056static struct isa_pnp_id sio_ids[] = { 1057 {0x0005d041, "Standard PC COM port"}, /* PNP0500 */ 1058 {0x0105d041, "16550A-compatible COM port"}, /* PNP0501 */ 1059 {0x0205d041, "Multiport serial device (non-intelligent 16550)"}, /* PNP0502 */ 1060 {0x1005d041, "Generic IRDA-compatible device"}, /* PNP0510 */ 1061 {0x1105d041, "Generic IRDA-compatible device"}, /* PNP0511 */ 1062 /* Devices that do not have a compatid */ 1063 {0x7602a904, NULL}, /* AEI0276 - 56K v.90 Fax Modem (LKT) */ 1064 {0x00007905, NULL}, /* AKY0000 - 56K Plug&Play Modem */ 1065 {0x01405407, NULL}, /* AZT4001 - AZT3000 PnP SOUND DEVICE, MODEM */ 1066 {0x56039008, NULL}, /* BDP0356 - Best Data 56x2 */ 1067 {0x36339008, NULL}, /* BDP3336 - Best Data Prods. 336F */ 1068 {0x0014490a, NULL}, /* BRI1400 - Boca 33.6 PnP */ 1069 {0x0015490a, NULL}, /* BRI1500 - Internal Fax Data */ 1070 {0x0034490a, NULL}, /* BRI3400 - Internal ACF Modem */ 1071 {0x00b4490a, NULL}, /* BRIB400 - Boca 56k PnP */ 1072 {0x0030320d, NULL}, /* CIR3000 - Cirrus Logic V43 */ 1073 {0x0100440e, NULL}, /* CRD0001 - Cardinal MVP288IV ? */ 1074 {0x1200c31e, NULL}, /* GVC0012 - VF1128HV-R9 (win modem?) */ 1075 {0x0303c31e, NULL}, /* GVC0303 - MaxTech 33.6 PnP D/F/V */ 1076 {0x0505c31e, NULL}, /* GVC0505 - GVC 56k Faxmodem */ 1077 {0x0050c31e, NULL}, /* GVC5000 - some GVC modem */ 1078 {0x3800f91e, NULL}, /* GWY0038 - Telepath with v.90 */ 1079 {0x9062f91e, NULL}, /* GWY6290 - Telepath with x2 Technology */ 1080 {0x0000f435, NULL}, /* MOT0000 - Motorola ModemSURFR 33.6 Intern */ 1081 {0x5015f435, NULL}, /* MOT1550 - Motorola ModemSURFR 56K Modem */ 1082 {0xf015f435, NULL}, /* MOT15F0 - Motorola VoiceSURFR 56K Modem */ 1083 {0x6045f435, NULL}, /* MOT4560 - Motorola ? */ 1084 {0x61e7a338, NULL}, /* NECE761 - 33.6Modem */ 1085 {0x39804f3f, NULL}, /* OZO8039 - Zoom 56k flex */ 1086 {0x3024a341, NULL}, /* PMC2430 - Pace 56 Voice Internal Modem */ 1087 {0x1000eb49, NULL}, /* ROK0010 - Rockwell ? */ 1088 {0x5002734a, NULL}, /* RSS0250 - 5614Jx3(G) Internal Modem */ 1089 {0xc100ad4d, NULL}, /* SMM00C1 - Leopard 56k PnP */ 1090 {0x9012b04e, NULL}, /* SUP1290 - Supra ? */ 1091 {0x1013b04e, NULL}, /* SUP1310 - SupraExpress 336i PnP */ 1092 {0x8013b04e, NULL}, /* SUP1380 - SupraExpress 288i PnP Voice */ 1093 {0x8113b04e, NULL}, /* SUP1381 - SupraExpress 336i PnP Voice */ 1094 {0x5016b04e, NULL}, /* SUP1650 - Supra 336i Sp Intl */ 1095 {0x7420b04e, NULL}, /* SUP2070 - Supra ? */ 1096 {0x8020b04e, NULL}, /* SUP2080 - Supra ? */ 1097 {0x8420b04e, NULL}, /* SUP2084 - SupraExpress 56i PnP */ 1098 {0x7121b04e, NULL}, /* SUP2171 - SupraExpress 56i Sp? */ 1099 {0x8024b04e, NULL}, /* SUP2480 - Supra ? */ 1100 {0x01007256, NULL}, /* USR0001 - U.S. Robotics Inc., Sportster W */ 1101 {0x02007256, NULL}, /* USR0002 - U.S. Robotics Inc. Sportster 33. */ 1102 {0x04007256, NULL}, /* USR0004 - USR Sportster 14.4k */ 1103 {0x06007256, NULL}, /* USR0006 - USR Sportster 33.6k */ 1104 {0x11007256, NULL}, /* USR0011 - USR ? */ 1105 {0x01017256, NULL}, /* USR0101 - USR ? */ 1106 {0x30207256, NULL}, /* USR2030 - U.S.Robotics Inc. Sportster 560 */ 1107 {0x50207256, NULL}, /* USR2050 - U.S.Robotics Inc. Sportster 33. */ 1108 {0x70207256, NULL}, /* USR2070 - U.S.Robotics Inc. Sportster 560 */ 1109 {0x30307256, NULL}, /* USR3030 - U.S. Robotics 56K FAX INT */ 1110 {0x31307256, NULL}, /* USR3031 - U.S. Robotics 56K FAX INT */ 1111 {0x50307256, NULL}, /* USR3050 - U.S. Robotics 56K FAX INT */ 1112 {0x70307256, NULL}, /* USR3070 - U.S. Robotics 56K Voice INT */ 1113 {0x90307256, NULL}, /* USR3090 - USR ? */ 1114 {0x90917256, NULL}, /* USR9190 - USR 56k Voice INT */ 1115 {0x0300695c, NULL}, /* WCI0003 - Fax/Voice/Modem/Speakphone/Asvd */ 1116 {0x61f7896a, NULL}, /* ZTIF761 - Zoom ComStar 33.6 */ 1117#ifdef PC98 1118 {0x0100e4a5, "RSA-98III"}, 1119#endif 1120 {0} 1121}; 1122 1123 1124 1125static int 1126sio_isa_probe(dev) 1127 device_t dev; 1128{ 1129#ifdef PC98 1130 int logical_id; 1131#endif 1132 /* Check isapnp ids */ 1133 if (ISA_PNP_PROBE(device_get_parent(dev), dev, sio_ids) == ENXIO) 1134 return (ENXIO); 1135#ifdef PC98 1136 logical_id = isa_get_logicalid(dev); 1137 if (logical_id == 0x0100e4a5) /* RSA-98III */ 1138 device_set_flags(dev, COM_IF_RSA98III << 24); 1139#endif 1140 return (sioprobe(dev, 0)); 1141} 1142 1143static int 1144sioprobe(dev, xrid) 1145 device_t dev; 1146 int xrid; 1147{ 1148#if 0 1149 static bool_t already_init; 1150 device_t xdev; 1151#endif 1152 bool_t failures[10]; 1153 int fn; 1154 device_t idev; 1155 Port_t iobase; 1156 intrmask_t irqmap[4]; 1157 intrmask_t irqs; 1158 u_char mcr_image; 1159 int result; 1160 u_long xirq; 1161 u_int flags = device_get_flags(dev); 1162 int rid; 1163 struct resource *port; 1164#ifdef PC98 1165 int irqout=0; 1166 int tmp; 1167 int port_shift = 0; 1168 struct siodev iod; 1169 Port_t rsabase; 1170#endif 1171 1172 rid = xrid; 1173#ifdef PC98 1174 port = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 1175 0, ~0, 1, RF_ACTIVE); /* XXX */ 1176#else 1177 port = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 1178 0, ~0, IO_COMSIZE, RF_ACTIVE); 1179#endif 1180 if (!port) 1181 return (ENXIO); 1182 1183#if 0 1184 /* 1185 * XXX this is broken - when we are first called, there are no 1186 * previously configured IO ports. We could hard code 1187 * 0x3f8, 0x2f8, 0x3e8, 0x2e8 etc but that's probably worse. 1188 * This code has been doing nothing since the conversion since 1189 * "count" is zero the first time around. 1190 */ 1191 if (!already_init) { 1192 /* 1193 * Turn off MCR_IENABLE for all likely serial ports. An unused 1194 * port with its MCR_IENABLE gate open will inhibit interrupts 1195 * from any used port that shares the interrupt vector. 1196 * XXX the gate enable is elsewhere for some multiports. 1197 */ 1198 device_t *devs; 1199 int count, i, xioport; 1200#ifdef PC98 1201 int xiftype; 1202#endif 1203 1204 devclass_get_devices(sio_devclass, &devs, &count); 1205#ifdef PC98 1206 for (i = 0; i < count; i++) { 1207 xdev = devs[i]; 1208 xioport = bus_get_resource_start(xdev, SYS_RES_IOPORT, 0); 1209 xiftype = GET_IFTYPE(device_get_flags(xdev)); 1210 if (device_is_enabled(xdev) && xioport > 0) { 1211 if (IS_8251(xiftype)) 1212 outb(xioport & 0xff00) | PC98SIO_cmd_port(xiftype & 0x0f), 0xf2); 1213 else { 1214 if (xiftype == COM_IF_RSA98III) 1215 xioport += 8; 1216 outb(xioport + (com_mcr << if_16550a_type[xiftype & 0x0f].port_shift), 0); 1217 } 1218 } 1219 } 1220#else 1221 for (i = 0; i < count; i++) { 1222 xdev = devs[i]; 1223 if (device_is_enabled(xdev) && 1224 bus_get_resource(xdev, SYS_RES_IOPORT, 0, &xioport, 1225 NULL) == 0) 1226 outb(xioport + com_mcr, 0); 1227 } 1228#endif 1229 free(devs, M_TEMP); 1230 already_init = TRUE; 1231 } 1232#endif 1233 1234 if (COM_LLCONSOLE(flags)) { 1235 printf("sio%d: reserved for low-level i/o\n", 1236 device_get_unit(dev)); 1237 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 1238 return (ENXIO); 1239 } 1240 1241#ifdef PC98 1242 DELAY(10); 1243 1244 /* 1245 * If the port is i8251 UART (internal, B98_01) 1246 */ 1247 if (pc98_check_if_type(dev, &iod) == -1) 1248 return (ENXIO); 1249 if (iod.irq > 0) 1250 bus_set_resource(dev, SYS_RES_IRQ, 0, iod.irq, 1); 1251 if (IS_8251(iod.if_type)) { 1252 outb(iod.cmd, 0); 1253 DELAY(10); 1254 outb(iod.cmd, 0); 1255 DELAY(10); 1256 outb(iod.cmd, 0); 1257 DELAY(10); 1258 outb(iod.cmd, CMD8251_RESET); 1259 DELAY(1000); /* for a while...*/ 1260 outb(iod.cmd, 0xf2); /* MODE (dummy) */ 1261 DELAY(10); 1262 outb(iod.cmd, 0x01); /* CMD (dummy) */ 1263 DELAY(1000); /* for a while...*/ 1264 if (( inb(iod.sts) & STS8251_TxEMP ) == 0 ) { 1265 result = (ENXIO); 1266 } 1267 if (if_8251_type[iod.if_type & 0x0f].check_irq) { 1268 COM_INT_DISABLE 1269 tmp = ( inb( iod.ctrl ) & ~(IEN_Rx|IEN_TxEMP|IEN_Tx)); 1270 outb( iod.ctrl, tmp|IEN_TxEMP ); 1271 DELAY(10); 1272 result = isa_irq_pending() ? 0 : ENXIO; 1273 outb( iod.ctrl, tmp ); 1274 COM_INT_ENABLE 1275 } else { 1276 /* 1277 * B98_01 doesn't activate TxEMP interrupt line 1278 * when being reset, so we can't check irq pending. 1279 */ 1280 result = 0; 1281 } 1282 if (epson_machine_id==0x20) { /* XXX */ 1283 result = 0; 1284 } 1285 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 1286 return result; 1287 } 1288#endif /* PC98 */ 1289 /* 1290 * If the device is on a multiport card and has an AST/4 1291 * compatible interrupt control register, initialize this 1292 * register and prepare to leave MCR_IENABLE clear in the mcr. 1293 * Otherwise, prepare to set MCR_IENABLE in the mcr. 1294 * Point idev to the device struct giving the correct id_irq. 1295 * This is the struct for the master device if there is one. 1296 */ 1297 idev = dev; 1298 mcr_image = MCR_IENABLE; 1299#ifdef COM_MULTIPORT 1300 if (COM_ISMULTIPORT(flags)) { 1301 Port_t xiobase; 1302 u_long io; 1303 1304 idev = devclass_get_device(sio_devclass, COM_MPMASTER(flags)); 1305 if (idev == NULL) { 1306 printf("sio%d: master device %d not configured\n", 1307 device_get_unit(dev), COM_MPMASTER(flags)); 1308 idev = dev; 1309 } 1310#ifndef PC98 1311 if (!COM_NOTAST4(flags)) { 1312 if (bus_get_resource(idev, SYS_RES_IOPORT, 0, &io, 1313 NULL) == 0) { 1314 xiobase = io; 1315 if (bus_get_resource(idev, SYS_RES_IRQ, 0, 1316 NULL, NULL) == 0) 1317 outb(xiobase + com_scr, 0x80); 1318 else 1319 outb(xiobase + com_scr, 0); 1320 } 1321 mcr_image = 0; 1322 } 1323#endif 1324 } 1325#endif /* COM_MULTIPORT */ 1326 if (bus_get_resource(idev, SYS_RES_IRQ, 0, NULL, NULL) != 0) 1327 mcr_image = 0; 1328 1329 bzero(failures, sizeof failures); 1330 iobase = rman_get_start(port); 1331 1332#ifdef PC98 1333 if (iod.if_type == COM_IF_RSA98III) { 1334 mcr_image = 0; 1335 1336 rsabase = iobase & 0xfff0; 1337 if (rsabase != iobase) 1338 return(0); 1339 iobase += 8; 1340 1341 outb(rsabase + rsa_msr, 0x04); 1342 outb(rsabase + rsa_frr, 0x00); 1343 if ((inb(rsabase + rsa_srr) & 0x36) != 0x36) 1344 return (0); 1345 outb(rsabase + rsa_ier, 0x00); 1346 outb(rsabase + rsa_frr, 0x00); 1347 outb(rsabase + rsa_tivsr, 0x00); 1348 outb(rsabase + rsa_tcr, 0x00); 1349 } 1350 1351 tmp = if_16550a_type[iod.if_type & 0x0f].irr_write; 1352 if (tmp != -1) { 1353 /* MC16550II */ 1354 switch (isa_get_irq(idev)) { 1355 case 3: irqout = 4; break; 1356 case 5: irqout = 5; break; 1357 case 6: irqout = 6; break; 1358 case 12: irqout = 7; break; 1359 default: 1360 printf("sio%d: irq configuration error\n", 1361 device_get_unit(dev)); 1362 return (0); 1363 } 1364 outb((isa_get_port(dev) & 0x00ff) | tmp, irqout); 1365 } 1366 port_shift = if_16550a_type[iod.if_type & 0x0f].port_shift; 1367#endif 1368 1369 /* 1370 * We don't want to get actual interrupts, just masked ones. 1371 * Interrupts from this line should already be masked in the ICU, 1372 * but mask them in the processor as well in case there are some 1373 * (misconfigured) shared interrupts. 1374 */ 1375 disable_intr(); 1376/* EXTRA DELAY? */ 1377 1378 /* 1379 * Initialize the speed and the word size and wait long enough to 1380 * drain the maximum of 16 bytes of junk in device output queues. 1381 * The speed is undefined after a master reset and must be set 1382 * before relying on anything related to output. There may be 1383 * junk after a (very fast) soft reboot and (apparently) after 1384 * master reset. 1385 * XXX what about the UART bug avoided by waiting in comparam()? 1386 * We don't want to to wait long enough to drain at 2 bps. 1387 */ 1388 if (iobase == siocniobase) 1389 DELAY((16 + 1) * 1000000 / (comdefaultrate / 10)); 1390 else { 1391#ifdef PC98 1392 tmp = ttspeedtab(SIO_TEST_SPEED, 1393 if_16550a_type[iod.if_type & 0x0f].speedtab); 1394 outb(iobase + (com_cfcr << port_shift), CFCR_DLAB|CFCR_8BITS); 1395 outb(iobase + (com_dlbl << port_shift), tmp & 0xff); 1396 outb(iobase + (com_dlbh << port_shift), (tmp >> 8) & 0xff); 1397 outb(iobase + (com_cfcr << port_shift), CFCR_8BITS); 1398#else 1399 outb(iobase + com_cfcr, CFCR_DLAB | CFCR_8BITS); 1400 outb(iobase + com_dlbl, COMBRD(SIO_TEST_SPEED) & 0xff); 1401 outb(iobase + com_dlbh, (u_int) COMBRD(SIO_TEST_SPEED) >> 8); 1402 outb(iobase + com_cfcr, CFCR_8BITS); 1403#endif 1404 DELAY((16 + 1) * 1000000 / (SIO_TEST_SPEED / 10)); 1405 } 1406 1407 /* 1408 * Enable the interrupt gate and disable device interupts. This 1409 * should leave the device driving the interrupt line low and 1410 * guarantee an edge trigger if an interrupt can be generated. 1411 */ 1412/* EXTRA DELAY? */ 1413#ifdef PC98 1414 outb(iobase + (com_mcr << port_shift), mcr_image); 1415 outb(iobase + (com_ier << port_shift), 0); 1416#else 1417 outb(iobase + com_mcr, mcr_image); 1418 outb(iobase + com_ier, 0); 1419#endif 1420 DELAY(1000); /* XXX */ 1421 irqmap[0] = isa_irq_pending(); 1422 1423 /* 1424 * Attempt to set loopback mode so that we can send a null byte 1425 * without annoying any external device. 1426 */ 1427/* EXTRA DELAY? */ 1428#ifdef PC98 1429 outb(iobase + (com_mcr << port_shift), mcr_image | MCR_LOOPBACK); 1430#else 1431 outb(iobase + com_mcr, mcr_image | MCR_LOOPBACK); 1432#endif 1433 1434 /* 1435 * Attempt to generate an output interrupt. On 8250's, setting 1436 * IER_ETXRDY generates an interrupt independent of the current 1437 * setting and independent of whether the THR is empty. On 16450's, 1438 * setting IER_ETXRDY generates an interrupt independent of the 1439 * current setting. On 16550A's, setting IER_ETXRDY only 1440 * generates an interrupt when IER_ETXRDY is not already set. 1441 */ 1442#ifdef PC98 1443 outb(iobase + (com_ier << port_shift), IER_ETXRDY); 1444 if (iod.if_type == COM_IF_RSA98III) 1445 outb(rsabase + rsa_ier, 0x04); 1446#else 1447 outb(iobase + com_ier, IER_ETXRDY); 1448#endif /* PC98 */ 1449 1450 /* 1451 * On some 16x50 incompatibles, setting IER_ETXRDY doesn't generate 1452 * an interrupt. They'd better generate one for actually doing 1453 * output. Loopback may be broken on the same incompatibles but 1454 * it's unlikely to do more than allow the null byte out. 1455 */ 1456#ifdef PC98 1457 outb(iobase + (com_data << port_shift), 0); 1458#else 1459 outb(iobase + com_data, 0); 1460#endif 1461 DELAY((1 + 2) * 1000000 / (SIO_TEST_SPEED / 10)); 1462 1463 /* 1464 * Turn off loopback mode so that the interrupt gate works again 1465 * (MCR_IENABLE was hidden). This should leave the device driving 1466 * an interrupt line high. It doesn't matter if the interrupt 1467 * line oscillates while we are not looking at it, since interrupts 1468 * are disabled. 1469 */ 1470/* EXTRA DELAY? */ 1471#ifdef PC98 1472 outb(iobase + (com_mcr << port_shift), mcr_image); 1473#else 1474 outb(iobase + com_mcr, mcr_image); 1475#endif /* PC98 */ 1476 1477 /* 1478 * Some pcmcia cards have the "TXRDY bug", so we check everyone 1479 * for IIR_TXRDY implementation ( Palido 321s, DC-1S... ) 1480 */ 1481 if (COM_NOPROBE(flags)) { 1482 /* Reading IIR register twice */ 1483 for (fn = 0; fn < 2; fn ++) { 1484 DELAY(10000); 1485#ifdef PC98 1486 failures[6] = inb(iobase + (com_iir << port_shift)); 1487#else 1488 failures[6] = inb(iobase + com_iir); 1489#endif 1490 } 1491 /* Check IIR_TXRDY clear ? */ 1492 result = 0; 1493 if (failures[6] & IIR_TXRDY) { 1494 /* Nop, Double check with clearing IER */ 1495#ifdef PC98 1496 outb(iobase + (com_ier << port_shift), 0); 1497 if (inb(iobase + (com_iir << port_shift)) 1498 & IIR_NOPEND) { 1499#else 1500 outb(iobase + com_ier, 0); 1501 if (inb(iobase + com_iir) & IIR_NOPEND) { 1502#endif 1503 /* Ok. we're familia this gang */ 1504 SET_FLAG(dev, COM_C_IIR_TXRDYBUG); 1505 } else { 1506 /* Unknown, Just omit this chip.. XXX */ 1507 result = ENXIO; 1508 } 1509 } else { 1510 /* OK. this is well-known guys */ 1511 CLR_FLAG(dev, COM_C_IIR_TXRDYBUG); 1512 } 1513#ifdef PC98 1514 outb(iobase + (com_cfcr << port_shift), CFCR_8BITS); 1515#else 1516 outb(iobase + com_cfcr, CFCR_8BITS); 1517#endif 1518 enable_intr(); 1519 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 1520 return (iobase == siocniobase ? 0 : result); 1521 } 1522 1523 /* 1524 * Check that 1525 * o the CFCR, IER and MCR in UART hold the values written to them 1526 * (the values happen to be all distinct - this is good for 1527 * avoiding false positive tests from bus echoes). 1528 * o an output interrupt is generated and its vector is correct. 1529 * o the interrupt goes away when the IIR in the UART is read. 1530 */ 1531/* EXTRA DELAY? */ 1532#ifdef PC98 1533 failures[0] = inb(iobase + (com_cfcr << port_shift)) - CFCR_8BITS; 1534 failures[1] = inb(iobase + (com_ier << port_shift)) - IER_ETXRDY; 1535 failures[2] = inb(iobase + (com_mcr << port_shift)) - mcr_image; 1536#else 1537 failures[0] = inb(iobase + com_cfcr) - CFCR_8BITS; 1538 failures[1] = inb(iobase + com_ier) - IER_ETXRDY; 1539 failures[2] = inb(iobase + com_mcr) - mcr_image; 1540#endif 1541 DELAY(10000); /* Some internal modems need this time */ 1542 irqmap[1] = isa_irq_pending(); 1543#ifdef PC98 1544 failures[4] = (inb(iobase + (com_iir << port_shift)) & IIR_IMASK) 1545 - IIR_TXRDY; 1546 if (iod.if_type == COM_IF_RSA98III) 1547 inb(rsabase + rsa_srr); 1548#else 1549 failures[4] = (inb(iobase + com_iir) & IIR_IMASK) - IIR_TXRDY; 1550#endif 1551 DELAY(1000); /* XXX */ 1552 irqmap[2] = isa_irq_pending(); 1553#ifdef PC98 1554 failures[6] = (inb(iobase + (com_iir << port_shift)) & IIR_IMASK) 1555 - IIR_NOPEND; 1556 if (iod.if_type == COM_IF_RSA98III) 1557 inb(rsabase + rsa_srr); 1558#else 1559 failures[6] = (inb(iobase + com_iir) & IIR_IMASK) - IIR_NOPEND; 1560#endif 1561 1562 /* 1563 * Turn off all device interrupts and check that they go off properly. 1564 * Leave MCR_IENABLE alone. For ports without a master port, it gates 1565 * the OUT2 output of the UART to 1566 * the ICU input. Closing the gate would give a floating ICU input 1567 * (unless there is another device driving it) and spurious interrupts. 1568 * (On the system that this was first tested on, the input floats high 1569 * and gives a (masked) interrupt as soon as the gate is closed.) 1570 */ 1571#ifdef PC98 1572 outb(iobase + (com_ier << port_shift), 0); 1573 outb(iobase + (com_cfcr << port_shift), CFCR_8BITS); 1574 failures[7] = inb(iobase + (com_ier << port_shift)); 1575 if (iod.if_type == COM_IF_RSA98III) 1576 outb(rsabase + rsa_ier, 0x00); 1577#else 1578 outb(iobase + com_ier, 0); 1579 outb(iobase + com_cfcr, CFCR_8BITS); /* dummy to avoid bus echo */ 1580 failures[7] = inb(iobase + com_ier); 1581#endif 1582 DELAY(1000); /* XXX */ 1583 irqmap[3] = isa_irq_pending(); 1584#ifdef PC98 1585 failures[9] = (inb(iobase + (com_iir << port_shift)) & IIR_IMASK) 1586 - IIR_NOPEND; 1587 if (iod.if_type == COM_IF_RSA98III) { 1588 inb(rsabase + rsa_srr); 1589 outb(rsabase + rsa_frr, 0x00); 1590 } 1591#else 1592 failures[9] = (inb(iobase + com_iir) & IIR_IMASK) - IIR_NOPEND; 1593#endif 1594 1595 enable_intr(); 1596 1597 irqs = irqmap[1] & ~irqmap[0]; 1598 if (bus_get_resource(idev, SYS_RES_IRQ, 0, &xirq, NULL) == 0 && 1599 ((1 << xirq) & irqs) == 0) 1600 printf( 1601 "sio%d: configured irq %ld not in bitmap of probed irqs %#x\n", 1602 device_get_unit(dev), xirq, irqs); 1603 if (bootverbose) 1604 printf("sio%d: irq maps: %#x %#x %#x %#x\n", 1605 device_get_unit(dev), 1606 irqmap[0], irqmap[1], irqmap[2], irqmap[3]); 1607 1608 result = 0; 1609 for (fn = 0; fn < sizeof failures; ++fn) 1610 if (failures[fn]) { 1611#ifdef PC98 1612 outb(iobase + (com_mcr << port_shift), 0); 1613#else 1614 outb(iobase + com_mcr, 0); 1615#endif 1616 result = ENXIO; 1617 if (bootverbose) { 1618 printf("sio%d: probe failed test(s):", 1619 device_get_unit(dev)); 1620 for (fn = 0; fn < sizeof failures; ++fn) 1621 if (failures[fn]) 1622 printf(" %d", fn); 1623 printf("\n"); 1624 } 1625 break; 1626 } 1627 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 1628 return (iobase == siocniobase ? 0 : result); 1629} 1630 1631#ifdef COM_ESP 1632static int 1633espattach(com, esp_port) 1634 struct com_s *com; 1635 Port_t esp_port; 1636{ 1637 u_char dips; 1638 u_char val; 1639 1640 /* 1641 * Check the ESP-specific I/O port to see if we're an ESP 1642 * card. If not, return failure immediately. 1643 */ 1644 if ((inb(esp_port) & 0xf3) == 0) { 1645 printf(" port 0x%x is not an ESP board?\n", esp_port); 1646 return (0); 1647 } 1648 1649 /* 1650 * We've got something that claims to be a Hayes ESP card. 1651 * Let's hope so. 1652 */ 1653 1654 /* Get the dip-switch configuration */ 1655#ifdef PC98 1656 outb(esp_port + ESP98_CMD1, ESP_GETDIPS); 1657 dips = inb(esp_port + ESP98_STATUS1); 1658#else 1659 outb(esp_port + ESP_CMD1, ESP_GETDIPS); 1660 dips = inb(esp_port + ESP_STATUS1); 1661#endif 1662 1663 /* 1664 * Bits 0,1 of dips say which COM port we are. 1665 */ 1666#ifdef PC98 1667 if ((com->iobase & 0xff) == likely_com_ports[dips & 0x03]) 1668#else 1669 if (com->iobase == likely_com_ports[dips & 0x03]) 1670#endif 1671 printf(" : ESP"); 1672 else { 1673 printf(" esp_port has com %d\n", dips & 0x03); 1674 return (0); 1675 } 1676 1677 /* 1678 * Check for ESP version 2.0 or later: bits 4,5,6 = 010. 1679 */ 1680#ifdef PC98 1681 outb(esp_port + ESP98_CMD1, ESP_GETTEST); 1682 val = inb(esp_port + ESP98_STATUS1); /* clear reg 1 */ 1683 val = inb(esp_port + ESP98_STATUS2); 1684#else 1685 outb(esp_port + ESP_CMD1, ESP_GETTEST); 1686 val = inb(esp_port + ESP_STATUS1); /* clear reg 1 */ 1687 val = inb(esp_port + ESP_STATUS2); 1688#endif 1689 if ((val & 0x70) < 0x20) { 1690 printf("-old (%o)", val & 0x70); 1691 return (0); 1692 } 1693 1694 /* 1695 * Check for ability to emulate 16550: bit 7 == 1 1696 */ 1697 if ((dips & 0x80) == 0) { 1698 printf(" slave"); 1699 return (0); 1700 } 1701 1702 /* 1703 * Okay, we seem to be a Hayes ESP card. Whee. 1704 */ 1705 com->esp = TRUE; 1706 com->esp_port = esp_port; 1707 return (1); 1708} 1709#endif /* COM_ESP */ 1710 1711static int 1712sio_isa_attach(dev) 1713 device_t dev; 1714{ 1715 return (sioattach(dev, 0)); 1716} 1717 1718static int 1719sioattach(dev, xrid) 1720 device_t dev; 1721 int xrid; 1722{ 1723 struct com_s *com; 1724#ifdef COM_ESP 1725 Port_t *espp; 1726#endif 1727 Port_t iobase; 1728 int unit; 1729 u_int flags; 1730 int rid; 1731 struct resource *port; 1732 int ret; 1733#ifdef PC98 1734 int port_shift = 0; 1735 u_char *obuf; 1736 u_long obufsize; 1737#endif 1738 1739 rid = xrid; 1740#ifdef PC98 1741 port = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 1742 0, ~0, 1, RF_ACTIVE); /* XXX */ 1743#else 1744 port = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 1745 0, ~0, IO_COMSIZE, RF_ACTIVE); 1746#endif 1747 if (!port) 1748 return (ENXIO); 1749 1750 iobase = rman_get_start(port); 1751 unit = device_get_unit(dev); 1752 com = device_get_softc(dev); 1753 flags = device_get_flags(dev); 1754 1755 if (unit >= sio_numunits) 1756 sio_numunits = unit + 1; 1757 1758#ifdef PC98 1759 obufsize = 256; 1760 if (GET_IFTYPE(flags) == COM_IF_RSA98III) { 1761 iobase += 8; 1762 obufsize = 2048; 1763 } 1764 if ((obuf = malloc(obufsize * 2, M_DEVBUF, M_NOWAIT)) == NULL) 1765 return ENXIO; 1766 bzero(obuf, obufsize * 2); 1767#endif 1768 1769 /* 1770 * sioprobe() has initialized the device registers as follows: 1771 * o cfcr = CFCR_8BITS. 1772 * It is most important that CFCR_DLAB is off, so that the 1773 * data port is not hidden when we enable interrupts. 1774 * o ier = 0. 1775 * Interrupts are only enabled when the line is open. 1776 * o mcr = MCR_IENABLE, or 0 if the port has AST/4 compatible 1777 * interrupt control register or the config specifies no irq. 1778 * Keeping MCR_DTR and MCR_RTS off might stop the external 1779 * device from sending before we are ready. 1780 */ 1781 bzero(com, sizeof *com); 1782#ifdef PC98 1783 com->obufsize = obufsize; 1784 com->obuf1 = obuf; 1785 com->obuf2 = obuf + obufsize; 1786#endif 1787 com->unit = unit; 1788 com->ioportres = port; 1789 com->cfcr_image = CFCR_8BITS; 1790 com->dtr_wait = 3 * hz; 1791 com->loses_outints = COM_LOSESOUTINTS(flags) != 0; 1792 com->no_irq = bus_get_resource(dev, SYS_RES_IRQ, 0, NULL, NULL) != 0; 1793 com->tx_fifo_size = 1; 1794 com->obufs[0].l_head = com->obuf1; 1795 com->obufs[1].l_head = com->obuf2; 1796 1797 com->iobase = iobase; 1798#ifdef PC98 1799 com->pc98_if_type = GET_IFTYPE(flags); 1800 1801 if (pc98_set_ioport(com) == -1) { 1802 port_shift = if_16550a_type[com->pc98_if_type & 0x0f].port_shift; 1803 1804 com->data_port = iobase + (com_data << port_shift); 1805 com->int_id_port = iobase + (com_iir << port_shift); 1806 com->modem_ctl_port = iobase + (com_mcr << port_shift); 1807 com->mcr_image = inb(com->modem_ctl_port); 1808 com->line_status_port = iobase + (com_lsr << port_shift); 1809 com->modem_status_port = iobase + (com_msr << port_shift); 1810 com->intr_ctl_port = iobase + (com_ier << port_shift); 1811 } 1812 if (com->pc98_if_type == COM_IF_INTERNAL && pc98_check_8251fifo()) { 1813 com->pc98_8251fifo = 1; 1814 com->pc98_8251fifo_enable = 0; 1815 } 1816#else /* not PC98 */ 1817 com->data_port = iobase + com_data; 1818 com->int_id_port = iobase + com_iir; 1819 com->modem_ctl_port = iobase + com_mcr; 1820 com->mcr_image = inb(com->modem_ctl_port); 1821 com->line_status_port = iobase + com_lsr; 1822 com->modem_status_port = iobase + com_msr; 1823 com->intr_ctl_port = iobase + com_ier; 1824#endif 1825 1826 /* 1827 * We don't use all the flags from <sys/ttydefaults.h> since they 1828 * are only relevant for logins. It's important to have echo off 1829 * initially so that the line doesn't start blathering before the 1830 * echo flag can be turned off. 1831 */ 1832 com->it_in.c_iflag = 0; 1833 com->it_in.c_oflag = 0; 1834 com->it_in.c_cflag = TTYDEF_CFLAG; 1835 com->it_in.c_lflag = 0; 1836 if (unit == comconsole) { 1837#ifdef PC98 1838 if (IS_8251(com->pc98_if_type)) 1839 DELAY(100000); 1840#endif 1841 com->it_in.c_iflag = TTYDEF_IFLAG; 1842 com->it_in.c_oflag = TTYDEF_OFLAG; 1843 com->it_in.c_cflag = TTYDEF_CFLAG | CLOCAL; 1844 com->it_in.c_lflag = TTYDEF_LFLAG; 1845 com->lt_out.c_cflag = com->lt_in.c_cflag = CLOCAL; 1846 com->lt_out.c_ispeed = com->lt_out.c_ospeed = 1847 com->lt_in.c_ispeed = com->lt_in.c_ospeed = 1848 com->it_in.c_ispeed = com->it_in.c_ospeed = comdefaultrate; 1849 } else 1850 com->it_in.c_ispeed = com->it_in.c_ospeed = TTYDEF_SPEED; 1851 if (siosetwater(com, com->it_in.c_ispeed) != 0) { 1852 enable_intr(); 1853 /* 1854 * Leave i/o resources allocated if this is a `cn'-level 1855 * console, so that other devices can't snarf them. 1856 */ 1857 if (iobase != siocniobase) 1858 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 1859 return (ENOMEM); 1860 } 1861 enable_intr(); 1862 termioschars(&com->it_in); 1863 com->it_out = com->it_in; 1864 1865 /* attempt to determine UART type */ 1866 printf("sio%d: type", unit); 1867 1868 1869#ifndef PC98 1870#ifdef COM_MULTIPORT 1871 if (!COM_ISMULTIPORT(flags) && !COM_IIR_TXRDYBUG(flags)) 1872#else 1873 if (!COM_IIR_TXRDYBUG(flags)) 1874#endif 1875 { 1876 u_char scr; 1877 u_char scr1; 1878 u_char scr2; 1879 1880 scr = inb(iobase + com_scr); 1881 outb(iobase + com_scr, 0xa5); 1882 scr1 = inb(iobase + com_scr); 1883 outb(iobase + com_scr, 0x5a); 1884 scr2 = inb(iobase + com_scr); 1885 outb(iobase + com_scr, scr); 1886 if (scr1 != 0xa5 || scr2 != 0x5a) { 1887 printf(" 8250"); 1888 goto determined_type; 1889 } 1890 } 1891#endif /* !PC98 */ 1892#ifdef PC98 1893 if (IS_8251(com->pc98_if_type)) { 1894 if (com->pc98_8251fifo && !COM_NOFIFO(flags)) 1895 com->tx_fifo_size = 16; 1896 com_int_TxRx_disable( com ); 1897 com_cflag_and_speed_set( com, com->it_in.c_cflag, comdefaultrate ); 1898 com_tiocm_bic( com, TIOCM_DTR|TIOCM_RTS|TIOCM_LE ); 1899 com_send_break_off( com ); 1900 1901 if (com->pc98_if_type == COM_IF_INTERNAL) { 1902 printf(" (internal%s%s)", 1903 com->pc98_8251fifo ? " fifo" : "", 1904 PC98SIO_baud_rate_port(com->pc98_if_type) != -1 ? 1905 " v-fast" : ""); 1906 } else { 1907 printf(" 8251%s", if_8251_type[com->pc98_if_type & 0x0f].name); 1908 } 1909 } else { 1910 outb(iobase + (com_fifo << port_shift), FIFO_ENABLE | FIFO_RX_HIGH); 1911#else 1912 outb(iobase + com_fifo, FIFO_ENABLE | FIFO_RX_HIGH); 1913#endif /* PC98 */ 1914 DELAY(100); 1915 com->st16650a = 0; 1916 switch (inb(com->int_id_port) & IIR_FIFO_MASK) { 1917 case FIFO_RX_LOW: 1918 printf(" 16450"); 1919 break; 1920 case FIFO_RX_MEDL: 1921 printf(" 16450?"); 1922 break; 1923 case FIFO_RX_MEDH: 1924 printf(" 16550?"); 1925 break; 1926 case FIFO_RX_HIGH: 1927 if (COM_NOFIFO(flags)) { 1928 printf(" 16550A fifo disabled"); 1929 } else { 1930 com->hasfifo = TRUE; 1931#ifdef PC98 1932 com->tx_fifo_size = 0; /* XXX flag conflicts. */ 1933 printf(" 16550A"); 1934#else 1935 if (COM_ST16650A(flags)) { 1936 com->st16650a = 1; 1937 com->tx_fifo_size = 32; 1938 printf(" ST16650A"); 1939 } else { 1940 com->tx_fifo_size = COM_FIFOSIZE(flags); 1941 printf(" 16550A"); 1942 } 1943#endif 1944 } 1945#ifdef PC98 1946 if (com->pc98_if_type == COM_IF_RSA98III) { 1947 com->tx_fifo_size = 2048; 1948 com->rsabase = isa_get_port(dev); 1949 outb(com->rsabase + rsa_ier, 0x00); 1950 outb(com->rsabase + rsa_frr, 0x00); 1951 } 1952#endif 1953 1954#ifdef COM_ESP 1955#ifdef PC98 1956 if (com->pc98_if_type == COM_IF_ESP98) 1957#endif 1958 for (espp = likely_esp_ports; *espp != 0; espp++) 1959 if (espattach(com, *espp)) { 1960 com->tx_fifo_size = 1024; 1961 break; 1962 } 1963#endif 1964 if (!com->st16650a) { 1965 if (!com->tx_fifo_size) 1966 com->tx_fifo_size = 16; 1967 else 1968 printf(" lookalike with %d bytes FIFO", 1969 com->tx_fifo_size); 1970 } 1971 1972 break; 1973 } 1974 1975#ifdef PC98 1976 if (com->pc98_if_type == COM_IF_RSB3000) { 1977 /* Set RSB-2000/3000 Extended Buffer mode. */ 1978 u_char lcr; 1979 lcr = inb(iobase + (com_cfcr << port_shift)); 1980 outb(iobase + (com_cfcr << port_shift), lcr | CFCR_DLAB); 1981 outb(iobase + (com_emr << port_shift), EMR_EXBUFF | EMR_EFMODE); 1982 outb(iobase + (com_cfcr << port_shift), lcr); 1983 } 1984#endif 1985 1986#ifdef COM_ESP 1987 if (com->esp) { 1988 /* 1989 * Set 16550 compatibility mode. 1990 * We don't use the ESP_MODE_SCALE bit to increase the 1991 * fifo trigger levels because we can't handle large 1992 * bursts of input. 1993 * XXX flow control should be set in comparam(), not here. 1994 */ 1995#ifdef PC98 1996 outb(com->esp_port + ESP98_CMD1, ESP_SETMODE); 1997 outb(com->esp_port + ESP98_CMD2, ESP_MODE_RTS | ESP_MODE_FIFO); 1998#else 1999 outb(com->esp_port + ESP_CMD1, ESP_SETMODE); 2000 outb(com->esp_port + ESP_CMD2, ESP_MODE_RTS | ESP_MODE_FIFO); 2001#endif 2002 2003 /* Set RTS/CTS flow control. */ 2004#ifdef PC98 2005 outb(com->esp_port + ESP98_CMD1, ESP_SETFLOWTYPE); 2006 outb(com->esp_port + ESP98_CMD2, ESP_FLOW_RTS); 2007 outb(com->esp_port + ESP98_CMD2, ESP_FLOW_CTS); 2008#else 2009 outb(com->esp_port + ESP_CMD1, ESP_SETFLOWTYPE); 2010 outb(com->esp_port + ESP_CMD2, ESP_FLOW_RTS); 2011 outb(com->esp_port + ESP_CMD2, ESP_FLOW_CTS); 2012#endif 2013 2014 /* Set flow-control levels. */ 2015#ifdef PC98 2016 outb(com->esp_port + ESP98_CMD1, ESP_SETRXFLOW); 2017 outb(com->esp_port + ESP98_CMD2, HIBYTE(768)); 2018 outb(com->esp_port + ESP98_CMD2, LOBYTE(768)); 2019 outb(com->esp_port + ESP98_CMD2, HIBYTE(512)); 2020 outb(com->esp_port + ESP98_CMD2, LOBYTE(512)); 2021#else 2022 outb(com->esp_port + ESP_CMD1, ESP_SETRXFLOW); 2023 outb(com->esp_port + ESP_CMD2, HIBYTE(768)); 2024 outb(com->esp_port + ESP_CMD2, LOBYTE(768)); 2025 outb(com->esp_port + ESP_CMD2, HIBYTE(512)); 2026 outb(com->esp_port + ESP_CMD2, LOBYTE(512)); 2027#endif 2028 2029#ifdef PC98 2030 /* Set UART clock prescaler. */ 2031 outb(com->esp_port + ESP98_CMD1, ESP_SETCLOCK); 2032 outb(com->esp_port + ESP98_CMD2, 2); /* 4 times */ 2033#endif 2034 } 2035#endif /* COM_ESP */ 2036#ifdef PC98 2037 printf("%s", if_16550a_type[com->pc98_if_type & 0x0f].name); 2038 outb(iobase + (com_fifo << port_shift), 0); 2039#else 2040 outb(iobase + com_fifo, 0); 2041determined_type: ; 2042#endif 2043 2044#ifdef COM_MULTIPORT 2045 if (COM_ISMULTIPORT(flags)) { 2046 device_t masterdev; 2047 2048 com->multiport = TRUE; 2049 printf(" (multiport"); 2050 if (unit == COM_MPMASTER(flags)) 2051 printf(" master"); 2052 printf(")"); 2053 masterdev = devclass_get_device(sio_devclass, 2054 COM_MPMASTER(flags)); 2055 com->no_irq = (masterdev == NULL || bus_get_resource(masterdev, 2056 SYS_RES_IRQ, 0, NULL, NULL) != 0); 2057 } 2058#endif /* COM_MULTIPORT */ 2059#ifdef PC98 2060 } 2061#endif 2062 if (unit == comconsole) 2063 printf(", console"); 2064 if (COM_IIR_TXRDYBUG(flags)) 2065 printf(" with a bogus IIR_TXRDY register"); 2066 printf("\n"); 2067 2068 if (!sio_registered) { 2069 register_swi(SWI_TTY, siopoll); 2070 sio_registered = TRUE; 2071 } 2072 make_dev(&sio_cdevsw, unit, 2073 UID_ROOT, GID_WHEEL, 0600, "ttyd%r", unit); 2074 make_dev(&sio_cdevsw, unit | CONTROL_INIT_STATE, 2075 UID_ROOT, GID_WHEEL, 0600, "ttyid%r", unit); 2076 make_dev(&sio_cdevsw, unit | CONTROL_LOCK_STATE, 2077 UID_ROOT, GID_WHEEL, 0600, "ttyld%r", unit); 2078 make_dev(&sio_cdevsw, unit | CALLOUT_MASK, 2079 UID_UUCP, GID_DIALER, 0660, "cuaa%r", unit); 2080 make_dev(&sio_cdevsw, unit | CALLOUT_MASK | CONTROL_INIT_STATE, 2081 UID_UUCP, GID_DIALER, 0660, "cuaia%r", unit); 2082 make_dev(&sio_cdevsw, unit | CALLOUT_MASK | CONTROL_LOCK_STATE, 2083 UID_UUCP, GID_DIALER, 0660, "cuala%r", unit); 2084 com->flags = flags; 2085 com->pps.ppscap = PPS_CAPTUREASSERT | PPS_CAPTURECLEAR; 2086 pps_init(&com->pps); 2087 2088 rid = 0; 2089 com->irqres = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0ul, ~0ul, 1, 2090 RF_ACTIVE); 2091 if (com->irqres) { 2092 ret = BUS_SETUP_INTR(device_get_parent(dev), dev, com->irqres, 2093 INTR_TYPE_TTY | INTR_TYPE_FAST, 2094 siointr, com, &com->cookie); 2095 if (ret) { 2096 ret = BUS_SETUP_INTR(device_get_parent(dev), dev, 2097 com->irqres, INTR_TYPE_TTY, 2098 siointr, com, &com->cookie); 2099 if (ret == 0) 2100 device_printf(dev, "unable to activate interrupt in fast mode - using normal mode"); 2101 } 2102 if (ret) 2103 device_printf(dev, "could not activate interrupt\n"); 2104 } 2105 2106 return (0); 2107} 2108 2109static int 2110sioopen(dev, flag, mode, p) 2111 dev_t dev; 2112 int flag; 2113 int mode; 2114 struct proc *p; 2115{ 2116 struct com_s *com; 2117 int error; 2118 Port_t iobase; 2119 int mynor; 2120 int s; 2121 struct tty *tp; 2122 int unit; 2123#ifdef PC98 2124 int port_shift = 0; 2125#endif 2126 2127 mynor = minor(dev); 2128 unit = MINOR_TO_UNIT(mynor); 2129 com = com_addr(unit); 2130 if (com == NULL) 2131 return (ENXIO); 2132 if (com->gone) 2133 return (ENXIO); 2134 if (mynor & CONTROL_MASK) 2135 return (0); 2136 tp = dev->si_tty = com->tp = ttymalloc(com->tp); 2137 s = spltty(); 2138 2139#ifdef PC98 2140 if (!IS_8251(com->pc98_if_type)) 2141 port_shift = if_16550a_type[com->pc98_if_type & 0x0f].port_shift; 2142#endif 2143 /* 2144 * We jump to this label after all non-interrupted sleeps to pick 2145 * up any changes of the device state. 2146 */ 2147open_top: 2148 while (com->state & CS_DTR_OFF) { 2149 error = tsleep(&com->dtr_wait, TTIPRI | PCATCH, "siodtr", 0); 2150 if (com_addr(unit) == NULL) 2151 return (ENXIO); 2152 if (error != 0 || com->gone) 2153 goto out; 2154 } 2155 if (tp->t_state & TS_ISOPEN) { 2156 /* 2157 * The device is open, so everything has been initialized. 2158 * Handle conflicts. 2159 */ 2160 if (mynor & CALLOUT_MASK) { 2161 if (!com->active_out) { 2162 error = EBUSY; 2163 goto out; 2164 } 2165 } else { 2166 if (com->active_out) { 2167 if (flag & O_NONBLOCK) { 2168 error = EBUSY; 2169 goto out; 2170 } 2171 error = tsleep(&com->active_out, 2172 TTIPRI | PCATCH, "siobi", 0); 2173 if (com_addr(unit) == NULL) 2174 return (ENXIO); 2175 if (error != 0 || com->gone) 2176 goto out; 2177 goto open_top; 2178 } 2179 } 2180 if (tp->t_state & TS_XCLUDE && 2181 suser(p)) { 2182 error = EBUSY; 2183 goto out; 2184 } 2185 } else { 2186 /* 2187 * The device isn't open, so there are no conflicts. 2188 * Initialize it. Initialization is done twice in many 2189 * cases: to preempt sleeping callin opens if we are 2190 * callout, and to complete a callin open after DCD rises. 2191 */ 2192 tp->t_oproc = comstart; 2193 tp->t_param = comparam; 2194 tp->t_stop = comstop; 2195 tp->t_dev = dev; 2196 tp->t_termios = mynor & CALLOUT_MASK 2197 ? com->it_out : com->it_in; 2198#ifdef PC98 2199 if (!IS_8251(com->pc98_if_type)) 2200#endif 2201 (void)commctl(com, TIOCM_DTR | TIOCM_RTS, DMSET); 2202 com->poll = com->no_irq; 2203 com->poll_output = com->loses_outints; 2204 ++com->wopeners; 2205 error = comparam(tp, &tp->t_termios); 2206 --com->wopeners; 2207 if (error != 0) 2208 goto out; 2209#ifdef PC98 2210 if (IS_8251(com->pc98_if_type)) { 2211 com_tiocm_bis(com, TIOCM_DTR|TIOCM_RTS); 2212 pc98_msrint_start(dev); 2213 if (com->pc98_8251fifo) { 2214 com->pc98_8251fifo_enable = 1; 2215 outb(I8251F_fcr, CTRL8251F_ENABLE | 2216 CTRL8251F_XMT_RST | CTRL8251F_RCV_RST); 2217 } 2218 } 2219#endif 2220 /* 2221 * XXX we should goto open_top if comparam() slept. 2222 */ 2223 iobase = com->iobase; 2224 if (com->hasfifo) { 2225 /* 2226 * (Re)enable and drain fifos. 2227 * 2228 * Certain SMC chips cause problems if the fifos 2229 * are enabled while input is ready. Turn off the 2230 * fifo if necessary to clear the input. We test 2231 * the input ready bit after enabling the fifos 2232 * since we've already enabled them in comparam() 2233 * and to handle races between enabling and fresh 2234 * input. 2235 */ 2236 while (TRUE) { 2237#ifdef PC98 2238 outb(iobase + (com_fifo << port_shift), 2239 FIFO_RCV_RST | FIFO_XMT_RST 2240 | com->fifo_image); 2241 if (com->pc98_if_type == COM_IF_RSA98III) 2242 outb(com->rsabase + rsa_frr , 0x00); 2243#else 2244 outb(iobase + com_fifo, 2245 FIFO_RCV_RST | FIFO_XMT_RST 2246 | com->fifo_image); 2247#endif 2248 /* 2249 * XXX the delays are for superstitious 2250 * historical reasons. It must be less than 2251 * the character time at the maximum 2252 * supported speed (87 usec at 115200 bps 2253 * 8N1). Otherwise we might loop endlessly 2254 * if data is streaming in. We used to use 2255 * delays of 100. That usually worked 2256 * because DELAY(100) used to usually delay 2257 * for about 85 usec instead of 100. 2258 */ 2259 DELAY(50); 2260#ifndef PC98 2261 if (!(inb(com->line_status_port) & LSR_RXRDY)) 2262#else 2263 if (com->pc98_if_type == COM_IF_RSA98III 2264 ? !(inb(com->rsabase + rsa_srr) & 0x08) 2265 : !(inb(com->line_status_port) & LSR_RXRDY)) 2266#endif 2267 break; 2268#ifdef PC98 2269 outb(iobase + (com_fifo << port_shift), 0); 2270#else 2271 outb(iobase + com_fifo, 0); 2272#endif 2273 DELAY(50); 2274 (void) inb(com->data_port); 2275 } 2276 } 2277 2278 disable_intr(); 2279#ifdef PC98 2280 if (IS_8251(com->pc98_if_type)) { 2281 com_tiocm_bis(com, TIOCM_LE); 2282 com->pc98_prev_modem_status = pc98_get_modem_status(com); 2283 com_int_Rx_enable(com); 2284 } else { 2285#endif 2286 (void) inb(com->line_status_port); 2287 (void) inb(com->data_port); 2288 com->prev_modem_status = com->last_modem_status 2289 = inb(com->modem_status_port); 2290 if (COM_IIR_TXRDYBUG(com->flags)) { 2291 outb(com->intr_ctl_port, IER_ERXRDY | IER_ERLS 2292 | IER_EMSC); 2293 } else { 2294 outb(com->intr_ctl_port, IER_ERXRDY | IER_ETXRDY 2295 | IER_ERLS | IER_EMSC); 2296 } 2297#ifdef PC98 2298 if (com->pc98_if_type == COM_IF_RSA98III) { 2299 outb(com->rsabase + rsa_ier, 0x1d); 2300 outb(com->intr_ctl_port, IER_ERLS | IER_EMSC); 2301 } 2302#endif 2303#ifdef PC98 2304 } 2305#endif 2306 enable_intr(); 2307 /* 2308 * Handle initial DCD. Callout devices get a fake initial 2309 * DCD (trapdoor DCD). If we are callout, then any sleeping 2310 * callin opens get woken up and resume sleeping on "siobi" 2311 * instead of "siodcd". 2312 */ 2313 /* 2314 * XXX `mynor & CALLOUT_MASK' should be 2315 * `tp->t_cflag & (SOFT_CARRIER | TRAPDOOR_CARRIER) where 2316 * TRAPDOOR_CARRIER is the default initial state for callout 2317 * devices and SOFT_CARRIER is like CLOCAL except it hides 2318 * the true carrier. 2319 */ 2320#ifdef PC98 2321 if ((IS_8251(com->pc98_if_type) && 2322 (pc98_get_modem_status(com) & TIOCM_CAR)) || 2323 (!IS_8251(com->pc98_if_type) && 2324 (com->prev_modem_status & MSR_DCD)) || 2325 mynor & CALLOUT_MASK) 2326#else 2327 if (com->prev_modem_status & MSR_DCD || mynor & CALLOUT_MASK) 2328#endif 2329 (*linesw[tp->t_line].l_modem)(tp, 1); 2330 } 2331 /* 2332 * Wait for DCD if necessary. 2333 */ 2334 if (!(tp->t_state & TS_CARR_ON) && !(mynor & CALLOUT_MASK) 2335 && !(tp->t_cflag & CLOCAL) && !(flag & O_NONBLOCK)) { 2336 ++com->wopeners; 2337 error = tsleep(TSA_CARR_ON(tp), TTIPRI | PCATCH, "siodcd", 0); 2338 if (com_addr(unit) == NULL) 2339 return (ENXIO); 2340 --com->wopeners; 2341 if (error != 0 || com->gone) 2342 goto out; 2343 goto open_top; 2344 } 2345 error = (*linesw[tp->t_line].l_open)(dev, tp); 2346 disc_optim(tp, &tp->t_termios, com); 2347 if (tp->t_state & TS_ISOPEN && mynor & CALLOUT_MASK) 2348 com->active_out = TRUE; 2349 siosettimeout(); 2350out: 2351 splx(s); 2352 if (!(tp->t_state & TS_ISOPEN) && com->wopeners == 0) 2353 comhardclose(com); 2354 return (error); 2355} 2356 2357static int 2358sioclose(dev, flag, mode, p) 2359 dev_t dev; 2360 int flag; 2361 int mode; 2362 struct proc *p; 2363{ 2364 struct com_s *com; 2365 int mynor; 2366 int s; 2367 struct tty *tp; 2368 2369 mynor = minor(dev); 2370 if (mynor & CONTROL_MASK) 2371 return (0); 2372 com = com_addr(MINOR_TO_UNIT(mynor)); 2373 if (com == NULL) 2374 return (ENODEV); 2375 tp = com->tp; 2376 s = spltty(); 2377 (*linesw[tp->t_line].l_close)(tp, flag); 2378#ifdef PC98 2379 com->modem_checking = 0; 2380#endif 2381 disc_optim(tp, &tp->t_termios, com); 2382 comstop(tp, FREAD | FWRITE); 2383 comhardclose(com); 2384 ttyclose(tp); 2385 siosettimeout(); 2386 splx(s); 2387 if (com->gone) { 2388 printf("sio%d: gone\n", com->unit); 2389 s = spltty(); 2390 if (com->ibuf != NULL) 2391 free(com->ibuf, M_DEVBUF); 2392 bzero(tp, sizeof *tp); 2393 splx(s); 2394 } 2395 return (0); 2396} 2397 2398static void 2399comhardclose(com) 2400 struct com_s *com; 2401{ 2402 Port_t iobase; 2403 int s; 2404 struct tty *tp; 2405 int unit; 2406#ifdef PC98 2407 int port_shift = 0; 2408#endif 2409 2410 unit = com->unit; 2411 iobase = com->iobase; 2412 s = spltty(); 2413 com->poll = FALSE; 2414 com->poll_output = FALSE; 2415 com->do_timestamp = FALSE; 2416 com->do_dcd_timestamp = FALSE; 2417 com->pps.ppsparam.mode = 0; 2418#ifdef PC98 2419 if (IS_8251(com->pc98_if_type)) 2420 com_send_break_off(com); 2421 else { 2422 port_shift = if_16550a_type[com->pc98_if_type & 0x0f].port_shift; 2423 outb(iobase + (com_cfcr << port_shift), 2424 com->cfcr_image &= ~CFCR_SBREAK); 2425 } 2426#else 2427 outb(iobase + com_cfcr, com->cfcr_image &= ~CFCR_SBREAK); 2428#endif 2429 { 2430#ifdef PC98 2431 int tmp; 2432 if (IS_8251(com->pc98_if_type)) 2433 com_int_TxRx_disable(com); 2434 else 2435 outb(iobase + (com_ier << port_shift), 0); 2436 if (com->pc98_if_type == COM_IF_RSA98III) { 2437 outb(com->rsabase + rsa_ier, 0x00); 2438 } 2439#else 2440 outb(iobase + com_ier, 0); 2441#endif 2442 tp = com->tp; 2443#ifdef PC98 2444 if (IS_8251(com->pc98_if_type)) 2445 tmp = pc98_get_modem_status(com) & TIOCM_CAR; 2446 else 2447 tmp = com->prev_modem_status & MSR_DCD; 2448#endif 2449 if (tp->t_cflag & HUPCL 2450 /* 2451 * XXX we will miss any carrier drop between here and the 2452 * next open. Perhaps we should watch DCD even when the 2453 * port is closed; it is not sufficient to check it at 2454 * the next open because it might go up and down while 2455 * we're not watching. 2456 */ 2457 || (!com->active_out 2458#ifdef PC98 2459 && !(tmp) 2460#else 2461 && !(com->prev_modem_status & MSR_DCD) 2462#endif 2463 && !(com->it_in.c_cflag & CLOCAL)) 2464 || !(tp->t_state & TS_ISOPEN)) { 2465#ifdef PC98 2466 if (IS_8251(com->pc98_if_type)) 2467 com_tiocm_bic(com, TIOCM_DTR|TIOCM_RTS|TIOCM_LE); 2468 else 2469#endif 2470 (void)commctl(com, TIOCM_DTR, DMBIC); 2471 if (com->dtr_wait != 0 && !(com->state & CS_DTR_OFF)) { 2472 timeout(siodtrwakeup, com, com->dtr_wait); 2473 com->state |= CS_DTR_OFF; 2474 } 2475 } 2476#ifdef PC98 2477 else { 2478 if (IS_8251(com->pc98_if_type)) 2479 com_tiocm_bic(com, TIOCM_LE ); 2480 } 2481#endif 2482 } 2483#ifdef PC98 2484 if (com->pc98_8251fifo) { 2485 if (com->pc98_8251fifo_enable) 2486 outb(I8251F_fcr, CTRL8251F_XMT_RST | CTRL8251F_RCV_RST); 2487 com->pc98_8251fifo_enable = 0; 2488 } 2489#endif 2490 if (com->hasfifo) { 2491 /* 2492 * Disable fifos so that they are off after controlled 2493 * reboots. Some BIOSes fail to detect 16550s when the 2494 * fifos are enabled. 2495 */ 2496#ifdef PC98 2497 outb(iobase + (com_fifo << port_shift), 0); 2498#else 2499 outb(iobase + com_fifo, 0); 2500#endif 2501 } 2502 com->active_out = FALSE; 2503 wakeup(&com->active_out); 2504 wakeup(TSA_CARR_ON(tp)); /* restart any wopeners */ 2505 splx(s); 2506} 2507 2508static int 2509sioread(dev, uio, flag) 2510 dev_t dev; 2511 struct uio *uio; 2512 int flag; 2513{ 2514 int mynor; 2515 struct com_s *com; 2516 2517 mynor = minor(dev); 2518 if (mynor & CONTROL_MASK) 2519 return (ENODEV); 2520 com = com_addr(MINOR_TO_UNIT(mynor)); 2521 if (com == NULL || com->gone) 2522 return (ENODEV); 2523 return ((*linesw[com->tp->t_line].l_read)(com->tp, uio, flag)); 2524} 2525 2526static int 2527siowrite(dev, uio, flag) 2528 dev_t dev; 2529 struct uio *uio; 2530 int flag; 2531{ 2532 int mynor; 2533 struct com_s *com; 2534 int unit; 2535 2536 mynor = minor(dev); 2537 if (mynor & CONTROL_MASK) 2538 return (ENODEV); 2539 2540 unit = MINOR_TO_UNIT(mynor); 2541 com = com_addr(unit); 2542 if (com == NULL || com->gone) 2543 return (ENODEV); 2544 /* 2545 * (XXX) We disallow virtual consoles if the physical console is 2546 * a serial port. This is in case there is a display attached that 2547 * is not the console. In that situation we don't need/want the X 2548 * server taking over the console. 2549 */ 2550 if (constty != NULL && unit == comconsole) 2551 constty = NULL; 2552 return ((*linesw[com->tp->t_line].l_write)(com->tp, uio, flag)); 2553} 2554 2555static void 2556siobusycheck(chan) 2557 void *chan; 2558{ 2559 struct com_s *com; 2560 int s; 2561 2562 com = (struct com_s *)chan; 2563 2564 /* 2565 * Clear TS_BUSY if low-level output is complete. 2566 * spl locking is sufficient because siointr1() does not set CS_BUSY. 2567 * If siointr1() clears CS_BUSY after we look at it, then we'll get 2568 * called again. Reading the line status port outside of siointr1() 2569 * is safe because CS_BUSY is clear so there are no output interrupts 2570 * to lose. 2571 */ 2572 s = spltty(); 2573 if (com->state & CS_BUSY) 2574 com->extra_state &= ~CSE_BUSYCHECK; /* False alarm. */ 2575#ifdef PC98 2576 else if ((IS_8251(com->pc98_if_type) && 2577 ((com->pc98_8251fifo_enable && 2578 (inb(I8251F_lsr) & (STS8251F_TxRDY | STS8251F_TxEMP)) 2579 == (STS8251F_TxRDY | STS8251F_TxEMP)) || 2580 (!com->pc98_8251fifo_enable && 2581 (inb(com->sts_port) & (STS8251_TxRDY | STS8251_TxEMP)) 2582 == (STS8251_TxRDY | STS8251_TxEMP)))) || 2583 ((inb(com->line_status_port) & (LSR_TSRE | LSR_TXRDY)) 2584 == (LSR_TSRE | LSR_TXRDY))) { 2585#else 2586 else if ((inb(com->line_status_port) & (LSR_TSRE | LSR_TXRDY)) 2587 == (LSR_TSRE | LSR_TXRDY)) { 2588#endif 2589 com->tp->t_state &= ~TS_BUSY; 2590 ttwwakeup(com->tp); 2591 com->extra_state &= ~CSE_BUSYCHECK; 2592 } else 2593 timeout(siobusycheck, com, hz / 100); 2594 splx(s); 2595} 2596 2597static void 2598siodtrwakeup(chan) 2599 void *chan; 2600{ 2601 struct com_s *com; 2602 2603 com = (struct com_s *)chan; 2604 com->state &= ~CS_DTR_OFF; 2605 wakeup(&com->dtr_wait); 2606} 2607 2608static void 2609sioinput(com) 2610 struct com_s *com; 2611{ 2612 u_char *buf; 2613 int incc; 2614 u_char line_status; 2615 int recv_data; 2616 struct tty *tp; 2617 2618 buf = com->ibuf; 2619 tp = com->tp; 2620 if (!(tp->t_state & TS_ISOPEN) || !(tp->t_cflag & CREAD)) { 2621 com_events -= (com->iptr - com->ibuf); 2622 com->iptr = com->ibuf; 2623 return; 2624 } 2625 if (tp->t_state & TS_CAN_BYPASS_L_RINT) { 2626 /* 2627 * Avoid the grotesquely inefficient lineswitch routine 2628 * (ttyinput) in "raw" mode. It usually takes about 450 2629 * instructions (that's without canonical processing or echo!). 2630 * slinput is reasonably fast (usually 40 instructions plus 2631 * call overhead). 2632 */ 2633 do { 2634 enable_intr(); 2635 incc = com->iptr - buf; 2636 if (tp->t_rawq.c_cc + incc > tp->t_ihiwat 2637 && (com->state & CS_RTS_IFLOW 2638 || tp->t_iflag & IXOFF) 2639 && !(tp->t_state & TS_TBLOCK)) 2640 ttyblock(tp); 2641 com->delta_error_counts[CE_TTY_BUF_OVERFLOW] 2642 += b_to_q((char *)buf, incc, &tp->t_rawq); 2643 buf += incc; 2644 tk_nin += incc; 2645 tk_rawcc += incc; 2646 tp->t_rawcc += incc; 2647 ttwakeup(tp); 2648 if (tp->t_state & TS_TTSTOP 2649 && (tp->t_iflag & IXANY 2650 || tp->t_cc[VSTART] == tp->t_cc[VSTOP])) { 2651 tp->t_state &= ~TS_TTSTOP; 2652 tp->t_lflag &= ~FLUSHO; 2653 comstart(tp); 2654 } 2655 disable_intr(); 2656 } while (buf < com->iptr); 2657 } else { 2658 do { 2659 enable_intr(); 2660 line_status = buf[com->ierroff]; 2661 recv_data = *buf++; 2662 if (line_status 2663 & (LSR_BI | LSR_FE | LSR_OE | LSR_PE)) { 2664 if (line_status & LSR_BI) 2665 recv_data |= TTY_BI; 2666 if (line_status & LSR_FE) 2667 recv_data |= TTY_FE; 2668 if (line_status & LSR_OE) 2669 recv_data |= TTY_OE; 2670 if (line_status & LSR_PE) 2671 recv_data |= TTY_PE; 2672 } 2673 (*linesw[tp->t_line].l_rint)(recv_data, tp); 2674 disable_intr(); 2675 } while (buf < com->iptr); 2676 } 2677 com_events -= (com->iptr - com->ibuf); 2678 com->iptr = com->ibuf; 2679 2680 /* 2681 * There is now room for another low-level buffer full of input, 2682 * so enable RTS if it is now disabled and there is room in the 2683 * high-level buffer. 2684 */ 2685#ifdef PC98 2686 if (IS_8251(com->pc98_if_type)) { 2687 if ((com->state & CS_RTS_IFLOW) && 2688 !(com_tiocm_get(com) & TIOCM_RTS) && 2689 !(tp->t_state & TS_TBLOCK)) 2690 com_tiocm_bis(com, TIOCM_RTS); 2691 } else { 2692 if ((com->state & CS_RTS_IFLOW) && 2693 !(com->mcr_image & MCR_RTS) && 2694 !(tp->t_state & TS_TBLOCK)) 2695 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS); 2696 } 2697#else 2698 if ((com->state & CS_RTS_IFLOW) && !(com->mcr_image & MCR_RTS) && 2699 !(tp->t_state & TS_TBLOCK)) 2700 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS); 2701#endif 2702} 2703 2704void 2705siointr(arg) 2706 void *arg; 2707{ 2708#ifndef COM_MULTIPORT 2709 COM_LOCK(); 2710 siointr1((struct com_s *) arg); 2711 COM_UNLOCK(); 2712#else /* COM_MULTIPORT */ 2713 bool_t possibly_more_intrs; 2714 int unit; 2715 struct com_s *com; 2716#ifdef PC98 2717 u_char rsa_buf_status; 2718#endif 2719 2720 /* 2721 * Loop until there is no activity on any port. This is necessary 2722 * to get an interrupt edge more than to avoid another interrupt. 2723 * If the IRQ signal is just an OR of the IRQ signals from several 2724 * devices, then the edge from one may be lost because another is 2725 * on. 2726 */ 2727 COM_LOCK(); 2728 do { 2729 possibly_more_intrs = FALSE; 2730 for (unit = 0; unit < sio_numunits; ++unit) { 2731 com = com_addr(unit); 2732 /* 2733 * XXX COM_LOCK(); 2734 * would it work here, or be counter-productive? 2735 */ 2736#ifdef PC98 2737 if (com != NULL 2738 && !com->gone 2739 && IS_8251(com->pc98_if_type)){ 2740 siointr1(com); 2741 } else 2742#endif /* PC98 */ 2743#ifdef PC98 2744 if (com != NULL 2745 && !com->gone 2746 && com->pc98_if_type == COM_IF_RSA98III) { 2747 rsa_buf_status = inb(com->rsabase + rsa_srr) & 0xc9; 2748 if ((rsa_buf_status & 0xc8) 2749 || !(rsa_buf_status & 0x01)) { 2750 siointr1(com); 2751 if(rsa_buf_status 2752 != (inb(com->rsabase + rsa_srr) & 0xc9)) 2753 possibly_more_intrs = TRUE; 2754 } 2755 } else 2756#endif 2757 if (com != NULL 2758 && !com->gone 2759 && (inb(com->int_id_port) & IIR_IMASK) 2760 != IIR_NOPEND) { 2761 siointr1(com); 2762 possibly_more_intrs = TRUE; 2763 } 2764 /* XXX COM_UNLOCK(); */ 2765 } 2766 } while (possibly_more_intrs); 2767 COM_UNLOCK(); 2768#endif /* COM_MULTIPORT */ 2769} 2770 2771static void 2772siointr1(com) 2773 struct com_s *com; 2774{ 2775 u_char line_status; 2776 u_char modem_status; 2777 u_char *ioptr; 2778 u_char recv_data; 2779 u_char int_ctl; 2780 u_char int_ctl_new; 2781 struct timecounter *tc; 2782 u_int count; 2783 2784#ifdef PC98 2785 u_char tmp=0; 2786 u_char rsa_buf_status = 0; 2787 int rsa_tx_fifo_size=0; 2788 recv_data=0; 2789#endif /* PC98 */ 2790 2791 int_ctl = inb(com->intr_ctl_port); 2792 int_ctl_new = int_ctl; 2793 2794 while (!com->gone) { 2795#ifdef PC98 2796status_read:; 2797 if (IS_8251(com->pc98_if_type)) { 2798 if (com->pc98_8251fifo_enable) 2799 tmp = inb(I8251F_lsr); 2800 else 2801 tmp = inb(com->sts_port); 2802more_intr: 2803 line_status = 0; 2804 if (com->pc98_8251fifo_enable) { 2805 if (tmp & STS8251F_TxRDY) line_status |= LSR_TXRDY; 2806 if (tmp & STS8251F_RxRDY) line_status |= LSR_RXRDY; 2807 if (tmp & STS8251F_TxEMP) line_status |= LSR_TSRE; 2808 if (tmp & STS8251F_PE) line_status |= LSR_PE; 2809 if (tmp & STS8251F_OE) line_status |= LSR_OE; 2810 if (tmp & STS8251F_BD_SD) line_status |= LSR_BI; 2811 } else { 2812 if (tmp & STS8251_TxRDY) line_status |= LSR_TXRDY; 2813 if (tmp & STS8251_RxRDY) line_status |= LSR_RXRDY; 2814 if (tmp & STS8251_TxEMP) line_status |= LSR_TSRE; 2815 if (tmp & STS8251_PE) line_status |= LSR_PE; 2816 if (tmp & STS8251_OE) line_status |= LSR_OE; 2817 if (tmp & STS8251_FE) line_status |= LSR_FE; 2818 if (tmp & STS8251_BD_SD) line_status |= LSR_BI; 2819 } 2820 } else { 2821#endif /* PC98 */ 2822 if (com->pps.ppsparam.mode & PPS_CAPTUREBOTH) { 2823 modem_status = inb(com->modem_status_port); 2824 if ((modem_status ^ com->last_modem_status) & MSR_DCD) { 2825 tc = timecounter; 2826 count = tc->tc_get_timecount(tc); 2827 pps_event(&com->pps, tc, count, 2828 (modem_status & MSR_DCD) ? 2829 PPS_CAPTUREASSERT : PPS_CAPTURECLEAR); 2830 } 2831 } 2832 line_status = inb(com->line_status_port); 2833#ifdef PC98 2834 } 2835 if (com->pc98_if_type == COM_IF_RSA98III) 2836 rsa_buf_status = inb(com->rsabase + rsa_srr); 2837#endif /* PC98 */ 2838 2839 /* input event? (check first to help avoid overruns) */ 2840#ifndef PC98 2841 while (line_status & LSR_RCV_MASK) { 2842#else 2843 while ((line_status & LSR_RCV_MASK) 2844 || (com->pc98_if_type == COM_IF_RSA98III 2845 && (rsa_buf_status & 0x08))) { 2846#endif /* PC98 */ 2847 /* break/unnattached error bits or real input? */ 2848#ifdef PC98 2849 if (IS_8251(com->pc98_if_type)) { 2850 if (com->pc98_8251fifo_enable) { 2851 recv_data = inb(I8251F_data); 2852 if (tmp & (STS8251F_PE | STS8251F_OE | 2853 STS8251F_BD_SD)) { 2854 pc98_i8251_or_cmd(com, CMD8251_ER); 2855 recv_data = 0; 2856 } 2857 } else { 2858 recv_data = inb(com->data_port); 2859 if (tmp & (STS8251_PE | STS8251_OE | 2860 STS8251_FE | STS8251_BD_SD)) { 2861 pc98_i8251_or_cmd(com, CMD8251_ER); 2862 recv_data = 0; 2863 } 2864 } 2865 } else { 2866#endif /* PC98 */ 2867#ifdef PC98 2868 if (com->pc98_if_type == COM_IF_RSA98III) { 2869 if (!(rsa_buf_status & 0x08)) 2870 recv_data = 0; 2871 else 2872 recv_data = inb(com->data_port); 2873 } else 2874#endif 2875 if (!(line_status & LSR_RXRDY)) 2876 recv_data = 0; 2877 else 2878 recv_data = inb(com->data_port); 2879#ifdef PC98 2880 } 2881#endif 2882 if (line_status & (LSR_BI | LSR_FE | LSR_PE)) { 2883 /* 2884 * Don't store BI if IGNBRK or FE/PE if IGNPAR. 2885 * Otherwise, push the work to a higher level 2886 * (to handle PARMRK) if we're bypassing. 2887 * Otherwise, convert BI/FE and PE+INPCK to 0. 2888 * 2889 * This makes bypassing work right in the 2890 * usual "raw" case (IGNBRK set, and IGNPAR 2891 * and INPCK clear). 2892 * 2893 * Note: BI together with FE/PE means just BI. 2894 */ 2895 if (line_status & LSR_BI) { 2896#if defined(DDB) && defined(BREAK_TO_DEBUGGER) 2897 if (com->unit == comconsole) { 2898 breakpoint(); 2899 goto cont; 2900 } 2901#endif 2902 if (com->tp == NULL 2903 || com->tp->t_iflag & IGNBRK) 2904 goto cont; 2905 } else { 2906 if (com->tp == NULL 2907 || com->tp->t_iflag & IGNPAR) 2908 goto cont; 2909 } 2910 if (com->tp->t_state & TS_CAN_BYPASS_L_RINT 2911 && (line_status & (LSR_BI | LSR_FE) 2912 || com->tp->t_iflag & INPCK)) 2913 recv_data = 0; 2914 } 2915 ++com->bytes_in; 2916 if (com->hotchar != 0 && recv_data == com->hotchar) 2917 setsofttty(); 2918 ioptr = com->iptr; 2919 if (ioptr >= com->ibufend) 2920 CE_RECORD(com, CE_INTERRUPT_BUF_OVERFLOW); 2921 else { 2922 if (com->do_timestamp) 2923 microtime(&com->timestamp); 2924 ++com_events; 2925 schedsofttty(); 2926#if 0 /* for testing input latency vs efficiency */ 2927if (com->iptr - com->ibuf == 8) 2928 setsofttty(); 2929#endif 2930 ioptr[0] = recv_data; 2931 ioptr[com->ierroff] = line_status; 2932 com->iptr = ++ioptr; 2933 if (ioptr == com->ihighwater 2934 && com->state & CS_RTS_IFLOW) 2935#ifdef PC98 2936 IS_8251(com->pc98_if_type) ? 2937 com_tiocm_bic(com, TIOCM_RTS) : 2938#endif 2939 outb(com->modem_ctl_port, 2940 com->mcr_image &= ~MCR_RTS); 2941 if (line_status & LSR_OE) 2942 CE_RECORD(com, CE_OVERRUN); 2943 } 2944cont: 2945 /* 2946 * "& 0x7F" is to avoid the gcc-1.40 generating a slow 2947 * jump from the top of the loop to here 2948 */ 2949#ifdef PC98 2950 if (IS_8251(com->pc98_if_type)) 2951 goto status_read; 2952 else 2953#endif 2954 line_status = inb(com->line_status_port) & 0x7F; 2955#ifdef PC98 2956 if (com->pc98_if_type == COM_IF_RSA98III) 2957 rsa_buf_status = inb(com->rsabase + rsa_srr); 2958#endif /* PC98 */ 2959 } 2960 2961 /* modem status change? (always check before doing output) */ 2962#ifdef PC98 2963 if (!IS_8251(com->pc98_if_type)) { 2964#endif 2965 modem_status = inb(com->modem_status_port); 2966 if (modem_status != com->last_modem_status) { 2967 if (com->do_dcd_timestamp 2968 && !(com->last_modem_status & MSR_DCD) 2969 && modem_status & MSR_DCD) 2970 microtime(&com->dcd_timestamp); 2971 2972 /* 2973 * Schedule high level to handle DCD changes. Note 2974 * that we don't use the delta bits anywhere. Some 2975 * UARTs mess them up, and it's easy to remember the 2976 * previous bits and calculate the delta. 2977 */ 2978 com->last_modem_status = modem_status; 2979 if (!(com->state & CS_CHECKMSR)) { 2980 com_events += LOTS_OF_EVENTS; 2981 com->state |= CS_CHECKMSR; 2982 setsofttty(); 2983 } 2984 2985 /* handle CTS change immediately for crisp flow ctl */ 2986 if (com->state & CS_CTS_OFLOW) { 2987 if (modem_status & MSR_CTS) 2988 com->state |= CS_ODEVREADY; 2989 else 2990 com->state &= ~CS_ODEVREADY; 2991 } 2992 } 2993#ifdef PC98 2994 } 2995#endif 2996 2997 /* output queued and everything ready? */ 2998#ifndef PC98 2999 if (line_status & LSR_TXRDY 3000 && com->state >= (CS_BUSY | CS_TTGO | CS_ODEVREADY)) { 3001#else 3002 if (((com->pc98_if_type == COM_IF_RSA98III) 3003 ? (rsa_buf_status & 0x02) 3004 : (line_status & LSR_TXRDY)) 3005 && com->state >= (CS_BUSY | CS_TTGO | CS_ODEVREADY)) { 3006#endif 3007#ifdef PC98 3008 Port_t tmp_data_port; 3009 3010 if (IS_8251(com->pc98_if_type) && 3011 com->pc98_8251fifo_enable) 3012 tmp_data_port = I8251F_data; 3013 else 3014 tmp_data_port = com->data_port; 3015#endif 3016 3017 ioptr = com->obufq.l_head; 3018 if (com->tx_fifo_size > 1) { 3019 u_int ocount; 3020 3021 ocount = com->obufq.l_tail - ioptr; 3022#ifdef PC98 3023 if (com->pc98_if_type == COM_IF_RSA98III) { 3024 rsa_buf_status = inb(com->rsabase + rsa_srr); 3025 rsa_tx_fifo_size = 1024; 3026 if (!(rsa_buf_status & 0x01)) 3027 rsa_tx_fifo_size = 2048; 3028 if (ocount > rsa_tx_fifo_size) 3029 ocount = rsa_tx_fifo_size; 3030 } else 3031#endif 3032 if (ocount > com->tx_fifo_size) 3033 ocount = com->tx_fifo_size; 3034 com->bytes_out += ocount; 3035 do 3036#ifdef PC98 3037 outb(tmp_data_port, *ioptr++); 3038#else 3039 outb(com->data_port, *ioptr++); 3040#endif 3041 while (--ocount != 0); 3042 } else { 3043#ifdef PC98 3044 outb(tmp_data_port, *ioptr++); 3045#else 3046 outb(com->data_port, *ioptr++); 3047#endif 3048 ++com->bytes_out; 3049 } 3050#ifdef PC98 3051 if (IS_8251(com->pc98_if_type)) 3052 if (!(pc98_check_i8251_interrupt(com) & IEN_TxFLAG)) 3053 com_int_Tx_enable(com); 3054#endif 3055 com->obufq.l_head = ioptr; 3056 if (COM_IIR_TXRDYBUG(com->flags)) { 3057 int_ctl_new = int_ctl | IER_ETXRDY; 3058 } 3059 if (ioptr >= com->obufq.l_tail) { 3060 struct lbq *qp; 3061 3062 qp = com->obufq.l_next; 3063 qp->l_queued = FALSE; 3064 qp = qp->l_next; 3065 if (qp != NULL) { 3066 com->obufq.l_head = qp->l_head; 3067 com->obufq.l_tail = qp->l_tail; 3068 com->obufq.l_next = qp; 3069 } else { 3070 /* output just completed */ 3071 if (COM_IIR_TXRDYBUG(com->flags)) { 3072 int_ctl_new = int_ctl & ~IER_ETXRDY; 3073 } 3074 com->state &= ~CS_BUSY; 3075#if defined(PC98) 3076 if (IS_8251(com->pc98_if_type)) 3077 if ( pc98_check_i8251_interrupt(com) & IEN_TxFLAG ) 3078 com_int_Tx_disable(com); 3079#endif 3080 } 3081 if (!(com->state & CS_ODONE)) { 3082 com_events += LOTS_OF_EVENTS; 3083 com->state |= CS_ODONE; 3084 setsofttty(); /* handle at high level ASAP */ 3085 } 3086 } 3087 if (COM_IIR_TXRDYBUG(com->flags) && (int_ctl != int_ctl_new)) { 3088#ifdef PC98 3089 if (com->pc98_if_type == COM_IF_RSA98III) { 3090 int_ctl_new &= ~(IER_ETXRDY | IER_ERXRDY); 3091 outb(com->intr_ctl_port, int_ctl_new); 3092 outb(com->rsabase + rsa_ier, 0x1d); 3093 } else 3094#endif 3095 outb(com->intr_ctl_port, int_ctl_new); 3096 } 3097 } 3098#ifdef PC98 3099 else if (line_status & LSR_TXRDY) { 3100 if (IS_8251(com->pc98_if_type)) 3101 if ( pc98_check_i8251_interrupt(com) & IEN_TxFLAG ) 3102 com_int_Tx_disable(com); 3103 } 3104 if (IS_8251(com->pc98_if_type)) { 3105 if (com->pc98_8251fifo_enable) { 3106 if ((tmp = inb(I8251F_lsr)) & STS8251F_RxRDY) 3107 goto more_intr; 3108 } else { 3109 if ((tmp = inb(com->sts_port)) & STS8251_RxRDY) 3110 goto more_intr; 3111 } 3112 } 3113#endif 3114 3115 /* finished? */ 3116#ifndef COM_MULTIPORT 3117#ifdef PC98 3118 if (IS_8251(com->pc98_if_type)) 3119 return; 3120#endif 3121 if ((inb(com->int_id_port) & IIR_IMASK) == IIR_NOPEND) 3122#endif /* COM_MULTIPORT */ 3123 return; 3124 } 3125} 3126 3127static int 3128sioioctl(dev, cmd, data, flag, p) 3129 dev_t dev; 3130 u_long cmd; 3131 caddr_t data; 3132 int flag; 3133 struct proc *p; 3134{ 3135 struct com_s *com; 3136 int error; 3137 Port_t iobase; 3138 int mynor; 3139 int s; 3140 struct tty *tp; 3141#if defined(COMPAT_43) || defined(COMPAT_SUNOS) 3142 u_long oldcmd; 3143 struct termios term; 3144#endif 3145 3146 mynor = minor(dev); 3147 com = com_addr(MINOR_TO_UNIT(mynor)); 3148 if (com == NULL || com->gone) 3149 return (ENODEV); 3150 iobase = com->iobase; 3151 if (mynor & CONTROL_MASK) { 3152 struct termios *ct; 3153 3154 switch (mynor & CONTROL_MASK) { 3155 case CONTROL_INIT_STATE: 3156 ct = mynor & CALLOUT_MASK ? &com->it_out : &com->it_in; 3157 break; 3158 case CONTROL_LOCK_STATE: 3159 ct = mynor & CALLOUT_MASK ? &com->lt_out : &com->lt_in; 3160 break; 3161 default: 3162 return (ENODEV); /* /dev/nodev */ 3163 } 3164 switch (cmd) { 3165 case TIOCSETA: 3166 error = suser(p); 3167 if (error != 0) 3168 return (error); 3169 *ct = *(struct termios *)data; 3170 return (0); 3171 case TIOCGETA: 3172 *(struct termios *)data = *ct; 3173 return (0); 3174 case TIOCGETD: 3175 *(int *)data = TTYDISC; 3176 return (0); 3177 case TIOCGWINSZ: 3178 bzero(data, sizeof(struct winsize)); 3179 return (0); 3180 default: 3181 return (ENOTTY); 3182 } 3183 } 3184 tp = com->tp; 3185#if defined(COMPAT_43) || defined(COMPAT_SUNOS) 3186 term = tp->t_termios; 3187 oldcmd = cmd; 3188 error = ttsetcompat(tp, &cmd, data, &term); 3189 if (error != 0) 3190 return (error); 3191 if (cmd != oldcmd) 3192 data = (caddr_t)&term; 3193#endif 3194 if (cmd == TIOCSETA || cmd == TIOCSETAW || cmd == TIOCSETAF) { 3195 int cc; 3196 struct termios *dt = (struct termios *)data; 3197 struct termios *lt = mynor & CALLOUT_MASK 3198 ? &com->lt_out : &com->lt_in; 3199 3200 dt->c_iflag = (tp->t_iflag & lt->c_iflag) 3201 | (dt->c_iflag & ~lt->c_iflag); 3202 dt->c_oflag = (tp->t_oflag & lt->c_oflag) 3203 | (dt->c_oflag & ~lt->c_oflag); 3204 dt->c_cflag = (tp->t_cflag & lt->c_cflag) 3205 | (dt->c_cflag & ~lt->c_cflag); 3206 dt->c_lflag = (tp->t_lflag & lt->c_lflag) 3207 | (dt->c_lflag & ~lt->c_lflag); 3208 for (cc = 0; cc < NCCS; ++cc) 3209 if (lt->c_cc[cc] != 0) 3210 dt->c_cc[cc] = tp->t_cc[cc]; 3211 if (lt->c_ispeed != 0) 3212 dt->c_ispeed = tp->t_ispeed; 3213 if (lt->c_ospeed != 0) 3214 dt->c_ospeed = tp->t_ospeed; 3215 } 3216 error = (*linesw[tp->t_line].l_ioctl)(tp, cmd, data, flag, p); 3217 if (error != ENOIOCTL) 3218 return (error); 3219 s = spltty(); 3220 error = ttioctl(tp, cmd, data, flag); 3221 disc_optim(tp, &tp->t_termios, com); 3222 if (error != ENOIOCTL) { 3223 splx(s); 3224 return (error); 3225 } 3226#ifdef PC98 3227 if (IS_8251(com->pc98_if_type)) { 3228 switch (cmd) { 3229 case TIOCSBRK: 3230 com_send_break_on( com ); 3231 break; 3232 case TIOCCBRK: 3233 com_send_break_off( com ); 3234 break; 3235 case TIOCSDTR: 3236 com_tiocm_bis(com, TIOCM_DTR | TIOCM_RTS ); 3237 break; 3238 case TIOCCDTR: 3239 com_tiocm_bic(com, TIOCM_DTR); 3240 break; 3241 /* 3242 * XXX should disallow changing MCR_RTS if CS_RTS_IFLOW is set. The 3243 * changes get undone on the next call to comparam(). 3244 */ 3245 case TIOCMSET: 3246 com_tiocm_set( com, *(int *)data ); 3247 break; 3248 case TIOCMBIS: 3249 com_tiocm_bis( com, *(int *)data ); 3250 break; 3251 case TIOCMBIC: 3252 com_tiocm_bic( com, *(int *)data ); 3253 break; 3254 case TIOCMGET: 3255 *(int *)data = com_tiocm_get(com); 3256 break; 3257 case TIOCMSDTRWAIT: 3258 /* must be root since the wait applies to following logins */ 3259 error = suser(p); 3260 if (error != 0) { 3261 splx(s); 3262 return (error); 3263 } 3264 com->dtr_wait = *(int *)data * hz / 100; 3265 break; 3266 case TIOCMGDTRWAIT: 3267 *(int *)data = com->dtr_wait * 100 / hz; 3268 break; 3269 case TIOCTIMESTAMP: 3270 com->do_timestamp = TRUE; 3271 *(struct timeval *)data = com->timestamp; 3272 break; 3273 case TIOCDCDTIMESTAMP: 3274 com->do_dcd_timestamp = TRUE; 3275 *(struct timeval *)data = com->dcd_timestamp; 3276 break; 3277 default: 3278 splx(s); 3279 return (ENOTTY); 3280 } 3281 } else { 3282 int port_shift; 3283 port_shift = if_16550a_type[com->pc98_if_type & 0x0f].port_shift; 3284#endif 3285 switch (cmd) { 3286 case TIOCSBRK: 3287#ifdef PC98 3288 outb(iobase + (com_cfcr << port_shift), 3289 com->cfcr_image |= CFCR_SBREAK); 3290#else 3291 outb(iobase + com_cfcr, com->cfcr_image |= CFCR_SBREAK); 3292#endif 3293 break; 3294 case TIOCCBRK: 3295#ifdef PC98 3296 outb(iobase + (com_cfcr << port_shift), 3297 com->cfcr_image &= ~CFCR_SBREAK); 3298#else 3299 outb(iobase + com_cfcr, com->cfcr_image &= ~CFCR_SBREAK); 3300#endif 3301 break; 3302 case TIOCSDTR: 3303 (void)commctl(com, TIOCM_DTR, DMBIS); 3304 break; 3305 case TIOCCDTR: 3306 (void)commctl(com, TIOCM_DTR, DMBIC); 3307 break; 3308 /* 3309 * XXX should disallow changing MCR_RTS if CS_RTS_IFLOW is set. The 3310 * changes get undone on the next call to comparam(). 3311 */ 3312 case TIOCMSET: 3313 (void)commctl(com, *(int *)data, DMSET); 3314 break; 3315 case TIOCMBIS: 3316 (void)commctl(com, *(int *)data, DMBIS); 3317 break; 3318 case TIOCMBIC: 3319 (void)commctl(com, *(int *)data, DMBIC); 3320 break; 3321 case TIOCMGET: 3322 *(int *)data = commctl(com, 0, DMGET); 3323 break; 3324 case TIOCMSDTRWAIT: 3325 /* must be root since the wait applies to following logins */ 3326 error = suser(p); 3327 if (error != 0) { 3328 splx(s); 3329 return (error); 3330 } 3331 com->dtr_wait = *(int *)data * hz / 100; 3332 break; 3333 case TIOCMGDTRWAIT: 3334 *(int *)data = com->dtr_wait * 100 / hz; 3335 break; 3336 case TIOCTIMESTAMP: 3337 com->do_timestamp = TRUE; 3338 *(struct timeval *)data = com->timestamp; 3339 break; 3340 case TIOCDCDTIMESTAMP: 3341 com->do_dcd_timestamp = TRUE; 3342 *(struct timeval *)data = com->dcd_timestamp; 3343 break; 3344 default: 3345 splx(s); 3346 error = pps_ioctl(cmd, data, &com->pps); 3347 if (error == ENODEV) 3348 error = ENOTTY; 3349 return (error); 3350 } 3351#ifdef PC98 3352 } 3353#endif 3354 splx(s); 3355 return (0); 3356} 3357 3358static void 3359siopoll() 3360{ 3361 int unit; 3362 3363 if (com_events == 0) 3364 return; 3365repeat: 3366 for (unit = 0; unit < sio_numunits; ++unit) { 3367 struct com_s *com; 3368 int incc; 3369 struct tty *tp; 3370 3371 com = com_addr(unit); 3372 if (com == NULL) 3373 continue; 3374 tp = com->tp; 3375 if (tp == NULL || com->gone) { 3376 /* 3377 * Discard any events related to never-opened or 3378 * going-away devices. 3379 */ 3380 disable_intr(); 3381 incc = com->iptr - com->ibuf; 3382 com->iptr = com->ibuf; 3383 if (com->state & CS_CHECKMSR) { 3384 incc += LOTS_OF_EVENTS; 3385 com->state &= ~CS_CHECKMSR; 3386 } 3387 com_events -= incc; 3388 enable_intr(); 3389 continue; 3390 } 3391 if (com->iptr != com->ibuf) { 3392 disable_intr(); 3393 sioinput(com); 3394 enable_intr(); 3395 } 3396 if (com->state & CS_CHECKMSR) { 3397 u_char delta_modem_status; 3398 3399#ifdef PC98 3400 if (!IS_8251(com->pc98_if_type)) { 3401#endif 3402 disable_intr(); 3403 delta_modem_status = com->last_modem_status 3404 ^ com->prev_modem_status; 3405 com->prev_modem_status = com->last_modem_status; 3406 com_events -= LOTS_OF_EVENTS; 3407 com->state &= ~CS_CHECKMSR; 3408 enable_intr(); 3409 if (delta_modem_status & MSR_DCD) 3410 (*linesw[tp->t_line].l_modem) 3411 (tp, com->prev_modem_status & MSR_DCD); 3412#ifdef PC98 3413 } 3414#endif 3415 } 3416 if (com->state & CS_ODONE) { 3417 disable_intr(); 3418 com_events -= LOTS_OF_EVENTS; 3419 com->state &= ~CS_ODONE; 3420 enable_intr(); 3421 if (!(com->state & CS_BUSY) 3422 && !(com->extra_state & CSE_BUSYCHECK)) { 3423 timeout(siobusycheck, com, hz / 100); 3424 com->extra_state |= CSE_BUSYCHECK; 3425 } 3426 (*linesw[tp->t_line].l_start)(tp); 3427 } 3428 if (com_events == 0) 3429 break; 3430 } 3431 if (com_events >= LOTS_OF_EVENTS) 3432 goto repeat; 3433} 3434 3435static int 3436comparam(tp, t) 3437 struct tty *tp; 3438 struct termios *t; 3439{ 3440 u_int cfcr; 3441 int cflag; 3442 struct com_s *com; 3443 int divisor; 3444 u_char dlbh; 3445 u_char dlbl; 3446 Port_t iobase; 3447 int s; 3448 int unit; 3449#ifdef PC98 3450 int port_shift = 0; 3451 u_char param = 0; 3452#endif 3453 3454#ifdef PC98 3455 cfcr = 0; 3456 unit = DEV_TO_UNIT(tp->t_dev); 3457 com = com_addr(unit); 3458 iobase = com->iobase; 3459 if (IS_8251(com->pc98_if_type)) { 3460 divisor = pc98_ttspeedtab(com, t->c_ospeed); 3461 } else { 3462 port_shift = if_16550a_type[com->pc98_if_type & 0x0f].port_shift; 3463 3464 /* do historical conversions */ 3465 if (t->c_ispeed == 0) 3466 t->c_ispeed = t->c_ospeed; 3467 3468 /* check requested parameters */ 3469 divisor = ttspeedtab(t->c_ospeed, 3470 if_16550a_type[com->pc98_if_type & 0x0f].speedtab); 3471 } 3472#else 3473 /* do historical conversions */ 3474 if (t->c_ispeed == 0) 3475 t->c_ispeed = t->c_ospeed; 3476 3477 /* check requested parameters */ 3478 divisor = ttspeedtab(t->c_ospeed, comspeedtab); 3479#endif 3480 if (divisor < 0 || (divisor > 0 && t->c_ispeed != t->c_ospeed)) 3481 return (EINVAL); 3482 3483 /* parameters are OK, convert them to the com struct and the device */ 3484#ifndef PC98 3485 unit = DEV_TO_UNIT(tp->t_dev); 3486 com = com_addr(unit); 3487 if (com == NULL) 3488 return (ENODEV); 3489 iobase = com->iobase; 3490#endif 3491 s = spltty(); 3492#ifdef PC98 3493 if (IS_8251(com->pc98_if_type)) { 3494 if (divisor == 0) 3495 com_tiocm_bic( com, TIOCM_DTR|TIOCM_RTS|TIOCM_LE ); 3496 else 3497 com_tiocm_bis( com, TIOCM_DTR|TIOCM_RTS|TIOCM_LE ); 3498 } else { 3499#endif 3500 if (divisor == 0) 3501 (void)commctl(com, TIOCM_DTR, DMBIC); /* hang up line */ 3502 else 3503 (void)commctl(com, TIOCM_DTR, DMBIS); 3504#ifdef PC98 3505 } 3506#endif 3507 cflag = t->c_cflag; 3508#ifdef PC98 3509 if (!IS_8251(com->pc98_if_type)) { 3510#endif 3511 switch (cflag & CSIZE) { 3512 case CS5: 3513 cfcr = CFCR_5BITS; 3514 break; 3515 case CS6: 3516 cfcr = CFCR_6BITS; 3517 break; 3518 case CS7: 3519 cfcr = CFCR_7BITS; 3520 break; 3521 default: 3522 cfcr = CFCR_8BITS; 3523 break; 3524 } 3525 if (cflag & PARENB) { 3526 cfcr |= CFCR_PENAB; 3527 if (!(cflag & PARODD)) 3528 cfcr |= CFCR_PEVEN; 3529 } 3530 if (cflag & CSTOPB) 3531 cfcr |= CFCR_STOPB; 3532 3533 if (com->hasfifo && divisor != 0) { 3534 /* 3535 * Use a fifo trigger level low enough so that the input 3536 * latency from the fifo is less than about 16 msec and 3537 * the total latency is less than about 30 msec. These 3538 * latencies are reasonable for humans. Serial comms 3539 * protocols shouldn't expect anything better since modem 3540 * latencies are larger. 3541 */ 3542 com->fifo_image = t->c_ospeed <= 4800 3543 ? FIFO_ENABLE : FIFO_ENABLE | FIFO_RX_HIGH; 3544#ifdef COM_ESP 3545 /* 3546 * The Hayes ESP card needs the fifo DMA mode bit set 3547 * in compatibility mode. If not, it will interrupt 3548 * for each character received. 3549 */ 3550 if (com->esp) 3551 com->fifo_image |= FIFO_DMA_MODE; 3552#endif 3553#ifdef PC98 3554 outb(iobase + (com_fifo << port_shift), com->fifo_image); 3555#else 3556 outb(iobase + com_fifo, com->fifo_image); 3557#endif 3558 } 3559#ifdef PC98 3560 } 3561#endif 3562 3563 /* 3564 * This returns with interrupts disabled so that we can complete 3565 * the speed change atomically. Keeping interrupts disabled is 3566 * especially important while com_data is hidden. 3567 */ 3568 (void) siosetwater(com, t->c_ispeed); 3569 3570#ifdef PC98 3571 if (IS_8251(com->pc98_if_type)) 3572 com_cflag_and_speed_set(com, cflag, t->c_ospeed); 3573 else { 3574#endif 3575 if (divisor != 0) { 3576#ifdef PC98 3577 outb(iobase + (com_cfcr << port_shift), cfcr | CFCR_DLAB); 3578#else 3579 outb(iobase + com_cfcr, cfcr | CFCR_DLAB); 3580#endif 3581 /* 3582 * Only set the divisor registers if they would change, 3583 * since on some 16550 incompatibles (UMC8669F), setting 3584 * them while input is arriving them loses sync until 3585 * data stops arriving. 3586 */ 3587 dlbl = divisor & 0xFF; 3588#ifdef PC98 3589 if (inb(iobase + (com_dlbl << port_shift)) != dlbl) 3590 outb(iobase + (com_dlbl << port_shift), dlbl); 3591 dlbh = (u_int) divisor >> 8; 3592 if (inb(iobase + (com_dlbh << port_shift)) != dlbh) 3593 outb(iobase + (com_dlbh << port_shift), dlbh); 3594#else 3595 if (inb(iobase + com_dlbl) != dlbl) 3596 outb(iobase + com_dlbl, dlbl); 3597 dlbh = (u_int) divisor >> 8; 3598 if (inb(iobase + com_dlbh) != dlbh) 3599 outb(iobase + com_dlbh, dlbh); 3600#endif 3601 } 3602 3603 3604#ifdef PC98 3605 } 3606 outb(iobase + (com_cfcr << port_shift), com->cfcr_image = cfcr); 3607#else 3608 outb(iobase + com_cfcr, com->cfcr_image = cfcr); 3609#endif 3610 3611 if (!(tp->t_state & TS_TTSTOP)) 3612 com->state |= CS_TTGO; 3613 3614 if (cflag & CRTS_IFLOW) { 3615 if (com->st16650a) { 3616 outb(iobase + com_cfcr, 0xbf); 3617 outb(iobase + com_fifo, inb(iobase + com_fifo) | 0x40); 3618 } 3619 com->state |= CS_RTS_IFLOW; 3620 /* 3621 * If CS_RTS_IFLOW just changed from off to on, the change 3622 * needs to be propagated to MCR_RTS. This isn't urgent, 3623 * so do it later by calling comstart() instead of repeating 3624 * a lot of code from comstart() here. 3625 */ 3626 } else if (com->state & CS_RTS_IFLOW) { 3627 com->state &= ~CS_RTS_IFLOW; 3628 /* 3629 * CS_RTS_IFLOW just changed from on to off. Force MCR_RTS 3630 * on here, since comstart() won't do it later. 3631 */ 3632#ifdef PC98 3633 if (IS_8251(com->pc98_if_type)) 3634 com_tiocm_bis(com, TIOCM_RTS); 3635 else 3636#endif 3637 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS); 3638 if (com->st16650a) { 3639 outb(iobase + com_cfcr, 0xbf); 3640 outb(iobase + com_fifo, inb(iobase + com_fifo) & ~0x40); 3641 } 3642 } 3643 3644 3645 /* 3646 * Set up state to handle output flow control. 3647 * XXX - worth handling MDMBUF (DCD) flow control at the lowest level? 3648 * Now has 10+ msec latency, while CTS flow has 50- usec latency. 3649 */ 3650 com->state |= CS_ODEVREADY; 3651 com->state &= ~CS_CTS_OFLOW; 3652#ifdef PC98 3653 if (com->pc98_if_type == COM_IF_RSA98III) { 3654 param = inb(com->rsabase + rsa_msr); 3655 outb(com->rsabase + rsa_msr, param & 0x14); 3656 } 3657#endif 3658 if (cflag & CCTS_OFLOW) { 3659 com->state |= CS_CTS_OFLOW; 3660#ifdef PC98 3661 if (IS_8251(com->pc98_if_type)) { 3662 if (!(pc98_get_modem_status(com) & TIOCM_CTS)) 3663 com->state &= ~CS_ODEVREADY; 3664 } else { 3665#endif 3666#ifdef PC98 3667 if (com->pc98_if_type == COM_IF_RSA98III) { 3668 /* Set automatic flow control mode */ 3669 outb(com->rsabase + rsa_msr, param | 0x08); 3670 } else 3671#endif 3672 if (!(com->last_modem_status & MSR_CTS)) 3673 com->state &= ~CS_ODEVREADY; 3674 if (com->st16650a) { 3675 outb(iobase + com_cfcr, 0xbf); 3676 outb(iobase + com_fifo, inb(iobase + com_fifo) | 0x80); 3677 } 3678#ifdef PC98 3679 } 3680#endif 3681 } else { 3682 if (com->st16650a) { 3683 outb(iobase + com_cfcr, 0xbf); 3684 outb(iobase + com_fifo, inb(iobase + com_fifo) & ~0x80); 3685 } 3686 } 3687 3688 3689#ifdef PC98 3690 outb(iobase + (com_cfcr << port_shift), com->cfcr_image); 3691#else 3692 outb(iobase + com_cfcr, com->cfcr_image); 3693#endif 3694 3695 3696 /* XXX shouldn't call functions while intrs are disabled. */ 3697 disc_optim(tp, t, com); 3698 /* 3699 * Recover from fiddling with CS_TTGO. We used to call siointr1() 3700 * unconditionally, but that defeated the careful discarding of 3701 * stale input in sioopen(). 3702 */ 3703 if (com->state >= (CS_BUSY | CS_TTGO)) 3704 siointr1(com); 3705 3706 enable_intr(); 3707 splx(s); 3708 comstart(tp); 3709 if (com->ibufold != NULL) { 3710 free(com->ibufold, M_DEVBUF); 3711 com->ibufold = NULL; 3712 } 3713 return (0); 3714} 3715 3716static int 3717siosetwater(com, speed) 3718 struct com_s *com; 3719 speed_t speed; 3720{ 3721 int cp4ticks; 3722 u_char *ibuf; 3723 int ibufsize; 3724 struct tty *tp; 3725 3726 /* 3727 * Make the buffer size large enough to handle a softtty interrupt 3728 * latency of about 2 ticks without loss of throughput or data 3729 * (about 3 ticks if input flow control is not used or not honoured, 3730 * but a bit less for CS5-CS7 modes). 3731 */ 3732 cp4ticks = speed / 10 / hz * 4; 3733 for (ibufsize = 128; ibufsize < cp4ticks;) 3734 ibufsize <<= 1; 3735#ifdef PC98 3736 if (com->pc98_if_type == COM_IF_RSA98III) 3737 ibufsize = 2048; 3738#endif 3739 if (ibufsize == com->ibufsize) { 3740 disable_intr(); 3741 return (0); 3742 } 3743 3744 /* 3745 * Allocate input buffer. The extra factor of 2 in the size is 3746 * to allow for an error byte for each input byte. 3747 */ 3748 ibuf = malloc(2 * ibufsize, M_DEVBUF, M_NOWAIT); 3749 if (ibuf == NULL) { 3750 disable_intr(); 3751 return (ENOMEM); 3752 } 3753 3754 /* Initialize non-critical variables. */ 3755 com->ibufold = com->ibuf; 3756 com->ibufsize = ibufsize; 3757 tp = com->tp; 3758 if (tp != NULL) { 3759 tp->t_ififosize = 2 * ibufsize; 3760 tp->t_ispeedwat = (speed_t)-1; 3761 tp->t_ospeedwat = (speed_t)-1; 3762 } 3763 3764 /* 3765 * Read current input buffer, if any. Continue with interrupts 3766 * disabled. 3767 */ 3768 disable_intr(); 3769 if (com->iptr != com->ibuf) 3770 sioinput(com); 3771 3772 /*- 3773 * Initialize critical variables, including input buffer watermarks. 3774 * The external device is asked to stop sending when the buffer 3775 * exactly reaches high water, or when the high level requests it. 3776 * The high level is notified immediately (rather than at a later 3777 * clock tick) when this watermark is reached. 3778 * The buffer size is chosen so the watermark should almost never 3779 * be reached. 3780 * The low watermark is invisibly 0 since the buffer is always 3781 * emptied all at once. 3782 */ 3783 com->iptr = com->ibuf = ibuf; 3784 com->ibufend = ibuf + ibufsize; 3785 com->ierroff = ibufsize; 3786 com->ihighwater = ibuf + 3 * ibufsize / 4; 3787 return (0); 3788} 3789 3790static void 3791comstart(tp) 3792 struct tty *tp; 3793{ 3794 struct com_s *com; 3795 int s; 3796 int unit; 3797 3798 unit = DEV_TO_UNIT(tp->t_dev); 3799 com = com_addr(unit); 3800 if (com == NULL) 3801 return; 3802 s = spltty(); 3803 disable_intr(); 3804 if (tp->t_state & TS_TTSTOP) 3805 com->state &= ~CS_TTGO; 3806 else 3807 com->state |= CS_TTGO; 3808 if (tp->t_state & TS_TBLOCK) { 3809#ifdef PC98 3810 if (IS_8251(com->pc98_if_type)) { 3811 if ((com_tiocm_get(com) & TIOCM_RTS) && 3812 (com->state & CS_RTS_IFLOW)) 3813 com_tiocm_bic(com, TIOCM_RTS); 3814 } else { 3815 if ((com->mcr_image & MCR_RTS) && 3816 (com->state & CS_RTS_IFLOW)) 3817 outb(com->modem_ctl_port, com->mcr_image &= ~MCR_RTS); 3818 } 3819#else 3820 if (com->mcr_image & MCR_RTS && com->state & CS_RTS_IFLOW) 3821 outb(com->modem_ctl_port, com->mcr_image &= ~MCR_RTS); 3822#endif 3823 } else { 3824#ifdef PC98 3825 if (IS_8251(com->pc98_if_type)) { 3826 if (!(com_tiocm_get(com) & TIOCM_RTS) && 3827 com->iptr < com->ihighwater && 3828 com->state & CS_RTS_IFLOW) 3829 com_tiocm_bis(com, TIOCM_RTS); 3830 } else { 3831 if (!(com->mcr_image & MCR_RTS) && 3832 com->iptr < com->ihighwater && 3833 com->state & CS_RTS_IFLOW) 3834 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS); 3835 } 3836#else 3837 if (!(com->mcr_image & MCR_RTS) && com->iptr < com->ihighwater 3838 && com->state & CS_RTS_IFLOW) 3839 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS); 3840#endif 3841 } 3842 enable_intr(); 3843 if (tp->t_state & (TS_TIMEOUT | TS_TTSTOP)) { 3844 ttwwakeup(tp); 3845#ifdef PC98 3846/* if(IS_8251(com->pc98_if_type)) 3847 com_int_Tx_enable(com); */ 3848#endif 3849 splx(s); 3850 return; 3851 } 3852 if (tp->t_outq.c_cc != 0) { 3853 struct lbq *qp; 3854 struct lbq *next; 3855 3856 if (!com->obufs[0].l_queued) { 3857 com->obufs[0].l_tail 3858 = com->obuf1 + q_to_b(&tp->t_outq, com->obuf1, 3859#ifndef PC98 3860 sizeof com->obuf1); 3861#else 3862 com->obufsize); 3863#endif 3864 com->obufs[0].l_next = NULL; 3865 com->obufs[0].l_queued = TRUE; 3866 disable_intr(); 3867 if (com->state & CS_BUSY) { 3868 qp = com->obufq.l_next; 3869 while ((next = qp->l_next) != NULL) 3870 qp = next; 3871 qp->l_next = &com->obufs[0]; 3872 } else { 3873 com->obufq.l_head = com->obufs[0].l_head; 3874 com->obufq.l_tail = com->obufs[0].l_tail; 3875 com->obufq.l_next = &com->obufs[0]; 3876 com->state |= CS_BUSY; 3877 } 3878 enable_intr(); 3879 } 3880 if (tp->t_outq.c_cc != 0 && !com->obufs[1].l_queued) { 3881 com->obufs[1].l_tail 3882 = com->obuf2 + q_to_b(&tp->t_outq, com->obuf2, 3883#ifndef PC98 3884 sizeof com->obuf2); 3885#else 3886 com->obufsize); 3887#endif 3888 com->obufs[1].l_next = NULL; 3889 com->obufs[1].l_queued = TRUE; 3890 disable_intr(); 3891 if (com->state & CS_BUSY) { 3892 qp = com->obufq.l_next; 3893 while ((next = qp->l_next) != NULL) 3894 qp = next; 3895 qp->l_next = &com->obufs[1]; 3896 } else { 3897 com->obufq.l_head = com->obufs[1].l_head; 3898 com->obufq.l_tail = com->obufs[1].l_tail; 3899 com->obufq.l_next = &com->obufs[1]; 3900 com->state |= CS_BUSY; 3901 } 3902 enable_intr(); 3903 } 3904 tp->t_state |= TS_BUSY; 3905 } 3906 disable_intr(); 3907 if (com->state >= (CS_BUSY | CS_TTGO)) 3908 siointr1(com); /* fake interrupt to start output */ 3909 enable_intr(); 3910#ifdef PC98 3911/* if(IS_8251(com->pc98_if_type)) 3912 com_int_Tx_enable(com); */ 3913#endif 3914 ttwwakeup(tp); 3915 splx(s); 3916} 3917 3918static void 3919comstop(tp, rw) 3920 struct tty *tp; 3921 int rw; 3922{ 3923 struct com_s *com; 3924#ifdef PC98 3925 int port_shift = 0; 3926 int rsa98_tmp = 0; 3927#endif 3928 3929 com = com_addr(DEV_TO_UNIT(tp->t_dev)); 3930 if (com == NULL || com->gone) 3931 return; 3932#ifdef PC98 3933 if (!IS_8251(com->pc98_if_type)) 3934 port_shift = if_16550a_type[com->pc98_if_type & 0x0f].port_shift; 3935#endif 3936 disable_intr(); 3937 if (rw & FWRITE) { 3938 if (com->hasfifo) 3939#ifdef COM_ESP 3940 /* XXX avoid h/w bug. */ 3941 if (!com->esp) 3942#endif 3943#ifdef PC98 3944 outb(com->iobase + (com_fifo << port_shift), 3945 FIFO_XMT_RST | com->fifo_image); 3946 if (com->pc98_if_type == COM_IF_RSA98III) 3947 for(rsa98_tmp = 0; rsa98_tmp < 2048; rsa98_tmp++) 3948 outb(com->iobase + (com_fifo << port_shift), 3949 FIFO_XMT_RST | com->fifo_image); 3950#else 3951 outb(com->iobase + com_fifo, 3952 FIFO_XMT_RST | com->fifo_image); 3953#endif 3954 com->obufs[0].l_queued = FALSE; 3955 com->obufs[1].l_queued = FALSE; 3956 if (com->state & CS_ODONE) 3957 com_events -= LOTS_OF_EVENTS; 3958 com->state &= ~(CS_ODONE | CS_BUSY); 3959 com->tp->t_state &= ~TS_BUSY; 3960 } 3961 if (rw & FREAD) { 3962 if (com->hasfifo) 3963#ifdef COM_ESP 3964 /* XXX avoid h/w bug. */ 3965 if (!com->esp) 3966#endif 3967#ifdef PC98 3968 if (com->pc98_if_type == COM_IF_RSA98III) { 3969 for(rsa98_tmp = 0; rsa98_tmp < 2048; rsa98_tmp++) 3970 inb(com->data_port); 3971 } 3972 outb(com->iobase + (com_fifo << port_shift), 3973 FIFO_RCV_RST | com->fifo_image); 3974#else 3975 outb(com->iobase + com_fifo, 3976 FIFO_RCV_RST | com->fifo_image); 3977#endif 3978 com_events -= (com->iptr - com->ibuf); 3979 com->iptr = com->ibuf; 3980 } 3981 enable_intr(); 3982 comstart(tp); 3983} 3984 3985static int 3986commctl(com, bits, how) 3987 struct com_s *com; 3988 int bits; 3989 int how; 3990{ 3991 int mcr; 3992 int msr; 3993 3994 if (how == DMGET) { 3995 bits = TIOCM_LE; /* XXX - always enabled while open */ 3996 mcr = com->mcr_image; 3997 if (mcr & MCR_DTR) 3998 bits |= TIOCM_DTR; 3999 if (mcr & MCR_RTS) 4000 bits |= TIOCM_RTS; 4001 msr = com->prev_modem_status; 4002 if (msr & MSR_CTS) 4003 bits |= TIOCM_CTS; 4004 if (msr & MSR_DCD) 4005 bits |= TIOCM_CD; 4006 if (msr & MSR_DSR) 4007 bits |= TIOCM_DSR; 4008 /* 4009 * XXX - MSR_RI is naturally volatile, and we make MSR_TERI 4010 * more volatile by reading the modem status a lot. Perhaps 4011 * we should latch both bits until the status is read here. 4012 */ 4013 if (msr & (MSR_RI | MSR_TERI)) 4014 bits |= TIOCM_RI; 4015 return (bits); 4016 } 4017 mcr = 0; 4018 if (bits & TIOCM_DTR) 4019 mcr |= MCR_DTR; 4020 if (bits & TIOCM_RTS) 4021 mcr |= MCR_RTS; 4022 if (com->gone) 4023 return(0); 4024 disable_intr(); 4025 switch (how) { 4026 case DMSET: 4027 outb(com->modem_ctl_port, 4028 com->mcr_image = mcr | (com->mcr_image & MCR_IENABLE)); 4029 break; 4030 case DMBIS: 4031 outb(com->modem_ctl_port, com->mcr_image |= mcr); 4032 break; 4033 case DMBIC: 4034 outb(com->modem_ctl_port, com->mcr_image &= ~mcr); 4035 break; 4036 } 4037 enable_intr(); 4038 return (0); 4039} 4040 4041static void 4042siosettimeout() 4043{ 4044 struct com_s *com; 4045 bool_t someopen; 4046 int unit; 4047 4048 /* 4049 * Set our timeout period to 1 second if no polled devices are open. 4050 * Otherwise set it to max(1/200, 1/hz). 4051 * Enable timeouts iff some device is open. 4052 */ 4053 untimeout(comwakeup, (void *)NULL, sio_timeout_handle); 4054 sio_timeout = hz; 4055 someopen = FALSE; 4056 for (unit = 0; unit < sio_numunits; ++unit) { 4057 com = com_addr(unit); 4058 if (com != NULL && com->tp != NULL 4059 && com->tp->t_state & TS_ISOPEN && !com->gone) { 4060 someopen = TRUE; 4061 if (com->poll || com->poll_output) { 4062 sio_timeout = hz > 200 ? hz / 200 : 1; 4063 break; 4064 } 4065 } 4066 } 4067 if (someopen) { 4068 sio_timeouts_until_log = hz / sio_timeout; 4069 sio_timeout_handle = timeout(comwakeup, (void *)NULL, 4070 sio_timeout); 4071 } else { 4072 /* Flush error messages, if any. */ 4073 sio_timeouts_until_log = 1; 4074 comwakeup((void *)NULL); 4075 untimeout(comwakeup, (void *)NULL, sio_timeout_handle); 4076 } 4077} 4078 4079static void 4080comwakeup(chan) 4081 void *chan; 4082{ 4083 struct com_s *com; 4084 int unit; 4085 4086 sio_timeout_handle = timeout(comwakeup, (void *)NULL, sio_timeout); 4087 4088 /* 4089 * Recover from lost output interrupts. 4090 * Poll any lines that don't use interrupts. 4091 */ 4092 for (unit = 0; unit < sio_numunits; ++unit) { 4093 com = com_addr(unit); 4094 if (com != NULL && !com->gone 4095 && (com->state >= (CS_BUSY | CS_TTGO) || com->poll)) { 4096 disable_intr(); 4097 siointr1(com); 4098 enable_intr(); 4099 } 4100 } 4101 4102 /* 4103 * Check for and log errors, but not too often. 4104 */ 4105 if (--sio_timeouts_until_log > 0) 4106 return; 4107 sio_timeouts_until_log = hz / sio_timeout; 4108 for (unit = 0; unit < sio_numunits; ++unit) { 4109 int errnum; 4110 4111 com = com_addr(unit); 4112 if (com == NULL) 4113 continue; 4114 if (com->gone) 4115 continue; 4116 for (errnum = 0; errnum < CE_NTYPES; ++errnum) { 4117 u_int delta; 4118 u_long total; 4119 4120 disable_intr(); 4121 delta = com->delta_error_counts[errnum]; 4122 com->delta_error_counts[errnum] = 0; 4123 enable_intr(); 4124 if (delta == 0) 4125 continue; 4126 total = com->error_counts[errnum] += delta; 4127 log(LOG_ERR, "sio%d: %u more %s%s (total %lu)\n", 4128 unit, delta, error_desc[errnum], 4129 delta == 1 ? "" : "s", total); 4130 } 4131 } 4132} 4133 4134#ifdef PC98 4135/* commint is called when modem control line changes */ 4136static void 4137commint(dev_t dev) 4138{ 4139 register struct tty *tp; 4140 int stat,delta; 4141 struct com_s *com; 4142 int mynor,unit; 4143 4144 mynor = minor(dev); 4145 unit = MINOR_TO_UNIT(mynor); 4146 com = com_addr(unit); 4147 tp = com->tp; 4148 4149 stat = com_tiocm_get(com); 4150 delta = com_tiocm_get_delta(com); 4151 4152 if (com->state & CS_CTS_OFLOW) { 4153 if (stat & TIOCM_CTS) 4154 com->state |= CS_ODEVREADY; 4155 else 4156 com->state &= ~CS_ODEVREADY; 4157 } 4158 if ((delta & TIOCM_CAR) && (mynor & CALLOUT_MASK) == 0) { 4159 if (stat & TIOCM_CAR ) 4160 (void)(*linesw[tp->t_line].l_modem)(tp, 1); 4161 else if ((*linesw[tp->t_line].l_modem)(tp, 0) == 0) { 4162 /* negate DTR, RTS */ 4163 com_tiocm_bic(com, (tp->t_cflag & HUPCL) ? 4164 TIOCM_DTR|TIOCM_RTS|TIOCM_LE : TIOCM_LE ); 4165 /* disable IENABLE */ 4166 com_int_TxRx_disable( com ); 4167 } 4168 } 4169} 4170#endif 4171 4172static void 4173disc_optim(tp, t, com) 4174 struct tty *tp; 4175 struct termios *t; 4176 struct com_s *com; 4177{ 4178 if (!(t->c_iflag & (ICRNL | IGNCR | IMAXBEL | INLCR | ISTRIP | IXON)) 4179 && (!(t->c_iflag & BRKINT) || (t->c_iflag & IGNBRK)) 4180 && (!(t->c_iflag & PARMRK) 4181 || (t->c_iflag & (IGNPAR | IGNBRK)) == (IGNPAR | IGNBRK)) 4182 && !(t->c_lflag & (ECHO | ICANON | IEXTEN | ISIG | PENDIN)) 4183 && linesw[tp->t_line].l_rint == ttyinput) 4184 tp->t_state |= TS_CAN_BYPASS_L_RINT; 4185 else 4186 tp->t_state &= ~TS_CAN_BYPASS_L_RINT; 4187 com->hotchar = linesw[tp->t_line].l_hotchar; 4188} 4189 4190/* 4191 * Following are all routines needed for SIO to act as console 4192 */ 4193#include <sys/cons.h> 4194 4195struct siocnstate { 4196 u_char dlbl; 4197 u_char dlbh; 4198 u_char ier; 4199 u_char cfcr; 4200 u_char mcr; 4201}; 4202 4203static speed_t siocngetspeed __P((Port_t, struct speedtab *)); 4204static void siocnclose __P((struct siocnstate *sp, Port_t iobase)); 4205static void siocnopen __P((struct siocnstate *sp, Port_t iobase, int speed)); 4206static void siocntxwait __P((Port_t iobase)); 4207 4208static cn_probe_t siocnprobe; 4209static cn_init_t siocninit; 4210static cn_checkc_t siocncheckc; 4211static cn_getc_t siocngetc; 4212static cn_putc_t siocnputc; 4213 4214#ifdef __i386__ 4215CONS_DRIVER(sio, siocnprobe, siocninit, NULL, siocngetc, siocncheckc, 4216 siocnputc, NULL); 4217#endif 4218 4219/* To get the GDB related variables */ 4220#if DDB > 0 4221#include <ddb/ddb.h> 4222#endif 4223 4224static void 4225siocntxwait(iobase) 4226 Port_t iobase; 4227{ 4228 int timo; 4229 4230 /* 4231 * Wait for any pending transmission to finish. Required to avoid 4232 * the UART lockup bug when the speed is changed, and for normal 4233 * transmits. 4234 */ 4235 timo = 100000; 4236 while ((inb(iobase + com_lsr) & (LSR_TSRE | LSR_TXRDY)) 4237 != (LSR_TSRE | LSR_TXRDY) && --timo != 0) 4238 ; 4239} 4240 4241/* 4242 * Read the serial port specified and try to figure out what speed 4243 * it's currently running at. We're assuming the serial port has 4244 * been initialized and is basicly idle. This routine is only intended 4245 * to be run at system startup. 4246 * 4247 * If the value read from the serial port doesn't make sense, return 0. 4248 */ 4249 4250static speed_t 4251siocngetspeed(iobase, table) 4252 Port_t iobase; 4253 struct speedtab *table; 4254{ 4255 int code; 4256 u_char dlbh; 4257 u_char dlbl; 4258 u_char cfcr; 4259 4260 cfcr = inb(iobase + com_cfcr); 4261 outb(iobase + com_cfcr, CFCR_DLAB | cfcr); 4262 4263 dlbl = inb(iobase + com_dlbl); 4264 dlbh = inb(iobase + com_dlbh); 4265 4266 outb(iobase + com_cfcr, cfcr); 4267 4268 code = dlbh << 8 | dlbl; 4269 4270 for (; table->sp_speed != -1; table++) 4271 if (table->sp_code == code) 4272 return (table->sp_speed); 4273 4274 return (0); /* didn't match anything sane */ 4275} 4276 4277static void 4278siocnopen(sp, iobase, speed) 4279 struct siocnstate *sp; 4280 Port_t iobase; 4281 int speed; 4282{ 4283 int divisor; 4284 u_char dlbh; 4285 u_char dlbl; 4286 4287 /* 4288 * Save all the device control registers except the fifo register 4289 * and set our default ones (cs8 -parenb speed=comdefaultrate). 4290 * We can't save the fifo register since it is read-only. 4291 */ 4292 sp->ier = inb(iobase + com_ier); 4293 outb(iobase + com_ier, 0); /* spltty() doesn't stop siointr() */ 4294 siocntxwait(iobase); 4295 sp->cfcr = inb(iobase + com_cfcr); 4296 outb(iobase + com_cfcr, CFCR_DLAB | CFCR_8BITS); 4297 sp->dlbl = inb(iobase + com_dlbl); 4298 sp->dlbh = inb(iobase + com_dlbh); 4299 /* 4300 * Only set the divisor registers if they would change, since on 4301 * some 16550 incompatibles (Startech), setting them clears the 4302 * data input register. This also reduces the effects of the 4303 * UMC8669F bug. 4304 */ 4305 divisor = ttspeedtab(speed, comspeedtab); 4306 dlbl = divisor & 0xFF; 4307 if (sp->dlbl != dlbl) 4308 outb(iobase + com_dlbl, dlbl); 4309 dlbh = (u_int) divisor >> 8; 4310 if (sp->dlbh != dlbh) 4311 outb(iobase + com_dlbh, dlbh); 4312 outb(iobase + com_cfcr, CFCR_8BITS); 4313 sp->mcr = inb(iobase + com_mcr); 4314 /* 4315 * We don't want interrupts, but must be careful not to "disable" 4316 * them by clearing the MCR_IENABLE bit, since that might cause 4317 * an interrupt by floating the IRQ line. 4318 */ 4319 outb(iobase + com_mcr, (sp->mcr & MCR_IENABLE) | MCR_DTR | MCR_RTS); 4320} 4321 4322static void 4323siocnclose(sp, iobase) 4324 struct siocnstate *sp; 4325 Port_t iobase; 4326{ 4327 /* 4328 * Restore the device control registers. 4329 */ 4330 siocntxwait(iobase); 4331 outb(iobase + com_cfcr, CFCR_DLAB | CFCR_8BITS); 4332 if (sp->dlbl != inb(iobase + com_dlbl)) 4333 outb(iobase + com_dlbl, sp->dlbl); 4334 if (sp->dlbh != inb(iobase + com_dlbh)) 4335 outb(iobase + com_dlbh, sp->dlbh); 4336 outb(iobase + com_cfcr, sp->cfcr); 4337 /* 4338 * XXX damp oscillations of MCR_DTR and MCR_RTS by not restoring them. 4339 */ 4340 outb(iobase + com_mcr, sp->mcr | MCR_DTR | MCR_RTS); 4341 outb(iobase + com_ier, sp->ier); 4342} 4343 4344static void 4345siocnprobe(cp) 4346 struct consdev *cp; 4347{ 4348 speed_t boot_speed; 4349 u_char cfcr; 4350 int s, unit; 4351 struct siocnstate sp; 4352 4353 /* 4354 * Find our first enabled console, if any. If it is a high-level 4355 * console device, then initialize it and return successfully. 4356 * If it is a low-level console device, then initialize it and 4357 * return unsuccessfully. It must be initialized in both cases 4358 * for early use by console drivers and debuggers. Initializing 4359 * the hardware is not necessary in all cases, since the i/o 4360 * routines initialize it on the fly, but it is necessary if 4361 * input might arrive while the hardware is switched back to an 4362 * uninitialized state. We can't handle multiple console devices 4363 * yet because our low-level routines don't take a device arg. 4364 * We trust the user to set the console flags properly so that we 4365 * don't need to probe. 4366 */ 4367 cp->cn_pri = CN_DEAD; 4368 4369 for (unit = 0; unit < 16; unit++) { /* XXX need to know how many */ 4370 int flags; 4371 int disabled; 4372 if (resource_int_value("sio", unit, "disabled", &disabled) == 0) { 4373 if (disabled) 4374 continue; 4375 } 4376 if (resource_int_value("sio", unit, "flags", &flags)) 4377 continue; 4378 if (COM_CONSOLE(flags) || COM_DEBUGGER(flags)) { 4379 int port; 4380 Port_t iobase; 4381 4382 if (resource_int_value("sio", unit, "port", &port)) 4383 continue; 4384 iobase = port; 4385 s = spltty(); 4386 if (boothowto & RB_SERIAL) { 4387 boot_speed = siocngetspeed(iobase, comspeedtab); 4388 if (boot_speed) 4389 comdefaultrate = boot_speed; 4390 } 4391 4392 /* 4393 * Initialize the divisor latch. We can't rely on 4394 * siocnopen() to do this the first time, since it 4395 * avoids writing to the latch if the latch appears 4396 * to have the correct value. Also, if we didn't 4397 * just read the speed from the hardware, then we 4398 * need to set the speed in hardware so that 4399 * switching it later is null. 4400 */ 4401 cfcr = inb(iobase + com_cfcr); 4402 outb(iobase + com_cfcr, CFCR_DLAB | cfcr); 4403 outb(iobase + com_dlbl, 4404 COMBRD(comdefaultrate) & 0xff); 4405 outb(iobase + com_dlbh, 4406 (u_int) COMBRD(comdefaultrate) >> 8); 4407 outb(iobase + com_cfcr, cfcr); 4408 4409 siocnopen(&sp, iobase, comdefaultrate); 4410 4411 splx(s); 4412 if (COM_CONSOLE(flags) && !COM_LLCONSOLE(flags)) { 4413 cp->cn_dev = makedev(CDEV_MAJOR, unit); 4414 cp->cn_pri = COM_FORCECONSOLE(flags) 4415 || boothowto & RB_SERIAL 4416 ? CN_REMOTE : CN_NORMAL; 4417 siocniobase = iobase; 4418 siocnunit = unit; 4419 } 4420 if (COM_DEBUGGER(flags)) { 4421 printf("sio%d: gdb debugging port\n", unit); 4422 siogdbiobase = iobase; 4423 siogdbunit = unit; 4424#if DDB > 0 4425 gdbdev = makedev(CDEV_MAJOR, unit); 4426 gdb_getc = siocngetc; 4427 gdb_putc = siocnputc; 4428#endif 4429 } 4430 } 4431 } 4432#ifdef __i386__ 4433#if DDB > 0 4434 /* 4435 * XXX Ugly Compatability. 4436 * If no gdb port has been specified, set it to be the console 4437 * as some configuration files don't specify the gdb port. 4438 */ 4439 if (gdbdev == NODEV && (boothowto & RB_GDB)) { 4440 printf("Warning: no GDB port specified. Defaulting to sio%d.\n", 4441 siocnunit); 4442 printf("Set flag 0x80 on desired GDB port in your\n"); 4443 printf("configuration file (currently sio only).\n"); 4444 siogdbiobase = siocniobase; 4445 siogdbunit = siocnunit; 4446 gdbdev = makedev(CDEV_MAJOR, siocnunit); 4447 gdb_getc = siocngetc; 4448 gdb_putc = siocnputc; 4449 } 4450#endif 4451#endif 4452} 4453 4454#ifdef __alpha__ 4455 4456CONS_DRIVER(sio, NULL, NULL, NULL, siocngetc, siocncheckc, siocnputc, NULL); 4457 4458int 4459siocnattach(port, speed) 4460 int port; 4461 int speed; 4462{ 4463 int s; 4464 u_char cfcr; 4465 struct siocnstate sp; 4466 4467 siocniobase = port; 4468 comdefaultrate = speed; 4469 sio_consdev.cn_pri = CN_NORMAL; 4470 sio_consdev.cn_dev = makedev(CDEV_MAJOR, 0); 4471 4472 s = spltty(); 4473 4474 /* 4475 * Initialize the divisor latch. We can't rely on 4476 * siocnopen() to do this the first time, since it 4477 * avoids writing to the latch if the latch appears 4478 * to have the correct value. Also, if we didn't 4479 * just read the speed from the hardware, then we 4480 * need to set the speed in hardware so that 4481 * switching it later is null. 4482 */ 4483 cfcr = inb(siocniobase + com_cfcr); 4484 outb(siocniobase + com_cfcr, CFCR_DLAB | cfcr); 4485 outb(siocniobase + com_dlbl, 4486 COMBRD(comdefaultrate) & 0xff); 4487 outb(siocniobase + com_dlbh, 4488 (u_int) COMBRD(comdefaultrate) >> 8); 4489 outb(siocniobase + com_cfcr, cfcr); 4490 4491 siocnopen(&sp, siocniobase, comdefaultrate); 4492 splx(s); 4493 4494 cn_tab = &sio_consdev; 4495 return (0); 4496} 4497 4498int 4499siogdbattach(port, speed) 4500 int port; 4501 int speed; 4502{ 4503 int s; 4504 u_char cfcr; 4505 struct siocnstate sp; 4506 4507 siogdbiobase = port; 4508 gdbdefaultrate = speed; 4509 4510 s = spltty(); 4511 4512 /* 4513 * Initialize the divisor latch. We can't rely on 4514 * siocnopen() to do this the first time, since it 4515 * avoids writing to the latch if the latch appears 4516 * to have the correct value. Also, if we didn't 4517 * just read the speed from the hardware, then we 4518 * need to set the speed in hardware so that 4519 * switching it later is null. 4520 */ 4521 cfcr = inb(siogdbiobase + com_cfcr); 4522 outb(siogdbiobase + com_cfcr, CFCR_DLAB | cfcr); 4523 outb(siogdbiobase + com_dlbl, 4524 COMBRD(gdbdefaultrate) & 0xff); 4525 outb(siogdbiobase + com_dlbh, 4526 (u_int) COMBRD(gdbdefaultrate) >> 8); 4527 outb(siogdbiobase + com_cfcr, cfcr); 4528 4529 siocnopen(&sp, siogdbiobase, gdbdefaultrate); 4530 splx(s); 4531 4532 return (0); 4533} 4534 4535#endif 4536 4537static void 4538siocninit(cp) 4539 struct consdev *cp; 4540{ 4541 comconsole = DEV_TO_UNIT(cp->cn_dev); 4542} 4543 4544static int 4545siocncheckc(dev) 4546 dev_t dev; 4547{ 4548 int c; 4549 Port_t iobase; 4550 int s; 4551 struct siocnstate sp; 4552 4553 if (minor(dev) == siogdbunit) 4554 iobase = siogdbiobase; 4555 else 4556 iobase = siocniobase; 4557 s = spltty(); 4558 siocnopen(&sp, iobase, comdefaultrate); 4559 if (inb(iobase + com_lsr) & LSR_RXRDY) 4560 c = inb(iobase + com_data); 4561 else 4562 c = -1; 4563 siocnclose(&sp, iobase); 4564 splx(s); 4565 return (c); 4566} 4567 4568 4569int 4570siocngetc(dev) 4571 dev_t dev; 4572{ 4573 int c; 4574 Port_t iobase; 4575 int s; 4576 struct siocnstate sp; 4577 4578 if (minor(dev) == siogdbunit) 4579 iobase = siogdbiobase; 4580 else 4581 iobase = siocniobase; 4582 s = spltty(); 4583 siocnopen(&sp, iobase, comdefaultrate); 4584 while (!(inb(iobase + com_lsr) & LSR_RXRDY)) 4585 ; 4586 c = inb(iobase + com_data); 4587 siocnclose(&sp, iobase); 4588 splx(s); 4589 return (c); 4590} 4591 4592void 4593siocnputc(dev, c) 4594 dev_t dev; 4595 int c; 4596{ 4597 int s; 4598 struct siocnstate sp; 4599 Port_t iobase; 4600 4601 if (minor(dev) == siogdbunit) 4602 iobase = siogdbiobase; 4603 else 4604 iobase = siocniobase; 4605 s = spltty(); 4606 siocnopen(&sp, iobase, comdefaultrate); 4607 siocntxwait(iobase); 4608 outb(iobase + com_data, c); 4609 siocnclose(&sp, iobase); 4610 splx(s); 4611} 4612 4613#ifdef __alpha__ 4614int 4615siogdbgetc() 4616{ 4617 int c; 4618 Port_t iobase; 4619 int s; 4620 struct siocnstate sp; 4621 4622 iobase = siogdbiobase; 4623 s = spltty(); 4624 siocnopen(&sp, iobase, gdbdefaultrate); 4625 while (!(inb(iobase + com_lsr) & LSR_RXRDY)) 4626 ; 4627 c = inb(iobase + com_data); 4628 siocnclose(&sp, iobase); 4629 splx(s); 4630 return (c); 4631} 4632 4633void 4634siogdbputc(c) 4635 int c; 4636{ 4637 int s; 4638 struct siocnstate sp; 4639 4640 s = spltty(); 4641 siocnopen(&sp, siogdbiobase, gdbdefaultrate); 4642 siocntxwait(siogdbiobase); 4643 outb(siogdbiobase + com_data, c); 4644 siocnclose(&sp, siogdbiobase); 4645 splx(s); 4646} 4647#endif 4648 4649DRIVER_MODULE(sio, isa, sio_isa_driver, sio_devclass, 0, 0); 4650#if NCARD > 0 4651DRIVER_MODULE(sio, pccard, sio_pccard_driver, sio_devclass, 0, 0); 4652#endif 4653#if NPCI > 0 4654DRIVER_MODULE(sio, pci, sio_pci_driver, sio_devclass, 0, 0); 4655#endif 4656 4657#ifdef PC98 4658/* 4659 * pc98 local function 4660 */ 4661 4662static void 4663com_tiocm_set(struct com_s *com, int msr) 4664{ 4665 int s; 4666 int tmp = 0; 4667 int mask = CMD8251_TxEN|CMD8251_RxEN|CMD8251_DTR|CMD8251_RTS; 4668 4669 s=spltty(); 4670 com->pc98_prev_modem_status = ( msr & (TIOCM_LE|TIOCM_DTR|TIOCM_RTS) ) 4671 | ( com->pc98_prev_modem_status & ~(TIOCM_LE|TIOCM_DTR|TIOCM_RTS) ); 4672 tmp |= (CMD8251_TxEN|CMD8251_RxEN); 4673 if ( msr & TIOCM_DTR ) tmp |= CMD8251_DTR; 4674 if ( msr & TIOCM_RTS ) tmp |= CMD8251_RTS; 4675 pc98_i8251_clear_or_cmd( com, mask, tmp ); 4676 splx(s); 4677} 4678 4679static void 4680com_tiocm_bis(struct com_s *com, int msr) 4681{ 4682 int s; 4683 int tmp = 0; 4684 4685 s=spltty(); 4686 com->pc98_prev_modem_status |= ( msr & (TIOCM_LE|TIOCM_DTR|TIOCM_RTS) ); 4687 tmp |= CMD8251_TxEN|CMD8251_RxEN; 4688 if ( msr & TIOCM_DTR ) tmp |= CMD8251_DTR; 4689 if ( msr & TIOCM_RTS ) tmp |= CMD8251_RTS; 4690 4691 pc98_i8251_or_cmd( com, tmp ); 4692 splx(s); 4693} 4694 4695static void 4696com_tiocm_bic(struct com_s *com, int msr) 4697{ 4698 int s; 4699 int tmp = msr; 4700 4701 s=spltty(); 4702 com->pc98_prev_modem_status &= ~( msr & (TIOCM_LE|TIOCM_DTR|TIOCM_RTS) ); 4703 if ( msr & TIOCM_DTR ) tmp |= CMD8251_DTR; 4704 if ( msr & TIOCM_RTS ) tmp |= CMD8251_RTS; 4705 4706 pc98_i8251_clear_cmd( com, tmp ); 4707 splx(s); 4708} 4709 4710static int 4711com_tiocm_get(struct com_s *com) 4712{ 4713 return( com->pc98_prev_modem_status ); 4714} 4715 4716static int 4717com_tiocm_get_delta(struct com_s *com) 4718{ 4719 int tmp; 4720 4721 tmp = com->pc98_modem_delta; 4722 com->pc98_modem_delta = 0; 4723 return( tmp ); 4724} 4725 4726/* convert to TIOCM_?? ( ioctl.h ) */ 4727static int 4728pc98_get_modem_status(struct com_s *com) 4729{ 4730 register int msr; 4731 4732 msr = com->pc98_prev_modem_status 4733 & ~(TIOCM_CAR|TIOCM_RI|TIOCM_DSR|TIOCM_CTS); 4734 if (com->pc98_8251fifo_enable) { 4735 int stat2; 4736 4737 stat2 = inb(I8251F_msr); 4738 if ( stat2 & CICSCDF_CD ) msr |= TIOCM_CAR; 4739 if ( stat2 & CICSCDF_CI ) msr |= TIOCM_RI; 4740 if ( stat2 & CICSCDF_DR ) msr |= TIOCM_DSR; 4741 if ( stat2 & CICSCDF_CS ) msr |= TIOCM_CTS; 4742#if COM_CARRIER_DETECT_EMULATE 4743 if ( msr & (TIOCM_DSR|TIOCM_CTS) ) { 4744 msr |= TIOCM_CAR; 4745 } 4746#endif 4747 } else { 4748 int stat, stat2; 4749 4750 stat = inb(com->sts_port); 4751 stat2 = inb(com->in_modem_port); 4752 if ( !(stat2 & CICSCD_CD) ) msr |= TIOCM_CAR; 4753 if ( !(stat2 & CICSCD_CI) ) msr |= TIOCM_RI; 4754 if ( stat & STS8251_DSR ) msr |= TIOCM_DSR; 4755 if ( !(stat2 & CICSCD_CS) ) msr |= TIOCM_CTS; 4756#if COM_CARRIER_DETECT_EMULATE 4757 if ( msr & (TIOCM_DSR|TIOCM_CTS) ) { 4758 msr |= TIOCM_CAR; 4759 } 4760#endif 4761 } 4762 return(msr); 4763} 4764 4765static void 4766pc98_check_msr(void* chan) 4767{ 4768 int msr, delta; 4769 int s; 4770 register struct tty *tp; 4771 struct com_s *com; 4772 int mynor; 4773 int unit; 4774 dev_t dev; 4775 4776 dev=(dev_t)chan; 4777 mynor = minor(dev); 4778 unit = MINOR_TO_UNIT(mynor); 4779 com = com_addr(unit); 4780 tp = com->tp; 4781 4782 s = spltty(); 4783 msr = pc98_get_modem_status(com); 4784 /* make change flag */ 4785 delta = msr ^ com->pc98_prev_modem_status; 4786 if ( delta & TIOCM_CAR ) { 4787 if ( com->modem_car_chg_timer ) { 4788 if ( -- com->modem_car_chg_timer ) 4789 msr ^= TIOCM_CAR; 4790 } else { 4791 if ((com->modem_car_chg_timer = (msr & TIOCM_CAR) ? 4792 DCD_ON_RECOGNITION : DCD_OFF_TOLERANCE) != 0) 4793 msr ^= TIOCM_CAR; 4794 } 4795 } else 4796 com->modem_car_chg_timer = 0; 4797 delta = ( msr ^ com->pc98_prev_modem_status ) & 4798 (TIOCM_CAR|TIOCM_RI|TIOCM_DSR|TIOCM_CTS); 4799 com->pc98_prev_modem_status = msr; 4800 delta = ( com->pc98_modem_delta |= delta ); 4801 splx(s); 4802 if ( com->modem_checking || (tp->t_state & (TS_ISOPEN)) ) { 4803 if ( delta ) { 4804 commint(dev); 4805 } 4806 timeout(pc98_check_msr, (caddr_t)dev, 4807 PC98_CHECK_MODEM_INTERVAL); 4808 } else { 4809 com->modem_checking = 0; 4810 } 4811} 4812 4813static void 4814pc98_msrint_start(dev_t dev) 4815{ 4816 struct com_s *com; 4817 int mynor; 4818 int unit; 4819 int s = spltty(); 4820 4821 mynor = minor(dev); 4822 unit = MINOR_TO_UNIT(mynor); 4823 com = com_addr(unit); 4824 /* modem control line check routine envoke interval is 1/10 sec */ 4825 if ( com->modem_checking == 0 ) { 4826 com->pc98_prev_modem_status = pc98_get_modem_status(com); 4827 com->pc98_modem_delta = 0; 4828 timeout(pc98_check_msr, (caddr_t)dev, 4829 PC98_CHECK_MODEM_INTERVAL); 4830 com->modem_checking = 1; 4831 } 4832 splx(s); 4833} 4834 4835static void 4836pc98_disable_i8251_interrupt(struct com_s *com, int mod) 4837{ 4838 /* disable interrupt */ 4839 register int tmp; 4840 4841 mod |= ~(IEN_Tx|IEN_TxEMP|IEN_Rx); 4842 COM_INT_DISABLE 4843 tmp = inb( com->intr_ctrl_port ) & ~(IEN_Tx|IEN_TxEMP|IEN_Rx); 4844 outb( com->intr_ctrl_port, (com->intr_enable&=~mod) | tmp ); 4845 COM_INT_ENABLE 4846} 4847 4848static void 4849pc98_enable_i8251_interrupt(struct com_s *com, int mod) 4850{ 4851 register int tmp; 4852 4853 COM_INT_DISABLE 4854 tmp = inb( com->intr_ctrl_port ) & ~(IEN_Tx|IEN_TxEMP|IEN_Rx); 4855 outb( com->intr_ctrl_port, (com->intr_enable|=mod) | tmp ); 4856 COM_INT_ENABLE 4857} 4858 4859static int 4860pc98_check_i8251_interrupt(struct com_s *com) 4861{ 4862 return ( com->intr_enable & 0x07 ); 4863} 4864 4865static void 4866pc98_i8251_clear_cmd(struct com_s *com, int x) 4867{ 4868 int tmp; 4869 4870 COM_INT_DISABLE 4871 tmp = com->pc98_prev_siocmd & ~(x); 4872 if (com->pc98_8251fifo_enable) 4873 outb(I8251F_fcr, 0); 4874 outb(com->cmd_port, tmp); 4875 com->pc98_prev_siocmd = tmp & ~(CMD8251_ER|CMD8251_RESET|CMD8251_EH); 4876 if (com->pc98_8251fifo_enable) 4877 outb(I8251F_fcr, CTRL8251F_ENABLE); 4878 COM_INT_ENABLE 4879} 4880 4881static void 4882pc98_i8251_or_cmd(struct com_s *com, int x) 4883{ 4884 int tmp; 4885 4886 COM_INT_DISABLE 4887 if (com->pc98_8251fifo_enable) 4888 outb(I8251F_fcr, 0); 4889 tmp = com->pc98_prev_siocmd | (x); 4890 outb(com->cmd_port, tmp); 4891 com->pc98_prev_siocmd = tmp & ~(CMD8251_ER|CMD8251_RESET|CMD8251_EH); 4892 if (com->pc98_8251fifo_enable) 4893 outb(I8251F_fcr, CTRL8251F_ENABLE); 4894 COM_INT_ENABLE 4895} 4896 4897static void 4898pc98_i8251_set_cmd(struct com_s *com, int x) 4899{ 4900 int tmp; 4901 4902 COM_INT_DISABLE 4903 if (com->pc98_8251fifo_enable) 4904 outb(I8251F_fcr, 0); 4905 tmp = (x); 4906 outb(com->cmd_port, tmp); 4907 com->pc98_prev_siocmd = tmp & ~(CMD8251_ER|CMD8251_RESET|CMD8251_EH); 4908 if (com->pc98_8251fifo_enable) 4909 outb(I8251F_fcr, CTRL8251F_ENABLE); 4910 COM_INT_ENABLE 4911} 4912 4913static void 4914pc98_i8251_clear_or_cmd(struct com_s *com, int clr, int x) 4915{ 4916 int tmp; 4917 COM_INT_DISABLE 4918 if (com->pc98_8251fifo_enable) 4919 outb(I8251F_fcr, 0); 4920 tmp = com->pc98_prev_siocmd & ~(clr); 4921 tmp |= (x); 4922 outb(com->cmd_port, tmp); 4923 com->pc98_prev_siocmd = tmp & ~(CMD8251_ER|CMD8251_RESET|CMD8251_EH); 4924 if (com->pc98_8251fifo_enable) 4925 outb(I8251F_fcr, CTRL8251F_ENABLE); 4926 COM_INT_ENABLE 4927} 4928 4929static int 4930pc98_i8251_get_cmd(struct com_s *com) 4931{ 4932 return com->pc98_prev_siocmd; 4933} 4934 4935static int 4936pc98_i8251_get_mod(struct com_s *com) 4937{ 4938 return com->pc98_prev_siomod; 4939} 4940 4941static void 4942pc98_i8251_reset(struct com_s *com, int mode, int command) 4943{ 4944 if (com->pc98_8251fifo_enable) 4945 outb(I8251F_fcr, 0); 4946 outb(com->cmd_port, 0); /* dummy */ 4947 DELAY(2); 4948 outb(com->cmd_port, 0); /* dummy */ 4949 DELAY(2); 4950 outb(com->cmd_port, 0); /* dummy */ 4951 DELAY(2); 4952 outb(com->cmd_port, CMD8251_RESET); /* internal reset */ 4953 DELAY(2); 4954 outb(com->cmd_port, mode ); /* mode register */ 4955 com->pc98_prev_siomod = mode; 4956 DELAY(2); 4957 pc98_i8251_set_cmd( com, (command|CMD8251_ER) ); 4958 DELAY(10); 4959 if (com->pc98_8251fifo_enable) 4960 outb(I8251F_fcr, CTRL8251F_ENABLE | 4961 CTRL8251F_XMT_RST | CTRL8251F_RCV_RST); 4962} 4963 4964static void 4965pc98_check_sysclock(void) 4966{ 4967 /* get system clock from port */ 4968 if ( pc98_machine_type & M_8M ) { 4969 /* 8 MHz system & H98 */ 4970 sysclock = 8; 4971 } else { 4972 /* 5 MHz system */ 4973 sysclock = 5; 4974 } 4975} 4976 4977static void 4978com_cflag_and_speed_set( struct com_s *com, int cflag, int speed) 4979{ 4980 int cfcr=0, count; 4981 int previnterrupt; 4982 4983 count = pc98_ttspeedtab( com, speed ); 4984 if ( count < 0 ) return; 4985 4986 previnterrupt = pc98_check_i8251_interrupt(com); 4987 pc98_disable_i8251_interrupt( com, IEN_Tx|IEN_TxEMP|IEN_Rx ); 4988 4989 switch ( cflag&CSIZE ) { 4990 case CS5: 4991 cfcr = MOD8251_5BITS; break; 4992 case CS6: 4993 cfcr = MOD8251_6BITS; break; 4994 case CS7: 4995 cfcr = MOD8251_7BITS; break; 4996 case CS8: 4997 cfcr = MOD8251_8BITS; break; 4998 } 4999 if ( cflag&PARENB ) { 5000 if ( cflag&PARODD ) 5001 cfcr |= MOD8251_PODD; 5002 else 5003 cfcr |= MOD8251_PEVEN; 5004 } else 5005 cfcr |= MOD8251_PDISAB; 5006 5007 if ( cflag&CSTOPB ) 5008 cfcr |= MOD8251_STOP2; 5009 else 5010 cfcr |= MOD8251_STOP1; 5011 5012 if ( count & 0x10000 ) 5013 cfcr |= MOD8251_CLKX1; 5014 else 5015 cfcr |= MOD8251_CLKX16; 5016 5017 if (epson_machine_id != 0x20) { /* XXX */ 5018 int tmp; 5019 while (!((tmp = inb(com->sts_port)) & STS8251_TxEMP)) 5020 ; 5021 } 5022 /* set baud rate from ospeed */ 5023 pc98_set_baud_rate( com, count ); 5024 5025 if ( cfcr != pc98_i8251_get_mod(com) ) 5026 pc98_i8251_reset(com, cfcr, pc98_i8251_get_cmd(com) ); 5027 5028 pc98_enable_i8251_interrupt( com, previnterrupt ); 5029} 5030 5031static int 5032pc98_ttspeedtab(struct com_s *com, int speed) 5033{ 5034 int if_type, effect_sp, count = -1, mod; 5035 5036 if_type = com->pc98_if_type & 0x0f; 5037 5038 switch (com->pc98_if_type) { 5039 case COM_IF_INTERNAL: 5040 if (PC98SIO_baud_rate_port(if_type) != -1) { 5041 count = ttspeedtab(speed, if_8251_type[if_type].speedtab); 5042 if (count > 0) { 5043 count |= COM1_EXT_CLOCK; 5044 break; 5045 } 5046 } 5047 5048 /* for *1CLK asynchronous! mode, TEFUTEFU */ 5049 mod = (sysclock == 5) ? 2457600 : 1996800; 5050 effect_sp = ttspeedtab( speed, pc98speedtab ); 5051 if ( effect_sp < 0 ) /* XXX */ 5052 effect_sp = ttspeedtab( (speed - 1), pc98speedtab ); 5053 if ( effect_sp <= 0 ) 5054 return effect_sp; 5055 if ( effect_sp == speed ) 5056 mod /= 16; 5057 if ( mod % effect_sp ) 5058 return(-1); 5059 count = mod / effect_sp; 5060 if ( count > 65535 ) 5061 return(-1); 5062 if ( effect_sp != speed ) 5063 count |= 0x10000; 5064 break; 5065 case COM_IF_PC9861K_1: 5066 case COM_IF_PC9861K_2: 5067 count = 1; 5068 break; 5069 case COM_IF_IND_SS_1: 5070 case COM_IF_IND_SS_2: 5071 case COM_IF_PIO9032B_1: 5072 case COM_IF_PIO9032B_2: 5073 if ( speed == 0 ) return 0; 5074 count = ttspeedtab( speed, if_8251_type[if_type].speedtab ); 5075 break; 5076 case COM_IF_B98_01_1: 5077 case COM_IF_B98_01_2: 5078 if ( speed == 0 ) return 0; 5079 count = ttspeedtab( speed, if_8251_type[if_type].speedtab ); 5080#ifdef B98_01_OLD 5081 if (count == 0 || count == 1) { 5082 count += 4; 5083 count |= 0x20000; /* x1 mode for 76800 and 153600 */ 5084 } 5085#endif 5086 break; 5087 } 5088 5089 return count; 5090} 5091 5092static void 5093pc98_set_baud_rate( struct com_s *com, int count ) 5094{ 5095 int if_type, io, s; 5096 5097 if_type = com->pc98_if_type & 0x0f; 5098 io = com->iobase & 0xff00; 5099 5100 switch (com->pc98_if_type) { 5101 case COM_IF_INTERNAL: 5102 if (PC98SIO_baud_rate_port(if_type) != -1) { 5103 if (count & COM1_EXT_CLOCK) { 5104 outb((Port_t)PC98SIO_baud_rate_port(if_type), count & 0xff); 5105 break; 5106 } else { 5107 outb((Port_t)PC98SIO_baud_rate_port(if_type), 0x09); 5108 } 5109 } 5110 5111 if ( count < 0 ) { 5112 printf( "[ Illegal count : %d ]", count ); 5113 return; 5114 } else if ( count == 0 ) 5115 return; 5116 /* set i8253 */ 5117 s = splclock(); 5118 if (count != 3) 5119 outb( 0x77, 0xb6 ); 5120 else 5121 outb( 0x77, 0xb4 ); 5122 outb( 0x5f, 0); 5123 outb( 0x75, count & 0xff ); 5124 outb( 0x5f, 0); 5125 outb( 0x75, (count >> 8) & 0xff ); 5126 splx(s); 5127 break; 5128 case COM_IF_IND_SS_1: 5129 case COM_IF_IND_SS_2: 5130 outb(io | PC98SIO_intr_ctrl_port(if_type), 0); 5131 outb(io | PC98SIO_baud_rate_port(if_type), 0); 5132 outb(io | PC98SIO_baud_rate_port(if_type), 0xc0); 5133 outb(io | PC98SIO_baud_rate_port(if_type), (count >> 8) | 0x80); 5134 outb(io | PC98SIO_baud_rate_port(if_type), count & 0xff); 5135 break; 5136 case COM_IF_PIO9032B_1: 5137 case COM_IF_PIO9032B_2: 5138 outb(io | PC98SIO_baud_rate_port(if_type), count); 5139 break; 5140 case COM_IF_B98_01_1: 5141 case COM_IF_B98_01_2: 5142 outb(io | PC98SIO_baud_rate_port(if_type), count & 0x0f); 5143#ifdef B98_01_OLD 5144 /* 5145 * Some old B98_01 board should be controlled 5146 * in different way, but this hasn't been tested yet. 5147 */ 5148 outb(io | PC98SIO_func_port(if_type), 5149 (count & 0x20000) ? 0xf0 : 0xf2); 5150#endif 5151 break; 5152 } 5153} 5154static int 5155pc98_check_if_type(device_t dev, struct siodev *iod) 5156{ 5157 int irr, io, if_type, tmp; 5158 static short irq_tab[2][8] = { 5159 { 3, 5, 6, 9, 10, 12, 13, -1}, 5160 { 3, 10, 12, 13, 5, 6, 9, -1} 5161 }; 5162 5163 iod->if_type = if_type = GET_IFTYPE(device_get_flags(dev)); 5164 if ((if_type < 0 || if_type > COM_IF_END1) && 5165 (if_type < 0x10 || if_type > COM_IF_END2)) 5166 return(-1); 5167 if_type &= 0x0f; 5168 iod->irq = 0; 5169 io = isa_get_port(dev) & 0xff00; 5170 5171 if (IS_8251(iod->if_type)) { 5172 if (PC98SIO_func_port(if_type) != -1) { 5173 outb(io | PC98SIO_func_port(if_type), 0xf2); 5174 tmp = ttspeedtab(9600, if_8251_type[if_type].speedtab); 5175 if (tmp != -1 && PC98SIO_baud_rate_port(if_type) != -1) 5176 outb(io | PC98SIO_baud_rate_port(if_type), tmp); 5177 } 5178 5179 iod->cmd = io | PC98SIO_cmd_port(if_type); 5180 iod->sts = io | PC98SIO_sts_port(if_type); 5181 iod->mod = io | PC98SIO_in_modem_port(if_type); 5182 iod->ctrl = io | PC98SIO_intr_ctrl_port(if_type); 5183 5184 if (iod->if_type == COM_IF_INTERNAL) { 5185 iod->irq = 4; 5186 5187 if (pc98_check_8251vfast()) { 5188 PC98SIO_baud_rate_port(if_type) = I8251F_div; 5189 if_8251_type[if_type].speedtab = pc98fast_speedtab; 5190 } 5191 } else { 5192 tmp = inb( iod->mod ) & if_8251_type[if_type].irr_mask; 5193 if ((isa_get_port(dev) & 0xff) == IO_COM2) 5194 iod->irq = irq_tab[0][tmp]; 5195 else 5196 iod->irq = irq_tab[1][tmp]; 5197 } 5198 } else { 5199 irr = if_16550a_type[if_type].irr_read; 5200#ifdef COM_MULTIPORT 5201 if (!COM_ISMULTIPORT(device_get_flags(dev)) || 5202 device_get_unit(dev) == COM_MPMASTER(device_get_flags(dev))) 5203#endif 5204 if (irr != -1) { 5205 tmp = inb(io | irr); 5206 if (isa_get_port(dev) & 0x01) /* XXX depend on RSB-384 */ 5207 iod->irq = irq_tab[1][tmp >> 3]; 5208 else 5209 iod->irq = irq_tab[0][tmp & 0x07]; 5210 } 5211 } 5212 if ( iod->irq == -1 ) return -1; 5213 5214 return 0; 5215} 5216static int 5217pc98_set_ioport(struct com_s *com) 5218{ 5219 int if_type = com->pc98_if_type & 0x0f; 5220 int io = com->iobase & 0xff00; 5221 5222 if (IS_8251(com->pc98_if_type)) { 5223 pc98_check_sysclock(); 5224 com->data_port = io | PC98SIO_data_port(if_type); 5225 com->cmd_port = io | PC98SIO_cmd_port(if_type); 5226 com->sts_port = io | PC98SIO_sts_port(if_type); 5227 com->in_modem_port = io | PC98SIO_in_modem_port(if_type); 5228 com->intr_ctrl_port = io | PC98SIO_intr_ctrl_port(if_type); 5229 5230 return 0; 5231 } 5232 5233 return -1; 5234} 5235static int 5236pc98_check_8251vfast(void) 5237{ 5238 int i; 5239 5240 outb(I8251F_div, 0x8c); 5241 DELAY(10); 5242 for (i = 0; i < 100; i++) { 5243 if ((inb(I8251F_div) & 0x80) != 0) { 5244 i = 0; 5245 break; 5246 } 5247 DELAY(1); 5248 } 5249 outb(I8251F_div, 0); 5250 DELAY(10); 5251 for (; i < 100; i++) { 5252 if ((inb(I8251F_div) & 0x80) == 0) 5253 return 1; 5254 DELAY(1); 5255 } 5256 5257 return 0; 5258} 5259static int 5260pc98_check_8251fifo(void) 5261{ 5262 u_char tmp1, tmp2; 5263 5264 tmp1 = inb(I8251F_iir); 5265 DELAY(10); 5266 tmp2 = inb(I8251F_iir); 5267 if (((tmp1 ^ tmp2) & 0x40) != 0 && ((tmp1 | tmp2) & 0x20) == 0) 5268 return 1; 5269 5270 return 0; 5271} 5272#endif /* PC98 defined */ 5273