sio.c revision 48187
1/*- 2 * Copyright (c) 1991 The Regents of the University of California. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by the University of 16 * California, Berkeley and its contributors. 17 * 4. Neither the name of the University nor the names of its contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 25 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 31 * SUCH DAMAGE. 32 * 33 * $Id: sio.c,v 1.97 1999/05/30 16:53:22 phk Exp $ 34 * from: @(#)com.c 7.5 (Berkeley) 5/16/91 35 * from: i386/isa sio.c,v 1.234 36 */ 37 38#include "opt_comconsole.h" 39#include "opt_compat.h" 40#include "opt_ddb.h" 41#include "opt_devfs.h" 42#include "opt_sio.h" 43#include "sio.h" 44/* #include "pnp.h" */ 45#define NPNP 0 46 47/* 48 * Serial driver, based on 386BSD-0.1 com driver. 49 * Mostly rewritten to use pseudo-DMA. 50 * Works for National Semiconductor NS8250-NS16550AF UARTs. 51 * COM driver, based on HP dca driver. 52 * 53 * Changes for PC-Card integration: 54 * - Added PC-Card driver table and handlers 55 */ 56/*=============================================================== 57 * 386BSD(98),FreeBSD-1.1x(98) com driver. 58 * ----- 59 * modified for PC9801 by M.Ishii 60 * Kyoto University Microcomputer Club (KMC) 61 * Chou "TEFUTEFU" Hirotomi 62 * Kyoto Univ. the faculty of medicine 63 *=============================================================== 64 * FreeBSD-2.0.1(98) sio driver. 65 * ----- 66 * modified for pc98 Internal i8251 and MICRO CORE MC16550II 67 * T.Koike(hfc01340@niftyserve.or.jp) 68 * implement kernel device configuration 69 * aizu@orient.center.nitech.ac.jp 70 * 71 * Notes. 72 * ----- 73 * PC98 localization based on 386BSD(98) com driver. Using its PC98 local 74 * functions. 75 * This driver is under debugging,has bugs. 76 * 77 * 1) config 78 * options COM_MULTIPORT #if using MC16550II 79 * device sio0 at nec? port 0x30 tty irq 4 #internal 80 * device sio1 at nec? port 0xd2 tty irq 5 flags 0x101 #mc1 81 * device sio2 at nec? port 0x8d2 tty flags 0x101 #mc2 82 * # ~~~~~iobase ~~multi port flag 83 * # ~ master device is sio1 84 * 2) device 85 * cd /dev; MAKEDEV ttyd0 ttyd1 .. 86 * 3) /etc/rc.serial 87 * 57600bps is too fast for sio0(internal8251) 88 * my ex. 89 * #set default speed 9600 90 * modem() 91 * : 92 * stty </dev/ttyid$i crtscts 9600 93 * : # ~~~~ default speed(can change after init.) 94 * modem 0 1 2 95 * 4) COMCONSOLE 96 * not changed. 97 * 5) PC9861K,PIO9032B,B98_01 98 * not tested. 99 */ 100/* 101 * modified for AIWA B98-01 102 * by T.Hatanou <hatanou@yasuda.comm.waseda.ac.jp> last update: 15 Sep.1995 103 * 104 * How to configure... 105 * # options COM_MULTIPORT # support for MICROCORE MC16550II 106 * ... comment-out this line, which will conflict with B98_01. 107 * options "B98_01" # support for AIWA B98-01 108 * device sio1 at nec? port 0x00d1 tty irq ? 109 * device sio2 at nec? port 0x00d5 tty irq ? 110 * ... you can leave these lines `irq ?', irq will be autodetected. 111 */ 112/* 113 * Modified by Y.Takahashi of Kogakuin University. 114 */ 115 116#ifdef PC98 117#define COM_IF_INTERNAL 0x00 118#define COM_IF_PC9861K_1 0x01 119#define COM_IF_PC9861K_2 0x02 120#define COM_IF_IND_SS_1 0x03 121#define COM_IF_IND_SS_2 0x04 122#define COM_IF_PIO9032B_1 0x05 123#define COM_IF_PIO9032B_2 0x06 124#define COM_IF_B98_01_1 0x07 125#define COM_IF_B98_01_2 0x08 126#define COM_IF_END1 COM_IF_B98_01_2 127#define COM_IF_RSA98 0x10 /* same as COM_IF_NS16550 */ 128#define COM_IF_NS16550 0x11 129#define COM_IF_SECOND_CCU 0x12 /* same as COM_IF_NS16550 */ 130#define COM_IF_MC16550II 0x13 131#define COM_IF_MCRS98 0x14 /* same as COM_IF_MC16550II */ 132#define COM_IF_RSB3000 0x15 133#define COM_IF_RSB384 0x16 134#define COM_IF_MODEM_CARD 0x17 /* same as COM_IF_NS16550 */ 135#define COM_IF_RSA98III 0x18 136#define COM_IF_ESP98 0x19 137#define COM_IF_END2 COM_IF_ESP98 138#endif /* PC98 */ 139 140#include <sys/param.h> 141#include <sys/systm.h> 142#include <sys/reboot.h> 143#include <sys/malloc.h> 144#include <sys/tty.h> 145#include <sys/proc.h> 146#include <sys/module.h> 147#include <sys/conf.h> 148#include <sys/dkstat.h> 149#include <sys/fcntl.h> 150#include <sys/interrupt.h> 151#include <sys/kernel.h> 152#include <sys/syslog.h> 153#include <sys/sysctl.h> 154#include <sys/bus.h> 155#include <machine/bus.h> 156#include <sys/rman.h> 157#ifdef DEVFS 158#include <sys/devfsext.h> 159#endif 160#include <sys/timepps.h> 161 162#ifdef PC98 163#include <pc98/pc98/pc98.h> 164#include <pc98/pc98/pc98_machdep.h> 165#include <i386/isa/ic/i8251.h> 166#else 167#include <isa/isareg.h> 168#endif 169#include <isa/isavar.h> 170#include <machine/lock.h> 171 172#include <machine/clock.h> 173#include <machine/ipl.h> 174#ifndef SMP 175#include <machine/lock.h> 176#endif 177#include <machine/resource.h> 178 179#include <isa/sioreg.h> 180 181#ifdef COM_ESP 182#include <i386/isa/ic/esp.h> 183#endif 184#include <i386/isa/ic/ns16550.h> 185#ifdef PC98 186#include <i386/isa/ic/rsa.h> 187#endif 188 189#if 0 190 191#include "card.h" 192#if NCARD > 0 193#include <sys/module.h> 194#include <pccard/cardinfo.h> 195#include <pccard/slot.h> 196#endif 197 198#if NPNP > 0 199#include <i386/isa/pnp.h> 200#endif 201 202#endif 203 204#ifndef __i386__ 205#define disable_intr() 0 206#define enable_intr() 0 207#endif 208 209#ifdef SMP 210#define disable_intr() COM_DISABLE_INTR() 211#define enable_intr() COM_ENABLE_INTR() 212#endif /* SMP */ 213 214#ifndef EXTRA_SIO 215#if NPNP > 0 216#define EXTRA_SIO MAX_PNP_CARDS 217#else 218#define EXTRA_SIO 0 219#endif 220#endif 221 222#define NSIOTOT (NSIO + EXTRA_SIO) 223 224#define LOTS_OF_EVENTS 64 /* helps separate urgent events from input */ 225 226#define CALLOUT_MASK 0x80 227#define CONTROL_MASK 0x60 228#define CONTROL_INIT_STATE 0x20 229#define CONTROL_LOCK_STATE 0x40 230#define DEV_TO_UNIT(dev) (MINOR_TO_UNIT(minor(dev))) 231#define MINOR_MAGIC_MASK (CALLOUT_MASK | CONTROL_MASK) 232#define MINOR_TO_UNIT(mynor) ((mynor) & ~MINOR_MAGIC_MASK) 233 234#ifdef COM_MULTIPORT 235/* checks in flags for multiport and which is multiport "master chip" 236 * for a given card 237 */ 238#define COM_ISMULTIPORT(flags) ((flags) & 0x01) 239#define COM_MPMASTER(flags) (((flags) >> 8) & 0x0ff) 240#define COM_NOTAST4(flags) ((flags) & 0x04) 241#endif /* COM_MULTIPORT */ 242 243#define COM_CONSOLE(flags) ((flags) & 0x10) 244#define COM_FORCECONSOLE(flags) ((flags) & 0x20) 245#define COM_LLCONSOLE(flags) ((flags) & 0x40) 246#define COM_DEBUGGER(flags) ((flags) & 0x80) 247#define COM_LOSESOUTINTS(flags) ((flags) & 0x08) 248#define COM_NOFIFO(flags) ((flags) & 0x02) 249#define COM_ST16650A(flags) ((flags) & 0x20000) 250#define COM_C_NOPROBE (0x40000) 251#define COM_NOPROBE(flags) ((flags) & COM_C_NOPROBE) 252#define COM_C_IIR_TXRDYBUG (0x80000) 253#define COM_IIR_TXRDYBUG(flags) ((flags) & COM_C_IIR_TXRDYBUG) 254#define COM_FIFOSIZE(flags) (((flags) & 0xff000000) >> 24) 255 256#ifdef PC98 257#define com_emr com_msr /* Extension mode register for RSB-2000/3000 */ 258#else 259#define com_scr 7 /* scratch register for 16450-16550 (R/W) */ 260#endif 261 262/* 263 * com state bits. 264 * (CS_BUSY | CS_TTGO) and (CS_BUSY | CS_TTGO | CS_ODEVREADY) must be higher 265 * than the other bits so that they can be tested as a group without masking 266 * off the low bits. 267 * 268 * The following com and tty flags correspond closely: 269 * CS_BUSY = TS_BUSY (maintained by comstart(), siopoll() and 270 * siostop()) 271 * CS_TTGO = ~TS_TTSTOP (maintained by comparam() and comstart()) 272 * CS_CTS_OFLOW = CCTS_OFLOW (maintained by comparam()) 273 * CS_RTS_IFLOW = CRTS_IFLOW (maintained by comparam()) 274 * TS_FLUSH is not used. 275 * XXX I think TIOCSETA doesn't clear TS_TTSTOP when it clears IXON. 276 * XXX CS_*FLOW should be CF_*FLOW in com->flags (control flags not state). 277 */ 278#define CS_BUSY 0x80 /* output in progress */ 279#define CS_TTGO 0x40 /* output not stopped by XOFF */ 280#define CS_ODEVREADY 0x20 /* external device h/w ready (CTS) */ 281#define CS_CHECKMSR 1 /* check of MSR scheduled */ 282#define CS_CTS_OFLOW 2 /* use CTS output flow control */ 283#define CS_DTR_OFF 0x10 /* DTR held off */ 284#define CS_ODONE 4 /* output completed */ 285#define CS_RTS_IFLOW 8 /* use RTS input flow control */ 286#define CSE_BUSYCHECK 1 /* siobusycheck() scheduled */ 287 288static char const * const error_desc[] = { 289#define CE_OVERRUN 0 290 "silo overflow", 291#define CE_INTERRUPT_BUF_OVERFLOW 1 292 "interrupt-level buffer overflow", 293#define CE_TTY_BUF_OVERFLOW 2 294 "tty-level buffer overflow", 295}; 296 297#define CE_NTYPES 3 298#define CE_RECORD(com, errnum) (++(com)->delta_error_counts[errnum]) 299 300/* types. XXX - should be elsewhere */ 301typedef u_int Port_t; /* hardware port */ 302typedef u_char bool_t; /* boolean */ 303 304/* queue of linear buffers */ 305struct lbq { 306 u_char *l_head; /* next char to process */ 307 u_char *l_tail; /* one past the last char to process */ 308 struct lbq *l_next; /* next in queue */ 309 bool_t l_queued; /* nonzero if queued */ 310}; 311 312/* com device structure */ 313struct com_s { 314 u_int flags; /* Copy isa device flags */ 315 u_char state; /* miscellaneous flag bits */ 316 bool_t active_out; /* nonzero if the callout device is open */ 317 u_char cfcr_image; /* copy of value written to CFCR */ 318#ifdef COM_ESP 319 bool_t esp; /* is this unit a hayes esp board? */ 320#endif 321 u_char extra_state; /* more flag bits, separate for order trick */ 322 u_char fifo_image; /* copy of value written to FIFO */ 323 bool_t hasfifo; /* nonzero for 16550 UARTs */ 324 bool_t st16650a; /* Is a Startech 16650A or RTS/CTS compat */ 325 bool_t loses_outints; /* nonzero if device loses output interrupts */ 326 u_char mcr_image; /* copy of value written to MCR */ 327#ifdef COM_MULTIPORT 328 bool_t multiport; /* is this unit part of a multiport device? */ 329#endif /* COM_MULTIPORT */ 330 bool_t no_irq; /* nonzero if irq is not attached */ 331 bool_t gone; /* hardware disappeared */ 332 bool_t poll; /* nonzero if polling is required */ 333 bool_t poll_output; /* nonzero if polling for output is required */ 334 int unit; /* unit number */ 335 int dtr_wait; /* time to hold DTR down on close (* 1/hz) */ 336 u_int tx_fifo_size; 337 u_int wopeners; /* # processes waiting for DCD in open() */ 338 339 /* 340 * The high level of the driver never reads status registers directly 341 * because there would be too many side effects to handle conveniently. 342 * Instead, it reads copies of the registers stored here by the 343 * interrupt handler. 344 */ 345 u_char last_modem_status; /* last MSR read by intr handler */ 346 u_char prev_modem_status; /* last MSR handled by high level */ 347 348 u_char hotchar; /* ldisc-specific char to be handled ASAP */ 349 u_char *ibuf; /* start of input buffer */ 350 u_char *ibufend; /* end of input buffer */ 351 u_char *ibufold; /* old input buffer, to be freed */ 352 u_char *ihighwater; /* threshold in input buffer */ 353 u_char *iptr; /* next free spot in input buffer */ 354 int ibufsize; /* size of ibuf (not include error bytes) */ 355 int ierroff; /* offset of error bytes in ibuf */ 356 357 struct lbq obufq; /* head of queue of output buffers */ 358 struct lbq obufs[2]; /* output buffers */ 359 360#ifdef PC98 361 Port_t cmd_port; 362 Port_t sts_port; 363 Port_t in_modem_port; 364 Port_t intr_ctrl_port; 365 int intr_enable; 366 int pc98_prev_modem_status; 367 int pc98_modem_delta; 368 int modem_car_chg_timer; 369 int pc98_prev_siocmd; 370 int pc98_prev_siomod; 371 int modem_checking; 372 int pc98_if_type; 373#endif /* PC98 */ 374 Port_t data_port; /* i/o ports */ 375#ifdef COM_ESP 376 Port_t esp_port; 377#endif 378 Port_t int_id_port; 379 Port_t iobase; 380#ifdef PC98 381 Port_t rsabase; /* iobase address of a I/O-DATA RSA board */ 382#endif 383 Port_t modem_ctl_port; 384 Port_t line_status_port; 385 Port_t modem_status_port; 386 Port_t intr_ctl_port; /* Ports of IIR register */ 387 388 struct tty *tp; /* cross reference */ 389 390 /* Initial state. */ 391 struct termios it_in; /* should be in struct tty */ 392 struct termios it_out; 393 394 /* Lock state. */ 395 struct termios lt_in; /* should be in struct tty */ 396 struct termios lt_out; 397 398 bool_t do_timestamp; 399 bool_t do_dcd_timestamp; 400 struct timeval timestamp; 401 struct timeval dcd_timestamp; 402 struct pps_state pps; 403 404 u_long bytes_in; /* statistics */ 405 u_long bytes_out; 406 u_int delta_error_counts[CE_NTYPES]; 407 u_long error_counts[CE_NTYPES]; 408 409 /* 410 * Data area for output buffers. Someday we should build the output 411 * buffer queue without copying data. 412 */ 413#ifdef PC98 414 int obufsize; 415 u_char *obuf1; 416 u_char *obuf2; 417#else 418 u_char obuf1[256]; 419 u_char obuf2[256]; 420#endif 421#ifdef DEVFS 422 void *devfs_token_ttyd; 423 void *devfs_token_ttyl; 424 void *devfs_token_ttyi; 425 void *devfs_token_cuaa; 426 void *devfs_token_cual; 427 void *devfs_token_cuai; 428#endif 429}; 430 431#ifdef COM_ESP 432static int espattach __P((struct com_s *com, Port_t esp_port)); 433#endif 434static int sioattach __P((device_t dev)); 435 436static timeout_t siobusycheck; 437static timeout_t siodtrwakeup; 438static void comhardclose __P((struct com_s *com)); 439static void sioinput __P((struct com_s *com)); 440static void siointr1 __P((struct com_s *com)); 441static void siointr __P((void *arg)); 442static int commctl __P((struct com_s *com, int bits, int how)); 443static int comparam __P((struct tty *tp, struct termios *t)); 444static swihand_t siopoll; 445static int sioprobe __P((device_t dev)); 446static void siosettimeout __P((void)); 447static int siosetwater __P((struct com_s *com, speed_t speed)); 448static void comstart __P((struct tty *tp)); 449static timeout_t comwakeup; 450static void disc_optim __P((struct tty *tp, struct termios *t, 451 struct com_s *com)); 452 453 454static char driver_name[] = "sio"; 455 456/* table and macro for fast conversion from a unit number to its com struct */ 457static devclass_t sio_devclass; 458#define com_addr(unit) ((struct com_s *) \ 459 devclass_get_softc(sio_devclass, unit)) 460 461static device_method_t sio_methods[] = { 462 /* Device interface */ 463 DEVMETHOD(device_probe, sioprobe), 464 DEVMETHOD(device_attach, sioattach), 465 466 { 0, 0 } 467}; 468 469static driver_t sio_driver = { 470 driver_name, 471 sio_methods, 472 sizeof(struct com_s), 473}; 474 475static d_open_t sioopen; 476static d_close_t sioclose; 477static d_read_t sioread; 478static d_write_t siowrite; 479static d_ioctl_t sioioctl; 480static d_stop_t siostop; 481static d_devtotty_t siodevtotty; 482 483#define CDEV_MAJOR 28 484static struct cdevsw sio_cdevsw = { 485 /* open */ sioopen, 486 /* close */ sioclose, 487 /* read */ sioread, 488 /* write */ siowrite, 489 /* ioctl */ sioioctl, 490 /* stop */ siostop, 491 /* reset */ noreset, 492 /* devtotty */ siodevtotty, 493 /* poll */ ttpoll, 494 /* mmap */ nommap, 495 /* strategy */ nostrategy, 496 /* name */ driver_name, 497 /* parms */ noparms, 498 /* maj */ CDEV_MAJOR, 499 /* dump */ nodump, 500 /* psize */ nopsize, 501 /* flags */ D_TTY, 502 /* maxio */ 0, 503 /* bmaj */ -1 504}; 505 506int comconsole = -1; 507static volatile speed_t comdefaultrate = CONSPEED; 508#ifdef __alpha__ 509static volatile speed_t gdbdefaultrate = CONSPEED; 510#endif 511static u_int com_events; /* input chars + weighted output completions */ 512static Port_t siocniobase; 513static int siocnunit; 514static Port_t siogdbiobase; 515static int siogdbunit = -1; 516static bool_t sio_registered; 517static int sio_timeout; 518static int sio_timeouts_until_log; 519static struct callout_handle sio_timeout_handle 520 = CALLOUT_HANDLE_INITIALIZER(&sio_timeout_handle); 521#if 0 /* XXX */ 522static struct tty *sio_tty[NSIOTOT]; 523#else 524static struct tty sio_tty[NSIOTOT]; 525#endif 526static const int nsio_tty = NSIOTOT; 527 528#ifdef PC98 529struct siodev { 530 short if_type; 531 short irq; 532 Port_t cmd, sts, ctrl, mod; 533}; 534static int sysclock; 535 536#define COM_INT_DISABLE {int previpri; previpri=spltty(); 537#define COM_INT_ENABLE splx(previpri);} 538#define IEN_TxFLAG IEN_Tx 539 540#define COM_CARRIER_DETECT_EMULATE 0 541#define PC98_CHECK_MODEM_INTERVAL (hz/10) 542#define DCD_OFF_TOLERANCE 2 543#define DCD_ON_RECOGNITION 2 544#define IS_8251(if_type) (!(if_type & 0x10)) 545#define COM1_EXT_CLOCK 0x40000 546 547static void commint __P((dev_t dev)); 548static void com_tiocm_set __P((struct com_s *com, int msr)); 549static void com_tiocm_bis __P((struct com_s *com, int msr)); 550static void com_tiocm_bic __P((struct com_s *com, int msr)); 551static int com_tiocm_get __P((struct com_s *com)); 552static int com_tiocm_get_delta __P((struct com_s *com)); 553static void pc98_msrint_start __P((dev_t dev)); 554static void com_cflag_and_speed_set __P((struct com_s *com, int cflag, int speed)); 555static int pc98_ttspeedtab __P((struct com_s *com, int speed)); 556static int pc98_get_modem_status __P((struct com_s *com)); 557static timeout_t pc98_check_msr; 558static void pc98_set_baud_rate __P((struct com_s *com, int count)); 559static void pc98_i8251_reset __P((struct com_s *com, int mode, int command)); 560static void pc98_disable_i8251_interrupt __P((struct com_s *com, int mod)); 561static void pc98_enable_i8251_interrupt __P((struct com_s *com, int mod)); 562static int pc98_check_i8251_interrupt __P((struct com_s *com)); 563static int pc98_i8251_get_cmd __P((struct com_s *com)); 564static int pc98_i8251_get_mod __P((struct com_s *com)); 565static void pc98_i8251_set_cmd __P((struct com_s *com, int x)); 566static void pc98_i8251_or_cmd __P((struct com_s *com, int x)); 567static void pc98_i8251_clear_cmd __P((struct com_s *com, int x)); 568static void pc98_i8251_clear_or_cmd __P((struct com_s *com, int clr, int x)); 569static int pc98_check_if_type __P((device_t dev, struct siodev *iod)); 570static void pc98_check_sysclock __P((void)); 571static int pc98_set_ioport __P((struct com_s *com, int id_flags)); 572 573#define com_int_Tx_disable(com) \ 574 pc98_disable_i8251_interrupt(com,IEN_Tx|IEN_TxEMP) 575#define com_int_Tx_enable(com) \ 576 pc98_enable_i8251_interrupt(com,IEN_TxFLAG) 577#define com_int_Rx_disable(com) \ 578 pc98_disable_i8251_interrupt(com,IEN_Rx) 579#define com_int_Rx_enable(com) \ 580 pc98_enable_i8251_interrupt(com,IEN_Rx) 581#define com_int_TxRx_disable(com) \ 582 pc98_disable_i8251_interrupt(com,IEN_Tx|IEN_TxEMP|IEN_Rx) 583#define com_int_TxRx_enable(com) \ 584 pc98_enable_i8251_interrupt(com,IEN_TxFLAG|IEN_Rx) 585#define com_send_break_on(com) \ 586 pc98_i8251_or_cmd(com,CMD8251_SBRK) 587#define com_send_break_off(com) \ 588 pc98_i8251_clear_cmd(com,CMD8251_SBRK) 589 590static struct speedtab pc98speedtab[] = { /* internal RS232C interface */ 591 { 0, 0, }, 592 { 50, 50, }, 593 { 75, 75, }, 594 { 150, 150, }, 595 { 200, 200, }, 596 { 300, 300, }, 597 { 600, 600, }, 598 { 1200, 1200, }, 599 { 2400, 2400, }, 600 { 4800, 4800, }, 601 { 9600, 9600, }, 602 { 19200, 19200, }, 603 { 38400, 38400, }, 604 { 51200, 51200, }, 605 { 76800, 76800, }, 606 { 20800, 20800, }, 607 { 31200, 31200, }, 608 { 41600, 41600, }, 609 { 62400, 62400, }, 610 { -1, -1 } 611}; 612static struct speedtab pc98fast_speedtab[] = { 613 { 9600, 0x80 | COMBRD(9600), }, 614 { 19200, 0x80 | COMBRD(19200), }, 615 { 38400, 0x80 | COMBRD(38400), }, 616 { 57600, 0x80 | COMBRD(57600), }, 617 { 115200, 0x80 | COMBRD(115200), }, 618 { -1, -1 } 619}; 620static struct speedtab comspeedtab_pio9032b[] = { 621 { 300, 6, }, 622 { 600, 5, }, 623 { 1200, 4, }, 624 { 2400, 3, }, 625 { 4800, 2, }, 626 { 9600, 1, }, 627 { 19200, 0, }, 628 { 38400, 7, }, 629 { -1, -1 } 630}; 631static struct speedtab comspeedtab_b98_01[] = { 632 { 75, 11, }, 633 { 150, 10, }, 634 { 300, 9, }, 635 { 600, 8, }, 636 { 1200, 7, }, 637 { 2400, 6, }, 638 { 4800, 5, }, 639 { 9600, 4, }, 640 { 19200, 3, }, 641 { 38400, 2, }, 642 { 76800, 1, }, 643 { 153600, 0, }, 644 { -1, -1 } 645}; 646static struct speedtab comspeedtab_mc16550[] = { 647 { 300, 1536, }, 648 { 600, 768, }, 649 { 1200, 384, }, 650 { 2400, 192, }, 651 { 4800, 96, }, 652 { 9600, 48, }, 653 { 19200, 24, }, 654 { 38400, 12, }, 655 { 57600, 8, }, 656 { 115200, 4, }, 657 { 153600, 3, }, 658 { 230400, 2, }, 659 { 460800, 1, }, 660 { -1, -1 } 661}; 662static struct speedtab comspeedtab_rsb384[] = { 663 { 300, 3840, }, 664 { 600, 1920, }, 665 { 1200, 960, }, 666 { 2400, 480, }, 667 { 4800, 240, }, 668 { 9600, 120, }, 669 { 19200, 60, }, 670 { 38400, 30, }, 671 { 57600, 20, }, 672 { 115200, 10, }, 673 { 128000, 9, }, 674 { 144000, 8, }, 675 { 192000, 6, }, 676 { 230400, 5, }, 677 { 288000, 4, }, 678 { 384000, 3, }, 679 { 576000, 2, }, 680 { 1152000, 1, }, 681 { -1, -1 } 682}; 683static struct speedtab comspeedtab_rsa[] = { 684 { 0, 0 }, 685 { 50, COMBRD_RSA(50) }, 686 { 75, COMBRD_RSA(75) }, 687 { 110, COMBRD_RSA(110) }, 688 { 134, COMBRD_RSA(134) }, 689 { 150, COMBRD_RSA(150) }, 690 { 200, COMBRD_RSA(200) }, 691 { 300, COMBRD_RSA(300) }, 692 { 600, COMBRD_RSA(600) }, 693 { 1200, COMBRD_RSA(1200) }, 694 { 1800, COMBRD_RSA(1800) }, 695 { 2400, COMBRD_RSA(2400) }, 696 { 4800, COMBRD_RSA(4800) }, 697 { 9600, COMBRD_RSA(9600) }, 698 { 19200, COMBRD_RSA(19200) }, 699 { 38400, COMBRD_RSA(38400) }, 700 { 57600, COMBRD_RSA(57600) }, 701 { 115200, COMBRD_RSA(115200) }, 702 { 230400, COMBRD_RSA(230400) }, 703 { 460800, COMBRD_RSA(460800) }, 704 { 921600, COMBRD_RSA(921600) }, 705 { -1, -1 } 706}; 707#endif /* PC98 */ 708 709static struct speedtab comspeedtab[] = { 710 { 0, 0 }, 711 { 50, COMBRD(50) }, 712 { 75, COMBRD(75) }, 713 { 110, COMBRD(110) }, 714 { 134, COMBRD(134) }, 715 { 150, COMBRD(150) }, 716 { 200, COMBRD(200) }, 717 { 300, COMBRD(300) }, 718 { 600, COMBRD(600) }, 719 { 1200, COMBRD(1200) }, 720 { 1800, COMBRD(1800) }, 721 { 2400, COMBRD(2400) }, 722 { 4800, COMBRD(4800) }, 723 { 9600, COMBRD(9600) }, 724 { 19200, COMBRD(19200) }, 725 { 38400, COMBRD(38400) }, 726 { 57600, COMBRD(57600) }, 727 { 115200, COMBRD(115200) }, 728 { -1, -1 } 729}; 730 731#ifdef PC98 732struct { 733 char *name; 734 short port_table[7]; 735 short irr_mask; 736 struct speedtab *speedtab; 737 short check_irq; 738} if_8251_type[] = { 739 /* COM_IF_INTERNAL */ 740 { " (internal)", {0x30, 0x32, 0x32, 0x33, 0x35, -1, -1}, 741 -1, pc98speedtab, 1 }, 742 /* COM_IF_PC9861K_1 */ 743 { " (PC9861K)", {0xb1, 0xb3, 0xb3, 0xb0, 0xb0, -1, -1}, 744 3, NULL, 1 }, 745 /* COM_IF_PC9861K_2 */ 746 { " (PC9861K)", {0xb9, 0xbb, 0xbb, 0xb2, 0xb2, -1, -1}, 747 3, NULL, 1 }, 748 /* COM_IF_IND_SS_1 */ 749 { " (IND-SS)", {0xb1, 0xb3, 0xb3, 0xb0, 0xb0, 0xb3, -1}, 750 3, comspeedtab_mc16550, 1 }, 751 /* COM_IF_IND_SS_2 */ 752 { " (IND-SS)", {0xb9, 0xbb, 0xbb, 0xb2, 0xb2, 0xbb, -1}, 753 3, comspeedtab_mc16550, 1 }, 754 /* COM_IF_PIO9032B_1 */ 755 { " (PIO9032B)", {0xb1, 0xb3, 0xb3, 0xb0, 0xb0, 0xb8, -1}, 756 7, comspeedtab_pio9032b, 1 }, 757 /* COM_IF_PIO9032B_2 */ 758 { " (PIO9032B)", {0xb9, 0xbb, 0xbb, 0xb2, 0xb2, 0xba, -1}, 759 7, comspeedtab_pio9032b, 1 }, 760 /* COM_IF_B98_01_1 */ 761 { " (B98-01)", {0xb1, 0xb3, 0xb3, 0xb0, 0xb0, 0xd1, 0xd3}, 762 7, comspeedtab_b98_01, 0 }, 763 /* COM_IF_B98_01_2 */ 764 { " (B98-01)", {0xb9, 0xbb, 0xbb, 0xb2, 0xb2, 0xd5, 0xd7}, 765 7, comspeedtab_b98_01, 0 }, 766}; 767#define PC98SIO_data_port(type) (if_8251_type[type].port_table[0]) 768#define PC98SIO_cmd_port(type) (if_8251_type[type].port_table[1]) 769#define PC98SIO_sts_port(type) (if_8251_type[type].port_table[2]) 770#define PC98SIO_in_modem_port(type) (if_8251_type[type].port_table[3]) 771#define PC98SIO_intr_ctrl_port(type) (if_8251_type[type].port_table[4]) 772#define PC98SIO_baud_rate_port(type) (if_8251_type[type].port_table[5]) 773#define PC98SIO_func_port(type) (if_8251_type[type].port_table[6]) 774 775struct { 776 char *name; 777 short irr_read; 778 short irr_write; 779 short port_shift; 780 short io_size; 781 struct speedtab *speedtab; 782} if_16550a_type[] = { 783 /* COM_IF_RSA98 */ 784 { " (RSA-98)", -1, -1, 0, IO_COMSIZE, comspeedtab }, 785 /* COM_IF_NS16550 */ 786 { "", -1, -1, 0, IO_COMSIZE, comspeedtab }, 787 /* COM_IF_SECOND_CCU */ 788 { "", -1, -1, 0, IO_COMSIZE, comspeedtab }, 789 /* COM_IF_MC16550II */ 790 { " (MC16550II)", -1, 0x1000, 8, 1, comspeedtab_mc16550 }, 791 /* COM_IF_MCRS98 */ 792 { " (MC-RS98)", -1, 0x1000, 8, 1, comspeedtab_mc16550 }, 793 /* COM_IF_RSB3000 */ 794 { " (RSB-3000)", 0xbf, -1, 1, 1, comspeedtab_rsb384 }, 795 /* COM_IF_RSB384 */ 796 { " (RSB-384)", 0xbf, -1, 1, 1, comspeedtab_rsb384 }, 797 /* COM_IF_MODEM_CARD */ 798 { "", -1, -1, 0, IO_COMSIZE, comspeedtab }, 799 /* COM_IF_RSA98III */ 800 { " (RSA-98III)", -1, -1, 0, 16, comspeedtab_rsa }, 801 /* COM_IF_ESP98 */ 802 { " (ESP98)", -1, -1, 1, 1, comspeedtab_mc16550 }, 803}; 804#endif /* PC98 */ 805 806#ifdef COM_ESP 807#ifdef PC98 808 809/* XXX configure this properly. */ 810static Port_t likely_com_ports[] = { 0, 0xb0, 0xb1, 0 }; 811static Port_t likely_esp_ports[] = { 0xc0d0, 0 }; 812 813#define ESP98_CMD1 (ESP_CMD1 * 0x100) 814#define ESP98_CMD2 (ESP_CMD2 * 0x100) 815#define ESP98_STATUS1 (ESP_STATUS1 * 0x100) 816#define ESP98_STATUS2 (ESP_STATUS2 * 0x100) 817 818#else /* PC98 */ 819 820/* XXX configure this properly. */ 821static Port_t likely_com_ports[] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8, }; 822static Port_t likely_esp_ports[] = { 0x140, 0x180, 0x280, 0 }; 823 824#endif /* PC98 */ 825#endif 826 827/* 828 * handle sysctl read/write requests for console speed 829 * 830 * In addition to setting comdefaultrate for I/O through /dev/console, 831 * also set the initial and lock values for the /dev/ttyXX device 832 * if there is one associated with the console. Finally, if the /dev/tty 833 * device has already been open, change the speed on the open running port 834 * itself. 835 */ 836 837static int 838sysctl_machdep_comdefaultrate SYSCTL_HANDLER_ARGS 839{ 840 int error, s; 841 speed_t newspeed; 842 struct com_s *com; 843 struct tty *tp; 844 845 newspeed = comdefaultrate; 846 847 error = sysctl_handle_opaque(oidp, &newspeed, sizeof newspeed, req); 848 if (error || !req->newptr) 849 return (error); 850 851 comdefaultrate = newspeed; 852 853 if (comconsole < 0) /* serial console not selected? */ 854 return (0); 855 856 com = com_addr(comconsole); 857 if (!com) 858 return (ENXIO); 859 860 /* 861 * set the initial and lock rates for /dev/ttydXX and /dev/cuaXX 862 * (note, the lock rates really are boolean -- if non-zero, disallow 863 * speed changes) 864 */ 865 com->it_in.c_ispeed = com->it_in.c_ospeed = 866 com->lt_in.c_ispeed = com->lt_in.c_ospeed = 867 com->it_out.c_ispeed = com->it_out.c_ospeed = 868 com->lt_out.c_ispeed = com->lt_out.c_ospeed = comdefaultrate; 869 870 /* 871 * if we're open, change the running rate too 872 */ 873 tp = com->tp; 874 if (tp && (tp->t_state & TS_ISOPEN)) { 875 tp->t_termios.c_ispeed = 876 tp->t_termios.c_ospeed = comdefaultrate; 877 s = spltty(); 878 error = comparam(tp, &tp->t_termios); 879 splx(s); 880 } 881 return error; 882} 883 884SYSCTL_PROC(_machdep, OID_AUTO, conspeed, CTLTYPE_INT | CTLFLAG_RW, 885 0, 0, sysctl_machdep_comdefaultrate, "I", ""); 886 887#if NCARD > 0 888/* 889 * PC-Card (PCMCIA) specific code. 890 */ 891static int sioinit __P((struct pccard_devinfo *)); 892static void siounload __P((struct pccard_devinfo *)); 893static int card_intr __P((struct pccard_devinfo *)); 894 895PCCARD_MODULE(sio, sioinit, siounload, card_intr, 0, tty_imask); 896 897/* 898 * Initialize the device - called from Slot manager. 899 */ 900int 901sioinit(struct pccard_devinfo *devi) 902{ 903 904 /* validate unit number. */ 905 if (devi->isahd.id_unit >= (NSIOTOT)) 906 return(ENODEV); 907 /* Make sure it isn't already probed. */ 908 if (com_addr(devi->isahd.id_unit)) 909 return(EBUSY); 910 911 /* It's already probed as serial by Upper */ 912 devi->isahd.id_flags |= COM_C_NOPROBE; 913 914 /* 915 * Probe the device. If a value is returned, the 916 * device was found at the location. 917 */ 918 if (sioprobe(&devi->isahd) == 0) 919 return(ENXIO); 920 if (sioattach(&devi->isahd) == 0) 921 return(ENXIO); 922 923 return(0); 924} 925 926/* 927 * siounload - unload the driver and clear the table. 928 * XXX TODO: 929 * This is usually called when the card is ejected, but 930 * can be caused by a modunload of a controller driver. 931 * The idea is to reset the driver's view of the device 932 * and ensure that any driver entry points such as 933 * read and write do not hang. 934 */ 935static void 936siounload(struct pccard_devinfo *devi) 937{ 938 struct com_s *com; 939 940 if (!devi) { 941 printf("NULL devi in siounload\n"); 942 return; 943 } 944 com = com_addr(devi->isahd.id_unit); 945 if (!com) { 946 printf("NULL com in siounload\n"); 947 return; 948 } 949 if (!com->iobase) { 950 printf("sio%d already unloaded!\n",devi->isahd.id_unit); 951 return; 952 } 953 if (com->tp && (com->tp->t_state & TS_ISOPEN)) { 954 com->gone = 1; 955 printf("sio%d: unload\n", devi->isahd.id_unit); 956 com->tp->t_gen++; 957 ttyclose(com->tp); 958 ttwakeup(com->tp); 959 ttwwakeup(com->tp); 960 } else { 961 if (com->ibuf != NULL) 962 free(com->ibuf, M_DEVBUF); 963 free(com, M_DEVBUF); 964 printf("sio%d: unload,gone\n", devi->isahd.id_unit); 965 } 966} 967 968/* 969 * card_intr - Shared interrupt called from 970 * front end of PC-Card handler. 971 */ 972static int 973card_intr(struct pccard_devinfo *devi) 974{ 975 struct com_s *com; 976 977 COM_LOCK(); 978 com = com_addr(devi->isahd.id_unit); 979 if (com && !com->gone) 980 siointr1(com_addr(devi->isahd.id_unit)); 981 COM_UNLOCK(); 982 return(1); 983} 984#endif /* NCARD > 0 */ 985 986#define SET_FLAG(dev, bit) isa_set_flags(dev, isa_get_flags(dev) | (bit)) 987#define CLR_FLAG(dev, bit) isa_set_flags(dev, isa_get_flags(dev) & ~(bit)) 988 989static int 990sioprobe(dev) 991 device_t dev; 992{ 993 static bool_t already_init; 994 bool_t failures[10]; 995 int fn; 996 device_t idev; 997 Port_t iobase; 998 intrmask_t irqmap[4]; 999 intrmask_t irqs; 1000 u_char mcr_image; 1001 int result; 1002 device_t xdev; 1003 u_int flags = isa_get_flags(dev); 1004#ifdef PC98 1005 int irqout=0; 1006 int tmp; 1007 int port_shift = 0; 1008 struct siodev iod; 1009 Port_t rsabase = NULL; 1010#endif 1011 1012 if (!already_init) { 1013 /* 1014 * Turn off MCR_IENABLE for all likely serial ports. An unused 1015 * port with its MCR_IENABLE gate open will inhibit interrupts 1016 * from any used port that shares the interrupt vector. 1017 * XXX the gate enable is elsewhere for some multiports. 1018 */ 1019 device_t *devs; 1020 int count, i; 1021 1022 devclass_get_devices(sio_devclass, &devs, &count); 1023#ifdef PC98 1024 for (i = 0; i < count; i++) { 1025 xdev = devs[i]; 1026 tmp = (flags >> 24) & 0xff; 1027 if (IS_8251(tmp)) 1028 outb((isa_get_port(xdev) & 0xff00) | PC98SIO_cmd_port(tmp & 0x0f), 0xf2); 1029 else 1030 if (tmp == COM_IF_RSA98III) { 1031 rsabase = isa_get_port(xdev) & 0xfff0; 1032 outb(isa_get_port(xdev) + 8 + (com_mcr << if_16550a_type[tmp & 0x0f].port_shift), 0); 1033 } else 1034 outb(isa_get_port(xdev) + (com_mcr << if_16550a_type[tmp & 0x0f].port_shift), 0); 1035 } 1036#else 1037 for (i = 0; i < count; i++) { 1038 xdev = devs[i]; 1039 outb(isa_get_port(xdev) + com_mcr, 0); 1040 } 1041#endif 1042 free(devs, M_TEMP); 1043 already_init = TRUE; 1044 } 1045 1046 if (COM_LLCONSOLE(flags)) { 1047 printf("sio%d: reserved for low-level i/o\n", 1048 device_get_unit(dev)); 1049 return (ENXIO); 1050 } 1051 1052#ifdef PC98 1053 DELAY(10); 1054 1055 /* 1056 * If the port is i8251 UART (internal, B98_01) 1057 */ 1058 if (pc98_check_if_type(dev, &iod) == -1) 1059 return ENXIO; 1060 if (iod.irq > 0) 1061 isa_set_irq(dev, iod.irq); 1062 if (IS_8251(iod.if_type)) { 1063 outb(iod.cmd, 0); 1064 DELAY(10); 1065 outb(iod.cmd, 0); 1066 DELAY(10); 1067 outb(iod.cmd, 0); 1068 DELAY(10); 1069 outb(iod.cmd, CMD8251_RESET); 1070 DELAY(1000); /* for a while...*/ 1071 outb(iod.cmd, 0xf2); /* MODE (dummy) */ 1072 DELAY(10); 1073 outb(iod.cmd, 0x01); /* CMD (dummy) */ 1074 DELAY(1000); /* for a while...*/ 1075 if (( inb(iod.sts) & STS8251_TxEMP ) == 0 ) { 1076 result = ENXIO; 1077 } 1078 if (if_8251_type[iod.if_type & 0x0f].check_irq) { 1079 COM_INT_DISABLE 1080 tmp = ( inb( iod.ctrl ) & ~(IEN_Rx|IEN_TxEMP|IEN_Tx)); 1081 outb( iod.ctrl, tmp|IEN_TxEMP ); 1082 DELAY(10); 1083 result = isa_irq_pending() ? 0 : ENXIO; 1084 outb( iod.ctrl, tmp ); 1085 COM_INT_ENABLE 1086 } else { 1087 /* 1088 * B98_01 doesn't activate TxEMP interrupt line 1089 * when being reset, so we can't check irq pending. 1090 */ 1091 result = 0; 1092 } 1093 if (epson_machine_id==0x20) { /* XXX */ 1094 result = 0; 1095 } 1096 isa_set_portsize(dev, 4); 1097 return result; 1098 } 1099#endif /* PC98 */ 1100 /* 1101 * If the device is on a multiport card and has an AST/4 1102 * compatible interrupt control register, initialize this 1103 * register and prepare to leave MCR_IENABLE clear in the mcr. 1104 * Otherwise, prepare to set MCR_IENABLE in the mcr. 1105 * Point idev to the device struct giving the correct id_irq. 1106 * This is the struct for the master device if there is one. 1107 */ 1108 idev = dev; 1109 mcr_image = MCR_IENABLE; 1110#ifdef PC98 1111 if (iod.if_type == COM_IF_RSA98III) { 1112 mcr_image = 0; 1113 rsabase = isa_get_port(idev) & 0xfff0; 1114 if (rsabase != isa_get_port(idev)) 1115 return(0); 1116 outb(rsabase + rsa_msr, 0x04); 1117 outb(rsabase + rsa_frr, 0x00); 1118 if ((inb(rsabase + rsa_srr) & 0x36) != 0x36) 1119 return (0); 1120 outb(rsabase + rsa_ier, 0x00); 1121 outb(rsabase + rsa_frr, 0x00); 1122 outb(rsabase + rsa_tivsr, 0x00); 1123 outb(rsabase + rsa_tcr, 0x00); 1124 } 1125#endif /* PC98 */ 1126#ifdef COM_MULTIPORT 1127 if (COM_ISMULTIPORT(flags)) { 1128 idev = devclass_get_device(sio_devclass, COM_MPMASTER(flags)); 1129 if (idev == NULL) { 1130 printf("sio%d: master device %d not configured\n", 1131 device_get_unit(dev), COM_MPMASTER(flags)); 1132 isa_set_irq(dev, 0); 1133 idev = dev; 1134 } 1135#ifndef PC98 1136 if (!COM_NOTAST4(flags)) { 1137 outb(isa_get_port(idev) + com_scr, 1138 isa_get_irq(idev) >= 0 ? 0x80 : 0); 1139 mcr_image = 0; 1140 } 1141#endif /* !PC98 */ 1142 } 1143#endif /* COM_MULTIPORT */ 1144 if (isa_get_irq(idev) < 0) 1145 mcr_image = 0; 1146 1147#ifdef PC98 1148 tmp = if_16550a_type[iod.if_type & 0x0f].irr_write; 1149 if (tmp != -1) { 1150 /* MC16550II */ 1151 switch (isa_get_irq(idev)) { 1152 case 3: irqout = 4; break; 1153 case 5: irqout = 5; break; 1154 case 6: irqout = 6; break; 1155 case 12: irqout = 7; break; 1156 default: 1157 printf("sio%d: irq configuration error\n", 1158 device_get_unit(dev)); 1159 return (0); 1160 } 1161 outb((isa_get_port(dev) & 0x00ff) | tmp, irqout); 1162 } 1163 port_shift = if_16550a_type[iod.if_type & 0x0f].port_shift; 1164#endif 1165 bzero(failures, sizeof failures); 1166 iobase = isa_get_port(dev); 1167#ifdef PC98 1168 if (iod.if_type == COM_IF_RSA98III) 1169 iobase += 8; 1170#endif 1171 1172 /* 1173 * We don't want to get actual interrupts, just masked ones. 1174 * Interrupts from this line should already be masked in the ICU, 1175 * but mask them in the processor as well in case there are some 1176 * (misconfigured) shared interrupts. 1177 */ 1178 disable_intr(); 1179/* EXTRA DELAY? */ 1180 1181 /* 1182 * Initialize the speed and the word size and wait long enough to 1183 * drain the maximum of 16 bytes of junk in device output queues. 1184 * The speed is undefined after a master reset and must be set 1185 * before relying on anything related to output. There may be 1186 * junk after a (very fast) soft reboot and (apparently) after 1187 * master reset. 1188 * XXX what about the UART bug avoided by waiting in comparam()? 1189 * We don't want to to wait long enough to drain at 2 bps. 1190 */ 1191 if (iobase == siocniobase) 1192 DELAY((16 + 1) * 1000000 / (comdefaultrate / 10)); 1193 else { 1194#ifdef PC98 1195 tmp = ttspeedtab(SIO_TEST_SPEED, 1196 if_16550a_type[iod.if_type & 0x0f].speedtab); 1197 outb(iobase + (com_cfcr << port_shift), CFCR_DLAB|CFCR_8BITS); 1198 outb(iobase + (com_dlbl << port_shift), tmp & 0xff); 1199 outb(iobase + (com_dlbh << port_shift), (tmp >> 8) & 0xff); 1200 outb(iobase + (com_cfcr << port_shift), CFCR_8BITS); 1201#else 1202 outb(iobase + com_cfcr, CFCR_DLAB | CFCR_8BITS); 1203 outb(iobase + com_dlbl, COMBRD(SIO_TEST_SPEED) & 0xff); 1204 outb(iobase + com_dlbh, (u_int) COMBRD(SIO_TEST_SPEED) >> 8); 1205 outb(iobase + com_cfcr, CFCR_8BITS); 1206#endif 1207 DELAY((16 + 1) * 1000000 / (SIO_TEST_SPEED / 10)); 1208 } 1209 1210 /* 1211 * Enable the interrupt gate and disable device interupts. This 1212 * should leave the device driving the interrupt line low and 1213 * guarantee an edge trigger if an interrupt can be generated. 1214 */ 1215/* EXTRA DELAY? */ 1216#ifdef PC98 1217 outb(iobase + (com_mcr << port_shift), mcr_image); 1218 outb(iobase + (com_ier << port_shift), 0); 1219#else 1220 outb(iobase + com_mcr, mcr_image); 1221 outb(iobase + com_ier, 0); 1222#endif 1223 DELAY(1000); /* XXX */ 1224 irqmap[0] = isa_irq_pending(); 1225 1226 /* 1227 * Attempt to set loopback mode so that we can send a null byte 1228 * without annoying any external device. 1229 */ 1230/* EXTRA DELAY? */ 1231#ifdef PC98 1232 outb(iobase + (com_mcr << port_shift), mcr_image | MCR_LOOPBACK); 1233#else 1234 outb(iobase + com_mcr, mcr_image | MCR_LOOPBACK); 1235#endif 1236 1237 /* 1238 * Attempt to generate an output interrupt. On 8250's, setting 1239 * IER_ETXRDY generates an interrupt independent of the current 1240 * setting and independent of whether the THR is empty. On 16450's, 1241 * setting IER_ETXRDY generates an interrupt independent of the 1242 * current setting. On 16550A's, setting IER_ETXRDY only 1243 * generates an interrupt when IER_ETXRDY is not already set. 1244 */ 1245#ifdef PC98 1246 outb(iobase + (com_ier << port_shift), IER_ETXRDY); 1247 if (iod.if_type == COM_IF_RSA98III) 1248 outb(rsabase + rsa_ier, 0x04); 1249#else 1250 outb(iobase + com_ier, IER_ETXRDY); 1251#endif /* PC98 */ 1252 1253 /* 1254 * On some 16x50 incompatibles, setting IER_ETXRDY doesn't generate 1255 * an interrupt. They'd better generate one for actually doing 1256 * output. Loopback may be broken on the same incompatibles but 1257 * it's unlikely to do more than allow the null byte out. 1258 */ 1259#ifdef PC98 1260 outb(iobase + (com_data << port_shift), 0); 1261#else 1262 outb(iobase + com_data, 0); 1263#endif 1264 DELAY((1 + 2) * 1000000 / (SIO_TEST_SPEED / 10)); 1265 1266 /* 1267 * Turn off loopback mode so that the interrupt gate works again 1268 * (MCR_IENABLE was hidden). This should leave the device driving 1269 * an interrupt line high. It doesn't matter if the interrupt 1270 * line oscillates while we are not looking at it, since interrupts 1271 * are disabled. 1272 */ 1273/* EXTRA DELAY? */ 1274#ifdef PC98 1275 outb(iobase + (com_mcr << port_shift), mcr_image); 1276#else 1277 outb(iobase + com_mcr, mcr_image); 1278#endif /* PC98 */ 1279 1280 /* 1281 * It's a definitly Serial PCMCIA(16550A), but still be required 1282 * for IIR_TXRDY implementation ( Palido 321s, DC-1S... ) 1283 */ 1284 if ( COM_NOPROBE(flags) ) { 1285 /* Reading IIR register twice */ 1286 for ( fn = 0; fn < 2; fn ++ ) { 1287 DELAY(10000); 1288#ifdef PC98 1289 failures[6] = inb(iobase + (com_iir << port_shift)); 1290#else 1291 failures[6] = inb(iobase + com_iir); 1292#endif 1293 } 1294 /* Check IIR_TXRDY clear ? */ 1295#ifdef PC98 1296 isa_set_portsize(dev, 1297 if_16550a_type[iod.if_type & 0x0f].io_size); 1298#else 1299 isa_set_portsize(dev, IO_COMSIZE); 1300#endif 1301 result = 0; 1302 if ( failures[6] & IIR_TXRDY ) { 1303 /* Nop, Double check with clearing IER */ 1304#ifdef PC98 1305 outb(iobase + (com_ier << port_shift), 0); 1306 if (inb(iobase + 1307 (com_iir << port_shift)) & IIR_NOPEND) { 1308#else 1309 outb(iobase + com_ier, 0); 1310 if ( inb(iobase + com_iir) & IIR_NOPEND ) { 1311#endif 1312 /* Ok. we're familia this gang */ 1313 SET_FLAG(dev, COM_C_IIR_TXRDYBUG); /* Set IIR_TXRDYBUG */ 1314 } else { 1315 /* Unknow, Just omit this chip.. XXX*/ 1316 result = ENXIO; 1317 } 1318 } else { 1319 /* OK. this is well-known guys */ 1320 CLR_FLAG(dev, COM_C_IIR_TXRDYBUG); /*Clear IIR_TXRDYBUG*/ 1321 } 1322#ifdef PC98 1323 outb(iobase + (com_cfcr << port_shift), CFCR_8BITS); 1324#else 1325 outb(iobase + com_cfcr, CFCR_8BITS); 1326#endif 1327 enable_intr(); 1328 return (iobase == siocniobase ? 0 : result); 1329 } 1330 1331 /* 1332 * Check that 1333 * o the CFCR, IER and MCR in UART hold the values written to them 1334 * (the values happen to be all distinct - this is good for 1335 * avoiding false positive tests from bus echoes). 1336 * o an output interrupt is generated and its vector is correct. 1337 * o the interrupt goes away when the IIR in the UART is read. 1338 */ 1339/* EXTRA DELAY? */ 1340#ifdef PC98 1341 failures[0] = inb(iobase + (com_cfcr << port_shift)) - CFCR_8BITS; 1342 failures[1] = inb(iobase + (com_ier << port_shift)) - IER_ETXRDY; 1343 failures[2] = inb(iobase + (com_mcr << port_shift)) - mcr_image; 1344#else 1345 failures[0] = inb(iobase + com_cfcr) - CFCR_8BITS; 1346 failures[1] = inb(iobase + com_ier) - IER_ETXRDY; 1347 failures[2] = inb(iobase + com_mcr) - mcr_image; 1348#endif 1349 DELAY(10000); /* Some internal modems need this time */ 1350 irqmap[1] = isa_irq_pending(); 1351#ifdef PC98 1352 failures[4] = (inb(iobase + (com_iir << port_shift)) & IIR_IMASK) 1353 - IIR_TXRDY; 1354 if (iod.if_type == COM_IF_RSA98III) 1355 inb(rsabase + rsa_srr); 1356#else 1357 failures[4] = (inb(iobase + com_iir) & IIR_IMASK) - IIR_TXRDY; 1358#endif 1359 DELAY(1000); /* XXX */ 1360 irqmap[2] = isa_irq_pending(); 1361#ifdef PC98 1362 failures[6] = (inb(iobase + (com_iir << port_shift)) & IIR_IMASK) 1363 - IIR_NOPEND; 1364 if (iod.if_type == COM_IF_RSA98III) 1365 inb(rsabase + rsa_srr); 1366#else 1367 failures[6] = (inb(iobase + com_iir) & IIR_IMASK) - IIR_NOPEND; 1368#endif 1369 1370 /* 1371 * Turn off all device interrupts and check that they go off properly. 1372 * Leave MCR_IENABLE alone. For ports without a master port, it gates 1373 * the OUT2 output of the UART to 1374 * the ICU input. Closing the gate would give a floating ICU input 1375 * (unless there is another device driving it) and spurious interrupts. 1376 * (On the system that this was first tested on, the input floats high 1377 * and gives a (masked) interrupt as soon as the gate is closed.) 1378 */ 1379#ifdef PC98 1380 outb(iobase + (com_ier << port_shift), 0); 1381 outb(iobase + (com_cfcr << port_shift), CFCR_8BITS); 1382 failures[7] = inb(iobase + (com_ier << port_shift)); 1383 if (iod.if_type == COM_IF_RSA98III) 1384 outb(rsabase + rsa_ier, 0x00); 1385#else 1386 outb(iobase + com_ier, 0); 1387 outb(iobase + com_cfcr, CFCR_8BITS); /* dummy to avoid bus echo */ 1388 failures[7] = inb(iobase + com_ier); 1389#endif 1390 DELAY(1000); /* XXX */ 1391 irqmap[3] = isa_irq_pending(); 1392#ifdef PC98 1393 failures[9] = (inb(iobase + (com_iir << port_shift)) & IIR_IMASK) 1394 - IIR_NOPEND; 1395 if (iod.if_type == COM_IF_RSA98III) { 1396 inb(rsabase + rsa_srr); 1397 outb(rsabase + rsa_frr, 0x00); 1398 } 1399#else 1400 failures[9] = (inb(iobase + com_iir) & IIR_IMASK) - IIR_NOPEND; 1401#endif 1402 1403 enable_intr(); 1404 1405 irqs = irqmap[1] & ~irqmap[0]; 1406 if (isa_get_irq(idev) >= 0 && ((1 << isa_get_irq(idev)) & irqs) == 0) 1407 printf( 1408 "sio%d: configured irq %d not in bitmap of probed irqs %#x\n", 1409 device_get_unit(dev), isa_get_irq(idev), irqs); 1410 if (bootverbose) 1411 printf("sio%d: irq maps: %#x %#x %#x %#x\n", 1412 device_get_unit(dev), 1413 irqmap[0], irqmap[1], irqmap[2], irqmap[3]); 1414 1415#ifdef PC98 1416 isa_set_portsize(dev, if_16550a_type[iod.if_type & 0x0f].io_size); 1417#else 1418 isa_set_portsize(dev, IO_COMSIZE); 1419#endif 1420 result = 0; 1421 for (fn = 0; fn < sizeof failures; ++fn) 1422 if (failures[fn]) { 1423#ifdef PC98 1424 outb(iobase + (com_mcr << port_shift), 0); 1425#else 1426 outb(iobase + com_mcr, 0); 1427#endif 1428 result = ENXIO; 1429 if (bootverbose) { 1430 printf("sio%d: probe failed test(s):", 1431 device_get_unit(dev)); 1432 for (fn = 0; fn < sizeof failures; ++fn) 1433 if (failures[fn]) 1434 printf(" %d", fn); 1435 printf("\n"); 1436 } 1437 break; 1438 } 1439 return (iobase == siocniobase ? 0 : result); 1440} 1441 1442#ifdef COM_ESP 1443static int 1444espattach(com, esp_port) 1445 struct com_s *com; 1446 Port_t esp_port; 1447{ 1448 u_char dips; 1449 u_char val; 1450 1451 /* 1452 * Check the ESP-specific I/O port to see if we're an ESP 1453 * card. If not, return failure immediately. 1454 */ 1455 if ((inb(esp_port) & 0xf3) == 0) { 1456 printf(" port 0x%x is not an ESP board?\n", esp_port); 1457 return (0); 1458 } 1459 1460 /* 1461 * We've got something that claims to be a Hayes ESP card. 1462 * Let's hope so. 1463 */ 1464 1465 /* Get the dip-switch configuration */ 1466#ifdef PC98 1467 outb(esp_port + ESP98_CMD1, ESP_GETDIPS); 1468 dips = inb(esp_port + ESP98_STATUS1); 1469#else 1470 outb(esp_port + ESP_CMD1, ESP_GETDIPS); 1471 dips = inb(esp_port + ESP_STATUS1); 1472#endif 1473 1474 /* 1475 * Bits 0,1 of dips say which COM port we are. 1476 */ 1477#ifdef PC98 1478 if ((com->iobase & 0xff) == likely_com_ports[dips & 0x03]) 1479#else 1480 if (com->iobase == likely_com_ports[dips & 0x03]) 1481#endif 1482 printf(" : ESP"); 1483 else { 1484 printf(" esp_port has com %d\n", dips & 0x03); 1485 return (0); 1486 } 1487 1488 /* 1489 * Check for ESP version 2.0 or later: bits 4,5,6 = 010. 1490 */ 1491#ifdef PC98 1492 outb(esp_port + ESP98_CMD1, ESP_GETTEST); 1493 val = inb(esp_port + ESP98_STATUS1); /* clear reg 1 */ 1494 val = inb(esp_port + ESP98_STATUS2); 1495#else 1496 outb(esp_port + ESP_CMD1, ESP_GETTEST); 1497 val = inb(esp_port + ESP_STATUS1); /* clear reg 1 */ 1498 val = inb(esp_port + ESP_STATUS2); 1499#endif 1500 if ((val & 0x70) < 0x20) { 1501 printf("-old (%o)", val & 0x70); 1502 return (0); 1503 } 1504 1505 /* 1506 * Check for ability to emulate 16550: bit 7 == 1 1507 */ 1508 if ((dips & 0x80) == 0) { 1509 printf(" slave"); 1510 return (0); 1511 } 1512 1513 /* 1514 * Okay, we seem to be a Hayes ESP card. Whee. 1515 */ 1516 com->esp = TRUE; 1517 com->esp_port = esp_port; 1518 return (1); 1519} 1520#endif /* COM_ESP */ 1521 1522static int 1523sioattach(dev) 1524 device_t dev; 1525{ 1526 struct com_s *com; 1527#ifdef COM_ESP 1528 Port_t *espp; 1529#endif 1530 Port_t iobase; 1531 int unit; 1532 void *ih; 1533 struct resource *res; 1534 int zero = 0; 1535 u_int flags = isa_get_flags(dev); 1536#ifdef PC98 1537 int port_shift = 0; 1538 u_char *obuf; 1539 u_long obufsize; 1540#endif 1541 1542 iobase = isa_get_port(dev); 1543#ifdef PC98 1544 if (((flags >> 24) & 0xff) == COM_IF_RSA98III) 1545 iobase += 8; 1546#endif 1547 unit = device_get_unit(dev); 1548 com = device_get_softc(dev); 1549#ifdef PC98 1550 obufsize = 256; 1551 if (((flags >> 24) & 0xff) == COM_IF_RSA98III) 1552 obufsize = 2048; 1553 if ((obuf = malloc(obufsize * 2, M_DEVBUF, M_NOWAIT)) == NULL) 1554 return (0); 1555 bzero(obuf, obufsize * 2); 1556#endif 1557 1558 /* 1559 * sioprobe() has initialized the device registers as follows: 1560 * o cfcr = CFCR_8BITS. 1561 * It is most important that CFCR_DLAB is off, so that the 1562 * data port is not hidden when we enable interrupts. 1563 * o ier = 0. 1564 * Interrupts are only enabled when the line is open. 1565 * o mcr = MCR_IENABLE, or 0 if the port has AST/4 compatible 1566 * interrupt control register or the config specifies no irq. 1567 * Keeping MCR_DTR and MCR_RTS off might stop the external 1568 * device from sending before we are ready. 1569 */ 1570 bzero(com, sizeof *com); 1571#ifdef PC98 1572 com->obufsize = obufsize; 1573 com->obuf1 = obuf; 1574 com->obuf2 = obuf + obufsize; 1575#endif 1576 com->unit = unit; 1577 com->cfcr_image = CFCR_8BITS; 1578 com->dtr_wait = 3 * hz; 1579 com->loses_outints = COM_LOSESOUTINTS(flags) != 0; 1580 com->no_irq = isa_get_irq(dev) < 0; 1581 com->tx_fifo_size = 1; 1582 com->obufs[0].l_head = com->obuf1; 1583 com->obufs[1].l_head = com->obuf2; 1584 1585 com->iobase = iobase; 1586#ifdef PC98 1587 if (pc98_set_ioport(com, isa_get_flags(dev)) == -1) { 1588 com->pc98_if_type = (isa_get_flags(dev) >> 24) & 0xff; 1589 port_shift = if_16550a_type[com->pc98_if_type & 0x0f].port_shift; 1590 com->data_port = iobase + (com_data << port_shift); 1591 com->int_id_port = iobase + (com_iir << port_shift); 1592 com->modem_ctl_port = iobase + (com_mcr << port_shift); 1593 com->mcr_image = inb(com->modem_ctl_port); 1594 com->line_status_port = iobase + (com_lsr << port_shift); 1595 com->modem_status_port = iobase + (com_msr << port_shift); 1596 com->intr_ctl_port = iobase + (com_ier << port_shift); 1597 } 1598#else /* not PC98 */ 1599 com->data_port = iobase + com_data; 1600 com->int_id_port = iobase + com_iir; 1601 com->modem_ctl_port = iobase + com_mcr; 1602 com->mcr_image = inb(com->modem_ctl_port); 1603 com->line_status_port = iobase + com_lsr; 1604 com->modem_status_port = iobase + com_msr; 1605 com->intr_ctl_port = iobase + com_ier; 1606#endif 1607 1608 /* 1609 * We don't use all the flags from <sys/ttydefaults.h> since they 1610 * are only relevant for logins. It's important to have echo off 1611 * initially so that the line doesn't start blathering before the 1612 * echo flag can be turned off. 1613 */ 1614 com->it_in.c_iflag = 0; 1615 com->it_in.c_oflag = 0; 1616 com->it_in.c_cflag = TTYDEF_CFLAG; 1617 com->it_in.c_lflag = 0; 1618 if (unit == comconsole) { 1619#ifdef PC98 1620 if (IS_8251(com->pc98_if_type)) 1621 DELAY(100000); 1622#endif 1623 com->it_in.c_iflag = TTYDEF_IFLAG; 1624 com->it_in.c_oflag = TTYDEF_OFLAG; 1625 com->it_in.c_cflag = TTYDEF_CFLAG | CLOCAL; 1626 com->it_in.c_lflag = TTYDEF_LFLAG; 1627 com->lt_out.c_cflag = com->lt_in.c_cflag = CLOCAL; 1628 com->lt_out.c_ispeed = com->lt_out.c_ospeed = 1629 com->lt_in.c_ispeed = com->lt_in.c_ospeed = 1630 com->it_in.c_ispeed = com->it_in.c_ospeed = comdefaultrate; 1631 } else 1632 com->it_in.c_ispeed = com->it_in.c_ospeed = TTYDEF_SPEED; 1633 if (siosetwater(com, com->it_in.c_ispeed) != 0) { 1634 enable_intr(); 1635 free(com, M_DEVBUF); 1636 return (0); 1637 } 1638 enable_intr(); 1639 termioschars(&com->it_in); 1640 com->it_out = com->it_in; 1641 1642 /* attempt to determine UART type */ 1643 printf("sio%d: type", unit); 1644 1645 1646#ifndef PC98 1647#ifdef COM_MULTIPORT 1648 if (!COM_ISMULTIPORT(flags) && !COM_IIR_TXRDYBUG(flags)) 1649#else 1650 if (!COM_IIR_TXRDYBUG(flags)) 1651#endif 1652 { 1653 u_char scr; 1654 u_char scr1; 1655 u_char scr2; 1656 1657 scr = inb(iobase + com_scr); 1658 outb(iobase + com_scr, 0xa5); 1659 scr1 = inb(iobase + com_scr); 1660 outb(iobase + com_scr, 0x5a); 1661 scr2 = inb(iobase + com_scr); 1662 outb(iobase + com_scr, scr); 1663 if (scr1 != 0xa5 || scr2 != 0x5a) { 1664 printf(" 8250"); 1665 goto determined_type; 1666 } 1667 } 1668#endif /* !PC98 */ 1669#ifdef PC98 1670 if (IS_8251(com->pc98_if_type)) { 1671 com_int_TxRx_disable( com ); 1672 com_cflag_and_speed_set( com, com->it_in.c_cflag, comdefaultrate ); 1673 com_tiocm_bic( com, TIOCM_DTR|TIOCM_RTS|TIOCM_LE ); 1674 com_send_break_off( com ); 1675 printf(" 8251%s", if_8251_type[com->pc98_if_type & 0x0f].name); 1676 } else { 1677 outb(iobase + (com_fifo << port_shift), FIFO_ENABLE | FIFO_RX_HIGH); 1678#else 1679 outb(iobase + com_fifo, FIFO_ENABLE | FIFO_RX_HIGH); 1680#endif /* PC98 */ 1681 DELAY(100); 1682 com->st16650a = 0; 1683 switch (inb(com->int_id_port) & IIR_FIFO_MASK) { 1684 case FIFO_RX_LOW: 1685 printf(" 16450"); 1686 break; 1687 case FIFO_RX_MEDL: 1688 printf(" 16450?"); 1689 break; 1690 case FIFO_RX_MEDH: 1691 printf(" 16550?"); 1692 break; 1693 case FIFO_RX_HIGH: 1694 if (COM_NOFIFO(flags)) { 1695 printf(" 16550A fifo disabled"); 1696 } else { 1697 com->hasfifo = TRUE; 1698#ifdef PC98 1699 com->tx_fifo_size = 0; /* XXX flag conflicts. */ 1700 printf(" 16550A"); 1701#else 1702 if (COM_ST16650A(flags)) { 1703 com->st16650a = 1; 1704 com->tx_fifo_size = 32; 1705 printf(" ST16650A"); 1706 } else { 1707 com->tx_fifo_size = COM_FIFOSIZE(flags); 1708 printf(" 16550A"); 1709 } 1710#endif 1711 } 1712#ifdef PC98 1713 if (com->pc98_if_type == COM_IF_RSA98III) { 1714 com->tx_fifo_size = 2048; 1715 com->rsabase = isa_get_port(dev); 1716 outb(com->rsabase + rsa_ier, 0x00); 1717 outb(com->rsabase + rsa_frr, 0x00); 1718 } 1719#endif 1720 1721#ifdef COM_ESP 1722#ifdef PC98 1723 if (com->pc98_if_type == COM_IF_ESP98) 1724#endif 1725 for (espp = likely_esp_ports; *espp != 0; espp++) 1726 if (espattach(com, *espp)) { 1727 com->tx_fifo_size = 1024; 1728 break; 1729 } 1730#endif 1731 if (!com->st16650a) { 1732 if (!com->tx_fifo_size) 1733 com->tx_fifo_size = 16; 1734 else 1735 printf(" lookalike with %d bytes FIFO", 1736 com->tx_fifo_size); 1737 } 1738 1739 break; 1740 } 1741 1742#ifdef PC98 1743 if (com->pc98_if_type == COM_IF_RSB3000) { 1744 /* Set RSB-2000/3000 Extended Buffer mode. */ 1745 u_char lcr; 1746 lcr = inb(iobase + (com_cfcr << port_shift)); 1747 outb(iobase + (com_cfcr << port_shift), lcr | CFCR_DLAB); 1748 outb(iobase + (com_emr << port_shift), EMR_EXBUFF | EMR_EFMODE); 1749 outb(iobase + (com_cfcr << port_shift), lcr); 1750 } 1751#endif 1752 1753#ifdef COM_ESP 1754 if (com->esp) { 1755 /* 1756 * Set 16550 compatibility mode. 1757 * We don't use the ESP_MODE_SCALE bit to increase the 1758 * fifo trigger levels because we can't handle large 1759 * bursts of input. 1760 * XXX flow control should be set in comparam(), not here. 1761 */ 1762#ifdef PC98 1763 outb(com->esp_port + ESP98_CMD1, ESP_SETMODE); 1764 outb(com->esp_port + ESP98_CMD2, ESP_MODE_RTS | ESP_MODE_FIFO); 1765#else 1766 outb(com->esp_port + ESP_CMD1, ESP_SETMODE); 1767 outb(com->esp_port + ESP_CMD2, ESP_MODE_RTS | ESP_MODE_FIFO); 1768#endif 1769 1770 /* Set RTS/CTS flow control. */ 1771#ifdef PC98 1772 outb(com->esp_port + ESP98_CMD1, ESP_SETFLOWTYPE); 1773 outb(com->esp_port + ESP98_CMD2, ESP_FLOW_RTS); 1774 outb(com->esp_port + ESP98_CMD2, ESP_FLOW_CTS); 1775#else 1776 outb(com->esp_port + ESP_CMD1, ESP_SETFLOWTYPE); 1777 outb(com->esp_port + ESP_CMD2, ESP_FLOW_RTS); 1778 outb(com->esp_port + ESP_CMD2, ESP_FLOW_CTS); 1779#endif 1780 1781 /* Set flow-control levels. */ 1782#ifdef PC98 1783 outb(com->esp_port + ESP98_CMD1, ESP_SETRXFLOW); 1784 outb(com->esp_port + ESP98_CMD2, HIBYTE(768)); 1785 outb(com->esp_port + ESP98_CMD2, LOBYTE(768)); 1786 outb(com->esp_port + ESP98_CMD2, HIBYTE(512)); 1787 outb(com->esp_port + ESP98_CMD2, LOBYTE(512)); 1788#else 1789 outb(com->esp_port + ESP_CMD1, ESP_SETRXFLOW); 1790 outb(com->esp_port + ESP_CMD2, HIBYTE(768)); 1791 outb(com->esp_port + ESP_CMD2, LOBYTE(768)); 1792 outb(com->esp_port + ESP_CMD2, HIBYTE(512)); 1793 outb(com->esp_port + ESP_CMD2, LOBYTE(512)); 1794#endif 1795 1796#ifdef PC98 1797 /* Set UART clock prescaler. */ 1798 outb(com->esp_port + ESP98_CMD1, ESP_SETCLOCK); 1799 outb(com->esp_port + ESP98_CMD2, 2); /* 4 times */ 1800#endif 1801 } 1802#endif /* COM_ESP */ 1803#ifdef PC98 1804 printf("%s", if_16550a_type[com->pc98_if_type & 0x0f].name); 1805 outb(iobase + (com_fifo << port_shift), 0); 1806#else 1807 outb(iobase + com_fifo, 0); 1808determined_type: ; 1809#endif 1810 1811#ifdef COM_MULTIPORT 1812 if (COM_ISMULTIPORT(flags)) { 1813 com->multiport = TRUE; 1814 printf(" (multiport"); 1815 if (unit == COM_MPMASTER(flags)) 1816 printf(" master"); 1817 printf(")"); 1818 com->no_irq = 1819 isa_get_irq(devclass_get_device 1820 (sio_devclass, COM_MPMASTER(flags))) < 0; 1821 } 1822#endif /* COM_MULTIPORT */ 1823#ifdef PC98 1824 } 1825#endif 1826 if (unit == comconsole) 1827 printf(", console"); 1828 if ( COM_IIR_TXRDYBUG(flags) ) 1829 printf(" with a bogus IIR_TXRDY register"); 1830 printf("\n"); 1831 1832 if (!sio_registered) { 1833 register_swi(SWI_TTY, siopoll); 1834 sio_registered = TRUE; 1835 } 1836#ifdef DEVFS 1837 com->devfs_token_ttyd = devfs_add_devswf(&sio_cdevsw, 1838 unit, DV_CHR, 1839 UID_ROOT, GID_WHEEL, 0600, "ttyd%r", unit); 1840 com->devfs_token_ttyi = devfs_add_devswf(&sio_cdevsw, 1841 unit | CONTROL_INIT_STATE, DV_CHR, 1842 UID_ROOT, GID_WHEEL, 0600, "ttyid%r", unit); 1843 com->devfs_token_ttyl = devfs_add_devswf(&sio_cdevsw, 1844 unit | CONTROL_LOCK_STATE, DV_CHR, 1845 UID_ROOT, GID_WHEEL, 0600, "ttyld%r", unit); 1846 com->devfs_token_cuaa = devfs_add_devswf(&sio_cdevsw, 1847 unit | CALLOUT_MASK, DV_CHR, 1848 UID_UUCP, GID_DIALER, 0660, "cuaa%r", unit); 1849 com->devfs_token_cuai = devfs_add_devswf(&sio_cdevsw, 1850 unit | CALLOUT_MASK | CONTROL_INIT_STATE, DV_CHR, 1851 UID_UUCP, GID_DIALER, 0660, "cuaia%r", unit); 1852 com->devfs_token_cual = devfs_add_devswf(&sio_cdevsw, 1853 unit | CALLOUT_MASK | CONTROL_LOCK_STATE, DV_CHR, 1854 UID_UUCP, GID_DIALER, 0660, "cuala%r", unit); 1855#endif 1856 com->flags = isa_get_flags(dev); /* Heritate id_flags for later */ 1857 com->pps.ppscap = PPS_CAPTUREASSERT | PPS_CAPTURECLEAR; 1858 pps_init(&com->pps); 1859 1860 res = bus_alloc_resource(dev, SYS_RES_IRQ, &zero, 0ul, ~0ul, 1, 1861 RF_SHAREABLE | RF_ACTIVE); 1862 BUS_SETUP_INTR(device_get_parent(dev), dev, res, 1863 INTR_TYPE_TTY | INTR_TYPE_FAST, 1864 siointr, com, &ih); 1865 1866 return (0); 1867} 1868 1869static int 1870sioopen(dev, flag, mode, p) 1871 dev_t dev; 1872 int flag; 1873 int mode; 1874 struct proc *p; 1875{ 1876 struct com_s *com; 1877 int error; 1878 Port_t iobase; 1879 int mynor; 1880 int s; 1881 struct tty *tp; 1882 int unit; 1883#ifdef PC98 1884 int port_shift = 0; 1885#endif 1886 1887 mynor = minor(dev); 1888 unit = MINOR_TO_UNIT(mynor); 1889 if ((u_int) unit >= NSIOTOT || (com = com_addr(unit)) == NULL) 1890 return (ENXIO); 1891 if (com->gone) 1892 return (ENXIO); 1893 if (mynor & CONTROL_MASK) 1894 return (0); 1895#if 0 /* XXX */ 1896 tp = com->tp = sio_tty[unit] = ttymalloc(sio_tty[unit]); 1897#else 1898 tp = com->tp = &sio_tty[unit]; 1899#endif 1900 s = spltty(); 1901 1902#ifdef PC98 1903 if (!IS_8251(com->pc98_if_type)) 1904 port_shift = if_16550a_type[com->pc98_if_type & 0x0f].port_shift; 1905#endif 1906 /* 1907 * We jump to this label after all non-interrupted sleeps to pick 1908 * up any changes of the device state. 1909 */ 1910open_top: 1911 while (com->state & CS_DTR_OFF) { 1912 error = tsleep(&com->dtr_wait, TTIPRI | PCATCH, "siodtr", 0); 1913 if (com_addr(unit) == NULL) 1914 return (ENXIO); 1915 if (error != 0 || com->gone) 1916 goto out; 1917 } 1918 if (tp->t_state & TS_ISOPEN) { 1919 /* 1920 * The device is open, so everything has been initialized. 1921 * Handle conflicts. 1922 */ 1923 if (mynor & CALLOUT_MASK) { 1924 if (!com->active_out) { 1925 error = EBUSY; 1926 goto out; 1927 } 1928 } else { 1929 if (com->active_out) { 1930 if (flag & O_NONBLOCK) { 1931 error = EBUSY; 1932 goto out; 1933 } 1934 error = tsleep(&com->active_out, 1935 TTIPRI | PCATCH, "siobi", 0); 1936 if (com_addr(unit) == NULL) 1937 return (ENXIO); 1938 if (error != 0 || com->gone) 1939 goto out; 1940 goto open_top; 1941 } 1942 } 1943 if (tp->t_state & TS_XCLUDE && 1944 suser(p)) { 1945 error = EBUSY; 1946 goto out; 1947 } 1948 } else { 1949 /* 1950 * The device isn't open, so there are no conflicts. 1951 * Initialize it. Initialization is done twice in many 1952 * cases: to preempt sleeping callin opens if we are 1953 * callout, and to complete a callin open after DCD rises. 1954 */ 1955 tp->t_oproc = comstart; 1956 tp->t_param = comparam; 1957 tp->t_dev = dev; 1958 tp->t_termios = mynor & CALLOUT_MASK 1959 ? com->it_out : com->it_in; 1960#ifdef PC98 1961 if (!IS_8251(com->pc98_if_type)) 1962#endif 1963 (void)commctl(com, TIOCM_DTR | TIOCM_RTS, DMSET); 1964 com->poll = com->no_irq; 1965 com->poll_output = com->loses_outints; 1966 ++com->wopeners; 1967 error = comparam(tp, &tp->t_termios); 1968 --com->wopeners; 1969 if (error != 0) 1970 goto out; 1971#ifdef PC98 1972 if (IS_8251(com->pc98_if_type)) { 1973 com_tiocm_bis(com, TIOCM_DTR|TIOCM_RTS); 1974 pc98_msrint_start(dev); 1975 } 1976#endif 1977 /* 1978 * XXX we should goto open_top if comparam() slept. 1979 */ 1980 iobase = com->iobase; 1981 if (com->hasfifo) { 1982 /* 1983 * (Re)enable and drain fifos. 1984 * 1985 * Certain SMC chips cause problems if the fifos 1986 * are enabled while input is ready. Turn off the 1987 * fifo if necessary to clear the input. We test 1988 * the input ready bit after enabling the fifos 1989 * since we've already enabled them in comparam() 1990 * and to handle races between enabling and fresh 1991 * input. 1992 */ 1993 while (TRUE) { 1994#ifdef PC98 1995 outb(iobase + (com_fifo << port_shift), 1996 FIFO_RCV_RST | FIFO_XMT_RST 1997 | com->fifo_image); 1998 if (com->pc98_if_type == COM_IF_RSA98III) 1999 outb(com->rsabase + rsa_frr , 0x00); 2000#else 2001 outb(iobase + com_fifo, 2002 FIFO_RCV_RST | FIFO_XMT_RST 2003 | com->fifo_image); 2004#endif 2005 /* 2006 * XXX the delays are for superstitious 2007 * historical reasons. It must be less than 2008 * the character time at the maximum 2009 * supported speed (87 usec at 115200 bps 2010 * 8N1). Otherwise we might loop endlessly 2011 * if data is streaming in. We used to use 2012 * delays of 100. That usually worked 2013 * because DELAY(100) used to usually delay 2014 * for about 85 usec instead of 100. 2015 */ 2016 DELAY(50); 2017#ifndef PC98 2018 if (!(inb(com->line_status_port) & LSR_RXRDY)) 2019#else 2020 if (com->pc98_if_type == COM_IF_RSA98III 2021 ? !(inb(com->rsabase + rsa_srr) & 0x08) 2022 : !(inb(com->line_status_port) & LSR_RXRDY)) 2023#endif 2024 break; 2025#ifdef PC98 2026 outb(iobase + (com_fifo << port_shift), 0); 2027#else 2028 outb(iobase + com_fifo, 0); 2029#endif 2030 DELAY(50); 2031 (void) inb(com->data_port); 2032 } 2033 } 2034 2035 disable_intr(); 2036#ifdef PC98 2037 if (IS_8251(com->pc98_if_type)) { 2038 com_tiocm_bis(com, TIOCM_LE); 2039 com->pc98_prev_modem_status = pc98_get_modem_status(com); 2040 com_int_Rx_enable(com); 2041 } else { 2042#endif 2043 (void) inb(com->line_status_port); 2044 (void) inb(com->data_port); 2045 com->prev_modem_status = com->last_modem_status 2046 = inb(com->modem_status_port); 2047 if (COM_IIR_TXRDYBUG(com->flags)) { 2048 outb(com->intr_ctl_port, IER_ERXRDY | IER_ERLS 2049 | IER_EMSC); 2050 } else { 2051 outb(com->intr_ctl_port, IER_ERXRDY | IER_ETXRDY 2052 | IER_ERLS | IER_EMSC); 2053 } 2054#ifdef PC98 2055 if (com->pc98_if_type == COM_IF_RSA98III) { 2056 outb(com->rsabase + rsa_ier, 0x1d); 2057 outb(com->intr_ctl_port, IER_ERLS | IER_EMSC); 2058 } 2059#endif 2060#ifdef PC98 2061 } 2062#endif 2063 enable_intr(); 2064 /* 2065 * Handle initial DCD. Callout devices get a fake initial 2066 * DCD (trapdoor DCD). If we are callout, then any sleeping 2067 * callin opens get woken up and resume sleeping on "siobi" 2068 * instead of "siodcd". 2069 */ 2070 /* 2071 * XXX `mynor & CALLOUT_MASK' should be 2072 * `tp->t_cflag & (SOFT_CARRIER | TRAPDOOR_CARRIER) where 2073 * TRAPDOOR_CARRIER is the default initial state for callout 2074 * devices and SOFT_CARRIER is like CLOCAL except it hides 2075 * the true carrier. 2076 */ 2077#ifdef PC98 2078 if ((IS_8251(com->pc98_if_type) && 2079 (pc98_get_modem_status(com) & TIOCM_CAR)) || 2080 (!IS_8251(com->pc98_if_type) && 2081 (com->prev_modem_status & MSR_DCD)) || 2082 mynor & CALLOUT_MASK) 2083#else 2084 if (com->prev_modem_status & MSR_DCD || mynor & CALLOUT_MASK) 2085#endif 2086 (*linesw[tp->t_line].l_modem)(tp, 1); 2087 } 2088 /* 2089 * Wait for DCD if necessary. 2090 */ 2091 if (!(tp->t_state & TS_CARR_ON) && !(mynor & CALLOUT_MASK) 2092 && !(tp->t_cflag & CLOCAL) && !(flag & O_NONBLOCK)) { 2093 ++com->wopeners; 2094 error = tsleep(TSA_CARR_ON(tp), TTIPRI | PCATCH, "siodcd", 0); 2095 if (com_addr(unit) == NULL) 2096 return (ENXIO); 2097 --com->wopeners; 2098 if (error != 0 || com->gone) 2099 goto out; 2100 goto open_top; 2101 } 2102 error = (*linesw[tp->t_line].l_open)(dev, tp); 2103 disc_optim(tp, &tp->t_termios, com); 2104 if (tp->t_state & TS_ISOPEN && mynor & CALLOUT_MASK) 2105 com->active_out = TRUE; 2106 siosettimeout(); 2107out: 2108 splx(s); 2109 if (!(tp->t_state & TS_ISOPEN) && com->wopeners == 0) 2110 comhardclose(com); 2111 return (error); 2112} 2113 2114static int 2115sioclose(dev, flag, mode, p) 2116 dev_t dev; 2117 int flag; 2118 int mode; 2119 struct proc *p; 2120{ 2121 struct com_s *com; 2122 int mynor; 2123 int s; 2124 struct tty *tp; 2125 2126 mynor = minor(dev); 2127 if (mynor & CONTROL_MASK) 2128 return (0); 2129 com = com_addr(MINOR_TO_UNIT(mynor)); 2130 tp = com->tp; 2131 s = spltty(); 2132 (*linesw[tp->t_line].l_close)(tp, flag); 2133#ifdef PC98 2134 com->modem_checking = 0; 2135#endif 2136 disc_optim(tp, &tp->t_termios, com); 2137 siostop(tp, FREAD | FWRITE); 2138 comhardclose(com); 2139 ttyclose(tp); 2140 siosettimeout(); 2141 splx(s); 2142 if (com->gone) { 2143 printf("sio%d: gone\n", com->unit); 2144 s = spltty(); 2145 if (com->ibuf != NULL) 2146 free(com->ibuf, M_DEVBUF); 2147 bzero(tp, sizeof *tp); 2148 free(com, M_DEVBUF); 2149 splx(s); 2150 } 2151 return (0); 2152} 2153 2154static void 2155comhardclose(com) 2156 struct com_s *com; 2157{ 2158 Port_t iobase; 2159 int s; 2160 struct tty *tp; 2161 int unit; 2162#ifdef PC98 2163 int port_shift = 0; 2164#endif 2165 2166 unit = com->unit; 2167 iobase = com->iobase; 2168 s = spltty(); 2169 com->poll = FALSE; 2170 com->poll_output = FALSE; 2171 com->do_timestamp = FALSE; 2172 com->do_dcd_timestamp = FALSE; 2173 com->pps.ppsparam.mode = 0; 2174#ifdef PC98 2175 if (IS_8251(com->pc98_if_type)) 2176 com_send_break_off(com); 2177 else { 2178 port_shift = if_16550a_type[com->pc98_if_type & 0x0f].port_shift; 2179 outb(iobase + (com_cfcr << port_shift), 2180 com->cfcr_image &= ~CFCR_SBREAK); 2181 } 2182#else 2183 outb(iobase + com_cfcr, com->cfcr_image &= ~CFCR_SBREAK); 2184#endif 2185 { 2186#ifdef PC98 2187 int tmp; 2188 if (IS_8251(com->pc98_if_type)) 2189 com_int_TxRx_disable(com); 2190 else 2191 outb(iobase + (com_ier << port_shift), 0); 2192 if (com->pc98_if_type == COM_IF_RSA98III) { 2193 outb(com->rsabase + rsa_ier, 0x00); 2194 } 2195#else 2196 outb(iobase + com_ier, 0); 2197#endif 2198 tp = com->tp; 2199#ifdef PC98 2200 if (IS_8251(com->pc98_if_type)) 2201 tmp = pc98_get_modem_status(com) & TIOCM_CAR; 2202 else 2203 tmp = com->prev_modem_status & MSR_DCD; 2204#endif 2205 if (tp->t_cflag & HUPCL 2206 /* 2207 * XXX we will miss any carrier drop between here and the 2208 * next open. Perhaps we should watch DCD even when the 2209 * port is closed; it is not sufficient to check it at 2210 * the next open because it might go up and down while 2211 * we're not watching. 2212 */ 2213 || (!com->active_out 2214#ifdef PC98 2215 && !(tmp) 2216#else 2217 && !(com->prev_modem_status & MSR_DCD) 2218#endif 2219 && !(com->it_in.c_cflag & CLOCAL)) 2220 || !(tp->t_state & TS_ISOPEN)) { 2221#ifdef PC98 2222 if (IS_8251(com->pc98_if_type)) 2223 com_tiocm_bic(com, TIOCM_DTR|TIOCM_RTS|TIOCM_LE); 2224 else 2225#endif 2226 (void)commctl(com, TIOCM_DTR, DMBIC); 2227 if (com->dtr_wait != 0 && !(com->state & CS_DTR_OFF)) { 2228 timeout(siodtrwakeup, com, com->dtr_wait); 2229 com->state |= CS_DTR_OFF; 2230 } 2231 } 2232#ifdef PC98 2233 else { 2234 if (IS_8251(com->pc98_if_type)) 2235 com_tiocm_bic(com, TIOCM_LE ); 2236 } 2237#endif 2238 } 2239 if (com->hasfifo) { 2240 /* 2241 * Disable fifos so that they are off after controlled 2242 * reboots. Some BIOSes fail to detect 16550s when the 2243 * fifos are enabled. 2244 */ 2245#ifdef PC98 2246 outb(iobase + (com_fifo << port_shift), 0); 2247#else 2248 outb(iobase + com_fifo, 0); 2249#endif 2250 } 2251 com->active_out = FALSE; 2252 wakeup(&com->active_out); 2253 wakeup(TSA_CARR_ON(tp)); /* restart any wopeners */ 2254 splx(s); 2255} 2256 2257static int 2258sioread(dev, uio, flag) 2259 dev_t dev; 2260 struct uio *uio; 2261 int flag; 2262{ 2263 int mynor; 2264 struct com_s *com; 2265 2266 mynor = minor(dev); 2267 if (mynor & CONTROL_MASK) 2268 return (ENODEV); 2269 com = com_addr(MINOR_TO_UNIT(mynor)); 2270 if (com->gone) 2271 return (ENODEV); 2272 return ((*linesw[com->tp->t_line].l_read)(com->tp, uio, flag)); 2273} 2274 2275static int 2276siowrite(dev, uio, flag) 2277 dev_t dev; 2278 struct uio *uio; 2279 int flag; 2280{ 2281 int mynor; 2282 struct com_s *com; 2283 int unit; 2284 2285 mynor = minor(dev); 2286 if (mynor & CONTROL_MASK) 2287 return (ENODEV); 2288 2289 unit = MINOR_TO_UNIT(mynor); 2290 com = com_addr(unit); 2291 if (com->gone) 2292 return (ENODEV); 2293 /* 2294 * (XXX) We disallow virtual consoles if the physical console is 2295 * a serial port. This is in case there is a display attached that 2296 * is not the console. In that situation we don't need/want the X 2297 * server taking over the console. 2298 */ 2299 if (constty != NULL && unit == comconsole) 2300 constty = NULL; 2301 return ((*linesw[com->tp->t_line].l_write)(com->tp, uio, flag)); 2302} 2303 2304static void 2305siobusycheck(chan) 2306 void *chan; 2307{ 2308 struct com_s *com; 2309 int s; 2310 2311 com = (struct com_s *)chan; 2312 2313 /* 2314 * Clear TS_BUSY if low-level output is complete. 2315 * spl locking is sufficient because siointr1() does not set CS_BUSY. 2316 * If siointr1() clears CS_BUSY after we look at it, then we'll get 2317 * called again. Reading the line status port outside of siointr1() 2318 * is safe because CS_BUSY is clear so there are no output interrupts 2319 * to lose. 2320 */ 2321 s = spltty(); 2322 if (com->state & CS_BUSY) 2323 com->extra_state &= ~CSE_BUSYCHECK; /* False alarm. */ 2324#ifdef PC98 2325 else if ((IS_8251(com->pc98_if_type) && 2326 (inb(com->sts_port) & (STS8251_TxRDY | STS8251_TxEMP)) 2327 == (STS8251_TxRDY | STS8251_TxEMP)) || 2328 (inb(com->line_status_port) & (LSR_TSRE | LSR_TXRDY)) 2329 == (LSR_TSRE | LSR_TXRDY)) { 2330#else 2331 else if ((inb(com->line_status_port) & (LSR_TSRE | LSR_TXRDY)) 2332 == (LSR_TSRE | LSR_TXRDY)) { 2333#endif 2334 com->tp->t_state &= ~TS_BUSY; 2335 ttwwakeup(com->tp); 2336 com->extra_state &= ~CSE_BUSYCHECK; 2337 } else 2338 timeout(siobusycheck, com, hz / 100); 2339 splx(s); 2340} 2341 2342static void 2343siodtrwakeup(chan) 2344 void *chan; 2345{ 2346 struct com_s *com; 2347 2348 com = (struct com_s *)chan; 2349 com->state &= ~CS_DTR_OFF; 2350 wakeup(&com->dtr_wait); 2351} 2352 2353static void 2354sioinput(com) 2355 struct com_s *com; 2356{ 2357 u_char *buf; 2358 int incc; 2359 u_char line_status; 2360 int recv_data; 2361 struct tty *tp; 2362#ifdef PC98 2363 u_char tmp; 2364#endif 2365 2366 buf = com->ibuf; 2367 tp = com->tp; 2368 if (!(tp->t_state & TS_ISOPEN) || !(tp->t_cflag & CREAD)) { 2369 com_events -= (com->iptr - com->ibuf); 2370 com->iptr = com->ibuf; 2371 return; 2372 } 2373 if (tp->t_state & TS_CAN_BYPASS_L_RINT) { 2374 /* 2375 * Avoid the grotesquely inefficient lineswitch routine 2376 * (ttyinput) in "raw" mode. It usually takes about 450 2377 * instructions (that's without canonical processing or echo!). 2378 * slinput is reasonably fast (usually 40 instructions plus 2379 * call overhead). 2380 */ 2381 do { 2382 enable_intr(); 2383 incc = com->iptr - buf; 2384 if (tp->t_rawq.c_cc + incc > tp->t_ihiwat 2385 && (com->state & CS_RTS_IFLOW 2386 || tp->t_iflag & IXOFF) 2387 && !(tp->t_state & TS_TBLOCK)) 2388 ttyblock(tp); 2389 com->delta_error_counts[CE_TTY_BUF_OVERFLOW] 2390 += b_to_q((char *)buf, incc, &tp->t_rawq); 2391 buf += incc; 2392 tk_nin += incc; 2393 tk_rawcc += incc; 2394 tp->t_rawcc += incc; 2395 ttwakeup(tp); 2396 if (tp->t_state & TS_TTSTOP 2397 && (tp->t_iflag & IXANY 2398 || tp->t_cc[VSTART] == tp->t_cc[VSTOP])) { 2399 tp->t_state &= ~TS_TTSTOP; 2400 tp->t_lflag &= ~FLUSHO; 2401 comstart(tp); 2402 } 2403 disable_intr(); 2404 } while (buf < com->iptr); 2405 } else { 2406 do { 2407 enable_intr(); 2408 line_status = buf[com->ierroff]; 2409 recv_data = *buf++; 2410 if (line_status 2411 & (LSR_BI | LSR_FE | LSR_OE | LSR_PE)) { 2412 if (line_status & LSR_BI) 2413 recv_data |= TTY_BI; 2414 if (line_status & LSR_FE) 2415 recv_data |= TTY_FE; 2416 if (line_status & LSR_OE) 2417 recv_data |= TTY_OE; 2418 if (line_status & LSR_PE) 2419 recv_data |= TTY_PE; 2420 } 2421 (*linesw[tp->t_line].l_rint)(recv_data, tp); 2422 disable_intr(); 2423 } while (buf < com->iptr); 2424 } 2425 com_events -= (com->iptr - com->ibuf); 2426 com->iptr = com->ibuf; 2427 2428 /* 2429 * There is now room for another low-level buffer full of input, 2430 * so enable RTS if it is now disabled and there is room in the 2431 * high-level buffer. 2432 */ 2433#ifdef PC98 2434 if (IS_8251(com->pc98_if_type)) 2435 tmp = com_tiocm_get(com) & TIOCM_RTS; 2436 else 2437 tmp = com->mcr_image & MCR_RTS; 2438 if ((com->state & CS_RTS_IFLOW) && !(tmp) && 2439 !(tp->t_state & TS_TBLOCK)) 2440 if (IS_8251(com->pc98_if_type)) 2441 com_tiocm_bis(com, TIOCM_RTS); 2442 else 2443 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS); 2444#else 2445 if ((com->state & CS_RTS_IFLOW) && !(com->mcr_image & MCR_RTS) && 2446 !(tp->t_state & TS_TBLOCK)) 2447 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS); 2448#endif 2449} 2450 2451void 2452siointr(arg) 2453 void *arg; 2454{ 2455#ifndef COM_MULTIPORT 2456 COM_LOCK(); 2457 siointr1((struct com_s *) arg); 2458 COM_UNLOCK(); 2459#else /* COM_MULTIPORT */ 2460 bool_t possibly_more_intrs; 2461 int unit; 2462 struct com_s *com; 2463#ifdef PC98 2464 u_char rsa_buf_status; 2465#endif 2466 2467 /* 2468 * Loop until there is no activity on any port. This is necessary 2469 * to get an interrupt edge more than to avoid another interrupt. 2470 * If the IRQ signal is just an OR of the IRQ signals from several 2471 * devices, then the edge from one may be lost because another is 2472 * on. 2473 */ 2474 COM_LOCK(); 2475 do { 2476 possibly_more_intrs = FALSE; 2477 for (unit = 0; unit < NSIOTOT; ++unit) { 2478 com = com_addr(unit); 2479 /* 2480 * XXX COM_LOCK(); 2481 * would it work here, or be counter-productive? 2482 */ 2483#ifdef PC98 2484 if (com != NULL 2485 && !com->gone 2486 && IS_8251(com->pc98_if_type)){ 2487 siointr1(com); 2488 } else 2489#endif /* PC98 */ 2490#ifdef PC98 2491 if (com != NULL 2492 && !com->gone 2493 && com->pc98_if_type == COM_IF_RSA98III) { 2494 rsa_buf_status = inb(com->rsabase + rsa_srr) & 0xc9; 2495 if ((rsa_buf_status & 0xc8) 2496 || !(rsa_buf_status & 0x01)) { 2497 siointr1(com); 2498 if(rsa_buf_status 2499 != (inb(com->rsabase + rsa_srr) & 0xc9)) 2500 possibly_more_intrs = TRUE; 2501 } 2502 } else 2503#endif 2504 if (com != NULL 2505 && !com->gone 2506 && (inb(com->int_id_port) & IIR_IMASK) 2507 != IIR_NOPEND) { 2508 siointr1(com); 2509 possibly_more_intrs = TRUE; 2510 } 2511 /* XXX COM_UNLOCK(); */ 2512 } 2513 } while (possibly_more_intrs); 2514 COM_UNLOCK(); 2515#endif /* COM_MULTIPORT */ 2516} 2517 2518static void 2519siointr1(com) 2520 struct com_s *com; 2521{ 2522 u_char line_status; 2523 u_char modem_status; 2524 u_char *ioptr; 2525 u_char recv_data; 2526 u_char int_ctl; 2527 u_char int_ctl_new; 2528 struct timecounter *tc; 2529 u_int count; 2530 2531#ifdef PC98 2532 u_char tmp=0; 2533 u_char rsa_buf_status = 0; 2534 int rsa_tx_fifo_size=0; 2535 recv_data=0; 2536#endif /* PC98 */ 2537 2538 int_ctl = inb(com->intr_ctl_port); 2539 int_ctl_new = int_ctl; 2540 2541 while (!com->gone) { 2542#ifdef PC98 2543status_read:; 2544 if (IS_8251(com->pc98_if_type)) { 2545 tmp = inb(com->sts_port); 2546more_intr: 2547 line_status = 0; 2548 if (tmp & STS8251_TxRDY) line_status |= LSR_TXRDY; 2549 if (tmp & STS8251_RxRDY) line_status |= LSR_RXRDY; 2550 if (tmp & STS8251_TxEMP) line_status |= LSR_TSRE; 2551 if (tmp & STS8251_PE) line_status |= LSR_PE; 2552 if (tmp & STS8251_OE) line_status |= LSR_OE; 2553 if (tmp & STS8251_FE) line_status |= LSR_FE; 2554 if (tmp & STS8251_BD_SD) line_status |= LSR_BI; 2555 } else { 2556#endif /* PC98 */ 2557 if (com->pps.ppsparam.mode & PPS_CAPTUREBOTH) { 2558 modem_status = inb(com->modem_status_port); 2559 if ((modem_status ^ com->last_modem_status) & MSR_DCD) { 2560 tc = timecounter; 2561 count = tc->tc_get_timecount(tc); 2562 pps_event(&com->pps, tc, count, 2563 (modem_status & MSR_DCD) ? 2564 PPS_CAPTURECLEAR : PPS_CAPTUREASSERT); 2565 } 2566 } 2567 line_status = inb(com->line_status_port); 2568#ifdef PC98 2569 } 2570 if (com->pc98_if_type == COM_IF_RSA98III) 2571 rsa_buf_status = inb(com->rsabase + rsa_srr); 2572#endif /* PC98 */ 2573 2574 /* input event? (check first to help avoid overruns) */ 2575#ifndef PC98 2576 while (line_status & LSR_RCV_MASK) { 2577#else 2578 while ((line_status & LSR_RCV_MASK) 2579 || (com->pc98_if_type == COM_IF_RSA98III 2580 && (rsa_buf_status & 0x08))) { 2581#endif /* PC98 */ 2582 /* break/unnattached error bits or real input? */ 2583#ifdef PC98 2584 if (IS_8251(com->pc98_if_type)) { 2585 recv_data = inb(com->data_port); 2586 if (tmp & 0x78) { 2587 pc98_i8251_or_cmd(com,CMD8251_ER); 2588 recv_data = 0; 2589 } 2590 } else { 2591#endif /* PC98 */ 2592#ifdef PC98 2593 if (com->pc98_if_type == COM_IF_RSA98III) { 2594 if (!(rsa_buf_status & 0x08)) 2595 recv_data = 0; 2596 else { 2597 recv_data = inb(com->data_port); 2598 } 2599 } else 2600#endif 2601 if (!(line_status & LSR_RXRDY)) 2602 recv_data = 0; 2603 else 2604 recv_data = inb(com->data_port); 2605#ifdef PC98 2606 } 2607#endif 2608 if (line_status & (LSR_BI | LSR_FE | LSR_PE)) { 2609 /* 2610 * Don't store BI if IGNBRK or FE/PE if IGNPAR. 2611 * Otherwise, push the work to a higher level 2612 * (to handle PARMRK) if we're bypassing. 2613 * Otherwise, convert BI/FE and PE+INPCK to 0. 2614 * 2615 * This makes bypassing work right in the 2616 * usual "raw" case (IGNBRK set, and IGNPAR 2617 * and INPCK clear). 2618 * 2619 * Note: BI together with FE/PE means just BI. 2620 */ 2621 if (line_status & LSR_BI) { 2622#if defined(DDB) && defined(BREAK_TO_DEBUGGER) 2623 if (com->unit == comconsole) { 2624 breakpoint(); 2625 goto cont; 2626 } 2627#endif 2628 if (com->tp == NULL 2629 || com->tp->t_iflag & IGNBRK) 2630 goto cont; 2631 } else { 2632 if (com->tp == NULL 2633 || com->tp->t_iflag & IGNPAR) 2634 goto cont; 2635 } 2636 if (com->tp->t_state & TS_CAN_BYPASS_L_RINT 2637 && (line_status & (LSR_BI | LSR_FE) 2638 || com->tp->t_iflag & INPCK)) 2639 recv_data = 0; 2640 } 2641 ++com->bytes_in; 2642 if (com->hotchar != 0 && recv_data == com->hotchar) 2643 setsofttty(); 2644 ioptr = com->iptr; 2645 if (ioptr >= com->ibufend) 2646 CE_RECORD(com, CE_INTERRUPT_BUF_OVERFLOW); 2647 else { 2648 if (com->do_timestamp) 2649 microtime(&com->timestamp); 2650 ++com_events; 2651 schedsofttty(); 2652#if 0 /* for testing input latency vs efficiency */ 2653if (com->iptr - com->ibuf == 8) 2654 setsofttty(); 2655#endif 2656 ioptr[0] = recv_data; 2657 ioptr[com->ierroff] = line_status; 2658 com->iptr = ++ioptr; 2659 if (ioptr == com->ihighwater 2660 && com->state & CS_RTS_IFLOW) 2661#ifdef PC98 2662 if (IS_8251(com->pc98_if_type)) 2663 com_tiocm_bic(com, TIOCM_RTS); 2664 else 2665#endif 2666 outb(com->modem_ctl_port, 2667 com->mcr_image &= ~MCR_RTS); 2668 if (line_status & LSR_OE) 2669 CE_RECORD(com, CE_OVERRUN); 2670 } 2671cont: 2672 /* 2673 * "& 0x7F" is to avoid the gcc-1.40 generating a slow 2674 * jump from the top of the loop to here 2675 */ 2676#ifdef PC98 2677 if (IS_8251(com->pc98_if_type)) 2678 goto status_read; 2679 else 2680#endif 2681 line_status = inb(com->line_status_port) & 0x7F; 2682#ifdef PC98 2683 if (com->pc98_if_type == COM_IF_RSA98III) 2684 rsa_buf_status = inb(com->rsabase + rsa_srr); 2685#endif /* PC98 */ 2686 } 2687 2688 /* modem status change? (always check before doing output) */ 2689#ifdef PC98 2690 if (!IS_8251(com->pc98_if_type)) { 2691#endif 2692 modem_status = inb(com->modem_status_port); 2693 if (modem_status != com->last_modem_status) { 2694 if (com->do_dcd_timestamp 2695 && !(com->last_modem_status & MSR_DCD) 2696 && modem_status & MSR_DCD) 2697 microtime(&com->dcd_timestamp); 2698 2699 /* 2700 * Schedule high level to handle DCD changes. Note 2701 * that we don't use the delta bits anywhere. Some 2702 * UARTs mess them up, and it's easy to remember the 2703 * previous bits and calculate the delta. 2704 */ 2705 com->last_modem_status = modem_status; 2706 if (!(com->state & CS_CHECKMSR)) { 2707 com_events += LOTS_OF_EVENTS; 2708 com->state |= CS_CHECKMSR; 2709 setsofttty(); 2710 } 2711 2712 /* handle CTS change immediately for crisp flow ctl */ 2713 if (com->state & CS_CTS_OFLOW) { 2714 if (modem_status & MSR_CTS) 2715 com->state |= CS_ODEVREADY; 2716 else 2717 com->state &= ~CS_ODEVREADY; 2718 } 2719 } 2720#ifdef PC98 2721 } 2722#endif 2723 2724 /* output queued and everything ready? */ 2725#ifndef PC98 2726 if (line_status & LSR_TXRDY 2727 && com->state >= (CS_BUSY | CS_TTGO | CS_ODEVREADY)) { 2728#else 2729 if (((com->pc98_if_type == COM_IF_RSA98III) 2730 ? (rsa_buf_status & 0x02) 2731 : (line_status & LSR_TXRDY)) 2732 && com->state >= (CS_BUSY | CS_TTGO | CS_ODEVREADY)) { 2733#endif 2734 ioptr = com->obufq.l_head; 2735 if (com->tx_fifo_size > 1) { 2736 u_int ocount; 2737 2738 ocount = com->obufq.l_tail - ioptr; 2739#ifdef PC98 2740 if (com->pc98_if_type == COM_IF_RSA98III) { 2741 rsa_buf_status = inb(com->rsabase + rsa_srr); 2742 rsa_tx_fifo_size = 1024; 2743 if (!(rsa_buf_status & 0x01)) 2744 rsa_tx_fifo_size = 2048; 2745 if (ocount > rsa_tx_fifo_size) 2746 ocount = rsa_tx_fifo_size; 2747 } else 2748#endif 2749 if (ocount > com->tx_fifo_size) 2750 ocount = com->tx_fifo_size; 2751 com->bytes_out += ocount; 2752 do 2753 outb(com->data_port, *ioptr++); 2754 while (--ocount != 0); 2755 } else { 2756 outb(com->data_port, *ioptr++); 2757 ++com->bytes_out; 2758 } 2759#ifdef PC98 2760 if (IS_8251(com->pc98_if_type)) 2761 if (!(pc98_check_i8251_interrupt(com) & IEN_TxFLAG)) 2762 com_int_Tx_enable(com); 2763#endif 2764 com->obufq.l_head = ioptr; 2765 if (COM_IIR_TXRDYBUG(com->flags)) { 2766 int_ctl_new = int_ctl | IER_ETXRDY; 2767 } 2768 if (ioptr >= com->obufq.l_tail) { 2769 struct lbq *qp; 2770 2771 qp = com->obufq.l_next; 2772 qp->l_queued = FALSE; 2773 qp = qp->l_next; 2774 if (qp != NULL) { 2775 com->obufq.l_head = qp->l_head; 2776 com->obufq.l_tail = qp->l_tail; 2777 com->obufq.l_next = qp; 2778 } else { 2779 /* output just completed */ 2780 if ( COM_IIR_TXRDYBUG(com->flags) ) { 2781 int_ctl_new = int_ctl & ~IER_ETXRDY; 2782 } 2783 com->state &= ~CS_BUSY; 2784#if defined(PC98) 2785 if (IS_8251(com->pc98_if_type)) 2786 if ( pc98_check_i8251_interrupt(com) & IEN_TxFLAG ) 2787 com_int_Tx_disable(com); 2788#endif 2789 } 2790 if (!(com->state & CS_ODONE)) { 2791 com_events += LOTS_OF_EVENTS; 2792 com->state |= CS_ODONE; 2793 setsofttty(); /* handle at high level ASAP */ 2794 } 2795 } 2796 if ( COM_IIR_TXRDYBUG(com->flags) && (int_ctl != int_ctl_new)) { 2797#ifdef PC98 2798 if (com->pc98_if_type == COM_IF_RSA98III) { 2799 int_ctl_new &= ~(IER_ETXRDY | IER_ERXRDY); 2800 outb(com->intr_ctl_port, int_ctl_new); 2801 outb(com->rsabase + rsa_ier, 0x1d); 2802 } else 2803#endif 2804 outb(com->intr_ctl_port, int_ctl_new); 2805 } 2806 } 2807#ifdef PC98 2808 else if (line_status & LSR_TXRDY) { 2809 if (IS_8251(com->pc98_if_type)) 2810 if ( pc98_check_i8251_interrupt(com) & IEN_TxFLAG ) 2811 com_int_Tx_disable(com); 2812 } 2813 if (IS_8251(com->pc98_if_type)) 2814 if ((tmp = inb(com->sts_port)) & STS8251_RxRDY) 2815 goto more_intr; 2816#endif 2817 2818 /* finished? */ 2819#ifndef COM_MULTIPORT 2820#ifdef PC98 2821 if (IS_8251(com->pc98_if_type)) 2822 return; 2823#endif 2824 if ((inb(com->int_id_port) & IIR_IMASK) == IIR_NOPEND) 2825#endif /* COM_MULTIPORT */ 2826 return; 2827 } 2828} 2829 2830static int 2831sioioctl(dev, cmd, data, flag, p) 2832 dev_t dev; 2833 u_long cmd; 2834 caddr_t data; 2835 int flag; 2836 struct proc *p; 2837{ 2838 struct com_s *com; 2839 int error; 2840 Port_t iobase; 2841 int mynor; 2842 int s; 2843 struct tty *tp; 2844#if defined(COMPAT_43) || defined(COMPAT_SUNOS) 2845 u_long oldcmd; 2846 struct termios term; 2847#endif 2848 2849 mynor = minor(dev); 2850 com = com_addr(MINOR_TO_UNIT(mynor)); 2851 if (com->gone) 2852 return (ENODEV); 2853 iobase = com->iobase; 2854 if (mynor & CONTROL_MASK) { 2855 struct termios *ct; 2856 2857 switch (mynor & CONTROL_MASK) { 2858 case CONTROL_INIT_STATE: 2859 ct = mynor & CALLOUT_MASK ? &com->it_out : &com->it_in; 2860 break; 2861 case CONTROL_LOCK_STATE: 2862 ct = mynor & CALLOUT_MASK ? &com->lt_out : &com->lt_in; 2863 break; 2864 default: 2865 return (ENODEV); /* /dev/nodev */ 2866 } 2867 switch (cmd) { 2868 case TIOCSETA: 2869 error = suser(p); 2870 if (error != 0) 2871 return (error); 2872 *ct = *(struct termios *)data; 2873 return (0); 2874 case TIOCGETA: 2875 *(struct termios *)data = *ct; 2876 return (0); 2877 case TIOCGETD: 2878 *(int *)data = TTYDISC; 2879 return (0); 2880 case TIOCGWINSZ: 2881 bzero(data, sizeof(struct winsize)); 2882 return (0); 2883 default: 2884 return (ENOTTY); 2885 } 2886 } 2887 tp = com->tp; 2888#if defined(COMPAT_43) || defined(COMPAT_SUNOS) 2889 term = tp->t_termios; 2890 oldcmd = cmd; 2891 error = ttsetcompat(tp, &cmd, data, &term); 2892 if (error != 0) 2893 return (error); 2894 if (cmd != oldcmd) 2895 data = (caddr_t)&term; 2896#endif 2897 if (cmd == TIOCSETA || cmd == TIOCSETAW || cmd == TIOCSETAF) { 2898 int cc; 2899 struct termios *dt = (struct termios *)data; 2900 struct termios *lt = mynor & CALLOUT_MASK 2901 ? &com->lt_out : &com->lt_in; 2902 2903 dt->c_iflag = (tp->t_iflag & lt->c_iflag) 2904 | (dt->c_iflag & ~lt->c_iflag); 2905 dt->c_oflag = (tp->t_oflag & lt->c_oflag) 2906 | (dt->c_oflag & ~lt->c_oflag); 2907 dt->c_cflag = (tp->t_cflag & lt->c_cflag) 2908 | (dt->c_cflag & ~lt->c_cflag); 2909 dt->c_lflag = (tp->t_lflag & lt->c_lflag) 2910 | (dt->c_lflag & ~lt->c_lflag); 2911 for (cc = 0; cc < NCCS; ++cc) 2912 if (lt->c_cc[cc] != 0) 2913 dt->c_cc[cc] = tp->t_cc[cc]; 2914 if (lt->c_ispeed != 0) 2915 dt->c_ispeed = tp->t_ispeed; 2916 if (lt->c_ospeed != 0) 2917 dt->c_ospeed = tp->t_ospeed; 2918 } 2919 error = (*linesw[tp->t_line].l_ioctl)(tp, cmd, data, flag, p); 2920 if (error != ENOIOCTL) 2921 return (error); 2922 s = spltty(); 2923 error = ttioctl(tp, cmd, data, flag); 2924 disc_optim(tp, &tp->t_termios, com); 2925 if (error != ENOIOCTL) { 2926 splx(s); 2927 return (error); 2928 } 2929#ifdef PC98 2930 if (IS_8251(com->pc98_if_type)) { 2931 switch (cmd) { 2932 case TIOCSBRK: 2933 com_send_break_on( com ); 2934 break; 2935 case TIOCCBRK: 2936 com_send_break_off( com ); 2937 break; 2938 case TIOCSDTR: 2939 com_tiocm_bis(com, TIOCM_DTR | TIOCM_RTS ); 2940 break; 2941 case TIOCCDTR: 2942 com_tiocm_bic(com, TIOCM_DTR); 2943 break; 2944 /* 2945 * XXX should disallow changing MCR_RTS if CS_RTS_IFLOW is set. The 2946 * changes get undone on the next call to comparam(). 2947 */ 2948 case TIOCMSET: 2949 com_tiocm_set( com, *(int *)data ); 2950 break; 2951 case TIOCMBIS: 2952 com_tiocm_bis( com, *(int *)data ); 2953 break; 2954 case TIOCMBIC: 2955 com_tiocm_bic( com, *(int *)data ); 2956 break; 2957 case TIOCMGET: 2958 *(int *)data = com_tiocm_get(com); 2959 break; 2960 case TIOCMSDTRWAIT: 2961 /* must be root since the wait applies to following logins */ 2962 error = suser(p); 2963 if (error != 0) { 2964 splx(s); 2965 return (error); 2966 } 2967 com->dtr_wait = *(int *)data * hz / 100; 2968 break; 2969 case TIOCMGDTRWAIT: 2970 *(int *)data = com->dtr_wait * 100 / hz; 2971 break; 2972 case TIOCTIMESTAMP: 2973 com->do_timestamp = TRUE; 2974 *(struct timeval *)data = com->timestamp; 2975 break; 2976 case TIOCDCDTIMESTAMP: 2977 com->do_dcd_timestamp = TRUE; 2978 *(struct timeval *)data = com->dcd_timestamp; 2979 break; 2980 default: 2981 splx(s); 2982 return (ENOTTY); 2983 } 2984 } else { 2985 int port_shift; 2986 port_shift = if_16550a_type[com->pc98_if_type & 0x0f].port_shift; 2987#endif 2988 switch (cmd) { 2989 case TIOCSBRK: 2990#ifdef PC98 2991 outb(iobase + (com_cfcr << port_shift), 2992 com->cfcr_image |= CFCR_SBREAK); 2993#else 2994 outb(iobase + com_cfcr, com->cfcr_image |= CFCR_SBREAK); 2995#endif 2996 break; 2997 case TIOCCBRK: 2998#ifdef PC98 2999 outb(iobase + (com_cfcr << port_shift), 3000 com->cfcr_image &= ~CFCR_SBREAK); 3001#else 3002 outb(iobase + com_cfcr, com->cfcr_image &= ~CFCR_SBREAK); 3003#endif 3004 break; 3005 case TIOCSDTR: 3006 (void)commctl(com, TIOCM_DTR, DMBIS); 3007 break; 3008 case TIOCCDTR: 3009 (void)commctl(com, TIOCM_DTR, DMBIC); 3010 break; 3011 /* 3012 * XXX should disallow changing MCR_RTS if CS_RTS_IFLOW is set. The 3013 * changes get undone on the next call to comparam(). 3014 */ 3015 case TIOCMSET: 3016 (void)commctl(com, *(int *)data, DMSET); 3017 break; 3018 case TIOCMBIS: 3019 (void)commctl(com, *(int *)data, DMBIS); 3020 break; 3021 case TIOCMBIC: 3022 (void)commctl(com, *(int *)data, DMBIC); 3023 break; 3024 case TIOCMGET: 3025 *(int *)data = commctl(com, 0, DMGET); 3026 break; 3027 case TIOCMSDTRWAIT: 3028 /* must be root since the wait applies to following logins */ 3029 error = suser(p); 3030 if (error != 0) { 3031 splx(s); 3032 return (error); 3033 } 3034 com->dtr_wait = *(int *)data * hz / 100; 3035 break; 3036 case TIOCMGDTRWAIT: 3037 *(int *)data = com->dtr_wait * 100 / hz; 3038 break; 3039 case TIOCTIMESTAMP: 3040 com->do_timestamp = TRUE; 3041 *(struct timeval *)data = com->timestamp; 3042 break; 3043 case TIOCDCDTIMESTAMP: 3044 com->do_dcd_timestamp = TRUE; 3045 *(struct timeval *)data = com->dcd_timestamp; 3046 break; 3047 default: 3048 splx(s); 3049 error = pps_ioctl(cmd, data, &com->pps); 3050 if (error == ENODEV) 3051 error = ENOTTY; 3052 return (error); 3053 } 3054#ifdef PC98 3055 } 3056#endif 3057 splx(s); 3058 return (0); 3059} 3060 3061static void 3062siopoll() 3063{ 3064 int unit; 3065 3066 if (com_events == 0) 3067 return; 3068repeat: 3069 for (unit = 0; unit < NSIOTOT; ++unit) { 3070 struct com_s *com; 3071 int incc; 3072 struct tty *tp; 3073 3074 com = com_addr(unit); 3075 if (com == NULL) 3076 continue; 3077 tp = com->tp; 3078 if (tp == NULL || com->gone) { 3079 /* 3080 * Discard any events related to never-opened or 3081 * going-away devices. 3082 */ 3083 disable_intr(); 3084 incc = com->iptr - com->ibuf; 3085 com->iptr = com->ibuf; 3086 if (com->state & CS_CHECKMSR) { 3087 incc += LOTS_OF_EVENTS; 3088 com->state &= ~CS_CHECKMSR; 3089 } 3090 com_events -= incc; 3091 enable_intr(); 3092 continue; 3093 } 3094 if (com->iptr != com->ibuf) { 3095 disable_intr(); 3096 sioinput(com); 3097 enable_intr(); 3098 } 3099 if (com->state & CS_CHECKMSR) { 3100 u_char delta_modem_status; 3101 3102#ifdef PC98 3103 if (!IS_8251(com->pc98_if_type)) { 3104#endif 3105 disable_intr(); 3106 delta_modem_status = com->last_modem_status 3107 ^ com->prev_modem_status; 3108 com->prev_modem_status = com->last_modem_status; 3109 com_events -= LOTS_OF_EVENTS; 3110 com->state &= ~CS_CHECKMSR; 3111 enable_intr(); 3112 if (delta_modem_status & MSR_DCD) 3113 (*linesw[tp->t_line].l_modem) 3114 (tp, com->prev_modem_status & MSR_DCD); 3115#ifdef PC98 3116 } 3117#endif 3118 } 3119 if (com->state & CS_ODONE) { 3120 disable_intr(); 3121 com_events -= LOTS_OF_EVENTS; 3122 com->state &= ~CS_ODONE; 3123 enable_intr(); 3124 if (!(com->state & CS_BUSY) 3125 && !(com->extra_state & CSE_BUSYCHECK)) { 3126 timeout(siobusycheck, com, hz / 100); 3127 com->extra_state |= CSE_BUSYCHECK; 3128 } 3129 (*linesw[tp->t_line].l_start)(tp); 3130 } 3131 if (com_events == 0) 3132 break; 3133 } 3134 if (com_events >= LOTS_OF_EVENTS) 3135 goto repeat; 3136} 3137 3138static int 3139comparam(tp, t) 3140 struct tty *tp; 3141 struct termios *t; 3142{ 3143 u_int cfcr; 3144 int cflag; 3145 struct com_s *com; 3146 int divisor; 3147 u_char dlbh; 3148 u_char dlbl; 3149 Port_t iobase; 3150 int s; 3151 int unit; 3152#ifdef PC98 3153 int port_shift = 0; 3154 u_char param = 0; 3155#endif 3156 3157#ifdef PC98 3158 cfcr = 0; 3159 unit = DEV_TO_UNIT(tp->t_dev); 3160 com = com_addr(unit); 3161 iobase = com->iobase; 3162 if (IS_8251(com->pc98_if_type)) { 3163 divisor = pc98_ttspeedtab(com, t->c_ospeed); 3164 } else { 3165 port_shift = if_16550a_type[com->pc98_if_type & 0x0f].port_shift; 3166 3167 /* do historical conversions */ 3168 if (t->c_ispeed == 0) 3169 t->c_ispeed = t->c_ospeed; 3170 3171 /* check requested parameters */ 3172 divisor = ttspeedtab(t->c_ospeed, 3173 if_16550a_type[com->pc98_if_type & 0x0f].speedtab); 3174 } 3175#else 3176 /* do historical conversions */ 3177 if (t->c_ispeed == 0) 3178 t->c_ispeed = t->c_ospeed; 3179 3180 /* check requested parameters */ 3181 divisor = ttspeedtab(t->c_ospeed, comspeedtab); 3182#endif 3183 if (divisor < 0 || divisor > 0 && t->c_ispeed != t->c_ospeed) 3184 return (EINVAL); 3185 3186 /* parameters are OK, convert them to the com struct and the device */ 3187#ifndef PC98 3188 unit = DEV_TO_UNIT(tp->t_dev); 3189 com = com_addr(unit); 3190 iobase = com->iobase; 3191#endif 3192 s = spltty(); 3193#ifdef PC98 3194 if (IS_8251(com->pc98_if_type)) { 3195 if (divisor == 0) 3196 com_tiocm_bic( com, TIOCM_DTR|TIOCM_RTS|TIOCM_LE ); 3197 else 3198 com_tiocm_bis( com, TIOCM_DTR|TIOCM_RTS|TIOCM_LE ); 3199 } else { 3200#endif 3201 if (divisor == 0) 3202 (void)commctl(com, TIOCM_DTR, DMBIC); /* hang up line */ 3203 else 3204 (void)commctl(com, TIOCM_DTR, DMBIS); 3205#ifdef PC98 3206 } 3207#endif 3208 cflag = t->c_cflag; 3209#ifdef PC98 3210 if (!IS_8251(com->pc98_if_type)) { 3211#endif 3212 switch (cflag & CSIZE) { 3213 case CS5: 3214 cfcr = CFCR_5BITS; 3215 break; 3216 case CS6: 3217 cfcr = CFCR_6BITS; 3218 break; 3219 case CS7: 3220 cfcr = CFCR_7BITS; 3221 break; 3222 default: 3223 cfcr = CFCR_8BITS; 3224 break; 3225 } 3226 if (cflag & PARENB) { 3227 cfcr |= CFCR_PENAB; 3228 if (!(cflag & PARODD)) 3229 cfcr |= CFCR_PEVEN; 3230 } 3231 if (cflag & CSTOPB) 3232 cfcr |= CFCR_STOPB; 3233 3234 if (com->hasfifo && divisor != 0) { 3235 /* 3236 * Use a fifo trigger level low enough so that the input 3237 * latency from the fifo is less than about 16 msec and 3238 * the total latency is less than about 30 msec. These 3239 * latencies are reasonable for humans. Serial comms 3240 * protocols shouldn't expect anything better since modem 3241 * latencies are larger. 3242 */ 3243 com->fifo_image = t->c_ospeed <= 4800 3244 ? FIFO_ENABLE : FIFO_ENABLE | FIFO_RX_HIGH; 3245#ifdef COM_ESP 3246 /* 3247 * The Hayes ESP card needs the fifo DMA mode bit set 3248 * in compatibility mode. If not, it will interrupt 3249 * for each character received. 3250 */ 3251 if (com->esp) 3252 com->fifo_image |= FIFO_DMA_MODE; 3253#endif 3254#ifdef PC98 3255 outb(iobase + (com_fifo << port_shift), com->fifo_image); 3256#else 3257 outb(iobase + com_fifo, com->fifo_image); 3258#endif 3259 } 3260#ifdef PC98 3261 } 3262#endif 3263 3264 /* 3265 * This returns with interrupts disabled so that we can complete 3266 * the speed change atomically. Keeping interrupts disabled is 3267 * especially important while com_data is hidden. 3268 */ 3269 (void) siosetwater(com, t->c_ispeed); 3270 3271#ifdef PC98 3272 if (IS_8251(com->pc98_if_type)) 3273 com_cflag_and_speed_set(com, cflag, t->c_ospeed); 3274 else { 3275#endif 3276 if (divisor != 0) { 3277#ifdef PC98 3278 outb(iobase + (com_cfcr << port_shift), cfcr | CFCR_DLAB); 3279#else 3280 outb(iobase + com_cfcr, cfcr | CFCR_DLAB); 3281#endif 3282 /* 3283 * Only set the divisor registers if they would change, 3284 * since on some 16550 incompatibles (UMC8669F), setting 3285 * them while input is arriving them loses sync until 3286 * data stops arriving. 3287 */ 3288 dlbl = divisor & 0xFF; 3289#ifdef PC98 3290 if (inb(iobase + (com_dlbl << port_shift)) != dlbl) 3291 outb(iobase + (com_dlbl << port_shift), dlbl); 3292 dlbh = (u_int) divisor >> 8; 3293 if (inb(iobase + (com_dlbh << port_shift)) != dlbh) 3294 outb(iobase + (com_dlbh << port_shift), dlbh); 3295#else 3296 if (inb(iobase + com_dlbl) != dlbl) 3297 outb(iobase + com_dlbl, dlbl); 3298 dlbh = (u_int) divisor >> 8; 3299 if (inb(iobase + com_dlbh) != dlbh) 3300 outb(iobase + com_dlbh, dlbh); 3301#endif 3302 } 3303 3304 3305#ifdef PC98 3306 } 3307 outb(iobase + (com_cfcr << port_shift), com->cfcr_image = cfcr); 3308#else 3309 outb(iobase + com_cfcr, com->cfcr_image = cfcr); 3310#endif 3311 3312 if (!(tp->t_state & TS_TTSTOP)) 3313 com->state |= CS_TTGO; 3314 3315 if (cflag & CRTS_IFLOW) { 3316 if (com->st16650a) { 3317 outb(iobase + com_cfcr, 0xbf); 3318 outb(iobase + com_fifo, inb(iobase + com_fifo) | 0x40); 3319 } 3320 com->state |= CS_RTS_IFLOW; 3321 /* 3322 * If CS_RTS_IFLOW just changed from off to on, the change 3323 * needs to be propagated to MCR_RTS. This isn't urgent, 3324 * so do it later by calling comstart() instead of repeating 3325 * a lot of code from comstart() here. 3326 */ 3327 } else if (com->state & CS_RTS_IFLOW) { 3328 com->state &= ~CS_RTS_IFLOW; 3329 /* 3330 * CS_RTS_IFLOW just changed from on to off. Force MCR_RTS 3331 * on here, since comstart() won't do it later. 3332 */ 3333#ifdef PC98 3334 if (IS_8251(com->pc98_if_type)) 3335 com_tiocm_bis(com, TIOCM_RTS); 3336 else 3337#endif 3338 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS); 3339 if (com->st16650a) { 3340 outb(iobase + com_cfcr, 0xbf); 3341 outb(iobase + com_fifo, inb(iobase + com_fifo) & ~0x40); 3342 } 3343 } 3344 3345 3346 /* 3347 * Set up state to handle output flow control. 3348 * XXX - worth handling MDMBUF (DCD) flow control at the lowest level? 3349 * Now has 10+ msec latency, while CTS flow has 50- usec latency. 3350 */ 3351 com->state |= CS_ODEVREADY; 3352 com->state &= ~CS_CTS_OFLOW; 3353#ifdef PC98 3354 if (com->pc98_if_type == COM_IF_RSA98III) { 3355 param = inb(com->rsabase + rsa_msr); 3356 outb(com->rsabase + rsa_msr, param & 0x14); 3357 } 3358#endif 3359 if (cflag & CCTS_OFLOW) { 3360 com->state |= CS_CTS_OFLOW; 3361#ifdef PC98 3362 if (IS_8251(com->pc98_if_type)) { 3363 if (!(pc98_get_modem_status(com) & TIOCM_CTS)) 3364 com->state &= ~CS_ODEVREADY; 3365 } else { 3366#endif 3367#ifdef PC98 3368 if (com->pc98_if_type == COM_IF_RSA98III) { 3369 /* Set automatic flow control mode */ 3370 outb(com->rsabase + rsa_msr, param | 0x08); 3371 } else 3372#endif 3373 if (!(com->last_modem_status & MSR_CTS)) 3374 com->state &= ~CS_ODEVREADY; 3375 if (com->st16650a) { 3376 outb(iobase + com_cfcr, 0xbf); 3377 outb(iobase + com_fifo, inb(iobase + com_fifo) | 0x80); 3378 } 3379#ifdef PC98 3380 } 3381#endif 3382 } else { 3383 if (com->st16650a) { 3384 outb(iobase + com_cfcr, 0xbf); 3385 outb(iobase + com_fifo, inb(iobase + com_fifo) & ~0x80); 3386 } 3387 } 3388 3389 3390#ifdef PC98 3391 outb(iobase + (com_cfcr << port_shift), com->cfcr_image); 3392#else 3393 outb(iobase + com_cfcr, com->cfcr_image); 3394#endif 3395 3396 3397 /* XXX shouldn't call functions while intrs are disabled. */ 3398 disc_optim(tp, t, com); 3399 /* 3400 * Recover from fiddling with CS_TTGO. We used to call siointr1() 3401 * unconditionally, but that defeated the careful discarding of 3402 * stale input in sioopen(). 3403 */ 3404 if (com->state >= (CS_BUSY | CS_TTGO)) 3405 siointr1(com); 3406 3407 enable_intr(); 3408 splx(s); 3409 comstart(tp); 3410 if (com->ibufold != NULL) { 3411 free(com->ibufold, M_DEVBUF); 3412 com->ibufold = NULL; 3413 } 3414 return (0); 3415} 3416 3417static int 3418siosetwater(com, speed) 3419 struct com_s *com; 3420 speed_t speed; 3421{ 3422 int cp4ticks; 3423 u_char *ibuf; 3424 int ibufsize; 3425 struct tty *tp; 3426 3427 /* 3428 * Make the buffer size large enough to handle a softtty interrupt 3429 * latency of about 2 ticks without loss of throughput or data 3430 * (about 3 ticks if input flow control is not used or not honoured, 3431 * but a bit less for CS5-CS7 modes). 3432 */ 3433 cp4ticks = speed / 10 / hz * 4; 3434 for (ibufsize = 128; ibufsize < cp4ticks;) 3435 ibufsize <<= 1; 3436#ifdef PC98 3437 if (com->pc98_if_type == COM_IF_RSA98III) 3438 ibufsize = 2048; 3439#endif 3440 if (ibufsize == com->ibufsize) { 3441 disable_intr(); 3442 return (0); 3443 } 3444 3445 /* 3446 * Allocate input buffer. The extra factor of 2 in the size is 3447 * to allow for an error byte for each input byte. 3448 */ 3449 ibuf = malloc(2 * ibufsize, M_DEVBUF, M_NOWAIT); 3450 if (ibuf == NULL) { 3451 disable_intr(); 3452 return (ENOMEM); 3453 } 3454 3455 /* Initialize non-critical variables. */ 3456 com->ibufold = com->ibuf; 3457 com->ibufsize = ibufsize; 3458 tp = com->tp; 3459 if (tp != NULL) { 3460 tp->t_ififosize = 2 * ibufsize; 3461 tp->t_ispeedwat = (speed_t)-1; 3462 tp->t_ospeedwat = (speed_t)-1; 3463 } 3464 3465 /* 3466 * Read current input buffer, if any. Continue with interrupts 3467 * disabled. 3468 */ 3469 disable_intr(); 3470 if (com->iptr != com->ibuf) 3471 sioinput(com); 3472 3473 /*- 3474 * Initialize critical variables, including input buffer watermarks. 3475 * The external device is asked to stop sending when the buffer 3476 * exactly reaches high water, or when the high level requests it. 3477 * The high level is notified immediately (rather than at a later 3478 * clock tick) when this watermark is reached. 3479 * The buffer size is chosen so the watermark should almost never 3480 * be reached. 3481 * The low watermark is invisibly 0 since the buffer is always 3482 * emptied all at once. 3483 */ 3484 com->iptr = com->ibuf = ibuf; 3485 com->ibufend = ibuf + ibufsize; 3486 com->ierroff = ibufsize; 3487 com->ihighwater = ibuf + 3 * ibufsize / 4; 3488 return (0); 3489} 3490 3491static void 3492comstart(tp) 3493 struct tty *tp; 3494{ 3495 struct com_s *com; 3496 int s; 3497 int unit; 3498#ifdef PC98 3499 int tmp; 3500#endif 3501 3502 unit = DEV_TO_UNIT(tp->t_dev); 3503 com = com_addr(unit); 3504 s = spltty(); 3505 disable_intr(); 3506 if (tp->t_state & TS_TTSTOP) 3507 com->state &= ~CS_TTGO; 3508 else 3509 com->state |= CS_TTGO; 3510 if (tp->t_state & TS_TBLOCK) { 3511#ifdef PC98 3512 if (IS_8251(com->pc98_if_type)) 3513 tmp = com_tiocm_get(com) & TIOCM_RTS; 3514 else 3515 tmp = com->mcr_image & MCR_RTS; 3516 if (tmp && (com->state & CS_RTS_IFLOW)) 3517#else 3518 if (com->mcr_image & MCR_RTS && com->state & CS_RTS_IFLOW) 3519#endif 3520#ifdef PC98 3521 if (IS_8251(com->pc98_if_type)) 3522 com_tiocm_bic(com, TIOCM_RTS); 3523 else 3524#endif 3525 outb(com->modem_ctl_port, com->mcr_image &= ~MCR_RTS); 3526 } else { 3527#ifdef PC98 3528 if (IS_8251(com->pc98_if_type)) 3529 tmp = com_tiocm_get(com) & TIOCM_RTS; 3530 else 3531 tmp = com->mcr_image & MCR_RTS; 3532 if (!(tmp) && com->iptr < com->ihighwater 3533 && com->state & CS_RTS_IFLOW) 3534#else 3535 if (!(com->mcr_image & MCR_RTS) && com->iptr < com->ihighwater 3536 && com->state & CS_RTS_IFLOW) 3537#endif 3538#ifdef PC98 3539 if (IS_8251(com->pc98_if_type)) 3540 com_tiocm_bis(com, TIOCM_RTS); 3541 else 3542#endif 3543 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS); 3544 } 3545 enable_intr(); 3546 if (tp->t_state & (TS_TIMEOUT | TS_TTSTOP)) { 3547 ttwwakeup(tp); 3548#ifdef PC98 3549/* if(IS_8251(com->pc98_if_type)) 3550 com_int_Tx_enable(com); */ 3551#endif 3552 splx(s); 3553 return; 3554 } 3555 if (tp->t_outq.c_cc != 0) { 3556 struct lbq *qp; 3557 struct lbq *next; 3558 3559 if (!com->obufs[0].l_queued) { 3560 com->obufs[0].l_tail 3561 = com->obuf1 + q_to_b(&tp->t_outq, com->obuf1, 3562#ifndef PC98 3563 sizeof com->obuf1); 3564#else 3565 com->obufsize); 3566#endif 3567 com->obufs[0].l_next = NULL; 3568 com->obufs[0].l_queued = TRUE; 3569 disable_intr(); 3570 if (com->state & CS_BUSY) { 3571 qp = com->obufq.l_next; 3572 while ((next = qp->l_next) != NULL) 3573 qp = next; 3574 qp->l_next = &com->obufs[0]; 3575 } else { 3576 com->obufq.l_head = com->obufs[0].l_head; 3577 com->obufq.l_tail = com->obufs[0].l_tail; 3578 com->obufq.l_next = &com->obufs[0]; 3579 com->state |= CS_BUSY; 3580 } 3581 enable_intr(); 3582 } 3583 if (tp->t_outq.c_cc != 0 && !com->obufs[1].l_queued) { 3584 com->obufs[1].l_tail 3585 = com->obuf2 + q_to_b(&tp->t_outq, com->obuf2, 3586#ifndef PC98 3587 sizeof com->obuf2); 3588#else 3589 com->obufsize); 3590#endif 3591 com->obufs[1].l_next = NULL; 3592 com->obufs[1].l_queued = TRUE; 3593 disable_intr(); 3594 if (com->state & CS_BUSY) { 3595 qp = com->obufq.l_next; 3596 while ((next = qp->l_next) != NULL) 3597 qp = next; 3598 qp->l_next = &com->obufs[1]; 3599 } else { 3600 com->obufq.l_head = com->obufs[1].l_head; 3601 com->obufq.l_tail = com->obufs[1].l_tail; 3602 com->obufq.l_next = &com->obufs[1]; 3603 com->state |= CS_BUSY; 3604 } 3605 enable_intr(); 3606 } 3607 tp->t_state |= TS_BUSY; 3608 } 3609 disable_intr(); 3610 if (com->state >= (CS_BUSY | CS_TTGO)) 3611 siointr1(com); /* fake interrupt to start output */ 3612 enable_intr(); 3613#ifdef PC98 3614/* if(IS_8251(com->pc98_if_type)) 3615 com_int_Tx_enable(com); */ 3616#endif 3617 ttwwakeup(tp); 3618 splx(s); 3619} 3620 3621static void 3622siostop(tp, rw) 3623 struct tty *tp; 3624 int rw; 3625{ 3626 struct com_s *com; 3627#ifdef PC98 3628 int port_shift = 0; 3629 int rsa98_tmp = 0; 3630#endif 3631 3632 com = com_addr(DEV_TO_UNIT(tp->t_dev)); 3633 if (com->gone) 3634 return; 3635#ifdef PC98 3636 if (IS_8251(com->pc98_if_type)) 3637 port_shift = if_16550a_type[com->pc98_if_type & 0x0f].port_shift; 3638#endif 3639 disable_intr(); 3640 if (rw & FWRITE) { 3641 if (com->hasfifo) 3642#ifdef COM_ESP 3643 /* XXX avoid h/w bug. */ 3644 if (!com->esp) 3645#endif 3646#ifdef PC98 3647 outb(com->iobase + (com_fifo << port_shift), 3648 FIFO_XMT_RST | com->fifo_image); 3649 if (com->pc98_if_type == COM_IF_RSA98III) 3650 for(rsa98_tmp = 0; rsa98_tmp < 2048; rsa98_tmp++) 3651 outb(com->iobase + (com_fifo << port_shift), 3652 FIFO_XMT_RST | com->fifo_image); 3653#else 3654 outb(com->iobase + com_fifo, 3655 FIFO_XMT_RST | com->fifo_image); 3656#endif 3657 com->obufs[0].l_queued = FALSE; 3658 com->obufs[1].l_queued = FALSE; 3659 if (com->state & CS_ODONE) 3660 com_events -= LOTS_OF_EVENTS; 3661 com->state &= ~(CS_ODONE | CS_BUSY); 3662 com->tp->t_state &= ~TS_BUSY; 3663 } 3664 if (rw & FREAD) { 3665 if (com->hasfifo) 3666#ifdef COM_ESP 3667 /* XXX avoid h/w bug. */ 3668 if (!com->esp) 3669#endif 3670#ifdef PC98 3671 if (com->pc98_if_type == COM_IF_RSA98III) { 3672 for(rsa98_tmp = 0; rsa98_tmp < 2048; rsa98_tmp++) 3673 inb(com->data_port); 3674 } 3675 outb(com->iobase + (com_fifo << port_shift), 3676 FIFO_RCV_RST | com->fifo_image); 3677#else 3678 outb(com->iobase + com_fifo, 3679 FIFO_RCV_RST | com->fifo_image); 3680#endif 3681 com_events -= (com->iptr - com->ibuf); 3682 com->iptr = com->ibuf; 3683 } 3684 enable_intr(); 3685 comstart(tp); 3686} 3687 3688static struct tty * 3689siodevtotty(dev) 3690 dev_t dev; 3691{ 3692 int mynor; 3693 int unit; 3694 3695 mynor = minor(dev); 3696 if (mynor & CONTROL_MASK) 3697 return (NULL); 3698 unit = MINOR_TO_UNIT(mynor); 3699 if ((u_int) unit >= NSIOTOT) 3700 return (NULL); 3701 return (&sio_tty[unit]); 3702} 3703 3704static int 3705commctl(com, bits, how) 3706 struct com_s *com; 3707 int bits; 3708 int how; 3709{ 3710 int mcr; 3711 int msr; 3712 3713 if (how == DMGET) { 3714 bits = TIOCM_LE; /* XXX - always enabled while open */ 3715 mcr = com->mcr_image; 3716 if (mcr & MCR_DTR) 3717 bits |= TIOCM_DTR; 3718 if (mcr & MCR_RTS) 3719 bits |= TIOCM_RTS; 3720 msr = com->prev_modem_status; 3721 if (msr & MSR_CTS) 3722 bits |= TIOCM_CTS; 3723 if (msr & MSR_DCD) 3724 bits |= TIOCM_CD; 3725 if (msr & MSR_DSR) 3726 bits |= TIOCM_DSR; 3727 /* 3728 * XXX - MSR_RI is naturally volatile, and we make MSR_TERI 3729 * more volatile by reading the modem status a lot. Perhaps 3730 * we should latch both bits until the status is read here. 3731 */ 3732 if (msr & (MSR_RI | MSR_TERI)) 3733 bits |= TIOCM_RI; 3734 return (bits); 3735 } 3736 mcr = 0; 3737 if (bits & TIOCM_DTR) 3738 mcr |= MCR_DTR; 3739 if (bits & TIOCM_RTS) 3740 mcr |= MCR_RTS; 3741 if (com->gone) 3742 return(0); 3743 disable_intr(); 3744 switch (how) { 3745 case DMSET: 3746 outb(com->modem_ctl_port, 3747 com->mcr_image = mcr | (com->mcr_image & MCR_IENABLE)); 3748 break; 3749 case DMBIS: 3750 outb(com->modem_ctl_port, com->mcr_image |= mcr); 3751 break; 3752 case DMBIC: 3753 outb(com->modem_ctl_port, com->mcr_image &= ~mcr); 3754 break; 3755 } 3756 enable_intr(); 3757 return (0); 3758} 3759 3760static void 3761siosettimeout() 3762{ 3763 struct com_s *com; 3764 bool_t someopen; 3765 int unit; 3766 3767 /* 3768 * Set our timeout period to 1 second if no polled devices are open. 3769 * Otherwise set it to max(1/200, 1/hz). 3770 * Enable timeouts iff some device is open. 3771 */ 3772 untimeout(comwakeup, (void *)NULL, sio_timeout_handle); 3773 sio_timeout = hz; 3774 someopen = FALSE; 3775 for (unit = 0; unit < NSIOTOT; ++unit) { 3776 com = com_addr(unit); 3777 if (com != NULL && com->tp != NULL 3778 && com->tp->t_state & TS_ISOPEN && !com->gone) { 3779 someopen = TRUE; 3780 if (com->poll || com->poll_output) { 3781 sio_timeout = hz > 200 ? hz / 200 : 1; 3782 break; 3783 } 3784 } 3785 } 3786 if (someopen) { 3787 sio_timeouts_until_log = hz / sio_timeout; 3788 sio_timeout_handle = timeout(comwakeup, (void *)NULL, 3789 sio_timeout); 3790 } else { 3791 /* Flush error messages, if any. */ 3792 sio_timeouts_until_log = 1; 3793 comwakeup((void *)NULL); 3794 untimeout(comwakeup, (void *)NULL, sio_timeout_handle); 3795 } 3796} 3797 3798static void 3799comwakeup(chan) 3800 void *chan; 3801{ 3802 struct com_s *com; 3803 int unit; 3804 3805 sio_timeout_handle = timeout(comwakeup, (void *)NULL, sio_timeout); 3806 3807 /* 3808 * Recover from lost output interrupts. 3809 * Poll any lines that don't use interrupts. 3810 */ 3811 for (unit = 0; unit < NSIOTOT; ++unit) { 3812 com = com_addr(unit); 3813 if (com != NULL && !com->gone 3814 && (com->state >= (CS_BUSY | CS_TTGO) || com->poll)) { 3815 disable_intr(); 3816 siointr1(com); 3817 enable_intr(); 3818 } 3819 } 3820 3821 /* 3822 * Check for and log errors, but not too often. 3823 */ 3824 if (--sio_timeouts_until_log > 0) 3825 return; 3826 sio_timeouts_until_log = hz / sio_timeout; 3827 for (unit = 0; unit < NSIOTOT; ++unit) { 3828 int errnum; 3829 3830 com = com_addr(unit); 3831 if (com == NULL) 3832 continue; 3833 if (com->gone) 3834 continue; 3835 for (errnum = 0; errnum < CE_NTYPES; ++errnum) { 3836 u_int delta; 3837 u_long total; 3838 3839 disable_intr(); 3840 delta = com->delta_error_counts[errnum]; 3841 com->delta_error_counts[errnum] = 0; 3842 enable_intr(); 3843 if (delta == 0) 3844 continue; 3845 total = com->error_counts[errnum] += delta; 3846 log(LOG_ERR, "sio%d: %u more %s%s (total %lu)\n", 3847 unit, delta, error_desc[errnum], 3848 delta == 1 ? "" : "s", total); 3849 } 3850 } 3851} 3852 3853#ifdef PC98 3854/* commint is called when modem control line changes */ 3855static void 3856commint(dev_t dev) 3857{ 3858 register struct tty *tp; 3859 int stat,delta; 3860 struct com_s *com; 3861 int mynor,unit; 3862 3863 mynor = minor(dev); 3864 unit = MINOR_TO_UNIT(mynor); 3865 com = com_addr(unit); 3866 tp = com->tp; 3867 3868 stat = com_tiocm_get(com); 3869 delta = com_tiocm_get_delta(com); 3870 3871 if (com->state & CS_CTS_OFLOW) { 3872 if (stat & TIOCM_CTS) 3873 com->state |= CS_ODEVREADY; 3874 else 3875 com->state &= ~CS_ODEVREADY; 3876 } 3877 if ((delta & TIOCM_CAR) && (mynor & CALLOUT_MASK) == 0) { 3878 if (stat & TIOCM_CAR ) 3879 (void)(*linesw[tp->t_line].l_modem)(tp, 1); 3880 else if ((*linesw[tp->t_line].l_modem)(tp, 0) == 0) { 3881 /* negate DTR, RTS */ 3882 com_tiocm_bic(com, (tp->t_cflag & HUPCL) ? 3883 TIOCM_DTR|TIOCM_RTS|TIOCM_LE : TIOCM_LE ); 3884 /* disable IENABLE */ 3885 com_int_TxRx_disable( com ); 3886 } 3887 } 3888} 3889#endif 3890 3891static void 3892disc_optim(tp, t, com) 3893 struct tty *tp; 3894 struct termios *t; 3895 struct com_s *com; 3896{ 3897 if (!(t->c_iflag & (ICRNL | IGNCR | IMAXBEL | INLCR | ISTRIP | IXON)) 3898 && (!(t->c_iflag & BRKINT) || (t->c_iflag & IGNBRK)) 3899 && (!(t->c_iflag & PARMRK) 3900 || (t->c_iflag & (IGNPAR | IGNBRK)) == (IGNPAR | IGNBRK)) 3901 && !(t->c_lflag & (ECHO | ICANON | IEXTEN | ISIG | PENDIN)) 3902 && linesw[tp->t_line].l_rint == ttyinput) 3903 tp->t_state |= TS_CAN_BYPASS_L_RINT; 3904 else 3905 tp->t_state &= ~TS_CAN_BYPASS_L_RINT; 3906 com->hotchar = linesw[tp->t_line].l_hotchar; 3907} 3908 3909/* 3910 * Following are all routines needed for SIO to act as console 3911 */ 3912#include <machine/cons.h> 3913 3914struct siocnstate { 3915 u_char dlbl; 3916 u_char dlbh; 3917 u_char ier; 3918 u_char cfcr; 3919 u_char mcr; 3920}; 3921 3922static speed_t siocngetspeed __P((Port_t, struct speedtab *)); 3923static void siocnclose __P((struct siocnstate *sp, Port_t iobase)); 3924static void siocnopen __P((struct siocnstate *sp, Port_t iobase, int speed)); 3925static void siocntxwait __P((Port_t iobase)); 3926 3927#ifdef __i386__ 3928static cn_probe_t siocnprobe; 3929static cn_init_t siocninit; 3930static cn_checkc_t siocncheckc; 3931static cn_getc_t siocngetc; 3932static cn_putc_t siocnputc; 3933 3934CONS_DRIVER(sio, siocnprobe, siocninit, NULL, siocngetc, siocncheckc, siocnputc); 3935 3936/* To get the GDB related variables */ 3937#if DDB > 0 3938#include <ddb/ddb.h> 3939#endif 3940#endif 3941 3942static void 3943siocntxwait(iobase) 3944 Port_t iobase; 3945{ 3946 int timo; 3947 3948 /* 3949 * Wait for any pending transmission to finish. Required to avoid 3950 * the UART lockup bug when the speed is changed, and for normal 3951 * transmits. 3952 */ 3953 timo = 100000; 3954 while ((inb(iobase + com_lsr) & (LSR_TSRE | LSR_TXRDY)) 3955 != (LSR_TSRE | LSR_TXRDY) && --timo != 0) 3956 ; 3957} 3958 3959/* 3960 * Read the serial port specified and try to figure out what speed 3961 * it's currently running at. We're assuming the serial port has 3962 * been initialized and is basicly idle. This routine is only intended 3963 * to be run at system startup. 3964 * 3965 * If the value read from the serial port doesn't make sense, return 0. 3966 */ 3967 3968static speed_t 3969siocngetspeed(iobase, table) 3970 Port_t iobase; 3971 struct speedtab *table; 3972{ 3973 int code; 3974 u_char dlbh; 3975 u_char dlbl; 3976 u_char cfcr; 3977 3978 cfcr = inb(iobase + com_cfcr); 3979 outb(iobase + com_cfcr, CFCR_DLAB | cfcr); 3980 3981 dlbl = inb(iobase + com_dlbl); 3982 dlbh = inb(iobase + com_dlbh); 3983 3984 outb(iobase + com_cfcr, cfcr); 3985 3986 code = dlbh << 8 | dlbl; 3987 3988 for ( ; table->sp_speed != -1; table++) 3989 if (table->sp_code == code) 3990 return (table->sp_speed); 3991 3992 return 0; /* didn't match anything sane */ 3993} 3994 3995static void 3996siocnopen(sp, iobase, speed) 3997 struct siocnstate *sp; 3998 Port_t iobase; 3999 int speed; 4000{ 4001 int divisor; 4002 u_char dlbh; 4003 u_char dlbl; 4004 4005 /* 4006 * Save all the device control registers except the fifo register 4007 * and set our default ones (cs8 -parenb speed=comdefaultrate). 4008 * We can't save the fifo register since it is read-only. 4009 */ 4010 sp->ier = inb(iobase + com_ier); 4011 outb(iobase + com_ier, 0); /* spltty() doesn't stop siointr() */ 4012 siocntxwait(iobase); 4013 sp->cfcr = inb(iobase + com_cfcr); 4014 outb(iobase + com_cfcr, CFCR_DLAB | CFCR_8BITS); 4015 sp->dlbl = inb(iobase + com_dlbl); 4016 sp->dlbh = inb(iobase + com_dlbh); 4017 /* 4018 * Only set the divisor registers if they would change, since on 4019 * some 16550 incompatibles (Startech), setting them clears the 4020 * data input register. This also reduces the effects of the 4021 * UMC8669F bug. 4022 */ 4023 divisor = ttspeedtab(speed, comspeedtab); 4024 dlbl = divisor & 0xFF; 4025 if (sp->dlbl != dlbl) 4026 outb(iobase + com_dlbl, dlbl); 4027 dlbh = (u_int) divisor >> 8; 4028 if (sp->dlbh != dlbh) 4029 outb(iobase + com_dlbh, dlbh); 4030 outb(iobase + com_cfcr, CFCR_8BITS); 4031 sp->mcr = inb(iobase + com_mcr); 4032 /* 4033 * We don't want interrupts, but must be careful not to "disable" 4034 * them by clearing the MCR_IENABLE bit, since that might cause 4035 * an interrupt by floating the IRQ line. 4036 */ 4037 outb(iobase + com_mcr, (sp->mcr & MCR_IENABLE) | MCR_DTR | MCR_RTS); 4038} 4039 4040static void 4041siocnclose(sp, iobase) 4042 struct siocnstate *sp; 4043 Port_t iobase; 4044{ 4045 /* 4046 * Restore the device control registers. 4047 */ 4048 siocntxwait(iobase); 4049 outb(iobase + com_cfcr, CFCR_DLAB | CFCR_8BITS); 4050 if (sp->dlbl != inb(iobase + com_dlbl)) 4051 outb(iobase + com_dlbl, sp->dlbl); 4052 if (sp->dlbh != inb(iobase + com_dlbh)) 4053 outb(iobase + com_dlbh, sp->dlbh); 4054 outb(iobase + com_cfcr, sp->cfcr); 4055 /* 4056 * XXX damp oscillations of MCR_DTR and MCR_RTS by not restoring them. 4057 */ 4058 outb(iobase + com_mcr, sp->mcr | MCR_DTR | MCR_RTS); 4059 outb(iobase + com_ier, sp->ier); 4060} 4061 4062#ifdef __i386__ 4063static 4064#endif 4065void 4066siocnprobe(cp) 4067 struct consdev *cp; 4068{ 4069 speed_t boot_speed; 4070 u_char cfcr; 4071 int s, unit; 4072 struct siocnstate sp; 4073 4074 /* 4075 * Find our first enabled console, if any. If it is a high-level 4076 * console device, then initialize it and return successfully. 4077 * If it is a low-level console device, then initialize it and 4078 * return unsuccessfully. It must be initialized in both cases 4079 * for early use by console drivers and debuggers. Initializing 4080 * the hardware is not necessary in all cases, since the i/o 4081 * routines initialize it on the fly, but it is necessary if 4082 * input might arrive while the hardware is switched back to an 4083 * uninitialized state. We can't handle multiple console devices 4084 * yet because our low-level routines don't take a device arg. 4085 * We trust the user to set the console flags properly so that we 4086 * don't need to probe. 4087 */ 4088 cp->cn_pri = CN_DEAD; 4089 4090 for (unit = 0; unit < 16; unit++) { /* XXX need to know how many */ 4091 int flags; 4092 if (resource_int_value("sio", unit, "flags", &flags)) 4093 continue; 4094 if (COM_CONSOLE(flags) || COM_DEBUGGER(flags)) { 4095 int port; 4096 Port_t iobase; 4097 4098 if (resource_int_value("sio", unit, "port", &port)) 4099 continue; 4100 iobase = port; 4101 s = spltty(); 4102 if (boothowto & RB_SERIAL) { 4103 boot_speed = siocngetspeed(iobase, comspeedtab); 4104 if (boot_speed) 4105 comdefaultrate = boot_speed; 4106 } 4107 4108 /* 4109 * Initialize the divisor latch. We can't rely on 4110 * siocnopen() to do this the first time, since it 4111 * avoids writing to the latch if the latch appears 4112 * to have the correct value. Also, if we didn't 4113 * just read the speed from the hardware, then we 4114 * need to set the speed in hardware so that 4115 * switching it later is null. 4116 */ 4117 cfcr = inb(iobase + com_cfcr); 4118 outb(iobase + com_cfcr, CFCR_DLAB | cfcr); 4119 outb(iobase + com_dlbl, 4120 COMBRD(comdefaultrate) & 0xff); 4121 outb(iobase + com_dlbh, 4122 (u_int) COMBRD(comdefaultrate) >> 8); 4123 outb(iobase + com_cfcr, cfcr); 4124 4125 siocnopen(&sp, iobase, comdefaultrate); 4126 4127 splx(s); 4128 if (COM_CONSOLE(flags) && !COM_LLCONSOLE(flags)) { 4129 cp->cn_dev = makedev(CDEV_MAJOR, unit); 4130 cp->cn_pri = COM_FORCECONSOLE(flags) 4131 || boothowto & RB_SERIAL 4132 ? CN_REMOTE : CN_NORMAL; 4133 printf("sio%d: system console\n", unit); 4134 siocniobase = iobase; 4135 siocnunit = unit; 4136 } 4137 if (COM_DEBUGGER(flags) && !COM_LLCONSOLE(flags)) { 4138 printf("sio%d: gdb debugging port\n", unit); 4139 siogdbiobase = iobase; 4140 siogdbunit = unit; 4141#ifdef __i386__ 4142#if DDB > 0 4143 gdbdev = makedev(CDEV_MAJOR, unit); 4144 gdb_getc = siocngetc; 4145 gdb_putc = siocnputc; 4146#endif 4147#endif 4148 } 4149 } 4150 } 4151#ifdef __i386__ 4152#if DDB > 0 4153 /* 4154 * XXX Ugly Compatability. 4155 * If no gdb port has been specified, set it to be the console 4156 * as some configuration files don't specify the gdb port. 4157 */ 4158 if (gdbdev == NODEV && (boothowto & RB_GDB)) { 4159 printf("Warning: no GDB port specified. Defaulting to sio%d.\n", 4160 siocnunit); 4161 printf("Set flag 0x80 on desired GDB port in your\n"); 4162 printf("configuration file (currently sio only).\n"); 4163 siogdbiobase = siocniobase; 4164 siogdbunit = siocnunit; 4165 gdbdev = makedev(CDEV_MAJOR, siocnunit); 4166 gdb_getc = siocngetc; 4167 gdb_putc = siocnputc; 4168 } 4169#endif 4170#endif 4171} 4172 4173#ifdef __alpha__ 4174 4175struct consdev siocons = { 4176 NULL, NULL, siocngetc, siocncheckc, siocnputc, 4177 NULL, 0, CN_NORMAL, 4178}; 4179 4180extern struct consdev *cn_tab; 4181 4182int 4183siocnattach(port, speed) 4184 int port; 4185 int speed; 4186{ 4187 int s; 4188 u_char cfcr; 4189 struct siocnstate sp; 4190 4191 siocniobase = port; 4192 comdefaultrate = speed; 4193 4194 s = spltty(); 4195 4196 /* 4197 * Initialize the divisor latch. We can't rely on 4198 * siocnopen() to do this the first time, since it 4199 * avoids writing to the latch if the latch appears 4200 * to have the correct value. Also, if we didn't 4201 * just read the speed from the hardware, then we 4202 * need to set the speed in hardware so that 4203 * switching it later is null. 4204 */ 4205 cfcr = inb(siocniobase + com_cfcr); 4206 outb(siocniobase + com_cfcr, CFCR_DLAB | cfcr); 4207 outb(siocniobase + com_dlbl, 4208 COMBRD(comdefaultrate) & 0xff); 4209 outb(siocniobase + com_dlbh, 4210 (u_int) COMBRD(comdefaultrate) >> 8); 4211 outb(siocniobase + com_cfcr, cfcr); 4212 4213 siocnopen(&sp, siocniobase, comdefaultrate); 4214 splx(s); 4215 4216 siocons.cn_dev = makedev(CDEV_MAJOR, 0); 4217 cn_tab = &siocons; 4218 return 0; 4219} 4220 4221int 4222siogdbattach(port, speed) 4223 int port; 4224 int speed; 4225{ 4226 int s; 4227 u_char cfcr; 4228 struct siocnstate sp; 4229 4230 siogdbiobase = port; 4231 gdbdefaultrate = speed; 4232 4233 s = spltty(); 4234 4235 /* 4236 * Initialize the divisor latch. We can't rely on 4237 * siocnopen() to do this the first time, since it 4238 * avoids writing to the latch if the latch appears 4239 * to have the correct value. Also, if we didn't 4240 * just read the speed from the hardware, then we 4241 * need to set the speed in hardware so that 4242 * switching it later is null. 4243 */ 4244 cfcr = inb(siogdbiobase + com_cfcr); 4245 outb(siogdbiobase + com_cfcr, CFCR_DLAB | cfcr); 4246 outb(siogdbiobase + com_dlbl, 4247 COMBRD(gdbdefaultrate) & 0xff); 4248 outb(siogdbiobase + com_dlbh, 4249 (u_int) COMBRD(gdbdefaultrate) >> 8); 4250 outb(siogdbiobase + com_cfcr, cfcr); 4251 4252 siocnopen(&sp, siogdbiobase, gdbdefaultrate); 4253 splx(s); 4254 4255 return 0; 4256} 4257 4258#endif 4259 4260#ifdef __i386__ 4261static 4262#endif 4263void 4264siocninit(cp) 4265 struct consdev *cp; 4266{ 4267 comconsole = DEV_TO_UNIT(cp->cn_dev); 4268} 4269 4270#ifdef __i386__ 4271static 4272#endif 4273int 4274siocncheckc(dev) 4275 dev_t dev; 4276{ 4277 int c; 4278 Port_t iobase; 4279 int s; 4280 struct siocnstate sp; 4281 4282 if (minor(dev) == siogdbunit) 4283 iobase = siogdbiobase; 4284 else 4285 iobase = siocniobase; 4286 s = spltty(); 4287 siocnopen(&sp, iobase, comdefaultrate); 4288 if (inb(iobase + com_lsr) & LSR_RXRDY) 4289 c = inb(iobase + com_data); 4290 else 4291 c = -1; 4292 siocnclose(&sp, iobase); 4293 splx(s); 4294 return (c); 4295} 4296 4297 4298int 4299siocngetc(dev) 4300 dev_t dev; 4301{ 4302 int c; 4303 Port_t iobase; 4304 int s; 4305 struct siocnstate sp; 4306 4307 if (minor(dev) == siogdbunit) 4308 iobase = siogdbiobase; 4309 else 4310 iobase = siocniobase; 4311 s = spltty(); 4312 siocnopen(&sp, iobase, comdefaultrate); 4313 while (!(inb(iobase + com_lsr) & LSR_RXRDY)) 4314 ; 4315 c = inb(iobase + com_data); 4316 siocnclose(&sp, iobase); 4317 splx(s); 4318 return (c); 4319} 4320 4321void 4322siocnputc(dev, c) 4323 dev_t dev; 4324 int c; 4325{ 4326 int s; 4327 struct siocnstate sp; 4328 Port_t iobase; 4329 4330 if (minor(dev) == siogdbunit) 4331 iobase = siogdbiobase; 4332 else 4333 iobase = siocniobase; 4334 s = spltty(); 4335 siocnopen(&sp, iobase, comdefaultrate); 4336 siocntxwait(iobase); 4337 outb(iobase + com_data, c); 4338 siocnclose(&sp, iobase); 4339 splx(s); 4340} 4341 4342#ifdef __alpha__ 4343int 4344siogdbgetc() 4345{ 4346 int c; 4347 Port_t iobase; 4348 int s; 4349 struct siocnstate sp; 4350 4351 iobase = siogdbiobase; 4352 s = spltty(); 4353 siocnopen(&sp, iobase, gdbdefaultrate); 4354 while (!(inb(iobase + com_lsr) & LSR_RXRDY)) 4355 ; 4356 c = inb(iobase + com_data); 4357 siocnclose(&sp, iobase); 4358 splx(s); 4359 return (c); 4360} 4361 4362void 4363siogdbputc(c) 4364 int c; 4365{ 4366 int s; 4367 struct siocnstate sp; 4368 4369 s = spltty(); 4370 siocnopen(&sp, siogdbiobase, gdbdefaultrate); 4371 siocntxwait(siogdbiobase); 4372 outb(siogdbiobase + com_data, c); 4373 siocnclose(&sp, siogdbiobase); 4374 splx(s); 4375} 4376#endif 4377 4378 4379/* 4380 * support PnP cards if we are using 'em 4381 */ 4382 4383#if NPNP > 0 4384 4385static pnpid_t siopnp_ids[] = { 4386 { 0x5015f435, "MOT1550"}, 4387 { 0x8113b04e, "Supra1381"}, 4388 { 0x9012b04e, "Supra1290"}, 4389 { 0x7121b04e, "SupraExpress 56i Sp"}, 4390 { 0x11007256, "USR0011"}, 4391 { 0x30207256, "USR2030"}, 4392 { 0x31307256, "USR3031"}, 4393 { 0x90307256, "USR3090"}, 4394 { 0x0100440e, "Cardinal MVP288IV"}, 4395 { 0 } 4396}; 4397 4398static char *siopnp_probe(u_long csn, u_long vend_id); 4399static void siopnp_attach(u_long csn, u_long vend_id, char *name, 4400 struct isa_device *dev); 4401static u_long nsiopnp = NSIO; 4402 4403static struct pnp_device siopnp = { 4404 "siopnp", 4405 siopnp_probe, 4406 siopnp_attach, 4407 &nsiopnp, 4408 &tty_imask 4409}; 4410DATA_SET (pnpdevice_set, siopnp); 4411 4412static char * 4413siopnp_probe(u_long csn, u_long vend_id) 4414{ 4415 pnpid_t *id; 4416 char *s = NULL; 4417 4418 for(id = siopnp_ids; id->vend_id != 0; id++) { 4419 if (vend_id == id->vend_id) { 4420 s = id->id_str; 4421 break; 4422 } 4423 } 4424 4425 if (s) { 4426 struct pnp_cinfo d; 4427 read_pnp_parms(&d, 0); 4428 if (d.enable == 0 || d.flags & 1) { 4429 printf("CSN %lu is disabled.\n", csn); 4430 return (NULL); 4431 } 4432 4433 } 4434 4435 return (s); 4436} 4437 4438static void 4439siopnp_attach(u_long csn, u_long vend_id, char *name, struct isa_device *dev) 4440{ 4441 struct pnp_cinfo d; 4442 4443 if (dev->id_unit >= NSIOTOT) 4444 return; 4445 4446 if (read_pnp_parms(&d, 0) == 0) { 4447 printf("failed to read pnp parms\n"); 4448 return; 4449 } 4450 4451 write_pnp_parms(&d, 0); 4452 4453 enable_pnp_card(); 4454 4455 dev->id_iobase = d.port[0]; 4456 dev->id_irq = (1 << d.irq[0]); 4457 dev->id_ointr = siointr; 4458 dev->id_ri_flags = RI_FAST; 4459 dev->id_drq = -1; 4460 4461 if (dev->id_driver == NULL) { 4462 dev->id_driver = &siodriver; 4463 dev->id_id = isa_compat_nextid(); 4464 } 4465 4466 if ((dev->id_alive = sioprobe(dev)) != 0) 4467 sioattach(dev); 4468 else 4469 printf("sio%d: probe failed\n", dev->id_unit); 4470} 4471#endif 4472 4473DEV_DRIVER_MODULE(sio, isa, sio_driver, sio_devclass, 4474 CDEV_MAJOR, NOMAJ, sio_cdevsw, 0, 0); 4475 4476#ifdef PC98 4477/* 4478 * pc98 local function 4479 */ 4480 4481static void 4482com_tiocm_set(struct com_s *com, int msr) 4483{ 4484 int s; 4485 int tmp = 0; 4486 int mask = CMD8251_TxEN|CMD8251_RxEN|CMD8251_DTR|CMD8251_RTS; 4487 4488 s=spltty(); 4489 com->pc98_prev_modem_status = ( msr & (TIOCM_LE|TIOCM_DTR|TIOCM_RTS) ) 4490 | ( com->pc98_prev_modem_status & ~(TIOCM_LE|TIOCM_DTR|TIOCM_RTS) ); 4491 tmp |= (CMD8251_TxEN|CMD8251_RxEN); 4492 if ( msr & TIOCM_DTR ) tmp |= CMD8251_DTR; 4493 if ( msr & TIOCM_RTS ) tmp |= CMD8251_RTS; 4494 pc98_i8251_clear_or_cmd( com, mask, tmp ); 4495 splx(s); 4496} 4497 4498static void 4499com_tiocm_bis(struct com_s *com, int msr) 4500{ 4501 int s; 4502 int tmp = 0; 4503 4504 s=spltty(); 4505 com->pc98_prev_modem_status |= ( msr & (TIOCM_LE|TIOCM_DTR|TIOCM_RTS) ); 4506 tmp |= CMD8251_TxEN|CMD8251_RxEN; 4507 if ( msr & TIOCM_DTR ) tmp |= CMD8251_DTR; 4508 if ( msr & TIOCM_RTS ) tmp |= CMD8251_RTS; 4509 4510 pc98_i8251_or_cmd( com, tmp ); 4511 splx(s); 4512} 4513 4514static void 4515com_tiocm_bic(struct com_s *com, int msr) 4516{ 4517 int s; 4518 int tmp = msr; 4519 4520 s=spltty(); 4521 com->pc98_prev_modem_status &= ~( msr & (TIOCM_LE|TIOCM_DTR|TIOCM_RTS) ); 4522 if ( msr & TIOCM_DTR ) tmp |= CMD8251_DTR; 4523 if ( msr & TIOCM_RTS ) tmp |= CMD8251_RTS; 4524 4525 pc98_i8251_clear_cmd( com, tmp ); 4526 splx(s); 4527} 4528 4529static int 4530com_tiocm_get(struct com_s *com) 4531{ 4532 return( com->pc98_prev_modem_status ); 4533} 4534 4535static int 4536com_tiocm_get_delta(struct com_s *com) 4537{ 4538 int tmp; 4539 4540 tmp = com->pc98_modem_delta; 4541 com->pc98_modem_delta = 0; 4542 return( tmp ); 4543} 4544 4545/* convert to TIOCM_?? ( ioctl.h ) */ 4546static int 4547pc98_get_modem_status(struct com_s *com) 4548{ 4549 int stat, stat2; 4550 register int msr; 4551 4552 stat = inb(com->sts_port); 4553 stat2 = inb(com->in_modem_port); 4554 msr = com->pc98_prev_modem_status 4555 & ~(TIOCM_CAR|TIOCM_RI|TIOCM_DSR|TIOCM_CTS); 4556 if ( !(stat2 & CICSCD_CD) ) msr |= TIOCM_CAR; 4557 if ( !(stat2 & CICSCD_CI) ) msr |= TIOCM_RI; 4558 if ( stat & STS8251_DSR ) msr |= TIOCM_DSR; 4559 if ( !(stat2 & CICSCD_CS) ) msr |= TIOCM_CTS; 4560#if COM_CARRIER_DETECT_EMULATE 4561 if ( msr & (TIOCM_DSR|TIOCM_CTS) ) { 4562 msr |= TIOCM_CAR; 4563 } 4564#endif 4565 return(msr); 4566} 4567 4568static void 4569pc98_check_msr(void* chan) 4570{ 4571 int msr, delta; 4572 int s; 4573 register struct tty *tp; 4574 struct com_s *com; 4575 int mynor; 4576 int unit; 4577 dev_t dev; 4578 4579 dev=(dev_t)chan; 4580 mynor = minor(dev); 4581 unit = MINOR_TO_UNIT(mynor); 4582 com = com_addr(unit); 4583 tp = com->tp; 4584 4585 s = spltty(); 4586 msr = pc98_get_modem_status(com); 4587 /* make change flag */ 4588 delta = msr ^ com->pc98_prev_modem_status; 4589 if ( delta & TIOCM_CAR ) { 4590 if ( com->modem_car_chg_timer ) { 4591 if ( -- com->modem_car_chg_timer ) 4592 msr ^= TIOCM_CAR; 4593 } else { 4594 if ((com->modem_car_chg_timer = (msr & TIOCM_CAR) ? 4595 DCD_ON_RECOGNITION : DCD_OFF_TOLERANCE) != 0) 4596 msr ^= TIOCM_CAR; 4597 } 4598 } else 4599 com->modem_car_chg_timer = 0; 4600 delta = ( msr ^ com->pc98_prev_modem_status ) & 4601 (TIOCM_CAR|TIOCM_RI|TIOCM_DSR|TIOCM_CTS); 4602 com->pc98_prev_modem_status = msr; 4603 delta = ( com->pc98_modem_delta |= delta ); 4604 splx(s); 4605 if ( com->modem_checking || (tp->t_state & (TS_ISOPEN)) ) { 4606 if ( delta ) { 4607 commint(dev); 4608 } 4609 timeout(pc98_check_msr, (caddr_t)dev, 4610 PC98_CHECK_MODEM_INTERVAL); 4611 } else { 4612 com->modem_checking = 0; 4613 } 4614} 4615 4616static void 4617pc98_msrint_start(dev_t dev) 4618{ 4619 struct com_s *com; 4620 int mynor; 4621 int unit; 4622 int s = spltty(); 4623 4624 mynor = minor(dev); 4625 unit = MINOR_TO_UNIT(mynor); 4626 com = com_addr(unit); 4627 /* modem control line check routine envoke interval is 1/10 sec */ 4628 if ( com->modem_checking == 0 ) { 4629 com->pc98_prev_modem_status = pc98_get_modem_status(com); 4630 com->pc98_modem_delta = 0; 4631 timeout(pc98_check_msr, (caddr_t)dev, 4632 PC98_CHECK_MODEM_INTERVAL); 4633 com->modem_checking = 1; 4634 } 4635 splx(s); 4636} 4637 4638static void 4639pc98_disable_i8251_interrupt(struct com_s *com, int mod) 4640{ 4641 /* disable interrupt */ 4642 register int tmp; 4643 4644 mod |= ~(IEN_Tx|IEN_TxEMP|IEN_Rx); 4645 COM_INT_DISABLE 4646 tmp = inb( com->intr_ctrl_port ) & ~(IEN_Tx|IEN_TxEMP|IEN_Rx); 4647 outb( com->intr_ctrl_port, (com->intr_enable&=~mod) | tmp ); 4648 COM_INT_ENABLE 4649} 4650 4651static void 4652pc98_enable_i8251_interrupt(struct com_s *com, int mod) 4653{ 4654 register int tmp; 4655 4656 COM_INT_DISABLE 4657 tmp = inb( com->intr_ctrl_port ) & ~(IEN_Tx|IEN_TxEMP|IEN_Rx); 4658 outb( com->intr_ctrl_port, (com->intr_enable|=mod) | tmp ); 4659 COM_INT_ENABLE 4660} 4661 4662static int 4663pc98_check_i8251_interrupt(struct com_s *com) 4664{ 4665 return ( com->intr_enable & 0x07 ); 4666} 4667 4668static void 4669pc98_i8251_clear_cmd(struct com_s *com, int x) 4670{ 4671 int tmp; 4672 4673 COM_INT_DISABLE 4674 tmp = com->pc98_prev_siocmd & ~(x); 4675 outb(com->cmd_port, tmp); 4676 com->pc98_prev_siocmd = tmp & ~(CMD8251_ER|CMD8251_RESET|CMD8251_EH); 4677 COM_INT_ENABLE 4678} 4679 4680static void 4681pc98_i8251_or_cmd(struct com_s *com, int x) 4682{ 4683 int tmp; 4684 4685 COM_INT_DISABLE 4686 tmp = com->pc98_prev_siocmd | (x); 4687 outb(com->cmd_port, tmp); 4688 com->pc98_prev_siocmd = tmp & ~(CMD8251_ER|CMD8251_RESET|CMD8251_EH); 4689 COM_INT_ENABLE 4690} 4691 4692static void 4693pc98_i8251_set_cmd(struct com_s *com, int x) 4694{ 4695 int tmp; 4696 4697 COM_INT_DISABLE 4698 tmp = (x); 4699 outb(com->cmd_port, tmp); 4700 com->pc98_prev_siocmd = tmp & ~(CMD8251_ER|CMD8251_RESET|CMD8251_EH); 4701 COM_INT_ENABLE 4702} 4703 4704static void 4705pc98_i8251_clear_or_cmd(struct com_s *com, int clr, int x) 4706{ 4707 int tmp; 4708 COM_INT_DISABLE 4709 tmp = com->pc98_prev_siocmd & ~(clr); 4710 tmp |= (x); 4711 outb(com->cmd_port, tmp); 4712 com->pc98_prev_siocmd = tmp & ~(CMD8251_ER|CMD8251_RESET|CMD8251_EH); 4713 COM_INT_ENABLE 4714} 4715 4716static int 4717pc98_i8251_get_cmd(struct com_s *com) 4718{ 4719 return com->pc98_prev_siocmd; 4720} 4721 4722static int 4723pc98_i8251_get_mod(struct com_s *com) 4724{ 4725 return com->pc98_prev_siomod; 4726} 4727 4728static void 4729pc98_i8251_reset(struct com_s *com, int mode, int command) 4730{ 4731 outb(com->cmd_port, 0); /* dummy */ 4732 DELAY(2); 4733 outb(com->cmd_port, 0); /* dummy */ 4734 DELAY(2); 4735 outb(com->cmd_port, 0); /* dummy */ 4736 DELAY(2); 4737 outb(com->cmd_port, CMD8251_RESET); /* internal reset */ 4738 DELAY(2); 4739 outb(com->cmd_port, mode ); /* mode register */ 4740 com->pc98_prev_siomod = mode; 4741 DELAY(2); 4742 pc98_i8251_set_cmd( com, (command|CMD8251_ER) ); 4743} 4744 4745static void 4746pc98_check_sysclock(void) 4747{ 4748 /* get system clock from port */ 4749 if ( pc98_machine_type & M_8M ) { 4750 /* 8 MHz system & H98 */ 4751 sysclock = 8; 4752 } else { 4753 /* 5 MHz system */ 4754 sysclock = 5; 4755 } 4756} 4757 4758static void 4759com_cflag_and_speed_set( struct com_s *com, int cflag, int speed) 4760{ 4761 int cfcr=0, count; 4762 int previnterrupt; 4763 4764 count = pc98_ttspeedtab( com, speed ); 4765 if ( count < 0 ) return; 4766 4767 previnterrupt = pc98_check_i8251_interrupt(com); 4768 pc98_disable_i8251_interrupt( com, IEN_Tx|IEN_TxEMP|IEN_Rx ); 4769 4770 switch ( cflag&CSIZE ) { 4771 case CS5: 4772 cfcr = MOD8251_5BITS; break; 4773 case CS6: 4774 cfcr = MOD8251_6BITS; break; 4775 case CS7: 4776 cfcr = MOD8251_7BITS; break; 4777 case CS8: 4778 cfcr = MOD8251_8BITS; break; 4779 } 4780 if ( cflag&PARENB ) { 4781 if ( cflag&PARODD ) 4782 cfcr |= MOD8251_PODD; 4783 else 4784 cfcr |= MOD8251_PEVEN; 4785 } else 4786 cfcr |= MOD8251_PDISAB; 4787 4788 if ( cflag&CSTOPB ) 4789 cfcr |= MOD8251_STOP2; 4790 else 4791 cfcr |= MOD8251_STOP1; 4792 4793 if ( count & 0x10000 ) 4794 cfcr |= MOD8251_CLKX1; 4795 else 4796 cfcr |= MOD8251_CLKX16; 4797 4798 if (epson_machine_id != 0x20) { /* XXX */ 4799 int tmp; 4800 while (!((tmp = inb(com->sts_port)) & STS8251_TxEMP)) 4801 ; 4802 } 4803 /* set baud rate from ospeed */ 4804 pc98_set_baud_rate( com, count ); 4805 4806 if ( cfcr != pc98_i8251_get_mod(com) ) 4807 pc98_i8251_reset(com, cfcr, pc98_i8251_get_cmd(com) ); 4808 4809 pc98_enable_i8251_interrupt( com, previnterrupt ); 4810} 4811 4812static int 4813pc98_ttspeedtab(struct com_s *com, int speed) 4814{ 4815 int if_type, effect_sp, count = -1, mod; 4816 4817 if_type = com->pc98_if_type & 0x0f; 4818 4819 switch (com->pc98_if_type) { 4820 case COM_IF_INTERNAL: 4821 if (PC98SIO_baud_rate_port(if_type) != -1) { 4822 count = ttspeedtab(speed, if_8251_type[if_type].speedtab); 4823 if (count > 0) { 4824 count |= COM1_EXT_CLOCK; 4825 break; 4826 } 4827 } 4828 4829 /* for *1CLK asynchronous! mode, TEFUTEFU */ 4830 mod = (sysclock == 5) ? 2457600 : 1996800; 4831 effect_sp = ttspeedtab( speed, pc98speedtab ); 4832 if ( effect_sp < 0 ) /* XXX */ 4833 effect_sp = ttspeedtab( (speed - 1), pc98speedtab ); 4834 if ( effect_sp <= 0 ) 4835 return effect_sp; 4836 if ( effect_sp == speed ) 4837 mod /= 16; 4838 if ( mod % effect_sp ) 4839 return(-1); 4840 count = mod / effect_sp; 4841 if ( count > 65535 ) 4842 return(-1); 4843 if ( effect_sp != speed ) 4844 count |= 0x10000; 4845 break; 4846 case COM_IF_PC9861K_1: 4847 case COM_IF_PC9861K_2: 4848 count = 1; 4849 break; 4850 case COM_IF_IND_SS_1: 4851 case COM_IF_IND_SS_2: 4852 case COM_IF_PIO9032B_1: 4853 case COM_IF_PIO9032B_2: 4854 if ( speed == 0 ) return 0; 4855 count = ttspeedtab( speed, if_8251_type[if_type].speedtab ); 4856 break; 4857 case COM_IF_B98_01_1: 4858 case COM_IF_B98_01_2: 4859 if ( speed == 0 ) return 0; 4860 count = ttspeedtab( speed, if_8251_type[if_type].speedtab ); 4861#ifdef B98_01_OLD 4862 if (count == 0 || count == 1) { 4863 count += 4; 4864 count |= 0x20000; /* x1 mode for 76800 and 153600 */ 4865 } 4866#endif 4867 break; 4868 } 4869 4870 return count; 4871} 4872 4873static void 4874pc98_set_baud_rate( struct com_s *com, int count ) 4875{ 4876 int if_type, io, s; 4877 4878 if_type = com->pc98_if_type & 0x0f; 4879 io = com->iobase & 0xff00; 4880 4881 switch (com->pc98_if_type) { 4882 case COM_IF_INTERNAL: 4883 if (PC98SIO_baud_rate_port(if_type) != -1) { 4884 if (count & COM1_EXT_CLOCK) { 4885 outb((Port_t)PC98SIO_baud_rate_port(if_type), count & 0xff); 4886 break; 4887 } else { 4888 outb((Port_t)PC98SIO_baud_rate_port(if_type), 0x09); 4889 } 4890 } 4891 4892 if ( count < 0 ) { 4893 printf( "[ Illegal count : %d ]", count ); 4894 return; 4895 } else if ( count == 0 ) 4896 return; 4897 /* set i8253 */ 4898 s = splclock(); 4899 if (count != 3) 4900 outb( 0x77, 0xb6 ); 4901 else 4902 outb( 0x77, 0xb4 ); 4903 outb( 0x5f, 0); 4904 outb( 0x75, count & 0xff ); 4905 outb( 0x5f, 0); 4906 outb( 0x75, (count >> 8) & 0xff ); 4907 splx(s); 4908 break; 4909 case COM_IF_IND_SS_1: 4910 case COM_IF_IND_SS_2: 4911 outb(io | PC98SIO_intr_ctrl_port(if_type), 0); 4912 outb(io | PC98SIO_baud_rate_port(if_type), 0); 4913 outb(io | PC98SIO_baud_rate_port(if_type), 0xc0); 4914 outb(io | PC98SIO_baud_rate_port(if_type), (count >> 8) | 0x80); 4915 outb(io | PC98SIO_baud_rate_port(if_type), count & 0xff); 4916 break; 4917 case COM_IF_PIO9032B_1: 4918 case COM_IF_PIO9032B_2: 4919 outb(io | PC98SIO_baud_rate_port(if_type), count); 4920 break; 4921 case COM_IF_B98_01_1: 4922 case COM_IF_B98_01_2: 4923 outb(io | PC98SIO_baud_rate_port(if_type), count & 0x0f); 4924#ifdef B98_01_OLD 4925 /* 4926 * Some old B98_01 board should be controlled 4927 * in different way, but this hasn't been tested yet. 4928 */ 4929 outb(io | PC98SIO_func_port(if_type), 4930 (count & 0x20000) ? 0xf0 : 0xf2); 4931#endif 4932 break; 4933 } 4934} 4935static int 4936pc98_check_if_type(device_t dev, struct siodev *iod) 4937{ 4938 int irr, io, if_type, tmp; 4939 static short irq_tab[2][8] = { 4940 { 3, 5, 6, 9, 10, 12, 13, -1}, 4941 { 3, 10, 12, 13, 5, 6, 9, -1} 4942 }; 4943 4944 iod->if_type = if_type = (isa_get_flags(dev) >> 24) & 0xff; 4945 if ((if_type < 0 || if_type > COM_IF_END1) && 4946 (if_type < 0x10 || if_type > COM_IF_END2)) 4947 return(-1); 4948 if_type &= 0x0f; 4949 iod->irq = 0; 4950 io = isa_get_port(dev) & 0xff00; 4951 4952 if (IS_8251(iod->if_type)) { 4953 if (PC98SIO_func_port(if_type) != -1) { 4954 outb(io | PC98SIO_func_port(if_type), 0xf2); 4955 tmp = ttspeedtab(9600, if_8251_type[if_type].speedtab); 4956 if (tmp != -1 && PC98SIO_baud_rate_port(if_type) != -1) 4957 outb(io | PC98SIO_baud_rate_port(if_type), tmp); 4958 } 4959 4960 iod->cmd = io | PC98SIO_cmd_port(if_type); 4961 iod->sts = io | PC98SIO_sts_port(if_type); 4962 iod->mod = io | PC98SIO_in_modem_port(if_type); 4963 iod->ctrl = io | PC98SIO_intr_ctrl_port(if_type); 4964 4965 if (iod->if_type == COM_IF_INTERNAL) { 4966 iod->irq = 4; 4967 4968 /* XXX check new internal port. */ 4969 outb(0x138, 0); 4970 DELAY(10); 4971 for (tmp = 0; tmp < 100; tmp++) { 4972 if ((inb(0x138) & 1) == 0) { 4973 PC98SIO_baud_rate_port(if_type) = 0x13a; 4974 if_8251_type[if_type].name = " (internal fast)"; 4975 if_8251_type[if_type].speedtab = pc98fast_speedtab; 4976 break; 4977 } 4978 DELAY(1); 4979 } 4980 } else { 4981 tmp = inb( iod->mod ) & if_8251_type[if_type].irr_mask; 4982 if ((isa_get_port(dev) & 0xff) == IO_COM2) 4983 iod->irq = irq_tab[0][tmp]; 4984 else 4985 iod->irq = irq_tab[1][tmp]; 4986 } 4987 } else { 4988 irr = if_16550a_type[if_type].irr_read; 4989#ifdef COM_MULTIPORT 4990 if (!COM_ISMULTIPORT(isa_get_flags(dev)) || 4991 device_get_unit(dev) == COM_MPMASTER(isa_get_flags(dev))) 4992#endif 4993 if (irr != -1) { 4994 tmp = inb(io | irr); 4995 if (isa_get_port(dev) & 0x01) /* XXX depend on RSB-384 */ 4996 iod->irq = irq_tab[1][tmp >> 3]; 4997 else 4998 iod->irq = irq_tab[0][tmp & 0x07]; 4999 } 5000 } 5001 if ( iod->irq == -1 ) return -1; 5002 5003 return 0; 5004} 5005static int 5006pc98_set_ioport( struct com_s *com, int id_flags ) 5007{ 5008 int io, if_type; 5009 5010 if_type = (id_flags >> 24) & 0xff; 5011 if (IS_8251(if_type)) { 5012 pc98_check_sysclock(); 5013 io = com->iobase & 0xff00; 5014 com->pc98_if_type = if_type; 5015 if_type &= 0x0f; 5016 com->data_port = io | PC98SIO_data_port(if_type); 5017 com->cmd_port = io | PC98SIO_cmd_port(if_type); 5018 com->sts_port = io | PC98SIO_sts_port(if_type); 5019 com->in_modem_port = io | PC98SIO_in_modem_port(if_type); 5020 com->intr_ctrl_port = io | PC98SIO_intr_ctrl_port(if_type); 5021 return 0; 5022 } 5023 5024 return -1; 5025} 5026#endif /* PC98 defined */ 5027