sio.c revision 225203
1/*- 2 * Copyright (c) 1991 The Regents of the University of California. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 4. Neither the name of the University nor the names of its contributors 14 * may be used to endorse or promote products derived from this software 15 * without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * $FreeBSD: head/sys/pc98/cbus/sio.c 225203 2011-08-26 21:46:36Z rwatson $ 30 * from: @(#)com.c 7.5 (Berkeley) 5/16/91 31 * from: i386/isa sio.c,v 1.234 32 */ 33 34#include "opt_comconsole.h" 35#include "opt_compat.h" 36#include "opt_gdb.h" 37#include "opt_kdb.h" 38#include "opt_sio.h" 39 40/* 41 * Serial driver, based on 386BSD-0.1 com driver. 42 * Mostly rewritten to use pseudo-DMA. 43 * Works for National Semiconductor NS8250-NS16550AF UARTs. 44 * COM driver, based on HP dca driver. 45 * 46 * Changes for PC Card integration: 47 * - Added PC Card driver table and handlers 48 */ 49/*=============================================================== 50 * 386BSD(98),FreeBSD-1.1x(98) com driver. 51 * ----- 52 * modified for PC9801 by M.Ishii 53 * Kyoto University Microcomputer Club (KMC) 54 * Chou "TEFUTEFU" Hirotomi 55 * Kyoto Univ. the faculty of medicine 56 *=============================================================== 57 * FreeBSD-2.0.1(98) sio driver. 58 * ----- 59 * modified for pc98 Internal i8251 and MICRO CORE MC16550II 60 * T.Koike(hfc01340@niftyserve.or.jp) 61 * implement kernel device configuration 62 * aizu@orient.center.nitech.ac.jp 63 * 64 * Notes. 65 * ----- 66 * PC98 localization based on 386BSD(98) com driver. Using its PC98 local 67 * functions. 68 * This driver is under debugging,has bugs. 69 */ 70/* 71 * modified for AIWA B98-01 72 * by T.Hatanou <hatanou@yasuda.comm.waseda.ac.jp> last update: 15 Sep.1995 73 */ 74/* 75 * Modified by Y.Takahashi of Kogakuin University. 76 */ 77/* 78 * modified for 8251(FIFO) by Seigo TANIMURA <tanimura@FreeBSD.org> 79 */ 80 81#include <sys/param.h> 82#include <sys/systm.h> 83#include <sys/bus.h> 84#include <sys/conf.h> 85#include <sys/fcntl.h> 86#include <sys/interrupt.h> 87#include <sys/kdb.h> 88#include <sys/kernel.h> 89#include <sys/limits.h> 90#include <sys/lock.h> 91#include <sys/malloc.h> 92#include <sys/module.h> 93#include <sys/mutex.h> 94#include <sys/proc.h> 95#include <sys/reboot.h> 96#include <sys/serial.h> 97#include <sys/sysctl.h> 98#include <sys/syslog.h> 99#include <sys/tty.h> 100#include <machine/bus.h> 101#include <sys/rman.h> 102#include <sys/timepps.h> 103#include <sys/uio.h> 104#include <sys/cons.h> 105 106#include <isa/isavar.h> 107 108#include <machine/resource.h> 109 110#include <dev/sio/sioreg.h> 111#include <dev/sio/siovar.h> 112 113#ifdef PC98 114#include <pc98/cbus/cbus.h> 115#include <pc98/pc98/pc98_machdep.h> 116#endif 117 118#ifdef COM_ESP 119#include <dev/ic/esp.h> 120#endif 121#include <dev/ic/ns16550.h> 122#ifdef PC98 123#include <dev/ic/i8251.h> 124#include <dev/ic/i8255.h> 125#include <dev/ic/rsa.h> 126#endif 127 128#define LOTS_OF_EVENTS 64 /* helps separate urgent events from input */ 129 130/* 131 * Meaning of flags: 132 * 133 * 0x00000001 shared IRQs 134 * 0x00000002 disable FIFO 135 * 0x00000008 recover sooner from lost output interrupts 136 * 0x00000010 device is potential system console 137 * 0x00000020 device is forced to become system console 138 * 0x00000040 device is reserved for low-level IO 139 * 0x00000080 use this port for remote kernel debugging 140 * 0x0000??00 minor number of master port 141 * 0x00010000 PPS timestamping on CTS instead of DCD 142 * 0x00080000 IIR_TXRDY bug 143 * 0x00400000 If no comconsole found then mark as a comconsole 144 * 0x1?000000 interface type 145 */ 146 147#ifdef COM_MULTIPORT 148/* checks in flags for multiport and which is multiport "master chip" 149 * for a given card 150 */ 151#define COM_ISMULTIPORT(flags) ((flags) & 0x01) 152#define COM_MPMASTER(flags) (((flags) >> 8) & 0x0ff) 153#ifndef PC98 154#define COM_NOTAST4(flags) ((flags) & 0x04) 155#endif 156#else 157#define COM_ISMULTIPORT(flags) (0) 158#endif /* COM_MULTIPORT */ 159 160#define COM_C_IIR_TXRDYBUG 0x80000 161#define COM_CONSOLE(flags) ((flags) & 0x10) 162#define COM_DEBUGGER(flags) ((flags) & 0x80) 163#ifndef PC98 164#define COM_FIFOSIZE(flags) (((flags) & 0xff000000) >> 24) 165#endif 166#define COM_FORCECONSOLE(flags) ((flags) & 0x20) 167#define COM_IIR_TXRDYBUG(flags) ((flags) & COM_C_IIR_TXRDYBUG) 168#define COM_LLCONSOLE(flags) ((flags) & 0x40) 169#define COM_LOSESOUTINTS(flags) ((flags) & 0x08) 170#define COM_NOFIFO(flags) ((flags) & 0x02) 171#ifndef PC98 172#define COM_NOSCR(flags) ((flags) & 0x100000) 173#endif 174#define COM_PPSCTS(flags) ((flags) & 0x10000) 175#ifndef PC98 176#define COM_ST16650A(flags) ((flags) & 0x20000) 177#define COM_TI16754(flags) ((flags) & 0x200000) 178#endif 179 180#define sio_getreg(com, off) \ 181 (bus_space_read_1((com)->bst, (com)->bsh, (off))) 182#define sio_setreg(com, off, value) \ 183 (bus_space_write_1((com)->bst, (com)->bsh, (off), (value))) 184 185/* 186 * com state bits. 187 * (CS_BUSY | CS_TTGO) and (CS_BUSY | CS_TTGO | CS_ODEVREADY) must be higher 188 * than the other bits so that they can be tested as a group without masking 189 * off the low bits. 190 * 191 * The following com and tty flags correspond closely: 192 * CS_BUSY = TS_BUSY (maintained by comstart(), siopoll() and 193 * comstop()) 194 * CS_TTGO = ~TS_TTSTOP (maintained by comparam() and comstart()) 195 * CS_CTS_OFLOW = CCTS_OFLOW (maintained by comparam()) 196 * CS_RTS_IFLOW = CRTS_IFLOW (maintained by comparam()) 197 * TS_FLUSH is not used. 198 * XXX I think TIOCSETA doesn't clear TS_TTSTOP when it clears IXON. 199 * XXX CS_*FLOW should be CF_*FLOW in com->flags (control flags not state). 200 */ 201#define CS_BUSY 0x80 /* output in progress */ 202#define CS_TTGO 0x40 /* output not stopped by XOFF */ 203#define CS_ODEVREADY 0x20 /* external device h/w ready (CTS) */ 204#define CS_CHECKMSR 1 /* check of MSR scheduled */ 205#define CS_CTS_OFLOW 2 /* use CTS output flow control */ 206#define CS_ODONE 4 /* output completed */ 207#define CS_RTS_IFLOW 8 /* use RTS input flow control */ 208#define CSE_BUSYCHECK 1 /* siobusycheck() scheduled */ 209 210static char const * const error_desc[] = { 211#define CE_OVERRUN 0 212 "silo overflow", 213#define CE_INTERRUPT_BUF_OVERFLOW 1 214 "interrupt-level buffer overflow", 215#define CE_TTY_BUF_OVERFLOW 2 216 "tty-level buffer overflow", 217}; 218 219#define CE_NTYPES 3 220#define CE_RECORD(com, errnum) (++(com)->delta_error_counts[errnum]) 221 222/* types. XXX - should be elsewhere */ 223typedef u_int Port_t; /* hardware port */ 224typedef u_char bool_t; /* boolean */ 225 226/* queue of linear buffers */ 227struct lbq { 228 u_char *l_head; /* next char to process */ 229 u_char *l_tail; /* one past the last char to process */ 230 struct lbq *l_next; /* next in queue */ 231 bool_t l_queued; /* nonzero if queued */ 232}; 233 234/* com device structure */ 235struct com_s { 236 u_char state; /* miscellaneous flag bits */ 237 u_char cfcr_image; /* copy of value written to CFCR */ 238#ifdef COM_ESP 239 bool_t esp; /* is this unit a hayes esp board? */ 240#endif 241 u_char extra_state; /* more flag bits, separate for order trick */ 242 u_char fifo_image; /* copy of value written to FIFO */ 243 bool_t hasfifo; /* nonzero for 16550 UARTs */ 244 bool_t loses_outints; /* nonzero if device loses output interrupts */ 245 u_char mcr_image; /* copy of value written to MCR */ 246#ifdef COM_MULTIPORT 247 bool_t multiport; /* is this unit part of a multiport device? */ 248#endif /* COM_MULTIPORT */ 249 bool_t no_irq; /* nonzero if irq is not attached */ 250 bool_t gone; /* hardware disappeared */ 251 bool_t poll; /* nonzero if polling is required */ 252 bool_t poll_output; /* nonzero if polling for output is required */ 253 bool_t st16650a; /* nonzero if Startech 16650A compatible */ 254 int unit; /* unit number */ 255 u_int flags; /* copy of device flags */ 256 u_int tx_fifo_size; 257 258 /* 259 * The high level of the driver never reads status registers directly 260 * because there would be too many side effects to handle conveniently. 261 * Instead, it reads copies of the registers stored here by the 262 * interrupt handler. 263 */ 264 u_char last_modem_status; /* last MSR read by intr handler */ 265 u_char prev_modem_status; /* last MSR handled by high level */ 266 267 u_char *ibuf; /* start of input buffer */ 268 u_char *ibufend; /* end of input buffer */ 269 u_char *ibufold; /* old input buffer, to be freed */ 270 u_char *ihighwater; /* threshold in input buffer */ 271 u_char *iptr; /* next free spot in input buffer */ 272 int ibufsize; /* size of ibuf (not include error bytes) */ 273 int ierroff; /* offset of error bytes in ibuf */ 274 275 struct lbq obufq; /* head of queue of output buffers */ 276 struct lbq obufs[2]; /* output buffers */ 277 278 bus_space_tag_t bst; 279 bus_space_handle_t bsh; 280 281#ifdef PC98 282 Port_t cmd_port; 283 Port_t sts_port; 284 Port_t in_modem_port; 285 Port_t intr_ctrl_port; 286 Port_t rsabase; /* Iobase address of an I/O-DATA RSA board. */ 287 int intr_enable; 288 int pc98_prev_modem_status; 289 int pc98_modem_delta; 290 int modem_car_chg_timer; 291 int pc98_prev_siocmd; 292 int pc98_prev_siomod; 293 int modem_checking; 294 int pc98_if_type; 295 296 bool_t pc98_8251fifo; 297 bool_t pc98_8251fifo_enable; 298#endif /* PC98 */ 299 Port_t data_port; /* i/o ports */ 300#ifdef COM_ESP 301 Port_t esp_port; 302#endif 303 Port_t int_ctl_port; 304 Port_t int_id_port; 305 Port_t modem_ctl_port; 306 Port_t line_status_port; 307 Port_t modem_status_port; 308 309 struct tty *tp; /* cross reference */ 310 311 struct pps_state pps; 312 int pps_bit; 313#ifdef KDB 314 int alt_brk_state; 315#endif 316 317 u_long bytes_in; /* statistics */ 318 u_long bytes_out; 319 u_int delta_error_counts[CE_NTYPES]; 320 u_long error_counts[CE_NTYPES]; 321 322 u_long rclk; 323 324 struct resource *irqres; 325 struct resource *ioportres; 326 int ioportrid; 327 void *cookie; 328 329 /* 330 * Data area for output buffers. Someday we should build the output 331 * buffer queue without copying data. 332 */ 333#ifdef PC98 334 int obufsize; 335 u_char *obuf1; 336 u_char *obuf2; 337#else 338 u_char obuf1[256]; 339 u_char obuf2[256]; 340#endif 341}; 342 343#ifdef COM_ESP 344static int espattach(struct com_s *com, Port_t esp_port); 345#endif 346 347static void combreak(struct tty *tp, int sig); 348static timeout_t siobusycheck; 349static u_int siodivisor(u_long rclk, speed_t speed); 350static void comclose(struct tty *tp); 351static int comopen(struct tty *tp, struct cdev *dev); 352static void sioinput(struct com_s *com); 353static void siointr1(struct com_s *com); 354static int siointr(void *arg); 355static int commodem(struct tty *tp, int sigon, int sigoff); 356static int comparam(struct tty *tp, struct termios *t); 357static void siopoll(void *); 358static void siosettimeout(void); 359static int siosetwater(struct com_s *com, speed_t speed); 360static void comstart(struct tty *tp); 361static void comstop(struct tty *tp, int rw); 362static timeout_t comwakeup; 363 364char sio_driver_name[] = "sio"; 365static struct mtx sio_lock; 366static int sio_inited; 367 368/* table and macro for fast conversion from a unit number to its com struct */ 369devclass_t sio_devclass; 370#define com_addr(unit) ((struct com_s *) \ 371 devclass_get_softc(sio_devclass, unit)) /* XXX */ 372 373int comconsole = -1; 374static volatile speed_t comdefaultrate = CONSPEED; 375static u_long comdefaultrclk = DEFAULT_RCLK; 376SYSCTL_ULONG(_machdep, OID_AUTO, conrclk, CTLFLAG_RW, &comdefaultrclk, 0, ""); 377static speed_t gdbdefaultrate = GDBSPEED; 378SYSCTL_UINT(_machdep, OID_AUTO, gdbspeed, CTLFLAG_RW, 379 &gdbdefaultrate, GDBSPEED, ""); 380static u_int com_events; /* input chars + weighted output completions */ 381static Port_t siocniobase; 382static int siocnunit = -1; 383static void *sio_slow_ih; 384static void *sio_fast_ih; 385static int sio_timeout; 386static int sio_timeouts_until_log; 387static struct callout_handle sio_timeout_handle 388 = CALLOUT_HANDLE_INITIALIZER(&sio_timeout_handle); 389static int sio_numunits; 390 391#ifdef PC98 392struct siodev { 393 short if_type; 394 short irq; 395 Port_t cmd, sts, ctrl, mod; 396}; 397static int sysclock; 398 399#define COM_INT_DISABLE {int previpri; previpri=spltty(); 400#define COM_INT_ENABLE splx(previpri);} 401#define IEN_TxFLAG IEN_Tx 402 403#define COM_CARRIER_DETECT_EMULATE 0 404#define PC98_CHECK_MODEM_INTERVAL (hz/10) 405#define DCD_OFF_TOLERANCE 2 406#define DCD_ON_RECOGNITION 2 407#define IS_8251(if_type) (!(if_type & 0x10)) 408#define COM1_EXT_CLOCK 0x40000 409 410static void commint(struct cdev *dev); 411static void com_tiocm_bis(struct com_s *com, int msr); 412static void com_tiocm_bic(struct com_s *com, int msr); 413static int com_tiocm_get(struct com_s *com); 414static int com_tiocm_get_delta(struct com_s *com); 415static void pc98_msrint_start(struct cdev *dev); 416static void com_cflag_and_speed_set(struct com_s *com, int cflag, int speed); 417static int pc98_ttspeedtab(struct com_s *com, int speed, u_int *divisor); 418static int pc98_get_modem_status(struct com_s *com); 419static timeout_t pc98_check_msr; 420static void pc98_set_baud_rate(struct com_s *com, u_int count); 421static void pc98_i8251_reset(struct com_s *com, int mode, int command); 422static void pc98_disable_i8251_interrupt(struct com_s *com, int mod); 423static void pc98_enable_i8251_interrupt(struct com_s *com, int mod); 424static int pc98_check_i8251_interrupt(struct com_s *com); 425static int pc98_i8251_get_cmd(struct com_s *com); 426static int pc98_i8251_get_mod(struct com_s *com); 427static void pc98_i8251_set_cmd(struct com_s *com, int x); 428static void pc98_i8251_or_cmd(struct com_s *com, int x); 429static void pc98_i8251_clear_cmd(struct com_s *com, int x); 430static void pc98_i8251_clear_or_cmd(struct com_s *com, int clr, int x); 431static int pc98_check_if_type(device_t dev, struct siodev *iod); 432static int pc98_check_8251vfast(void); 433static int pc98_check_8251fifo(void); 434static void pc98_check_sysclock(void); 435static void pc98_set_ioport(struct com_s *com); 436 437#define com_int_Tx_disable(com) \ 438 pc98_disable_i8251_interrupt(com,IEN_Tx|IEN_TxEMP) 439#define com_int_Tx_enable(com) \ 440 pc98_enable_i8251_interrupt(com,IEN_TxFLAG) 441#define com_int_Rx_disable(com) \ 442 pc98_disable_i8251_interrupt(com,IEN_Rx) 443#define com_int_Rx_enable(com) \ 444 pc98_enable_i8251_interrupt(com,IEN_Rx) 445#define com_int_TxRx_disable(com) \ 446 pc98_disable_i8251_interrupt(com,IEN_Tx|IEN_TxEMP|IEN_Rx) 447#define com_int_TxRx_enable(com) \ 448 pc98_enable_i8251_interrupt(com,IEN_TxFLAG|IEN_Rx) 449#define com_send_break_on(com) \ 450 (IS_8251((com)->pc98_if_type) ? \ 451 pc98_i8251_or_cmd((com), CMD8251_SBRK) : \ 452 sio_setreg((com), com_cfcr, (com)->cfcr_image |= CFCR_SBREAK)) 453#define com_send_break_off(com) \ 454 (IS_8251((com)->pc98_if_type) ? \ 455 pc98_i8251_clear_cmd((com), CMD8251_SBRK) : \ 456 sio_setreg((com), com_cfcr, (com)->cfcr_image &= ~CFCR_SBREAK)) 457 458static struct speedtab pc98speedtab[] = { /* internal RS232C interface */ 459 { 0, 0, }, 460 { 50, 50, }, 461 { 75, 75, }, 462 { 150, 150, }, 463 { 200, 200, }, 464 { 300, 300, }, 465 { 600, 600, }, 466 { 1200, 1200, }, 467 { 2400, 2400, }, 468 { 4800, 4800, }, 469 { 9600, 9600, }, 470 { 19200, 19200, }, 471 { 38400, 38400, }, 472 { 51200, 51200, }, 473 { 76800, 76800, }, 474 { 20800, 20800, }, 475 { 31200, 31200, }, 476 { 41600, 41600, }, 477 { 62400, 62400, }, 478 { -1, -1 } 479}; 480static struct speedtab pc98fast_speedtab[] = { 481 { 9600, 0x80 | (DEFAULT_RCLK / (16 * (9600))), }, 482 { 19200, 0x80 | (DEFAULT_RCLK / (16 * (19200))), }, 483 { 38400, 0x80 | (DEFAULT_RCLK / (16 * (38400))), }, 484 { 57600, 0x80 | (DEFAULT_RCLK / (16 * (57600))), }, 485 { 115200, 0x80 | (DEFAULT_RCLK / (16 * (115200))), }, 486 { -1, -1 } 487}; 488static struct speedtab comspeedtab_pio9032b[] = { 489 { 300, 6, }, 490 { 600, 5, }, 491 { 1200, 4, }, 492 { 2400, 3, }, 493 { 4800, 2, }, 494 { 9600, 1, }, 495 { 19200, 0, }, 496 { 38400, 7, }, 497 { -1, -1 } 498}; 499static struct speedtab comspeedtab_b98_01[] = { 500 { 75, 11, }, 501 { 150, 10, }, 502 { 300, 9, }, 503 { 600, 8, }, 504 { 1200, 7, }, 505 { 2400, 6, }, 506 { 4800, 5, }, 507 { 9600, 4, }, 508 { 19200, 3, }, 509 { 38400, 2, }, 510 { 76800, 1, }, 511 { 153600, 0, }, 512 { -1, -1 } 513}; 514static struct speedtab comspeedtab_ind[] = { 515 { 300, 1536, }, 516 { 600, 768, }, 517 { 1200, 384, }, 518 { 2400, 192, }, 519 { 4800, 96, }, 520 { 9600, 48, }, 521 { 19200, 24, }, 522 { 38400, 12, }, 523 { 57600, 8, }, 524 { 115200, 4, }, 525 { 153600, 3, }, 526 { 230400, 2, }, 527 { 460800, 1, }, 528 { -1, -1 } 529}; 530 531struct { 532 char *name; 533 short port_table[7]; 534 short irr_mask; 535 struct speedtab *speedtab; 536 short check_irq; 537} if_8251_type[] = { 538 /* COM_IF_INTERNAL */ 539 { " (internal)", {0x30, 0x32, 0x32, 0x33, 0x35, -1, -1}, 540 -1, pc98speedtab, 1 }, 541 /* COM_IF_PC9861K_1 */ 542 { " (PC9861K)", {0xb1, 0xb3, 0xb3, 0xb0, 0xb0, -1, -1}, 543 3, NULL, 1 }, 544 /* COM_IF_PC9861K_2 */ 545 { " (PC9861K)", {0xb9, 0xbb, 0xbb, 0xb2, 0xb2, -1, -1}, 546 3, NULL, 1 }, 547 /* COM_IF_IND_SS_1 */ 548 { " (IND-SS)", {0xb1, 0xb3, 0xb3, 0xb0, 0xb0, 0xb3, -1}, 549 3, comspeedtab_ind, 1 }, 550 /* COM_IF_IND_SS_2 */ 551 { " (IND-SS)", {0xb9, 0xbb, 0xbb, 0xb2, 0xb2, 0xbb, -1}, 552 3, comspeedtab_ind, 1 }, 553 /* COM_IF_PIO9032B_1 */ 554 { " (PIO9032B)", {0xb1, 0xb3, 0xb3, 0xb0, 0xb0, 0xb8, -1}, 555 7, comspeedtab_pio9032b, 1 }, 556 /* COM_IF_PIO9032B_2 */ 557 { " (PIO9032B)", {0xb9, 0xbb, 0xbb, 0xb2, 0xb2, 0xba, -1}, 558 7, comspeedtab_pio9032b, 1 }, 559 /* COM_IF_B98_01_1 */ 560 { " (B98-01)", {0xb1, 0xb3, 0xb3, 0xb0, 0xb0, 0xd1, 0xd3}, 561 7, comspeedtab_b98_01, 0 }, 562 /* COM_IF_B98_01_2 */ 563 { " (B98-01)", {0xb9, 0xbb, 0xbb, 0xb2, 0xb2, 0xd5, 0xd7}, 564 7, comspeedtab_b98_01, 0 }, 565}; 566#define PC98SIO_data_port(type) (if_8251_type[type].port_table[0]) 567#define PC98SIO_cmd_port(type) (if_8251_type[type].port_table[1]) 568#define PC98SIO_sts_port(type) (if_8251_type[type].port_table[2]) 569#define PC98SIO_in_modem_port(type) (if_8251_type[type].port_table[3]) 570#define PC98SIO_intr_ctrl_port(type) (if_8251_type[type].port_table[4]) 571#define PC98SIO_baud_rate_port(type) (if_8251_type[type].port_table[5]) 572#define PC98SIO_func_port(type) (if_8251_type[type].port_table[6]) 573 574#define I8251F_data 0x130 575#define I8251F_lsr 0x132 576#define I8251F_msr 0x134 577#define I8251F_iir 0x136 578#define I8251F_fcr 0x138 579#define I8251F_div 0x13a 580 581 582static bus_addr_t port_table_0[] = 583 {0x000, 0x001, 0x002, 0x003, 0x004, 0x005, 0x006, 0x007}; 584static bus_addr_t port_table_1[] = 585 {0x000, 0x002, 0x004, 0x006, 0x008, 0x00a, 0x00c, 0x00e}; 586static bus_addr_t port_table_8[] = 587 {0x000, 0x100, 0x200, 0x300, 0x400, 0x500, 0x600, 0x700}; 588static bus_addr_t port_table_rsa[] = { 589 0x008, 0x009, 0x00a, 0x00b, 0x00c, 0x00d, 0x00e, 0x00f, 590 0x000, 0x001, 0x002, 0x003, 0x004, 0x005, 0x006, 0x007 591}; 592 593struct { 594 char *name; 595 short irr_read; 596 short irr_write; 597 bus_addr_t *iat; 598 bus_size_t iatsz; 599 u_long rclk; 600} if_16550a_type[] = { 601 /* COM_IF_RSA98 */ 602 {" (RSA-98)", -1, -1, port_table_0, IO_COMSIZE, DEFAULT_RCLK}, 603 /* COM_IF_NS16550 */ 604 {"", -1, -1, port_table_0, IO_COMSIZE, DEFAULT_RCLK}, 605 /* COM_IF_SECOND_CCU */ 606 {"", -1, -1, port_table_0, IO_COMSIZE, DEFAULT_RCLK}, 607 /* COM_IF_MC16550II */ 608 {" (MC16550II)", -1, 0x1000, port_table_8, IO_COMSIZE, 609 DEFAULT_RCLK * 4}, 610 /* COM_IF_MCRS98 */ 611 {" (MC-RS98)", -1, 0x1000, port_table_8, IO_COMSIZE, DEFAULT_RCLK * 4}, 612 /* COM_IF_RSB3000 */ 613 {" (RSB-3000)", 0xbf, -1, port_table_1, IO_COMSIZE, DEFAULT_RCLK * 10}, 614 /* COM_IF_RSB384 */ 615 {" (RSB-384)", 0xbf, -1, port_table_1, IO_COMSIZE, DEFAULT_RCLK * 10}, 616 /* COM_IF_MODEM_CARD */ 617 {"", -1, -1, port_table_0, IO_COMSIZE, DEFAULT_RCLK}, 618 /* COM_IF_RSA98III */ 619 {" (RSA-98III)", -1, -1, port_table_rsa, 16, DEFAULT_RCLK * 8}, 620 /* COM_IF_ESP98 */ 621 {" (ESP98)", -1, -1, port_table_1, IO_COMSIZE, DEFAULT_RCLK * 4}, 622}; 623#endif /* PC98 */ 624 625#ifdef GDB 626static Port_t siogdbiobase = 0; 627#endif 628 629#ifdef COM_ESP 630#ifdef PC98 631 632/* XXX configure this properly. */ 633/* XXX quite broken for new-bus. */ 634static Port_t likely_com_ports[] = { 0, 0xb0, 0xb1, 0 }; 635static Port_t likely_esp_ports[] = { 0xc0d0, 0 }; 636 637#define ESP98_CMD1 (ESP_CMD1 * 0x100) 638#define ESP98_CMD2 (ESP_CMD2 * 0x100) 639#define ESP98_STATUS1 (ESP_STATUS1 * 0x100) 640#define ESP98_STATUS2 (ESP_STATUS2 * 0x100) 641 642#else /* PC98 */ 643 644/* XXX configure this properly. */ 645static Port_t likely_com_ports[] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8, }; 646static Port_t likely_esp_ports[] = { 0x140, 0x180, 0x280, 0 }; 647 648#endif /* PC98 */ 649#endif 650 651/* 652 * handle sysctl read/write requests for console speed 653 * 654 * In addition to setting comdefaultrate for I/O through /dev/console, 655 * also set the initial and lock values for the /dev/ttyXX device 656 * if there is one associated with the console. Finally, if the /dev/tty 657 * device has already been open, change the speed on the open running port 658 * itself. 659 */ 660 661static int 662sysctl_machdep_comdefaultrate(SYSCTL_HANDLER_ARGS) 663{ 664 int error, s; 665 speed_t newspeed; 666 struct com_s *com; 667 struct tty *tp; 668 669 newspeed = comdefaultrate; 670 671 error = sysctl_handle_opaque(oidp, &newspeed, sizeof newspeed, req); 672 if (error || !req->newptr) 673 return (error); 674 675 comdefaultrate = newspeed; 676 677 if (comconsole < 0) /* serial console not selected? */ 678 return (0); 679 680 com = com_addr(comconsole); 681 if (com == NULL) 682 return (ENXIO); 683 684 tp = com->tp; 685 if (tp == NULL) 686 return (ENXIO); 687 688 /* 689 * set the initial and lock rates for /dev/ttydXX and /dev/cuaXX 690 * (note, the lock rates really are boolean -- if non-zero, disallow 691 * speed changes) 692 */ 693 tp->t_init_in.c_ispeed = tp->t_init_in.c_ospeed = 694 tp->t_lock_in.c_ispeed = tp->t_lock_in.c_ospeed = 695 tp->t_init_out.c_ispeed = tp->t_init_out.c_ospeed = 696 tp->t_lock_out.c_ispeed = tp->t_lock_out.c_ospeed = comdefaultrate; 697 698 if (tp->t_state & TS_ISOPEN) { 699 tp->t_termios.c_ispeed = 700 tp->t_termios.c_ospeed = comdefaultrate; 701 s = spltty(); 702 error = comparam(tp, &tp->t_termios); 703 splx(s); 704 } 705 return error; 706} 707 708SYSCTL_PROC(_machdep, OID_AUTO, conspeed, CTLTYPE_INT | CTLFLAG_RW, 709 0, 0, sysctl_machdep_comdefaultrate, "I", ""); 710TUNABLE_INT("machdep.conspeed", __DEVOLATILE(int *, &comdefaultrate)); 711 712/* 713 * Unload the driver and clear the table. 714 * XXX this is mostly wrong. 715 * XXX TODO: 716 * This is usually called when the card is ejected, but 717 * can be caused by a kldunload of a controller driver. 718 * The idea is to reset the driver's view of the device 719 * and ensure that any driver entry points such as 720 * read and write do not hang. 721 */ 722int 723siodetach(device_t dev) 724{ 725 struct com_s *com; 726 727 com = (struct com_s *) device_get_softc(dev); 728 if (com == NULL) { 729 device_printf(dev, "NULL com in siounload\n"); 730 return (0); 731 } 732 com->gone = TRUE; 733 if (com->tp) 734 ttyfree(com->tp); 735 if (com->irqres) { 736 bus_teardown_intr(dev, com->irqres, com->cookie); 737 bus_release_resource(dev, SYS_RES_IRQ, 0, com->irqres); 738 } 739 if (com->ioportres) 740 bus_release_resource(dev, SYS_RES_IOPORT, com->ioportrid, 741 com->ioportres); 742 if (com->ibuf != NULL) 743 free(com->ibuf, M_DEVBUF); 744#ifdef PC98 745 if (com->obuf1 != NULL) 746 free(com->obuf1, M_DEVBUF); 747#endif 748 749 device_set_softc(dev, NULL); 750 free(com, M_DEVBUF); 751 return (0); 752} 753 754int 755sioprobe(dev, xrid, rclk, noprobe) 756 device_t dev; 757 int xrid; 758 u_long rclk; 759 int noprobe; 760{ 761#if 0 762 static bool_t already_init; 763 device_t xdev; 764#endif 765 struct com_s *com; 766 u_int divisor; 767 bool_t failures[10]; 768 int fn; 769 device_t idev; 770 Port_t iobase; 771 intrmask_t irqmap[4]; 772 intrmask_t irqs; 773 u_char mcr_image; 774 int result; 775 u_long xirq; 776 u_int flags = device_get_flags(dev); 777 int rid; 778 struct resource *port; 779#ifdef PC98 780 int tmp; 781 struct siodev iod; 782#endif 783 784#ifdef PC98 785 iod.if_type = GET_IFTYPE(flags); 786 if ((iod.if_type < 0 || iod.if_type > COM_IF_END1) && 787 (iod.if_type < 0x10 || iod.if_type > COM_IF_END2)) 788 return ENXIO; 789#endif 790 791 rid = xrid; 792#ifdef PC98 793 if (IS_8251(iod.if_type)) { 794 port = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid, 795 RF_ACTIVE); 796 } else if (iod.if_type == COM_IF_MODEM_CARD || 797 iod.if_type == COM_IF_RSA98III || 798 isa_get_vendorid(dev)) { 799 port = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 0, ~0, 800 if_16550a_type[iod.if_type & 0x0f].iatsz, RF_ACTIVE); 801 } else { 802 port = isa_alloc_resourcev(dev, SYS_RES_IOPORT, &rid, 803 if_16550a_type[iod.if_type & 0x0f].iat, 804 if_16550a_type[iod.if_type & 0x0f].iatsz, RF_ACTIVE); 805 } 806#else 807 port = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 808 0, ~0, IO_COMSIZE, RF_ACTIVE); 809#endif 810 if (!port) 811 return (ENXIO); 812#ifdef PC98 813 if (!IS_8251(iod.if_type)) { 814 if (isa_load_resourcev(port, 815 if_16550a_type[iod.if_type & 0x0f].iat, 816 if_16550a_type[iod.if_type & 0x0f].iatsz) != 0) { 817 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 818 return ENXIO; 819 } 820 } 821#endif 822 823 com = malloc(sizeof(*com), M_DEVBUF, M_NOWAIT | M_ZERO); 824 if (com == NULL) { 825 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 826 return (ENOMEM); 827 } 828 device_set_softc(dev, com); 829 com->bst = rman_get_bustag(port); 830 com->bsh = rman_get_bushandle(port); 831#ifdef PC98 832 if (!IS_8251(iod.if_type) && rclk == 0) 833 rclk = if_16550a_type[iod.if_type & 0x0f].rclk; 834#else 835 if (rclk == 0) 836 rclk = DEFAULT_RCLK; 837#endif 838 com->rclk = rclk; 839 840 while (sio_inited != 2) 841 if (atomic_cmpset_int(&sio_inited, 0, 1)) { 842 mtx_init(&sio_lock, sio_driver_name, NULL, 843 (comconsole != -1) ? 844 MTX_SPIN | MTX_QUIET : MTX_SPIN); 845 atomic_store_rel_int(&sio_inited, 2); 846 } 847 848#if 0 849 /* 850 * XXX this is broken - when we are first called, there are no 851 * previously configured IO ports. We could hard code 852 * 0x3f8, 0x2f8, 0x3e8, 0x2e8 etc but that's probably worse. 853 * This code has been doing nothing since the conversion since 854 * "count" is zero the first time around. 855 */ 856 if (!already_init) { 857 /* 858 * Turn off MCR_IENABLE for all likely serial ports. An unused 859 * port with its MCR_IENABLE gate open will inhibit interrupts 860 * from any used port that shares the interrupt vector. 861 * XXX the gate enable is elsewhere for some multiports. 862 */ 863 device_t *devs; 864 int count, i, xioport; 865#ifdef PC98 866 int xiftype; 867#endif 868 869 devclass_get_devices(sio_devclass, &devs, &count); 870#ifdef PC98 871 for (i = 0; i < count; i++) { 872 xdev = devs[i]; 873 xioport = bus_get_resource_start(xdev, SYS_RES_IOPORT, 0); 874 xiftype = GET_IFTYPE(device_get_flags(xdev)); 875 if (device_is_enabled(xdev) && xioport > 0) { 876 if (IS_8251(xiftype)) 877 outb((xioport & 0xff00) | PC98SIO_cmd_port(xiftype & 0x0f), 0xf2); 878 else 879 outb(xioport + if_16550a_type[xiftype & 0x0f].iat[com_mcr], 0); 880 } 881 } 882#else 883 for (i = 0; i < count; i++) { 884 xdev = devs[i]; 885 if (device_is_enabled(xdev) && 886 bus_get_resource(xdev, SYS_RES_IOPORT, 0, &xioport, 887 NULL) == 0) 888 outb(xioport + com_mcr, 0); 889 } 890#endif 891 free(devs, M_TEMP); 892 already_init = TRUE; 893 } 894#endif 895 896 if (COM_LLCONSOLE(flags)) { 897 printf("sio%d: reserved for low-level i/o\n", 898 device_get_unit(dev)); 899 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 900 device_set_softc(dev, NULL); 901 free(com, M_DEVBUF); 902 return (ENXIO); 903 } 904 905#ifdef PC98 906 DELAY(10); 907 908 /* 909 * If the port is i8251 UART (internal, B98_01) 910 */ 911 if (pc98_check_if_type(dev, &iod) == -1) { 912 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 913 device_set_softc(dev, NULL); 914 free(com, M_DEVBUF); 915 return (ENXIO); 916 } 917 if (iod.irq > 0) 918 bus_set_resource(dev, SYS_RES_IRQ, 0, iod.irq, 1); 919 if (IS_8251(iod.if_type)) { 920 outb(iod.cmd, 0); 921 DELAY(10); 922 outb(iod.cmd, 0); 923 DELAY(10); 924 outb(iod.cmd, 0); 925 DELAY(10); 926 outb(iod.cmd, CMD8251_RESET); 927 DELAY(1000); /* for a while...*/ 928 outb(iod.cmd, 0xf2); /* MODE (dummy) */ 929 DELAY(10); 930 outb(iod.cmd, 0x01); /* CMD (dummy) */ 931 DELAY(1000); /* for a while...*/ 932 if (( inb(iod.sts) & STS8251_TxEMP ) == 0 ) { 933 result = (ENXIO); 934 } 935 if (if_8251_type[iod.if_type & 0x0f].check_irq) { 936 COM_INT_DISABLE 937 tmp = ( inb( iod.ctrl ) & ~(IEN_Rx|IEN_TxEMP|IEN_Tx)); 938 outb( iod.ctrl, tmp|IEN_TxEMP ); 939 DELAY(10); 940 result = isa_irq_pending() ? 0 : ENXIO; 941 outb( iod.ctrl, tmp ); 942 COM_INT_ENABLE 943 } else { 944 /* 945 * B98_01 doesn't activate TxEMP interrupt line 946 * when being reset, so we can't check irq pending. 947 */ 948 result = 0; 949 } 950 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 951 if (result) { 952 device_set_softc(dev, NULL); 953 free(com, M_DEVBUF); 954 } 955 return result; 956 } 957#endif /* PC98 */ 958 /* 959 * If the device is on a multiport card and has an AST/4 960 * compatible interrupt control register, initialize this 961 * register and prepare to leave MCR_IENABLE clear in the mcr. 962 * Otherwise, prepare to set MCR_IENABLE in the mcr. 963 * Point idev to the device struct giving the correct id_irq. 964 * This is the struct for the master device if there is one. 965 */ 966 idev = dev; 967 mcr_image = MCR_IENABLE; 968#ifdef COM_MULTIPORT 969 if (COM_ISMULTIPORT(flags)) { 970#ifndef PC98 971 Port_t xiobase; 972 u_long io; 973#endif 974 975 idev = devclass_get_device(sio_devclass, COM_MPMASTER(flags)); 976 if (idev == NULL) { 977 printf("sio%d: master device %d not configured\n", 978 device_get_unit(dev), COM_MPMASTER(flags)); 979 idev = dev; 980 } 981#ifndef PC98 982 if (!COM_NOTAST4(flags)) { 983 if (bus_get_resource(idev, SYS_RES_IOPORT, 0, &io, 984 NULL) == 0) { 985 xiobase = io; 986 if (bus_get_resource(idev, SYS_RES_IRQ, 0, 987 NULL, NULL) == 0) 988 outb(xiobase + com_scr, 0x80); 989 else 990 outb(xiobase + com_scr, 0); 991 } 992 mcr_image = 0; 993 } 994#endif 995 } 996#endif /* COM_MULTIPORT */ 997 if (bus_get_resource(idev, SYS_RES_IRQ, 0, NULL, NULL) != 0) 998 mcr_image = 0; 999 1000 bzero(failures, sizeof failures); 1001 iobase = rman_get_start(port); 1002 1003#ifdef PC98 1004 if (iod.if_type == COM_IF_RSA98III) { 1005 mcr_image = 0; 1006 1007 outb(iobase + rsa_msr, 0x04); 1008 outb(iobase + rsa_frr, 0x00); 1009 if ((inb(iobase + rsa_srr) & 0x36) != 0x36) { 1010 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 1011 device_set_softc(dev, NULL); 1012 free(com, M_DEVBUF); 1013 return (ENXIO); 1014 } 1015 outb(iobase + rsa_ier, 0x00); 1016 outb(iobase + rsa_frr, 0x00); 1017 outb(iobase + rsa_tivsr, 0x00); 1018 outb(iobase + rsa_tcr, 0x00); 1019 } 1020 1021 tmp = if_16550a_type[iod.if_type & 0x0f].irr_write; 1022 if (tmp != -1) { 1023 /* MC16550II */ 1024 int irqout; 1025 switch (isa_get_irq(idev)) { 1026 case 3: irqout = 4; break; 1027 case 5: irqout = 5; break; 1028 case 6: irqout = 6; break; 1029 case 12: irqout = 7; break; 1030 default: 1031 printf("sio%d: irq configuration error\n", 1032 device_get_unit(dev)); 1033 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 1034 device_set_softc(dev, NULL); 1035 free(com, M_DEVBUF); 1036 return (ENXIO); 1037 } 1038 outb((iobase & 0x00ff) | tmp, irqout); 1039 } 1040#endif 1041 1042 /* 1043 * We don't want to get actual interrupts, just masked ones. 1044 * Interrupts from this line should already be masked in the ICU, 1045 * but mask them in the processor as well in case there are some 1046 * (misconfigured) shared interrupts. 1047 */ 1048 mtx_lock_spin(&sio_lock); 1049/* EXTRA DELAY? */ 1050 1051 /* 1052 * Initialize the speed and the word size and wait long enough to 1053 * drain the maximum of 16 bytes of junk in device output queues. 1054 * The speed is undefined after a master reset and must be set 1055 * before relying on anything related to output. There may be 1056 * junk after a (very fast) soft reboot and (apparently) after 1057 * master reset. 1058 * XXX what about the UART bug avoided by waiting in comparam()? 1059 * We don't want to to wait long enough to drain at 2 bps. 1060 */ 1061 if (iobase == siocniobase) 1062 DELAY((16 + 1) * 1000000 / (comdefaultrate / 10)); 1063 else { 1064 sio_setreg(com, com_cfcr, CFCR_DLAB | CFCR_8BITS); 1065 divisor = siodivisor(rclk, SIO_TEST_SPEED); 1066 sio_setreg(com, com_dlbl, divisor & 0xff); 1067 sio_setreg(com, com_dlbh, divisor >> 8); 1068 sio_setreg(com, com_cfcr, CFCR_8BITS); 1069 DELAY((16 + 1) * 1000000 / (SIO_TEST_SPEED / 10)); 1070 } 1071 1072 /* 1073 * Enable the interrupt gate and disable device interrupts. This 1074 * should leave the device driving the interrupt line low and 1075 * guarantee an edge trigger if an interrupt can be generated. 1076 */ 1077/* EXTRA DELAY? */ 1078 sio_setreg(com, com_mcr, mcr_image); 1079 sio_setreg(com, com_ier, 0); 1080 DELAY(1000); /* XXX */ 1081 irqmap[0] = isa_irq_pending(); 1082 1083 /* 1084 * Attempt to set loopback mode so that we can send a null byte 1085 * without annoying any external device. 1086 */ 1087/* EXTRA DELAY? */ 1088 sio_setreg(com, com_mcr, mcr_image | MCR_LOOPBACK); 1089 1090 /* 1091 * Attempt to generate an output interrupt. On 8250's, setting 1092 * IER_ETXRDY generates an interrupt independent of the current 1093 * setting and independent of whether the THR is empty. On 16450's, 1094 * setting IER_ETXRDY generates an interrupt independent of the 1095 * current setting. On 16550A's, setting IER_ETXRDY only 1096 * generates an interrupt when IER_ETXRDY is not already set. 1097 */ 1098 sio_setreg(com, com_ier, IER_ETXRDY); 1099#ifdef PC98 1100 if (iod.if_type == COM_IF_RSA98III) 1101 outb(iobase + rsa_ier, 0x04); 1102#endif 1103 1104 /* 1105 * On some 16x50 incompatibles, setting IER_ETXRDY doesn't generate 1106 * an interrupt. They'd better generate one for actually doing 1107 * output. Loopback may be broken on the same incompatibles but 1108 * it's unlikely to do more than allow the null byte out. 1109 */ 1110 sio_setreg(com, com_data, 0); 1111 if (iobase == siocniobase) 1112 DELAY((1 + 2) * 1000000 / (comdefaultrate / 10)); 1113 else 1114 DELAY((1 + 2) * 1000000 / (SIO_TEST_SPEED / 10)); 1115 1116 /* 1117 * Turn off loopback mode so that the interrupt gate works again 1118 * (MCR_IENABLE was hidden). This should leave the device driving 1119 * an interrupt line high. It doesn't matter if the interrupt 1120 * line oscillates while we are not looking at it, since interrupts 1121 * are disabled. 1122 */ 1123/* EXTRA DELAY? */ 1124 sio_setreg(com, com_mcr, mcr_image); 1125 1126 /* 1127 * It seems my Xircom CBEM56G Cardbus modem wants to be reset 1128 * to 8 bits *again*, or else probe test 0 will fail. 1129 * gwk@sgi.com, 4/19/2001 1130 */ 1131 sio_setreg(com, com_cfcr, CFCR_8BITS); 1132 1133 /* 1134 * Some PCMCIA cards (Palido 321s, DC-1S, ...) have the "TXRDY bug", 1135 * so we probe for a buggy IIR_TXRDY implementation even in the 1136 * noprobe case. We don't probe for it in the !noprobe case because 1137 * noprobe is always set for PCMCIA cards and the problem is not 1138 * known to affect any other cards. 1139 */ 1140 if (noprobe) { 1141 /* Read IIR a few times. */ 1142 for (fn = 0; fn < 2; fn ++) { 1143 DELAY(10000); 1144 failures[6] = sio_getreg(com, com_iir); 1145 } 1146 1147 /* IIR_TXRDY should be clear. Is it? */ 1148 result = 0; 1149 if (failures[6] & IIR_TXRDY) { 1150 /* 1151 * No. We seem to have the bug. Does our fix for 1152 * it work? 1153 */ 1154 sio_setreg(com, com_ier, 0); 1155 if (sio_getreg(com, com_iir) & IIR_NOPEND) { 1156 /* Yes. We discovered the TXRDY bug! */ 1157 SET_FLAG(dev, COM_C_IIR_TXRDYBUG); 1158 } else { 1159 /* No. Just fail. XXX */ 1160 result = ENXIO; 1161 sio_setreg(com, com_mcr, 0); 1162 } 1163 } else { 1164 /* Yes. No bug. */ 1165 CLR_FLAG(dev, COM_C_IIR_TXRDYBUG); 1166 } 1167 sio_setreg(com, com_ier, 0); 1168 sio_setreg(com, com_cfcr, CFCR_8BITS); 1169 mtx_unlock_spin(&sio_lock); 1170 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 1171 if (iobase == siocniobase) 1172 result = 0; 1173 if (result != 0) { 1174 device_set_softc(dev, NULL); 1175 free(com, M_DEVBUF); 1176 } 1177 return (result); 1178 } 1179 1180 /* 1181 * Check that 1182 * o the CFCR, IER and MCR in UART hold the values written to them 1183 * (the values happen to be all distinct - this is good for 1184 * avoiding false positive tests from bus echoes). 1185 * o an output interrupt is generated and its vector is correct. 1186 * o the interrupt goes away when the IIR in the UART is read. 1187 */ 1188/* EXTRA DELAY? */ 1189 failures[0] = sio_getreg(com, com_cfcr) - CFCR_8BITS; 1190 failures[1] = sio_getreg(com, com_ier) - IER_ETXRDY; 1191 failures[2] = sio_getreg(com, com_mcr) - mcr_image; 1192 DELAY(10000); /* Some internal modems need this time */ 1193 irqmap[1] = isa_irq_pending(); 1194 failures[4] = (sio_getreg(com, com_iir) & IIR_IMASK) - IIR_TXRDY; 1195#ifdef PC98 1196 if (iod.if_type == COM_IF_RSA98III) 1197 inb(iobase + rsa_srr); 1198#endif 1199 DELAY(1000); /* XXX */ 1200 irqmap[2] = isa_irq_pending(); 1201 failures[6] = (sio_getreg(com, com_iir) & IIR_IMASK) - IIR_NOPEND; 1202#ifdef PC98 1203 if (iod.if_type == COM_IF_RSA98III) 1204 inb(iobase + rsa_srr); 1205#endif 1206 1207 /* 1208 * Turn off all device interrupts and check that they go off properly. 1209 * Leave MCR_IENABLE alone. For ports without a master port, it gates 1210 * the OUT2 output of the UART to 1211 * the ICU input. Closing the gate would give a floating ICU input 1212 * (unless there is another device driving it) and spurious interrupts. 1213 * (On the system that this was first tested on, the input floats high 1214 * and gives a (masked) interrupt as soon as the gate is closed.) 1215 */ 1216 sio_setreg(com, com_ier, 0); 1217 sio_setreg(com, com_cfcr, CFCR_8BITS); /* dummy to avoid bus echo */ 1218 failures[7] = sio_getreg(com, com_ier); 1219#ifdef PC98 1220 if (iod.if_type == COM_IF_RSA98III) 1221 outb(iobase + rsa_ier, 0x00); 1222#endif 1223 DELAY(1000); /* XXX */ 1224 irqmap[3] = isa_irq_pending(); 1225 failures[9] = (sio_getreg(com, com_iir) & IIR_IMASK) - IIR_NOPEND; 1226#ifdef PC98 1227 if (iod.if_type == COM_IF_RSA98III) { 1228 inb(iobase + rsa_srr); 1229 outb(iobase + rsa_frr, 0x00); 1230 } 1231#endif 1232 1233 mtx_unlock_spin(&sio_lock); 1234 1235 irqs = irqmap[1] & ~irqmap[0]; 1236 if (bus_get_resource(idev, SYS_RES_IRQ, 0, &xirq, NULL) == 0 && 1237 ((1 << xirq) & irqs) == 0) { 1238 printf( 1239 "sio%d: configured irq %ld not in bitmap of probed irqs %#x\n", 1240 device_get_unit(dev), xirq, irqs); 1241 printf( 1242 "sio%d: port may not be enabled\n", 1243 device_get_unit(dev)); 1244 } 1245 if (bootverbose) 1246 printf("sio%d: irq maps: %#x %#x %#x %#x\n", 1247 device_get_unit(dev), 1248 irqmap[0], irqmap[1], irqmap[2], irqmap[3]); 1249 1250 result = 0; 1251 for (fn = 0; fn < sizeof failures; ++fn) 1252 if (failures[fn]) { 1253 sio_setreg(com, com_mcr, 0); 1254 result = ENXIO; 1255 if (bootverbose) { 1256 printf("sio%d: probe failed test(s):", 1257 device_get_unit(dev)); 1258 for (fn = 0; fn < sizeof failures; ++fn) 1259 if (failures[fn]) 1260 printf(" %d", fn); 1261 printf("\n"); 1262 } 1263 break; 1264 } 1265 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 1266 if (iobase == siocniobase) 1267 result = 0; 1268 if (result != 0) { 1269 device_set_softc(dev, NULL); 1270 free(com, M_DEVBUF); 1271 } 1272 return (result); 1273} 1274 1275#ifdef COM_ESP 1276static int 1277espattach(com, esp_port) 1278 struct com_s *com; 1279 Port_t esp_port; 1280{ 1281 u_char dips; 1282 u_char val; 1283 1284 /* 1285 * Check the ESP-specific I/O port to see if we're an ESP 1286 * card. If not, return failure immediately. 1287 */ 1288 if ((inb(esp_port) & 0xf3) == 0) { 1289 printf(" port 0x%x is not an ESP board?\n", esp_port); 1290 return (0); 1291 } 1292 1293 /* 1294 * We've got something that claims to be a Hayes ESP card. 1295 * Let's hope so. 1296 */ 1297 1298 /* Get the dip-switch configuration */ 1299#ifdef PC98 1300 outb(esp_port + ESP98_CMD1, ESP_GETDIPS); 1301 dips = inb(esp_port + ESP98_STATUS1); 1302#else 1303 outb(esp_port + ESP_CMD1, ESP_GETDIPS); 1304 dips = inb(esp_port + ESP_STATUS1); 1305#endif 1306 1307 /* 1308 * Bits 0,1 of dips say which COM port we are. 1309 */ 1310#ifdef PC98 1311 if ((rman_get_start(com->ioportres) & 0xff) == 1312 likely_com_ports[dips & 0x03]) 1313#else 1314 if (rman_get_start(com->ioportres) == likely_com_ports[dips & 0x03]) 1315#endif 1316 printf(" : ESP"); 1317 else { 1318 printf(" esp_port has com %d\n", dips & 0x03); 1319 return (0); 1320 } 1321 1322 /* 1323 * Check for ESP version 2.0 or later: bits 4,5,6 = 010. 1324 */ 1325#ifdef PC98 1326 outb(esp_port + ESP98_CMD1, ESP_GETTEST); 1327 val = inb(esp_port + ESP98_STATUS1); /* clear reg 1 */ 1328 val = inb(esp_port + ESP98_STATUS2); 1329#else 1330 outb(esp_port + ESP_CMD1, ESP_GETTEST); 1331 val = inb(esp_port + ESP_STATUS1); /* clear reg 1 */ 1332 val = inb(esp_port + ESP_STATUS2); 1333#endif 1334 if ((val & 0x70) < 0x20) { 1335 printf("-old (%o)", val & 0x70); 1336 return (0); 1337 } 1338 1339 /* 1340 * Check for ability to emulate 16550: bit 7 == 1 1341 */ 1342 if ((dips & 0x80) == 0) { 1343 printf(" slave"); 1344 return (0); 1345 } 1346 1347 /* 1348 * Okay, we seem to be a Hayes ESP card. Whee. 1349 */ 1350 com->esp = TRUE; 1351 com->esp_port = esp_port; 1352 return (1); 1353} 1354#endif /* COM_ESP */ 1355 1356int 1357sioattach(dev, xrid, rclk) 1358 device_t dev; 1359 int xrid; 1360 u_long rclk; 1361{ 1362 struct com_s *com; 1363#ifdef COM_ESP 1364 Port_t *espp; 1365#endif 1366 Port_t iobase; 1367 int unit; 1368 u_int flags; 1369 int rid; 1370 struct resource *port; 1371 int ret; 1372 int error; 1373 struct tty *tp; 1374#ifdef PC98 1375 u_char *obuf; 1376 u_long obufsize; 1377 int if_type = GET_IFTYPE(device_get_flags(dev)); 1378#endif 1379 1380 rid = xrid; 1381#ifdef PC98 1382 if (IS_8251(if_type)) { 1383 port = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid, 1384 RF_ACTIVE); 1385 } else if (if_type == COM_IF_MODEM_CARD || 1386 if_type == COM_IF_RSA98III || 1387 isa_get_vendorid(dev)) { 1388 port = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 0, ~0, 1389 if_16550a_type[if_type & 0x0f].iatsz, RF_ACTIVE); 1390 } else { 1391 port = isa_alloc_resourcev(dev, SYS_RES_IOPORT, &rid, 1392 if_16550a_type[if_type & 0x0f].iat, 1393 if_16550a_type[if_type & 0x0f].iatsz, RF_ACTIVE); 1394 } 1395#else 1396 port = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 1397 0, ~0, IO_COMSIZE, RF_ACTIVE); 1398#endif 1399 if (!port) 1400 return (ENXIO); 1401#ifdef PC98 1402 if (!IS_8251(if_type)) { 1403 if (isa_load_resourcev(port, 1404 if_16550a_type[if_type & 0x0f].iat, 1405 if_16550a_type[if_type & 0x0f].iatsz) != 0) { 1406 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 1407 return ENXIO; 1408 } 1409 } 1410#endif 1411 1412 iobase = rman_get_start(port); 1413 unit = device_get_unit(dev); 1414 com = device_get_softc(dev); 1415 flags = device_get_flags(dev); 1416 1417 if (unit >= sio_numunits) 1418 sio_numunits = unit + 1; 1419 1420#ifdef PC98 1421 obufsize = 256; 1422 if (if_type == COM_IF_RSA98III) 1423 obufsize = 2048; 1424 if ((obuf = malloc(obufsize * 2, M_DEVBUF, M_NOWAIT)) == NULL) { 1425 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 1426 return ENXIO; 1427 } 1428 bzero(obuf, obufsize * 2); 1429#endif 1430 1431 /* 1432 * sioprobe() has initialized the device registers as follows: 1433 * o cfcr = CFCR_8BITS. 1434 * It is most important that CFCR_DLAB is off, so that the 1435 * data port is not hidden when we enable interrupts. 1436 * o ier = 0. 1437 * Interrupts are only enabled when the line is open. 1438 * o mcr = MCR_IENABLE, or 0 if the port has AST/4 compatible 1439 * interrupt control register or the config specifies no irq. 1440 * Keeping MCR_DTR and MCR_RTS off might stop the external 1441 * device from sending before we are ready. 1442 */ 1443 bzero(com, sizeof *com); 1444 com->unit = unit; 1445 com->ioportres = port; 1446 com->ioportrid = rid; 1447 com->bst = rman_get_bustag(port); 1448 com->bsh = rman_get_bushandle(port); 1449 com->cfcr_image = CFCR_8BITS; 1450 com->loses_outints = COM_LOSESOUTINTS(flags) != 0; 1451 com->no_irq = bus_get_resource(dev, SYS_RES_IRQ, 0, NULL, NULL) != 0; 1452 com->tx_fifo_size = 1; 1453#ifdef PC98 1454 com->obufsize = obufsize; 1455 com->obuf1 = obuf; 1456 com->obuf2 = obuf + obufsize; 1457#endif 1458 com->obufs[0].l_head = com->obuf1; 1459 com->obufs[1].l_head = com->obuf2; 1460 1461#ifdef PC98 1462 com->pc98_if_type = if_type; 1463 1464 if (IS_8251(if_type)) { 1465 pc98_set_ioport(com); 1466 1467 if (if_type == COM_IF_INTERNAL && pc98_check_8251fifo()) { 1468 com->pc98_8251fifo = 1; 1469 com->pc98_8251fifo_enable = 0; 1470 } 1471 } else { 1472 bus_addr_t *iat = if_16550a_type[if_type & 0x0f].iat; 1473 1474 com->data_port = iobase + iat[com_data]; 1475 com->int_ctl_port = iobase + iat[com_ier]; 1476 com->int_id_port = iobase + iat[com_iir]; 1477 com->modem_ctl_port = iobase + iat[com_mcr]; 1478 com->mcr_image = inb(com->modem_ctl_port); 1479 com->line_status_port = iobase + iat[com_lsr]; 1480 com->modem_status_port = iobase + iat[com_msr]; 1481 } 1482#else /* not PC98 */ 1483 com->data_port = iobase + com_data; 1484 com->int_ctl_port = iobase + com_ier; 1485 com->int_id_port = iobase + com_iir; 1486 com->modem_ctl_port = iobase + com_mcr; 1487 com->mcr_image = inb(com->modem_ctl_port); 1488 com->line_status_port = iobase + com_lsr; 1489 com->modem_status_port = iobase + com_msr; 1490#endif 1491 1492 tp = com->tp = ttyalloc(); 1493 tp->t_oproc = comstart; 1494 tp->t_param = comparam; 1495 tp->t_stop = comstop; 1496 tp->t_modem = commodem; 1497 tp->t_break = combreak; 1498 tp->t_close = comclose; 1499 tp->t_open = comopen; 1500 tp->t_sc = com; 1501 1502#ifdef PC98 1503 if (!IS_8251(if_type) && rclk == 0) 1504 rclk = if_16550a_type[if_type & 0x0f].rclk; 1505#else 1506 if (rclk == 0) 1507 rclk = DEFAULT_RCLK; 1508#endif 1509 com->rclk = rclk; 1510 1511 if (unit == comconsole) 1512 ttyconsolemode(tp, comdefaultrate); 1513 error = siosetwater(com, tp->t_init_in.c_ispeed); 1514 mtx_unlock_spin(&sio_lock); 1515 if (error) { 1516 /* 1517 * Leave i/o resources allocated if this is a `cn'-level 1518 * console, so that other devices can't snarf them. 1519 */ 1520 if (iobase != siocniobase) 1521 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 1522 return (ENOMEM); 1523 } 1524 1525 /* attempt to determine UART type */ 1526 printf("sio%d: type", unit); 1527 1528#ifndef PC98 1529 if (!COM_ISMULTIPORT(flags) && 1530 !COM_IIR_TXRDYBUG(flags) && !COM_NOSCR(flags)) { 1531 u_char scr; 1532 u_char scr1; 1533 u_char scr2; 1534 1535 scr = sio_getreg(com, com_scr); 1536 sio_setreg(com, com_scr, 0xa5); 1537 scr1 = sio_getreg(com, com_scr); 1538 sio_setreg(com, com_scr, 0x5a); 1539 scr2 = sio_getreg(com, com_scr); 1540 sio_setreg(com, com_scr, scr); 1541 if (scr1 != 0xa5 || scr2 != 0x5a) { 1542 printf(" 8250 or not responding"); 1543 goto determined_type; 1544 } 1545 } 1546#endif /* !PC98 */ 1547#ifdef PC98 1548 if (IS_8251(com->pc98_if_type)) { 1549 if (com->pc98_8251fifo && !COM_NOFIFO(flags)) 1550 com->tx_fifo_size = 16; 1551 com_int_TxRx_disable( com ); 1552 com_cflag_and_speed_set( com, tp->t_init_in.c_cflag, comdefaultrate ); 1553 com_tiocm_bic( com, TIOCM_DTR|TIOCM_RTS|TIOCM_LE ); 1554 com_send_break_off( com ); 1555 1556 if (com->pc98_if_type == COM_IF_INTERNAL) { 1557 printf(" (internal%s%s)", 1558 com->pc98_8251fifo ? " fifo" : "", 1559 PC98SIO_baud_rate_port(com->pc98_if_type) != -1 ? 1560 " v-fast" : ""); 1561 } else { 1562 printf(" 8251%s", if_8251_type[com->pc98_if_type & 0x0f].name); 1563 } 1564 } else { 1565#endif /* PC98 */ 1566 sio_setreg(com, com_fifo, FIFO_ENABLE | FIFO_RX_HIGH); 1567 DELAY(100); 1568 switch (inb(com->int_id_port) & IIR_FIFO_MASK) { 1569 case FIFO_RX_LOW: 1570 printf(" 16450"); 1571 break; 1572 case FIFO_RX_MEDL: 1573 printf(" 16450?"); 1574 break; 1575 case FIFO_RX_MEDH: 1576 printf(" 16550?"); 1577 break; 1578 case FIFO_RX_HIGH: 1579 if (COM_NOFIFO(flags)) { 1580 printf(" 16550A fifo disabled"); 1581 break; 1582 } 1583 com->hasfifo = TRUE; 1584#ifdef PC98 1585 if (com->pc98_if_type == COM_IF_RSA98III) { 1586 com->tx_fifo_size = 2048; 1587 com->rsabase = iobase; 1588 outb(com->rsabase + rsa_ier, 0x00); 1589 outb(com->rsabase + rsa_frr, 0x00); 1590 } 1591#else 1592 if (COM_ST16650A(flags)) { 1593 printf(" ST16650A"); 1594 com->st16650a = TRUE; 1595 com->tx_fifo_size = 32; 1596 break; 1597 } 1598 if (COM_TI16754(flags)) { 1599 printf(" TI16754"); 1600 com->tx_fifo_size = 64; 1601 break; 1602 } 1603#endif 1604 printf(" 16550A"); 1605#ifdef COM_ESP 1606#ifdef PC98 1607 if (com->pc98_if_type == COM_IF_ESP98) 1608#endif 1609 for (espp = likely_esp_ports; *espp != 0; espp++) 1610 if (espattach(com, *espp)) { 1611 com->tx_fifo_size = 1024; 1612 break; 1613 } 1614 if (com->esp) 1615 break; 1616#endif 1617#ifdef PC98 1618 com->tx_fifo_size = 16; 1619#else 1620 com->tx_fifo_size = COM_FIFOSIZE(flags); 1621 if (com->tx_fifo_size == 0) 1622 com->tx_fifo_size = 16; 1623 else 1624 printf(" lookalike with %u bytes FIFO", 1625 com->tx_fifo_size); 1626#endif 1627 break; 1628 } 1629 1630#ifdef PC98 1631 if (com->pc98_if_type == COM_IF_RSB3000) { 1632 /* Set RSB-2000/3000 Extended Buffer mode. */ 1633 u_char lcr; 1634 lcr = sio_getreg(com, com_cfcr); 1635 sio_setreg(com, com_cfcr, lcr | CFCR_DLAB); 1636 sio_setreg(com, com_emr, EMR_EXBUFF | EMR_EFMODE); 1637 sio_setreg(com, com_cfcr, lcr); 1638 } 1639#endif 1640 1641#ifdef COM_ESP 1642 if (com->esp) { 1643 /* 1644 * Set 16550 compatibility mode. 1645 * We don't use the ESP_MODE_SCALE bit to increase the 1646 * fifo trigger levels because we can't handle large 1647 * bursts of input. 1648 * XXX flow control should be set in comparam(), not here. 1649 */ 1650#ifdef PC98 1651 outb(com->esp_port + ESP98_CMD1, ESP_SETMODE); 1652 outb(com->esp_port + ESP98_CMD2, ESP_MODE_RTS | ESP_MODE_FIFO); 1653#else 1654 outb(com->esp_port + ESP_CMD1, ESP_SETMODE); 1655 outb(com->esp_port + ESP_CMD2, ESP_MODE_RTS | ESP_MODE_FIFO); 1656#endif 1657 1658 /* Set RTS/CTS flow control. */ 1659#ifdef PC98 1660 outb(com->esp_port + ESP98_CMD1, ESP_SETFLOWTYPE); 1661 outb(com->esp_port + ESP98_CMD2, ESP_FLOW_RTS); 1662 outb(com->esp_port + ESP98_CMD2, ESP_FLOW_CTS); 1663#else 1664 outb(com->esp_port + ESP_CMD1, ESP_SETFLOWTYPE); 1665 outb(com->esp_port + ESP_CMD2, ESP_FLOW_RTS); 1666 outb(com->esp_port + ESP_CMD2, ESP_FLOW_CTS); 1667#endif 1668 1669 /* Set flow-control levels. */ 1670#ifdef PC98 1671 outb(com->esp_port + ESP98_CMD1, ESP_SETRXFLOW); 1672 outb(com->esp_port + ESP98_CMD2, HIBYTE(768)); 1673 outb(com->esp_port + ESP98_CMD2, LOBYTE(768)); 1674 outb(com->esp_port + ESP98_CMD2, HIBYTE(512)); 1675 outb(com->esp_port + ESP98_CMD2, LOBYTE(512)); 1676#else 1677 outb(com->esp_port + ESP_CMD1, ESP_SETRXFLOW); 1678 outb(com->esp_port + ESP_CMD2, HIBYTE(768)); 1679 outb(com->esp_port + ESP_CMD2, LOBYTE(768)); 1680 outb(com->esp_port + ESP_CMD2, HIBYTE(512)); 1681 outb(com->esp_port + ESP_CMD2, LOBYTE(512)); 1682#endif 1683 1684#ifdef PC98 1685 /* Set UART clock prescaler. */ 1686 outb(com->esp_port + ESP98_CMD1, ESP_SETCLOCK); 1687 outb(com->esp_port + ESP98_CMD2, 2); /* 4 times */ 1688#endif 1689 } 1690#endif /* COM_ESP */ 1691 sio_setreg(com, com_fifo, 0); 1692#ifdef PC98 1693 printf("%s", if_16550a_type[com->pc98_if_type & 0x0f].name); 1694#else 1695determined_type: ; 1696#endif 1697 1698#ifdef COM_MULTIPORT 1699 if (COM_ISMULTIPORT(flags)) { 1700 device_t masterdev; 1701 1702 com->multiport = TRUE; 1703 printf(" (multiport"); 1704 if (unit == COM_MPMASTER(flags)) 1705 printf(" master"); 1706 printf(")"); 1707 masterdev = devclass_get_device(sio_devclass, 1708 COM_MPMASTER(flags)); 1709 com->no_irq = (masterdev == NULL || bus_get_resource(masterdev, 1710 SYS_RES_IRQ, 0, NULL, NULL) != 0); 1711 } 1712#endif /* COM_MULTIPORT */ 1713#ifdef PC98 1714 } 1715#endif 1716 if (unit == comconsole) 1717 printf(", console"); 1718 if (COM_IIR_TXRDYBUG(flags)) 1719 printf(" with a buggy IIR_TXRDY implementation"); 1720 printf("\n"); 1721 1722 if (sio_fast_ih == NULL) { 1723 swi_add(&tty_intr_event, "sio", siopoll, NULL, SWI_TTY, 0, 1724 &sio_fast_ih); 1725 swi_add(&clk_intr_event, "sio", siopoll, NULL, SWI_CLOCK, 0, 1726 &sio_slow_ih); 1727 } 1728 1729 com->flags = flags; 1730 com->pps.ppscap = PPS_CAPTUREASSERT | PPS_CAPTURECLEAR; 1731 tp->t_pps = &com->pps; 1732 1733 if (COM_PPSCTS(flags)) 1734 com->pps_bit = MSR_CTS; 1735 else 1736 com->pps_bit = MSR_DCD; 1737 pps_init(&com->pps); 1738 1739 rid = 0; 1740 com->irqres = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, RF_ACTIVE); 1741 if (com->irqres) { 1742 ret = bus_setup_intr(dev, com->irqres, 1743 INTR_TYPE_TTY, 1744 siointr, NULL, com, &com->cookie); 1745 if (ret) { 1746 ret = bus_setup_intr(dev, 1747 com->irqres, INTR_TYPE_TTY, 1748 NULL, (driver_intr_t *)siointr, 1749 com, &com->cookie); 1750 if (ret == 0) 1751 device_printf(dev, "unable to activate interrupt in fast mode - using normal mode\n"); 1752 } 1753 if (ret) 1754 device_printf(dev, "could not activate interrupt\n"); 1755#if defined(KDB) 1756 /* 1757 * Enable interrupts for early break-to-debugger support 1758 * on the console. 1759 */ 1760 if (ret == 0 && unit == comconsole) 1761 outb(siocniobase + com_ier, IER_ERXRDY | IER_ERLS | 1762 IER_EMSC); 1763#endif 1764 } 1765 1766 /* We're ready, open the doors... */ 1767 ttycreate(tp, TS_CALLOUT, "d%r", unit); 1768 1769 return (0); 1770} 1771 1772static int 1773comopen(struct tty *tp, struct cdev *dev) 1774{ 1775 struct com_s *com; 1776 int i; 1777 1778 com = tp->t_sc; 1779 com->poll = com->no_irq; 1780 com->poll_output = com->loses_outints; 1781#ifdef PC98 1782 if (IS_8251(com->pc98_if_type)) { 1783 com_tiocm_bis(com, TIOCM_DTR|TIOCM_RTS); 1784 pc98_msrint_start(dev); 1785 if (com->pc98_8251fifo) { 1786 com->pc98_8251fifo_enable = 1; 1787 outb(I8251F_fcr, 1788 FIFO_ENABLE | FIFO_XMT_RST | FIFO_RCV_RST); 1789 } 1790 } 1791#endif 1792 if (com->hasfifo) { 1793 /* 1794 * (Re)enable and drain fifos. 1795 * 1796 * Certain SMC chips cause problems if the fifos 1797 * are enabled while input is ready. Turn off the 1798 * fifo if necessary to clear the input. We test 1799 * the input ready bit after enabling the fifos 1800 * since we've already enabled them in comparam() 1801 * and to handle races between enabling and fresh 1802 * input. 1803 */ 1804 for (i = 0; i < 500; i++) { 1805 sio_setreg(com, com_fifo, 1806 FIFO_RCV_RST | FIFO_XMT_RST | com->fifo_image); 1807#ifdef PC98 1808 if (com->pc98_if_type == COM_IF_RSA98III) 1809 outb(com->rsabase + rsa_frr , 0x00); 1810#endif 1811 /* 1812 * XXX the delays are for superstitious 1813 * historical reasons. It must be less than 1814 * the character time at the maximum 1815 * supported speed (87 usec at 115200 bps 1816 * 8N1). Otherwise we might loop endlessly 1817 * if data is streaming in. We used to use 1818 * delays of 100. That usually worked 1819 * because DELAY(100) used to usually delay 1820 * for about 85 usec instead of 100. 1821 */ 1822 DELAY(50); 1823#ifdef PC98 1824 if (com->pc98_if_type == COM_IF_RSA98III ? 1825 !(inb(com->rsabase + rsa_srr) & 0x08) : 1826 !(inb(com->line_status_port) & LSR_RXRDY)) 1827 break; 1828#else 1829 if (!(inb(com->line_status_port) & LSR_RXRDY)) 1830 break; 1831#endif 1832 sio_setreg(com, com_fifo, 0); 1833 DELAY(50); 1834 (void) inb(com->data_port); 1835 } 1836 if (i == 500) 1837 return (EIO); 1838 } 1839 1840 mtx_lock_spin(&sio_lock); 1841#ifdef PC98 1842 if (IS_8251(com->pc98_if_type)) { 1843 com_tiocm_bis(com, TIOCM_LE); 1844 com->pc98_prev_modem_status = pc98_get_modem_status(com); 1845 com_int_Rx_enable(com); 1846 } else { 1847#endif 1848 (void) inb(com->line_status_port); 1849 (void) inb(com->data_port); 1850 com->prev_modem_status = com->last_modem_status 1851 = inb(com->modem_status_port); 1852 outb(com->int_ctl_port, 1853 IER_ERXRDY | IER_ERLS | IER_EMSC 1854 | (COM_IIR_TXRDYBUG(com->flags) ? 0 : IER_ETXRDY)); 1855#ifdef PC98 1856 if (com->pc98_if_type == COM_IF_RSA98III) { 1857 outb(com->rsabase + rsa_ier, 0x1d); 1858 outb(com->int_ctl_port, IER_ERLS | IER_EMSC); 1859 } 1860#endif 1861#ifdef PC98 1862 } 1863#endif 1864 mtx_unlock_spin(&sio_lock); 1865 siosettimeout(); 1866 /* XXX: should be generic ? */ 1867#ifdef PC98 1868 if ((IS_8251(com->pc98_if_type) && 1869 (pc98_get_modem_status(com) & TIOCM_CAR)) || 1870 (!IS_8251(com->pc98_if_type) && 1871 (com->prev_modem_status & MSR_DCD)) || 1872 ISCALLOUT(dev)) 1873 ttyld_modem(tp, 1); 1874#else 1875 if (com->prev_modem_status & MSR_DCD || ISCALLOUT(dev)) 1876 ttyld_modem(tp, 1); 1877#endif 1878 return (0); 1879} 1880 1881static void 1882comclose(tp) 1883 struct tty *tp; 1884{ 1885 int s; 1886 struct com_s *com; 1887 1888 s = spltty(); 1889 com = tp->t_sc; 1890 com->poll = FALSE; 1891 com->poll_output = FALSE; 1892#ifdef PC98 1893 com_send_break_off(com); 1894#else 1895 sio_setreg(com, com_cfcr, com->cfcr_image &= ~CFCR_SBREAK); 1896#endif 1897 1898#if defined(KDB) 1899 /* 1900 * Leave interrupts enabled and don't clear DTR if this is the 1901 * console. This allows us to detect break-to-debugger events 1902 * while the console device is closed. 1903 */ 1904 if (com->unit != comconsole) 1905#endif 1906 { 1907#ifdef PC98 1908 int tmp; 1909 if (IS_8251(com->pc98_if_type)) 1910 com_int_TxRx_disable(com); 1911 else 1912 sio_setreg(com, com_ier, 0); 1913 if (com->pc98_if_type == COM_IF_RSA98III) 1914 outb(com->rsabase + rsa_ier, 0x00); 1915 if (IS_8251(com->pc98_if_type)) 1916 tmp = pc98_get_modem_status(com) & TIOCM_CAR; 1917 else 1918 tmp = com->prev_modem_status & MSR_DCD; 1919#else 1920 sio_setreg(com, com_ier, 0); 1921#endif 1922 if (tp->t_cflag & HUPCL 1923 /* 1924 * XXX we will miss any carrier drop between here and the 1925 * next open. Perhaps we should watch DCD even when the 1926 * port is closed; it is not sufficient to check it at 1927 * the next open because it might go up and down while 1928 * we're not watching. 1929 */ 1930 || (!tp->t_actout 1931#ifdef PC98 1932 && !(tmp) 1933#else 1934 && !(com->prev_modem_status & MSR_DCD) 1935#endif 1936 && !(tp->t_init_in.c_cflag & CLOCAL)) 1937 || !(tp->t_state & TS_ISOPEN)) { 1938#ifdef PC98 1939 if (IS_8251(com->pc98_if_type)) 1940 com_tiocm_bic(com, TIOCM_DTR|TIOCM_RTS|TIOCM_LE); 1941 else 1942#endif 1943 (void)commodem(tp, 0, SER_DTR); 1944 ttydtrwaitstart(tp); 1945 } 1946#ifdef PC98 1947 else { 1948 if (IS_8251(com->pc98_if_type)) 1949 com_tiocm_bic(com, TIOCM_LE); 1950 } 1951#endif 1952 } 1953#ifdef PC98 1954 if (com->pc98_8251fifo) { 1955 if (com->pc98_8251fifo_enable) 1956 outb(I8251F_fcr, FIFO_XMT_RST | FIFO_RCV_RST); 1957 com->pc98_8251fifo_enable = 0; 1958 } 1959#endif 1960 if (com->hasfifo) { 1961 /* 1962 * Disable fifos so that they are off after controlled 1963 * reboots. Some BIOSes fail to detect 16550s when the 1964 * fifos are enabled. 1965 */ 1966 sio_setreg(com, com_fifo, 0); 1967 } 1968 tp->t_actout = FALSE; 1969 wakeup(&tp->t_actout); 1970 wakeup(TSA_CARR_ON(tp)); /* restart any wopeners */ 1971 siosettimeout(); 1972 splx(s); 1973} 1974 1975static void 1976siobusycheck(chan) 1977 void *chan; 1978{ 1979 struct com_s *com; 1980 int s; 1981 1982 com = (struct com_s *)chan; 1983 1984 /* 1985 * Clear TS_BUSY if low-level output is complete. 1986 * spl locking is sufficient because siointr1() does not set CS_BUSY. 1987 * If siointr1() clears CS_BUSY after we look at it, then we'll get 1988 * called again. Reading the line status port outside of siointr1() 1989 * is safe because CS_BUSY is clear so there are no output interrupts 1990 * to lose. 1991 */ 1992 s = spltty(); 1993 if (com->state & CS_BUSY) 1994 com->extra_state &= ~CSE_BUSYCHECK; /* False alarm. */ 1995#ifdef PC98 1996 else if ((IS_8251(com->pc98_if_type) && 1997 ((com->pc98_8251fifo_enable && 1998 (inb(I8251F_lsr) & (FLSR_TxRDY | FLSR_TxEMP)) 1999 == (FLSR_TxRDY | FLSR_TxEMP)) || 2000 (!com->pc98_8251fifo_enable && 2001 (inb(com->sts_port) & (STS8251_TxRDY | STS8251_TxEMP)) 2002 == (STS8251_TxRDY | STS8251_TxEMP)))) || 2003 ((inb(com->line_status_port) & (LSR_TSRE | LSR_TXRDY)) 2004 == (LSR_TSRE | LSR_TXRDY))) { 2005#else 2006 else if ((inb(com->line_status_port) & (LSR_TSRE | LSR_TXRDY)) 2007 == (LSR_TSRE | LSR_TXRDY)) { 2008#endif 2009 com->tp->t_state &= ~TS_BUSY; 2010 ttwwakeup(com->tp); 2011 com->extra_state &= ~CSE_BUSYCHECK; 2012 } else 2013 timeout(siobusycheck, com, hz / 100); 2014 splx(s); 2015} 2016 2017static u_int 2018siodivisor(rclk, speed) 2019 u_long rclk; 2020 speed_t speed; 2021{ 2022 long actual_speed; 2023 u_int divisor; 2024 int error; 2025 2026 if (speed == 0) 2027 return (0); 2028#if UINT_MAX > (ULONG_MAX - 1) / 8 2029 if (speed > (ULONG_MAX - 1) / 8) 2030 return (0); 2031#endif 2032 divisor = (rclk / (8UL * speed) + 1) / 2; 2033 if (divisor == 0 || divisor >= 65536) 2034 return (0); 2035 actual_speed = rclk / (16UL * divisor); 2036 2037 /* 10 times error in percent: */ 2038 error = ((actual_speed - (long)speed) * 2000 / (long)speed + 1) / 2; 2039 2040 /* 3.0% maximum error tolerance: */ 2041 if (error < -30 || error > 30) 2042 return (0); 2043 2044 return (divisor); 2045} 2046 2047/* 2048 * Call this function with the sio_lock mutex held. It will return with the 2049 * lock still held. 2050 */ 2051static void 2052sioinput(com) 2053 struct com_s *com; 2054{ 2055 u_char *buf; 2056 int incc; 2057 u_char line_status; 2058 int recv_data; 2059 struct tty *tp; 2060 2061 buf = com->ibuf; 2062 tp = com->tp; 2063 if (!(tp->t_state & TS_ISOPEN) || !(tp->t_cflag & CREAD)) { 2064 com_events -= (com->iptr - com->ibuf); 2065 com->iptr = com->ibuf; 2066 return; 2067 } 2068 if (tp->t_state & TS_CAN_BYPASS_L_RINT) { 2069 /* 2070 * Avoid the grotesquely inefficient lineswitch routine 2071 * (ttyinput) in "raw" mode. It usually takes about 450 2072 * instructions (that's without canonical processing or echo!). 2073 * slinput is reasonably fast (usually 40 instructions plus 2074 * call overhead). 2075 */ 2076 do { 2077 /* 2078 * This may look odd, but it is using save-and-enable 2079 * semantics instead of the save-and-disable semantics 2080 * that are used everywhere else. 2081 */ 2082 mtx_unlock_spin(&sio_lock); 2083 incc = com->iptr - buf; 2084 if (tp->t_rawq.c_cc + incc > tp->t_ihiwat 2085 && (com->state & CS_RTS_IFLOW 2086 || tp->t_iflag & IXOFF) 2087 && !(tp->t_state & TS_TBLOCK)) 2088 ttyblock(tp); 2089 com->delta_error_counts[CE_TTY_BUF_OVERFLOW] 2090 += b_to_q((char *)buf, incc, &tp->t_rawq); 2091 buf += incc; 2092 tk_nin += incc; 2093 tk_rawcc += incc; 2094 tp->t_rawcc += incc; 2095 ttwakeup(tp); 2096 if (tp->t_state & TS_TTSTOP 2097 && (tp->t_iflag & IXANY 2098 || tp->t_cc[VSTART] == tp->t_cc[VSTOP])) { 2099 tp->t_state &= ~TS_TTSTOP; 2100 tp->t_lflag &= ~FLUSHO; 2101 comstart(tp); 2102 } 2103 mtx_lock_spin(&sio_lock); 2104 } while (buf < com->iptr); 2105 } else { 2106 do { 2107 /* 2108 * This may look odd, but it is using save-and-enable 2109 * semantics instead of the save-and-disable semantics 2110 * that are used everywhere else. 2111 */ 2112 mtx_unlock_spin(&sio_lock); 2113 line_status = buf[com->ierroff]; 2114 recv_data = *buf++; 2115 if (line_status 2116 & (LSR_BI | LSR_FE | LSR_OE | LSR_PE)) { 2117 if (line_status & LSR_BI) 2118 recv_data |= TTY_BI; 2119 if (line_status & LSR_FE) 2120 recv_data |= TTY_FE; 2121 if (line_status & LSR_OE) 2122 recv_data |= TTY_OE; 2123 if (line_status & LSR_PE) 2124 recv_data |= TTY_PE; 2125 } 2126 ttyld_rint(tp, recv_data); 2127 mtx_lock_spin(&sio_lock); 2128 } while (buf < com->iptr); 2129 } 2130 com_events -= (com->iptr - com->ibuf); 2131 com->iptr = com->ibuf; 2132 2133 /* 2134 * There is now room for another low-level buffer full of input, 2135 * so enable RTS if it is now disabled and there is room in the 2136 * high-level buffer. 2137 */ 2138#ifdef PC98 2139 if (IS_8251(com->pc98_if_type)) { 2140 if ((com->state & CS_RTS_IFLOW) && 2141 !(com_tiocm_get(com) & TIOCM_RTS) && 2142 !(tp->t_state & TS_TBLOCK)) 2143 com_tiocm_bis(com, TIOCM_RTS); 2144 } else { 2145 if ((com->state & CS_RTS_IFLOW) && 2146 !(com->mcr_image & MCR_RTS) && 2147 !(tp->t_state & TS_TBLOCK)) 2148 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS); 2149 } 2150#else 2151 if ((com->state & CS_RTS_IFLOW) && !(com->mcr_image & MCR_RTS) && 2152 !(tp->t_state & TS_TBLOCK)) 2153 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS); 2154#endif 2155} 2156 2157static int 2158siointr(arg) 2159 void *arg; 2160{ 2161 struct com_s *com; 2162#if defined(PC98) && defined(COM_MULTIPORT) 2163 u_char rsa_buf_status; 2164#endif 2165 2166#ifndef COM_MULTIPORT 2167 com = (struct com_s *)arg; 2168 2169 mtx_lock_spin(&sio_lock); 2170 siointr1(com); 2171 mtx_unlock_spin(&sio_lock); 2172#else /* COM_MULTIPORT */ 2173 bool_t possibly_more_intrs; 2174 int unit; 2175 2176 /* 2177 * Loop until there is no activity on any port. This is necessary 2178 * to get an interrupt edge more than to avoid another interrupt. 2179 * If the IRQ signal is just an OR of the IRQ signals from several 2180 * devices, then the edge from one may be lost because another is 2181 * on. 2182 */ 2183 mtx_lock_spin(&sio_lock); 2184 do { 2185 possibly_more_intrs = FALSE; 2186 for (unit = 0; unit < sio_numunits; ++unit) { 2187 com = com_addr(unit); 2188 /* 2189 * XXX COM_LOCK(); 2190 * would it work here, or be counter-productive? 2191 */ 2192#ifdef PC98 2193 if (com != NULL 2194 && !com->gone 2195 && IS_8251(com->pc98_if_type)) { 2196 siointr1(com); 2197 } else if (com != NULL 2198 && !com->gone 2199 && com->pc98_if_type == COM_IF_RSA98III) { 2200 rsa_buf_status = 2201 inb(com->rsabase + rsa_srr) & 0xc9; 2202 if ((rsa_buf_status & 0xc8) 2203 || !(rsa_buf_status & 0x01)) { 2204 siointr1(com); 2205 if (rsa_buf_status != 2206 (inb(com->rsabase + rsa_srr) & 0xc9)) 2207 possibly_more_intrs = TRUE; 2208 } 2209 } else 2210#endif 2211 if (com != NULL 2212 && !com->gone 2213 && (inb(com->int_id_port) & IIR_IMASK) 2214 != IIR_NOPEND) { 2215 siointr1(com); 2216 possibly_more_intrs = TRUE; 2217 } 2218 /* XXX COM_UNLOCK(); */ 2219 } 2220 } while (possibly_more_intrs); 2221 mtx_unlock_spin(&sio_lock); 2222#endif /* COM_MULTIPORT */ 2223 return (FILTER_HANDLED); 2224} 2225 2226static struct timespec siots[8]; 2227static int siotso; 2228static int volatile siotsunit = -1; 2229 2230static int 2231sysctl_siots(SYSCTL_HANDLER_ARGS) 2232{ 2233 char buf[128]; 2234 long long delta; 2235 size_t len; 2236 int error, i, tso; 2237 2238 for (i = 1, tso = siotso; i < tso; i++) { 2239 delta = (long long)(siots[i].tv_sec - siots[i - 1].tv_sec) * 2240 1000000000 + 2241 (siots[i].tv_nsec - siots[i - 1].tv_nsec); 2242 len = sprintf(buf, "%lld\n", delta); 2243 if (delta >= 110000) 2244 len += sprintf(buf + len - 1, ": *** %ld.%09ld\n", 2245 (long)siots[i].tv_sec, siots[i].tv_nsec) - 1; 2246 if (i == tso - 1) 2247 buf[len - 1] = '\0'; 2248 error = SYSCTL_OUT(req, buf, len); 2249 if (error != 0) 2250 return (error); 2251 } 2252 return (0); 2253} 2254 2255SYSCTL_PROC(_machdep, OID_AUTO, siots, CTLTYPE_STRING | CTLFLAG_RD, 2256 0, 0, sysctl_siots, "A", "sio timestamps"); 2257 2258static void 2259siointr1(com) 2260 struct com_s *com; 2261{ 2262 u_char int_ctl; 2263 u_char int_ctl_new; 2264 u_char line_status; 2265 u_char modem_status; 2266 u_char *ioptr; 2267 u_char recv_data; 2268#ifdef PC98 2269 u_char tmp = 0; 2270 u_char rsa_buf_status = 0; 2271 int rsa_tx_fifo_size = 0; 2272#endif /* PC98 */ 2273#if defined(KDB) 2274 int kdb_brk; 2275 2276again: 2277#endif 2278 2279 if (COM_IIR_TXRDYBUG(com->flags)) { 2280 int_ctl = inb(com->int_ctl_port); 2281 int_ctl_new = int_ctl; 2282 } else { 2283 int_ctl = 0; 2284 int_ctl_new = 0; 2285 } 2286 2287 while (!com->gone) { 2288#ifdef PC98 2289status_read:; 2290 if (IS_8251(com->pc98_if_type)) { 2291 if (com->pc98_8251fifo_enable) 2292 tmp = inb(I8251F_lsr); 2293 else 2294 tmp = inb(com->sts_port); 2295more_intr: 2296 line_status = 0; 2297 if (com->pc98_8251fifo_enable) { 2298 if (tmp & FLSR_TxRDY) line_status |= LSR_TXRDY; 2299 if (tmp & FLSR_RxRDY) line_status |= LSR_RXRDY; 2300 if (tmp & FLSR_TxEMP) line_status |= LSR_TSRE; 2301 if (tmp & FLSR_PE) line_status |= LSR_PE; 2302 if (tmp & FLSR_OE) line_status |= LSR_OE; 2303 if (tmp & FLSR_BI) line_status |= LSR_BI; 2304 } else { 2305 if (tmp & STS8251_TxRDY) line_status |= LSR_TXRDY; 2306 if (tmp & STS8251_RxRDY) line_status |= LSR_RXRDY; 2307 if (tmp & STS8251_TxEMP) line_status |= LSR_TSRE; 2308 if (tmp & STS8251_PE) line_status |= LSR_PE; 2309 if (tmp & STS8251_OE) line_status |= LSR_OE; 2310 if (tmp & STS8251_FE) line_status |= LSR_FE; 2311 if (tmp & STS8251_BI) line_status |= LSR_BI; 2312 } 2313 } else { 2314#endif /* PC98 */ 2315 if (com->pps.ppsparam.mode & PPS_CAPTUREBOTH) { 2316 modem_status = inb(com->modem_status_port); 2317 if ((modem_status ^ com->last_modem_status) & 2318 com->pps_bit) { 2319 pps_capture(&com->pps); 2320 pps_event(&com->pps, 2321 (modem_status & com->pps_bit) ? 2322 PPS_CAPTUREASSERT : PPS_CAPTURECLEAR); 2323 } 2324 } 2325 line_status = inb(com->line_status_port); 2326#ifdef PC98 2327 } 2328 if (com->pc98_if_type == COM_IF_RSA98III) 2329 rsa_buf_status = inb(com->rsabase + rsa_srr); 2330#endif /* PC98 */ 2331 2332 /* input event? (check first to help avoid overruns) */ 2333#ifndef PC98 2334 while (line_status & LSR_RCV_MASK) { 2335#else 2336 while ((line_status & LSR_RCV_MASK) 2337 || (com->pc98_if_type == COM_IF_RSA98III 2338 && (rsa_buf_status & 0x08))) { 2339#endif /* PC98 */ 2340 /* break/unnattached error bits or real input? */ 2341#ifdef PC98 2342 if (IS_8251(com->pc98_if_type)) { 2343 if (com->pc98_8251fifo_enable) { 2344 recv_data = inb(I8251F_data); 2345 if (tmp & 2346 (FLSR_PE | FLSR_OE | FLSR_BI)) { 2347 pc98_i8251_or_cmd(com, CMD8251_ER); 2348 recv_data = 0; 2349 } 2350 } else { 2351 recv_data = inb(com->data_port); 2352 if (tmp & (STS8251_PE | STS8251_OE | 2353 STS8251_FE | STS8251_BI)) { 2354 pc98_i8251_or_cmd(com, CMD8251_ER); 2355 recv_data = 0; 2356 } 2357 } 2358 } else if (com->pc98_if_type == COM_IF_RSA98III) { 2359 if (!(rsa_buf_status & 0x08)) 2360 recv_data = 0; 2361 else 2362 recv_data = inb(com->data_port); 2363 } else 2364#endif 2365 if (!(line_status & LSR_RXRDY)) 2366 recv_data = 0; 2367 else 2368 recv_data = inb(com->data_port); 2369#ifdef KDB 2370 if (com->unit == comconsole && 2371 (kdb_brk = kdb_alt_break(recv_data, 2372 &com->alt_brk_state)) != 0) { 2373 goto again; 2374 } 2375#endif /* KDB */ 2376 if (line_status & (LSR_BI | LSR_FE | LSR_PE)) { 2377 /* 2378 * Don't store BI if IGNBRK or FE/PE if IGNPAR. 2379 * Otherwise, push the work to a higher level 2380 * (to handle PARMRK) if we're bypassing. 2381 * Otherwise, convert BI/FE and PE+INPCK to 0. 2382 * 2383 * This makes bypassing work right in the 2384 * usual "raw" case (IGNBRK set, and IGNPAR 2385 * and INPCK clear). 2386 * 2387 * Note: BI together with FE/PE means just BI. 2388 */ 2389 if (line_status & LSR_BI) { 2390#if defined(KDB) 2391 if (com->unit == comconsole) { 2392 kdb_enter(KDB_WHY_BREAK, 2393 "Line break on console"); 2394 goto cont; 2395 } 2396#endif 2397 if (com->tp == NULL 2398 || com->tp->t_iflag & IGNBRK) 2399 goto cont; 2400 } else { 2401 if (com->tp == NULL 2402 || com->tp->t_iflag & IGNPAR) 2403 goto cont; 2404 } 2405 if (com->tp->t_state & TS_CAN_BYPASS_L_RINT 2406 && (line_status & (LSR_BI | LSR_FE) 2407 || com->tp->t_iflag & INPCK)) 2408 recv_data = 0; 2409 } 2410 ++com->bytes_in; 2411 if (com->tp != NULL && 2412 com->tp->t_hotchar != 0 && recv_data == com->tp->t_hotchar) 2413 swi_sched(sio_fast_ih, 0); 2414 ioptr = com->iptr; 2415 if (ioptr >= com->ibufend) 2416 CE_RECORD(com, CE_INTERRUPT_BUF_OVERFLOW); 2417 else { 2418 if (com->tp != NULL && com->tp->t_do_timestamp) 2419 microtime(&com->tp->t_timestamp); 2420 ++com_events; 2421 swi_sched(sio_slow_ih, SWI_DELAY); 2422#if 0 /* for testing input latency vs efficiency */ 2423if (com->iptr - com->ibuf == 8) 2424 swi_sched(sio_fast_ih, 0); 2425#endif 2426 ioptr[0] = recv_data; 2427 ioptr[com->ierroff] = line_status; 2428 com->iptr = ++ioptr; 2429 if (ioptr == com->ihighwater 2430 && com->state & CS_RTS_IFLOW) 2431#ifdef PC98 2432 IS_8251(com->pc98_if_type) ? 2433 com_tiocm_bic(com, TIOCM_RTS) : 2434#endif 2435 outb(com->modem_ctl_port, 2436 com->mcr_image &= ~MCR_RTS); 2437 if (line_status & LSR_OE) 2438 CE_RECORD(com, CE_OVERRUN); 2439 } 2440cont: 2441 if (line_status & LSR_TXRDY 2442 && com->state >= (CS_BUSY | CS_TTGO | CS_ODEVREADY)) 2443 goto txrdy; 2444 2445 /* 2446 * "& 0x7F" is to avoid the gcc-1.40 generating a slow 2447 * jump from the top of the loop to here 2448 */ 2449#ifdef PC98 2450 if (IS_8251(com->pc98_if_type)) 2451 goto status_read; 2452 else 2453#endif 2454 line_status = inb(com->line_status_port) & 0x7F; 2455#ifdef PC98 2456 if (com->pc98_if_type == COM_IF_RSA98III) 2457 rsa_buf_status = inb(com->rsabase + rsa_srr); 2458#endif /* PC98 */ 2459 } 2460 2461 /* modem status change? (always check before doing output) */ 2462#ifdef PC98 2463 if (!IS_8251(com->pc98_if_type)) { 2464#endif 2465 modem_status = inb(com->modem_status_port); 2466 if (modem_status != com->last_modem_status) { 2467 /* 2468 * Schedule high level to handle DCD changes. Note 2469 * that we don't use the delta bits anywhere. Some 2470 * UARTs mess them up, and it's easy to remember the 2471 * previous bits and calculate the delta. 2472 */ 2473 com->last_modem_status = modem_status; 2474 if (!(com->state & CS_CHECKMSR)) { 2475 com_events += LOTS_OF_EVENTS; 2476 com->state |= CS_CHECKMSR; 2477 swi_sched(sio_fast_ih, 0); 2478 } 2479 2480 /* handle CTS change immediately for crisp flow ctl */ 2481 if (com->state & CS_CTS_OFLOW) { 2482 if (modem_status & MSR_CTS) 2483 com->state |= CS_ODEVREADY; 2484 else 2485 com->state &= ~CS_ODEVREADY; 2486 } 2487 } 2488#ifdef PC98 2489 } 2490#endif 2491 2492txrdy: 2493 /* output queued and everything ready? */ 2494#ifndef PC98 2495 if (line_status & LSR_TXRDY 2496 && com->state >= (CS_BUSY | CS_TTGO | CS_ODEVREADY)) { 2497#else 2498 if (((com->pc98_if_type == COM_IF_RSA98III) 2499 ? (rsa_buf_status & 0x02) 2500 : (line_status & LSR_TXRDY)) 2501 && com->state >= (CS_BUSY | CS_TTGO | CS_ODEVREADY)) { 2502#endif 2503#ifdef PC98 2504 Port_t tmp_data_port; 2505 2506 if (IS_8251(com->pc98_if_type) && 2507 com->pc98_8251fifo_enable) 2508 tmp_data_port = I8251F_data; 2509 else 2510 tmp_data_port = com->data_port; 2511#endif 2512 2513 ioptr = com->obufq.l_head; 2514 if (com->tx_fifo_size > 1 && com->unit != siotsunit) { 2515 u_int ocount; 2516 2517 ocount = com->obufq.l_tail - ioptr; 2518#ifdef PC98 2519 if (com->pc98_if_type == COM_IF_RSA98III) { 2520 rsa_buf_status = inb(com->rsabase + rsa_srr); 2521 rsa_tx_fifo_size = 1024; 2522 if (!(rsa_buf_status & 0x01)) 2523 rsa_tx_fifo_size = 2048; 2524 if (ocount > rsa_tx_fifo_size) 2525 ocount = rsa_tx_fifo_size; 2526 } else 2527#endif 2528 if (ocount > com->tx_fifo_size) 2529 ocount = com->tx_fifo_size; 2530 com->bytes_out += ocount; 2531 do 2532#ifdef PC98 2533 outb(tmp_data_port, *ioptr++); 2534#else 2535 outb(com->data_port, *ioptr++); 2536#endif 2537 while (--ocount != 0); 2538 } else { 2539#ifdef PC98 2540 outb(tmp_data_port, *ioptr++); 2541#else 2542 outb(com->data_port, *ioptr++); 2543#endif 2544 ++com->bytes_out; 2545 if (com->unit == siotsunit 2546 && siotso < sizeof siots / sizeof siots[0]) 2547 nanouptime(&siots[siotso++]); 2548 } 2549#ifdef PC98 2550 if (IS_8251(com->pc98_if_type)) 2551 if (!(pc98_check_i8251_interrupt(com) & IEN_TxFLAG)) 2552 com_int_Tx_enable(com); 2553#endif 2554 com->obufq.l_head = ioptr; 2555 if (COM_IIR_TXRDYBUG(com->flags)) 2556 int_ctl_new = int_ctl | IER_ETXRDY; 2557 if (ioptr >= com->obufq.l_tail) { 2558 struct lbq *qp; 2559 2560 qp = com->obufq.l_next; 2561 qp->l_queued = FALSE; 2562 qp = qp->l_next; 2563 if (qp != NULL) { 2564 com->obufq.l_head = qp->l_head; 2565 com->obufq.l_tail = qp->l_tail; 2566 com->obufq.l_next = qp; 2567 } else { 2568 /* output just completed */ 2569 if (COM_IIR_TXRDYBUG(com->flags)) 2570 int_ctl_new = int_ctl 2571 & ~IER_ETXRDY; 2572 com->state &= ~CS_BUSY; 2573#if defined(PC98) 2574 if (IS_8251(com->pc98_if_type) && 2575 pc98_check_i8251_interrupt(com) & IEN_TxFLAG) 2576 com_int_Tx_disable(com); 2577#endif 2578 } 2579 if (!(com->state & CS_ODONE)) { 2580 com_events += LOTS_OF_EVENTS; 2581 com->state |= CS_ODONE; 2582 /* handle at high level ASAP */ 2583 swi_sched(sio_fast_ih, 0); 2584 } 2585 } 2586#ifdef PC98 2587 if (COM_IIR_TXRDYBUG(com->flags) 2588 && int_ctl != int_ctl_new) { 2589 if (com->pc98_if_type == COM_IF_RSA98III) { 2590 int_ctl_new &= ~(IER_ETXRDY | IER_ERXRDY); 2591 outb(com->int_ctl_port, int_ctl_new); 2592 outb(com->rsabase + rsa_ier, 0x1d); 2593 } else 2594 outb(com->int_ctl_port, int_ctl_new); 2595 } 2596#else 2597 if (COM_IIR_TXRDYBUG(com->flags) 2598 && int_ctl != int_ctl_new) 2599 outb(com->int_ctl_port, int_ctl_new); 2600#endif 2601 } 2602#ifdef PC98 2603 else if (line_status & LSR_TXRDY) { 2604 if (IS_8251(com->pc98_if_type)) 2605 if (pc98_check_i8251_interrupt(com) & IEN_TxFLAG) 2606 com_int_Tx_disable(com); 2607 } 2608 if (IS_8251(com->pc98_if_type)) { 2609 if (com->pc98_8251fifo_enable) { 2610 if ((tmp = inb(I8251F_lsr)) & FLSR_RxRDY) 2611 goto more_intr; 2612 } else { 2613 if ((tmp = inb(com->sts_port)) & STS8251_RxRDY) 2614 goto more_intr; 2615 } 2616 } 2617#endif 2618 2619 /* finished? */ 2620#ifndef COM_MULTIPORT 2621#ifdef PC98 2622 if (IS_8251(com->pc98_if_type)) 2623 return; 2624#endif 2625 if ((inb(com->int_id_port) & IIR_IMASK) == IIR_NOPEND) 2626#endif /* COM_MULTIPORT */ 2627 return; 2628 } 2629} 2630 2631/* software interrupt handler for SWI_TTY */ 2632static void 2633siopoll(void *dummy) 2634{ 2635 int unit; 2636 2637 if (com_events == 0) 2638 return; 2639repeat: 2640 for (unit = 0; unit < sio_numunits; ++unit) { 2641 struct com_s *com; 2642 int incc; 2643 struct tty *tp; 2644 2645 com = com_addr(unit); 2646 if (com == NULL) 2647 continue; 2648 tp = com->tp; 2649 if (tp == NULL || com->gone) { 2650 /* 2651 * Discard any events related to never-opened or 2652 * going-away devices. 2653 */ 2654 mtx_lock_spin(&sio_lock); 2655 incc = com->iptr - com->ibuf; 2656 com->iptr = com->ibuf; 2657 if (com->state & CS_CHECKMSR) { 2658 incc += LOTS_OF_EVENTS; 2659 com->state &= ~CS_CHECKMSR; 2660 } 2661 com_events -= incc; 2662 mtx_unlock_spin(&sio_lock); 2663 continue; 2664 } 2665 if (com->iptr != com->ibuf) { 2666 mtx_lock_spin(&sio_lock); 2667 sioinput(com); 2668 mtx_unlock_spin(&sio_lock); 2669 } 2670 if (com->state & CS_CHECKMSR) { 2671 u_char delta_modem_status; 2672 2673#ifdef PC98 2674 if (!IS_8251(com->pc98_if_type)) { 2675#endif 2676 mtx_lock_spin(&sio_lock); 2677 delta_modem_status = com->last_modem_status 2678 ^ com->prev_modem_status; 2679 com->prev_modem_status = com->last_modem_status; 2680 com_events -= LOTS_OF_EVENTS; 2681 com->state &= ~CS_CHECKMSR; 2682 mtx_unlock_spin(&sio_lock); 2683 if (delta_modem_status & MSR_DCD) 2684 ttyld_modem(tp, 2685 com->prev_modem_status & MSR_DCD); 2686#ifdef PC98 2687 } 2688#endif 2689 } 2690 if (com->state & CS_ODONE) { 2691 mtx_lock_spin(&sio_lock); 2692 com_events -= LOTS_OF_EVENTS; 2693 com->state &= ~CS_ODONE; 2694 mtx_unlock_spin(&sio_lock); 2695 if (!(com->state & CS_BUSY) 2696 && !(com->extra_state & CSE_BUSYCHECK)) { 2697 timeout(siobusycheck, com, hz / 100); 2698 com->extra_state |= CSE_BUSYCHECK; 2699 } 2700 ttyld_start(tp); 2701 } 2702 if (com_events == 0) 2703 break; 2704 } 2705 if (com_events >= LOTS_OF_EVENTS) 2706 goto repeat; 2707} 2708 2709static void 2710combreak(tp, sig) 2711 struct tty *tp; 2712 int sig; 2713{ 2714 struct com_s *com; 2715 2716 com = tp->t_sc; 2717 2718#ifdef PC98 2719 if (sig) 2720 com_send_break_on(com); 2721 else 2722 com_send_break_off(com); 2723#else 2724 if (sig) 2725 sio_setreg(com, com_cfcr, com->cfcr_image |= CFCR_SBREAK); 2726 else 2727 sio_setreg(com, com_cfcr, com->cfcr_image &= ~CFCR_SBREAK); 2728#endif 2729} 2730 2731static int 2732comparam(tp, t) 2733 struct tty *tp; 2734 struct termios *t; 2735{ 2736 u_int cfcr; 2737 int cflag; 2738 struct com_s *com; 2739 u_int divisor; 2740 u_char dlbh; 2741 u_char dlbl; 2742 u_char efr_flowbits; 2743 int s; 2744#ifdef PC98 2745 u_char param = 0; 2746#endif 2747 2748 com = tp->t_sc; 2749 if (com == NULL) 2750 return (ENODEV); 2751 2752#ifdef PC98 2753 cfcr = 0; 2754 2755 if (IS_8251(com->pc98_if_type)) { 2756 if (pc98_ttspeedtab(com, t->c_ospeed, &divisor) != 0) 2757 return (EINVAL); 2758 } else { 2759#endif 2760 /* check requested parameters */ 2761 if (t->c_ispeed != (t->c_ospeed != 0 ? t->c_ospeed : tp->t_ospeed)) 2762 return (EINVAL); 2763 divisor = siodivisor(com->rclk, t->c_ispeed); 2764 if (divisor == 0) 2765 return (EINVAL); 2766#ifdef PC98 2767 } 2768#endif 2769 2770 /* parameters are OK, convert them to the com struct and the device */ 2771 s = spltty(); 2772#ifdef PC98 2773 if (IS_8251(com->pc98_if_type)) { 2774 if (t->c_ospeed == 0) 2775 com_tiocm_bic(com, TIOCM_DTR|TIOCM_RTS|TIOCM_LE); 2776 else 2777 com_tiocm_bis(com, TIOCM_DTR|TIOCM_RTS|TIOCM_LE); 2778 } else 2779#endif 2780 if (t->c_ospeed == 0) 2781 (void)commodem(tp, 0, SER_DTR); /* hang up line */ 2782 else 2783 (void)commodem(tp, SER_DTR, 0); 2784 cflag = t->c_cflag; 2785#ifdef PC98 2786 if (!IS_8251(com->pc98_if_type)) { 2787#endif 2788 switch (cflag & CSIZE) { 2789 case CS5: 2790 cfcr = CFCR_5BITS; 2791 break; 2792 case CS6: 2793 cfcr = CFCR_6BITS; 2794 break; 2795 case CS7: 2796 cfcr = CFCR_7BITS; 2797 break; 2798 default: 2799 cfcr = CFCR_8BITS; 2800 break; 2801 } 2802 if (cflag & PARENB) { 2803 cfcr |= CFCR_PENAB; 2804 if (!(cflag & PARODD)) 2805 cfcr |= CFCR_PEVEN; 2806 } 2807 if (cflag & CSTOPB) 2808 cfcr |= CFCR_STOPB; 2809 2810 if (com->hasfifo) { 2811 /* 2812 * Use a fifo trigger level low enough so that the input 2813 * latency from the fifo is less than about 16 msec and 2814 * the total latency is less than about 30 msec. These 2815 * latencies are reasonable for humans. Serial comms 2816 * protocols shouldn't expect anything better since modem 2817 * latencies are larger. 2818 * 2819 * The fifo trigger level cannot be set at RX_HIGH for high 2820 * speed connections without further work on reducing 2821 * interrupt disablement times in other parts of the system, 2822 * without producing silo overflow errors. 2823 */ 2824 com->fifo_image = com->unit == siotsunit ? 0 2825 : t->c_ispeed <= 4800 2826 ? FIFO_ENABLE : FIFO_ENABLE | FIFO_RX_MEDH; 2827#ifdef COM_ESP 2828 /* 2829 * The Hayes ESP card needs the fifo DMA mode bit set 2830 * in compatibility mode. If not, it will interrupt 2831 * for each character received. 2832 */ 2833 if (com->esp) 2834 com->fifo_image |= FIFO_DMA_MODE; 2835#endif 2836 sio_setreg(com, com_fifo, com->fifo_image); 2837 } 2838#ifdef PC98 2839 } 2840#endif 2841 2842 /* 2843 * This returns with interrupts disabled so that we can complete 2844 * the speed change atomically. Keeping interrupts disabled is 2845 * especially important while com_data is hidden. 2846 */ 2847 (void) siosetwater(com, t->c_ispeed); 2848 2849#ifdef PC98 2850 if (IS_8251(com->pc98_if_type)) 2851 com_cflag_and_speed_set(com, cflag, t->c_ospeed); 2852 else { 2853#endif 2854 sio_setreg(com, com_cfcr, cfcr | CFCR_DLAB); 2855 /* 2856 * Only set the divisor registers if they would change, since on 2857 * some 16550 incompatibles (UMC8669F), setting them while input 2858 * is arriving loses sync until data stops arriving. 2859 */ 2860 dlbl = divisor & 0xFF; 2861 if (sio_getreg(com, com_dlbl) != dlbl) 2862 sio_setreg(com, com_dlbl, dlbl); 2863 dlbh = divisor >> 8; 2864 if (sio_getreg(com, com_dlbh) != dlbh) 2865 sio_setreg(com, com_dlbh, dlbh); 2866#ifdef PC98 2867 } 2868#endif 2869 2870 efr_flowbits = 0; 2871 2872 if (cflag & CRTS_IFLOW) { 2873 com->state |= CS_RTS_IFLOW; 2874 efr_flowbits |= EFR_AUTORTS; 2875 /* 2876 * If CS_RTS_IFLOW just changed from off to on, the change 2877 * needs to be propagated to MCR_RTS. This isn't urgent, 2878 * so do it later by calling comstart() instead of repeating 2879 * a lot of code from comstart() here. 2880 */ 2881 } else if (com->state & CS_RTS_IFLOW) { 2882 com->state &= ~CS_RTS_IFLOW; 2883 /* 2884 * CS_RTS_IFLOW just changed from on to off. Force MCR_RTS 2885 * on here, since comstart() won't do it later. 2886 */ 2887#ifdef PC98 2888 if (IS_8251(com->pc98_if_type)) 2889 com_tiocm_bis(com, TIOCM_RTS); 2890 else 2891 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS); 2892#else 2893 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS); 2894#endif 2895 } 2896 2897 /* 2898 * Set up state to handle output flow control. 2899 * XXX - worth handling MDMBUF (DCD) flow control at the lowest level? 2900 * Now has 10+ msec latency, while CTS flow has 50- usec latency. 2901 */ 2902 com->state |= CS_ODEVREADY; 2903 com->state &= ~CS_CTS_OFLOW; 2904#ifdef PC98 2905 if (com->pc98_if_type == COM_IF_RSA98III) { 2906 param = inb(com->rsabase + rsa_msr); 2907 outb(com->rsabase + rsa_msr, param & 0x14); 2908 } 2909#endif 2910 if (cflag & CCTS_OFLOW) { 2911 com->state |= CS_CTS_OFLOW; 2912 efr_flowbits |= EFR_AUTOCTS; 2913#ifdef PC98 2914 if (IS_8251(com->pc98_if_type)) { 2915 if (!(pc98_get_modem_status(com) & TIOCM_CTS)) 2916 com->state &= ~CS_ODEVREADY; 2917 } else if (com->pc98_if_type == COM_IF_RSA98III) { 2918 /* Set automatic flow control mode */ 2919 outb(com->rsabase + rsa_msr, param | 0x08); 2920 } else 2921#endif 2922 if (!(com->last_modem_status & MSR_CTS)) 2923 com->state &= ~CS_ODEVREADY; 2924 } 2925 2926#ifdef PC98 2927 if (!IS_8251(com->pc98_if_type)) 2928 sio_setreg(com, com_cfcr, com->cfcr_image = cfcr); 2929#else 2930 if (com->st16650a) { 2931 sio_setreg(com, com_lcr, LCR_EFR_ENABLE); 2932 sio_setreg(com, com_efr, 2933 (sio_getreg(com, com_efr) 2934 & ~(EFR_AUTOCTS | EFR_AUTORTS)) | efr_flowbits); 2935 } 2936 sio_setreg(com, com_cfcr, com->cfcr_image = cfcr); 2937#endif 2938 2939 /* XXX shouldn't call functions while intrs are disabled. */ 2940 ttyldoptim(tp); 2941 2942 mtx_unlock_spin(&sio_lock); 2943 splx(s); 2944 comstart(tp); 2945 if (com->ibufold != NULL) { 2946 free(com->ibufold, M_DEVBUF); 2947 com->ibufold = NULL; 2948 } 2949 return (0); 2950} 2951 2952/* 2953 * This function must be called with the sio_lock mutex released and will 2954 * return with it obtained. 2955 */ 2956static int 2957siosetwater(com, speed) 2958 struct com_s *com; 2959 speed_t speed; 2960{ 2961 int cp4ticks; 2962 u_char *ibuf; 2963 int ibufsize; 2964 struct tty *tp; 2965 2966 /* 2967 * Make the buffer size large enough to handle a softtty interrupt 2968 * latency of about 2 ticks without loss of throughput or data 2969 * (about 3 ticks if input flow control is not used or not honoured, 2970 * but a bit less for CS5-CS7 modes). 2971 */ 2972 cp4ticks = speed / 10 / hz * 4; 2973 for (ibufsize = 128; ibufsize < cp4ticks;) 2974 ibufsize <<= 1; 2975#ifdef PC98 2976 if (com->pc98_if_type == COM_IF_RSA98III) 2977 ibufsize = 2048; 2978#endif 2979 if (ibufsize == com->ibufsize) { 2980 mtx_lock_spin(&sio_lock); 2981 return (0); 2982 } 2983 2984 /* 2985 * Allocate input buffer. The extra factor of 2 in the size is 2986 * to allow for an error byte for each input byte. 2987 */ 2988 ibuf = malloc(2 * ibufsize, M_DEVBUF, M_NOWAIT); 2989 if (ibuf == NULL) { 2990 mtx_lock_spin(&sio_lock); 2991 return (ENOMEM); 2992 } 2993 2994 /* Initialize non-critical variables. */ 2995 com->ibufold = com->ibuf; 2996 com->ibufsize = ibufsize; 2997 tp = com->tp; 2998 if (tp != NULL) { 2999 tp->t_ififosize = 2 * ibufsize; 3000 tp->t_ispeedwat = (speed_t)-1; 3001 tp->t_ospeedwat = (speed_t)-1; 3002 } 3003 3004 /* 3005 * Read current input buffer, if any. Continue with interrupts 3006 * disabled. 3007 */ 3008 mtx_lock_spin(&sio_lock); 3009 if (com->iptr != com->ibuf) 3010 sioinput(com); 3011 3012 /*- 3013 * Initialize critical variables, including input buffer watermarks. 3014 * The external device is asked to stop sending when the buffer 3015 * exactly reaches high water, or when the high level requests it. 3016 * The high level is notified immediately (rather than at a later 3017 * clock tick) when this watermark is reached. 3018 * The buffer size is chosen so the watermark should almost never 3019 * be reached. 3020 * The low watermark is invisibly 0 since the buffer is always 3021 * emptied all at once. 3022 */ 3023 com->iptr = com->ibuf = ibuf; 3024 com->ibufend = ibuf + ibufsize; 3025 com->ierroff = ibufsize; 3026 com->ihighwater = ibuf + 3 * ibufsize / 4; 3027 return (0); 3028} 3029 3030static void 3031comstart(tp) 3032 struct tty *tp; 3033{ 3034 struct com_s *com; 3035 int s; 3036 3037 com = tp->t_sc; 3038 if (com == NULL) 3039 return; 3040 s = spltty(); 3041 mtx_lock_spin(&sio_lock); 3042 if (tp->t_state & TS_TTSTOP) 3043 com->state &= ~CS_TTGO; 3044 else 3045 com->state |= CS_TTGO; 3046 if (tp->t_state & TS_TBLOCK) { 3047#ifdef PC98 3048 if (IS_8251(com->pc98_if_type)) { 3049 if ((com_tiocm_get(com) & TIOCM_RTS) && 3050 (com->state & CS_RTS_IFLOW)) 3051 com_tiocm_bic(com, TIOCM_RTS); 3052 } else { 3053 if ((com->mcr_image & MCR_RTS) && 3054 (com->state & CS_RTS_IFLOW)) 3055 outb(com->modem_ctl_port, com->mcr_image &= ~MCR_RTS); 3056 } 3057#else 3058 if (com->mcr_image & MCR_RTS && com->state & CS_RTS_IFLOW) 3059 outb(com->modem_ctl_port, com->mcr_image &= ~MCR_RTS); 3060#endif 3061 } else { 3062#ifdef PC98 3063 if (IS_8251(com->pc98_if_type)) { 3064 if (!(com_tiocm_get(com) & TIOCM_RTS) && 3065 com->iptr < com->ihighwater && 3066 com->state & CS_RTS_IFLOW) 3067 com_tiocm_bis(com, TIOCM_RTS); 3068 } else { 3069 if (!(com->mcr_image & MCR_RTS) && 3070 com->iptr < com->ihighwater && 3071 com->state & CS_RTS_IFLOW) 3072 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS); 3073 } 3074#else 3075 if (!(com->mcr_image & MCR_RTS) && com->iptr < com->ihighwater 3076 && com->state & CS_RTS_IFLOW) 3077 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS); 3078#endif 3079 } 3080 mtx_unlock_spin(&sio_lock); 3081 if (tp->t_state & (TS_TIMEOUT | TS_TTSTOP)) { 3082 ttwwakeup(tp); 3083 splx(s); 3084 return; 3085 } 3086 if (tp->t_outq.c_cc != 0) { 3087 struct lbq *qp; 3088 struct lbq *next; 3089 3090 if (!com->obufs[0].l_queued) { 3091 com->obufs[0].l_tail 3092 = com->obuf1 + q_to_b(&tp->t_outq, com->obuf1, 3093#ifdef PC98 3094 com->obufsize); 3095#else 3096 sizeof com->obuf1); 3097#endif 3098 com->obufs[0].l_next = NULL; 3099 com->obufs[0].l_queued = TRUE; 3100 mtx_lock_spin(&sio_lock); 3101 if (com->state & CS_BUSY) { 3102 qp = com->obufq.l_next; 3103 while ((next = qp->l_next) != NULL) 3104 qp = next; 3105 qp->l_next = &com->obufs[0]; 3106 } else { 3107 com->obufq.l_head = com->obufs[0].l_head; 3108 com->obufq.l_tail = com->obufs[0].l_tail; 3109 com->obufq.l_next = &com->obufs[0]; 3110 com->state |= CS_BUSY; 3111 } 3112 mtx_unlock_spin(&sio_lock); 3113 } 3114 if (tp->t_outq.c_cc != 0 && !com->obufs[1].l_queued) { 3115 com->obufs[1].l_tail 3116 = com->obuf2 + q_to_b(&tp->t_outq, com->obuf2, 3117#ifdef PC98 3118 com->obufsize); 3119#else 3120 sizeof com->obuf2); 3121#endif 3122 com->obufs[1].l_next = NULL; 3123 com->obufs[1].l_queued = TRUE; 3124 mtx_lock_spin(&sio_lock); 3125 if (com->state & CS_BUSY) { 3126 qp = com->obufq.l_next; 3127 while ((next = qp->l_next) != NULL) 3128 qp = next; 3129 qp->l_next = &com->obufs[1]; 3130 } else { 3131 com->obufq.l_head = com->obufs[1].l_head; 3132 com->obufq.l_tail = com->obufs[1].l_tail; 3133 com->obufq.l_next = &com->obufs[1]; 3134 com->state |= CS_BUSY; 3135 } 3136 mtx_unlock_spin(&sio_lock); 3137 } 3138 tp->t_state |= TS_BUSY; 3139 } 3140 mtx_lock_spin(&sio_lock); 3141 if (com->state >= (CS_BUSY | CS_TTGO)) 3142 siointr1(com); /* fake interrupt to start output */ 3143 mtx_unlock_spin(&sio_lock); 3144 ttwwakeup(tp); 3145 splx(s); 3146} 3147 3148static void 3149comstop(tp, rw) 3150 struct tty *tp; 3151 int rw; 3152{ 3153 struct com_s *com; 3154#ifdef PC98 3155 int rsa98_tmp = 0; 3156#endif 3157 3158 com = tp->t_sc; 3159 if (com == NULL || com->gone) 3160 return; 3161 mtx_lock_spin(&sio_lock); 3162 if (rw & FWRITE) { 3163#ifdef PC98 3164 if (!IS_8251(com->pc98_if_type)) { 3165#endif 3166 if (com->hasfifo) 3167#ifdef COM_ESP 3168 /* XXX avoid h/w bug. */ 3169 if (!com->esp) 3170#endif 3171 sio_setreg(com, com_fifo, 3172 FIFO_XMT_RST | com->fifo_image); 3173#ifdef PC98 3174 if (com->pc98_if_type == COM_IF_RSA98III) 3175 for (rsa98_tmp = 0; rsa98_tmp < 2048; rsa98_tmp++) 3176 sio_setreg(com, com_fifo, 3177 FIFO_XMT_RST | com->fifo_image); 3178 } 3179#endif 3180 com->obufs[0].l_queued = FALSE; 3181 com->obufs[1].l_queued = FALSE; 3182 if (com->state & CS_ODONE) 3183 com_events -= LOTS_OF_EVENTS; 3184 com->state &= ~(CS_ODONE | CS_BUSY); 3185 com->tp->t_state &= ~TS_BUSY; 3186 } 3187 if (rw & FREAD) { 3188#ifdef PC98 3189 if (!IS_8251(com->pc98_if_type)) { 3190 if (com->pc98_if_type == COM_IF_RSA98III) 3191 for (rsa98_tmp = 0; rsa98_tmp < 2048; rsa98_tmp++) 3192 sio_getreg(com, com_data); 3193#endif 3194 if (com->hasfifo) 3195#ifdef COM_ESP 3196 /* XXX avoid h/w bug. */ 3197 if (!com->esp) 3198#endif 3199 sio_setreg(com, com_fifo, 3200 FIFO_RCV_RST | com->fifo_image); 3201#ifdef PC98 3202 } 3203#endif 3204 com_events -= (com->iptr - com->ibuf); 3205 com->iptr = com->ibuf; 3206 } 3207 mtx_unlock_spin(&sio_lock); 3208 comstart(tp); 3209} 3210 3211static int 3212commodem(struct tty *tp, int sigon, int sigoff) 3213{ 3214 struct com_s *com; 3215 int bitand, bitor, msr; 3216#ifdef PC98 3217 int clr, set; 3218#endif 3219 3220 com = tp->t_sc; 3221 if (com->gone) 3222 return(0); 3223 if (sigon != 0 || sigoff != 0) { 3224#ifdef PC98 3225 if (IS_8251(com->pc98_if_type)) { 3226 bitand = bitor = 0; 3227 clr = set = 0; 3228 if (sigoff & SER_DTR) { 3229 bitand |= TIOCM_DTR; 3230 clr |= CMD8251_DTR; 3231 } 3232 if (sigoff & SER_RTS) { 3233 bitand |= TIOCM_RTS; 3234 clr |= CMD8251_RxEN | CMD8251_RTS; 3235 } 3236 if (sigon & SER_DTR) { 3237 bitor |= TIOCM_DTR; 3238 set |= CMD8251_TxEN | CMD8251_RxEN | 3239 CMD8251_DTR; 3240 } 3241 if (sigon & SER_RTS) { 3242 bitor |= TIOCM_RTS; 3243 set |= CMD8251_TxEN | CMD8251_RxEN | 3244 CMD8251_RTS; 3245 } 3246 bitand = ~bitand; 3247 mtx_lock_spin(&sio_lock); 3248 com->pc98_prev_modem_status &= bitand; 3249 com->pc98_prev_modem_status |= bitor; 3250 pc98_i8251_clear_or_cmd(com, clr, set); 3251 mtx_unlock_spin(&sio_lock); 3252 return (0); 3253 } else { 3254#endif 3255 bitand = bitor = 0; 3256 if (sigoff & SER_DTR) 3257 bitand |= MCR_DTR; 3258 if (sigoff & SER_RTS) 3259 bitand |= MCR_RTS; 3260 if (sigon & SER_DTR) 3261 bitor |= MCR_DTR; 3262 if (sigon & SER_RTS) 3263 bitor |= MCR_RTS; 3264 bitand = ~bitand; 3265 mtx_lock_spin(&sio_lock); 3266 com->mcr_image &= bitand; 3267 com->mcr_image |= bitor; 3268 outb(com->modem_ctl_port, com->mcr_image); 3269 mtx_unlock_spin(&sio_lock); 3270 return (0); 3271#ifdef PC98 3272 } 3273#endif 3274 } else { 3275#ifdef PC98 3276 if (IS_8251(com->pc98_if_type)) 3277 return (com_tiocm_get(com)); 3278 else { 3279#endif 3280 bitor = 0; 3281 if (com->mcr_image & MCR_DTR) 3282 bitor |= SER_DTR; 3283 if (com->mcr_image & MCR_RTS) 3284 bitor |= SER_RTS; 3285 msr = com->prev_modem_status; 3286 if (msr & MSR_CTS) 3287 bitor |= SER_CTS; 3288 if (msr & MSR_DCD) 3289 bitor |= SER_DCD; 3290 if (msr & MSR_DSR) 3291 bitor |= SER_DSR; 3292 if (msr & MSR_DSR) 3293 bitor |= SER_DSR; 3294 if (msr & (MSR_RI | MSR_TERI)) 3295 bitor |= SER_RI; 3296 return (bitor); 3297#ifdef PC98 3298 } 3299#endif 3300 } 3301} 3302 3303static void 3304siosettimeout() 3305{ 3306 struct com_s *com; 3307 bool_t someopen; 3308 int unit; 3309 3310 /* 3311 * Set our timeout period to 1 second if no polled devices are open. 3312 * Otherwise set it to max(1/200, 1/hz). 3313 * Enable timeouts iff some device is open. 3314 */ 3315 untimeout(comwakeup, (void *)NULL, sio_timeout_handle); 3316 sio_timeout = hz; 3317 someopen = FALSE; 3318 for (unit = 0; unit < sio_numunits; ++unit) { 3319 com = com_addr(unit); 3320 if (com != NULL && com->tp != NULL 3321 && com->tp->t_state & TS_ISOPEN && !com->gone) { 3322 someopen = TRUE; 3323 if (com->poll || com->poll_output) { 3324 sio_timeout = hz > 200 ? hz / 200 : 1; 3325 break; 3326 } 3327 } 3328 } 3329 if (someopen) { 3330 sio_timeouts_until_log = hz / sio_timeout; 3331 sio_timeout_handle = timeout(comwakeup, (void *)NULL, 3332 sio_timeout); 3333 } else { 3334 /* Flush error messages, if any. */ 3335 sio_timeouts_until_log = 1; 3336 comwakeup((void *)NULL); 3337 untimeout(comwakeup, (void *)NULL, sio_timeout_handle); 3338 } 3339} 3340 3341static void 3342comwakeup(chan) 3343 void *chan; 3344{ 3345 struct com_s *com; 3346 int unit; 3347 3348 sio_timeout_handle = timeout(comwakeup, (void *)NULL, sio_timeout); 3349 3350 /* 3351 * Recover from lost output interrupts. 3352 * Poll any lines that don't use interrupts. 3353 */ 3354 for (unit = 0; unit < sio_numunits; ++unit) { 3355 com = com_addr(unit); 3356 if (com != NULL && !com->gone 3357 && (com->state >= (CS_BUSY | CS_TTGO) || com->poll)) { 3358 mtx_lock_spin(&sio_lock); 3359 siointr1(com); 3360 mtx_unlock_spin(&sio_lock); 3361 } 3362 } 3363 3364 /* 3365 * Check for and log errors, but not too often. 3366 */ 3367 if (--sio_timeouts_until_log > 0) 3368 return; 3369 sio_timeouts_until_log = hz / sio_timeout; 3370 for (unit = 0; unit < sio_numunits; ++unit) { 3371 int errnum; 3372 3373 com = com_addr(unit); 3374 if (com == NULL) 3375 continue; 3376 if (com->gone) 3377 continue; 3378 for (errnum = 0; errnum < CE_NTYPES; ++errnum) { 3379 u_int delta; 3380 u_long total; 3381 3382 mtx_lock_spin(&sio_lock); 3383 delta = com->delta_error_counts[errnum]; 3384 com->delta_error_counts[errnum] = 0; 3385 mtx_unlock_spin(&sio_lock); 3386 if (delta == 0) 3387 continue; 3388 total = com->error_counts[errnum] += delta; 3389 log(LOG_ERR, "sio%d: %u more %s%s (total %lu)\n", 3390 unit, delta, error_desc[errnum], 3391 delta == 1 ? "" : "s", total); 3392 } 3393 } 3394} 3395 3396#ifdef PC98 3397/* commint is called when modem control line changes */ 3398static void 3399commint(struct cdev *dev) 3400{ 3401 register struct tty *tp; 3402 int stat,delta; 3403 struct com_s *com; 3404 3405 com = dev->si_drv1; 3406 tp = com->tp; 3407 3408 stat = com_tiocm_get(com); 3409 delta = com_tiocm_get_delta(com); 3410 3411 if (com->state & CS_CTS_OFLOW) { 3412 if (stat & TIOCM_CTS) 3413 com->state |= CS_ODEVREADY; 3414 else 3415 com->state &= ~CS_ODEVREADY; 3416 } 3417 if ((delta & TIOCM_CAR) && (ISCALLOUT(dev)) == 0) { 3418 if (stat & TIOCM_CAR ) 3419 (void)ttyld_modem(tp, 1); 3420 else if (ttyld_modem(tp, 0) == 0) { 3421 /* negate DTR, RTS */ 3422 com_tiocm_bic(com, (tp->t_cflag & HUPCL) ? 3423 TIOCM_DTR|TIOCM_RTS|TIOCM_LE : TIOCM_LE ); 3424 /* disable IENABLE */ 3425 com_int_TxRx_disable( com ); 3426 } 3427 } 3428} 3429#endif 3430 3431/* 3432 * Following are all routines needed for SIO to act as console 3433 */ 3434struct siocnstate { 3435 u_char dlbl; 3436 u_char dlbh; 3437 u_char ier; 3438 u_char cfcr; 3439 u_char mcr; 3440}; 3441 3442/* 3443 * This is a function in order to not replicate "ttyd%d" more 3444 * places than absolutely necessary. 3445 */ 3446static void 3447siocnset(struct consdev *cd, int unit) 3448{ 3449 3450 cd->cn_unit = unit; 3451 sprintf(cd->cn_name, "ttyd%d", unit); 3452} 3453 3454static speed_t siocngetspeed(Port_t, u_long rclk); 3455static void siocnclose(struct siocnstate *sp, Port_t iobase); 3456static void siocnopen(struct siocnstate *sp, Port_t iobase, int speed); 3457static void siocntxwait(Port_t iobase); 3458 3459static cn_probe_t sio_cnprobe; 3460static cn_init_t sio_cninit; 3461static cn_term_t sio_cnterm; 3462static cn_getc_t sio_cngetc; 3463static cn_putc_t sio_cnputc; 3464 3465CONSOLE_DRIVER(sio); 3466 3467static void 3468siocntxwait(iobase) 3469 Port_t iobase; 3470{ 3471 int timo; 3472 3473 /* 3474 * Wait for any pending transmission to finish. Required to avoid 3475 * the UART lockup bug when the speed is changed, and for normal 3476 * transmits. 3477 */ 3478 timo = 100000; 3479 while ((inb(iobase + com_lsr) & (LSR_TSRE | LSR_TXRDY)) 3480 != (LSR_TSRE | LSR_TXRDY) && --timo != 0) 3481 ; 3482} 3483 3484/* 3485 * Read the serial port specified and try to figure out what speed 3486 * it's currently running at. We're assuming the serial port has 3487 * been initialized and is basicly idle. This routine is only intended 3488 * to be run at system startup. 3489 * 3490 * If the value read from the serial port doesn't make sense, return 0. 3491 */ 3492 3493static speed_t 3494siocngetspeed(iobase, rclk) 3495 Port_t iobase; 3496 u_long rclk; 3497{ 3498 u_int divisor; 3499 u_char dlbh; 3500 u_char dlbl; 3501 u_char cfcr; 3502 3503 cfcr = inb(iobase + com_cfcr); 3504 outb(iobase + com_cfcr, CFCR_DLAB | cfcr); 3505 3506 dlbl = inb(iobase + com_dlbl); 3507 dlbh = inb(iobase + com_dlbh); 3508 3509 outb(iobase + com_cfcr, cfcr); 3510 3511 divisor = dlbh << 8 | dlbl; 3512 3513 /* XXX there should be more sanity checking. */ 3514 if (divisor == 0) 3515 return (CONSPEED); 3516 return (rclk / (16UL * divisor)); 3517} 3518 3519static void 3520siocnopen(sp, iobase, speed) 3521 struct siocnstate *sp; 3522 Port_t iobase; 3523 int speed; 3524{ 3525 u_int divisor; 3526 u_char dlbh; 3527 u_char dlbl; 3528 3529 /* 3530 * Save all the device control registers except the fifo register 3531 * and set our default ones (cs8 -parenb speed=comdefaultrate). 3532 * We can't save the fifo register since it is read-only. 3533 */ 3534 sp->ier = inb(iobase + com_ier); 3535 outb(iobase + com_ier, 0); /* spltty() doesn't stop siointr() */ 3536 siocntxwait(iobase); 3537 sp->cfcr = inb(iobase + com_cfcr); 3538 outb(iobase + com_cfcr, CFCR_DLAB | CFCR_8BITS); 3539 sp->dlbl = inb(iobase + com_dlbl); 3540 sp->dlbh = inb(iobase + com_dlbh); 3541 /* 3542 * Only set the divisor registers if they would change, since on 3543 * some 16550 incompatibles (Startech), setting them clears the 3544 * data input register. This also reduces the effects of the 3545 * UMC8669F bug. 3546 */ 3547 divisor = siodivisor(comdefaultrclk, speed); 3548 dlbl = divisor & 0xFF; 3549 if (sp->dlbl != dlbl) 3550 outb(iobase + com_dlbl, dlbl); 3551 dlbh = divisor >> 8; 3552 if (sp->dlbh != dlbh) 3553 outb(iobase + com_dlbh, dlbh); 3554 outb(iobase + com_cfcr, CFCR_8BITS); 3555 sp->mcr = inb(iobase + com_mcr); 3556 /* 3557 * We don't want interrupts, but must be careful not to "disable" 3558 * them by clearing the MCR_IENABLE bit, since that might cause 3559 * an interrupt by floating the IRQ line. 3560 */ 3561 outb(iobase + com_mcr, (sp->mcr & MCR_IENABLE) | MCR_DTR | MCR_RTS); 3562} 3563 3564static void 3565siocnclose(sp, iobase) 3566 struct siocnstate *sp; 3567 Port_t iobase; 3568{ 3569 /* 3570 * Restore the device control registers. 3571 */ 3572 siocntxwait(iobase); 3573 outb(iobase + com_cfcr, CFCR_DLAB | CFCR_8BITS); 3574 if (sp->dlbl != inb(iobase + com_dlbl)) 3575 outb(iobase + com_dlbl, sp->dlbl); 3576 if (sp->dlbh != inb(iobase + com_dlbh)) 3577 outb(iobase + com_dlbh, sp->dlbh); 3578 outb(iobase + com_cfcr, sp->cfcr); 3579 /* 3580 * XXX damp oscillations of MCR_DTR and MCR_RTS by not restoring them. 3581 */ 3582 outb(iobase + com_mcr, sp->mcr | MCR_DTR | MCR_RTS); 3583 outb(iobase + com_ier, sp->ier); 3584} 3585 3586static void 3587sio_cnprobe(cp) 3588 struct consdev *cp; 3589{ 3590 speed_t boot_speed; 3591 u_char cfcr; 3592 u_int divisor; 3593 int s, unit; 3594 struct siocnstate sp; 3595 3596 /* 3597 * Find our first enabled console, if any. If it is a high-level 3598 * console device, then initialize it and return successfully. 3599 * If it is a low-level console device, then initialize it and 3600 * return unsuccessfully. It must be initialized in both cases 3601 * for early use by console drivers and debuggers. Initializing 3602 * the hardware is not necessary in all cases, since the i/o 3603 * routines initialize it on the fly, but it is necessary if 3604 * input might arrive while the hardware is switched back to an 3605 * uninitialized state. We can't handle multiple console devices 3606 * yet because our low-level routines don't take a device arg. 3607 * We trust the user to set the console flags properly so that we 3608 * don't need to probe. 3609 */ 3610 cp->cn_pri = CN_DEAD; 3611 3612 for (unit = 0; unit < 16; unit++) { /* XXX need to know how many */ 3613 int flags; 3614 3615 if (resource_disabled("sio", unit)) 3616 continue; 3617 if (resource_int_value("sio", unit, "flags", &flags)) 3618 continue; 3619 if (COM_CONSOLE(flags) || COM_DEBUGGER(flags)) { 3620 int port; 3621 Port_t iobase; 3622 3623 if (resource_int_value("sio", unit, "port", &port)) 3624 continue; 3625 iobase = port; 3626 s = spltty(); 3627 if ((boothowto & RB_SERIAL) && COM_CONSOLE(flags)) { 3628 boot_speed = 3629 siocngetspeed(iobase, comdefaultrclk); 3630 if (boot_speed) 3631 comdefaultrate = boot_speed; 3632 } 3633 3634 /* 3635 * Initialize the divisor latch. We can't rely on 3636 * siocnopen() to do this the first time, since it 3637 * avoids writing to the latch if the latch appears 3638 * to have the correct value. Also, if we didn't 3639 * just read the speed from the hardware, then we 3640 * need to set the speed in hardware so that 3641 * switching it later is null. 3642 */ 3643 cfcr = inb(iobase + com_cfcr); 3644 outb(iobase + com_cfcr, CFCR_DLAB | cfcr); 3645 divisor = siodivisor(comdefaultrclk, comdefaultrate); 3646 outb(iobase + com_dlbl, divisor & 0xff); 3647 outb(iobase + com_dlbh, divisor >> 8); 3648 outb(iobase + com_cfcr, cfcr); 3649 3650 siocnopen(&sp, iobase, comdefaultrate); 3651 3652 splx(s); 3653 if (COM_CONSOLE(flags) && !COM_LLCONSOLE(flags)) { 3654 siocnset(cp, unit); 3655 cp->cn_pri = COM_FORCECONSOLE(flags) 3656 || boothowto & RB_SERIAL 3657 ? CN_REMOTE : CN_NORMAL; 3658 siocniobase = iobase; 3659 siocnunit = unit; 3660 } 3661#ifdef GDB 3662 if (COM_DEBUGGER(flags)) 3663 siogdbiobase = iobase; 3664#endif 3665 } 3666 } 3667} 3668 3669static void 3670sio_cninit(cp) 3671 struct consdev *cp; 3672{ 3673 comconsole = cp->cn_unit; 3674} 3675 3676static void 3677sio_cnterm(cp) 3678 struct consdev *cp; 3679{ 3680 comconsole = -1; 3681} 3682 3683static int 3684sio_cngetc(struct consdev *cd) 3685{ 3686 int c; 3687 Port_t iobase; 3688 int s; 3689 struct siocnstate sp; 3690 speed_t speed; 3691 3692 if (cd != NULL && cd->cn_unit == siocnunit) { 3693 iobase = siocniobase; 3694 speed = comdefaultrate; 3695 } else { 3696#ifdef GDB 3697 iobase = siogdbiobase; 3698 speed = gdbdefaultrate; 3699#else 3700 return (-1); 3701#endif 3702 } 3703 s = spltty(); 3704 siocnopen(&sp, iobase, speed); 3705 if (inb(iobase + com_lsr) & LSR_RXRDY) 3706 c = inb(iobase + com_data); 3707 else 3708 c = -1; 3709 siocnclose(&sp, iobase); 3710 splx(s); 3711 return (c); 3712} 3713 3714static void 3715sio_cnputc(struct consdev *cd, int c) 3716{ 3717 int need_unlock; 3718 int s; 3719 struct siocnstate sp; 3720 Port_t iobase; 3721 speed_t speed; 3722 3723 if (cd != NULL && cd->cn_unit == siocnunit) { 3724 iobase = siocniobase; 3725 speed = comdefaultrate; 3726 } else { 3727#ifdef GDB 3728 iobase = siogdbiobase; 3729 speed = gdbdefaultrate; 3730#else 3731 return; 3732#endif 3733 } 3734 s = spltty(); 3735 need_unlock = 0; 3736 if (!kdb_active && sio_inited == 2 && !mtx_owned(&sio_lock)) { 3737 mtx_lock_spin(&sio_lock); 3738 need_unlock = 1; 3739 } 3740 siocnopen(&sp, iobase, speed); 3741 siocntxwait(iobase); 3742 outb(iobase + com_data, c); 3743 siocnclose(&sp, iobase); 3744 if (need_unlock) 3745 mtx_unlock_spin(&sio_lock); 3746 splx(s); 3747} 3748 3749/* 3750 * Remote gdb(1) support. 3751 */ 3752 3753#if defined(GDB) 3754 3755#include <gdb/gdb.h> 3756 3757static gdb_probe_f siogdbprobe; 3758static gdb_init_f siogdbinit; 3759static gdb_term_f siogdbterm; 3760static gdb_getc_f siogdbgetc; 3761static gdb_putc_f siogdbputc; 3762 3763GDB_DBGPORT(sio, siogdbprobe, siogdbinit, siogdbterm, siogdbgetc, siogdbputc); 3764 3765static int 3766siogdbprobe(void) 3767{ 3768 return ((siogdbiobase != 0) ? 0 : -1); 3769} 3770 3771static void 3772siogdbinit(void) 3773{ 3774} 3775 3776static void 3777siogdbterm(void) 3778{ 3779} 3780 3781static void 3782siogdbputc(int c) 3783{ 3784 sio_cnputc(NULL, c); 3785} 3786 3787static int 3788siogdbgetc(void) 3789{ 3790 return (sio_cngetc(NULL)); 3791} 3792 3793#endif 3794 3795#ifdef PC98 3796/* 3797 * pc98 local function 3798 */ 3799static void 3800com_tiocm_bis(struct com_s *com, int msr) 3801{ 3802 int s; 3803 int tmp = 0; 3804 3805 s=spltty(); 3806 com->pc98_prev_modem_status |= ( msr & (TIOCM_LE|TIOCM_DTR|TIOCM_RTS) ); 3807 tmp |= CMD8251_TxEN|CMD8251_RxEN; 3808 if ( msr & TIOCM_DTR ) tmp |= CMD8251_DTR; 3809 if ( msr & TIOCM_RTS ) tmp |= CMD8251_RTS; 3810 3811 pc98_i8251_or_cmd( com, tmp ); 3812 splx(s); 3813} 3814 3815static void 3816com_tiocm_bic(struct com_s *com, int msr) 3817{ 3818 int s; 3819 int tmp = msr; 3820 3821 s=spltty(); 3822 com->pc98_prev_modem_status &= ~( msr & (TIOCM_LE|TIOCM_DTR|TIOCM_RTS) ); 3823 if ( msr & TIOCM_DTR ) tmp |= CMD8251_DTR; 3824 if ( msr & TIOCM_RTS ) tmp |= CMD8251_RTS; 3825 3826 pc98_i8251_clear_cmd( com, tmp ); 3827 splx(s); 3828} 3829 3830static int 3831com_tiocm_get(struct com_s *com) 3832{ 3833 return( com->pc98_prev_modem_status ); 3834} 3835 3836static int 3837com_tiocm_get_delta(struct com_s *com) 3838{ 3839 int tmp; 3840 3841 tmp = com->pc98_modem_delta; 3842 com->pc98_modem_delta = 0; 3843 return( tmp ); 3844} 3845 3846/* convert to TIOCM_?? ( ioctl.h ) */ 3847static int 3848pc98_get_modem_status(struct com_s *com) 3849{ 3850 register int msr; 3851 3852 msr = com->pc98_prev_modem_status 3853 & ~(TIOCM_CAR|TIOCM_RI|TIOCM_DSR|TIOCM_CTS); 3854 if (com->pc98_8251fifo_enable) { 3855 int stat2; 3856 3857 stat2 = inb(I8251F_msr); 3858 if ( stat2 & MSR_DCD ) msr |= TIOCM_CAR; 3859 if ( stat2 & MSR_RI ) msr |= TIOCM_RI; 3860 if ( stat2 & MSR_DSR ) msr |= TIOCM_DSR; 3861 if ( stat2 & MSR_CTS ) msr |= TIOCM_CTS; 3862#if COM_CARRIER_DETECT_EMULATE 3863 if ( msr & (TIOCM_DSR|TIOCM_CTS) ) { 3864 msr |= TIOCM_CAR; 3865 } 3866#endif 3867 } else { 3868 int stat, stat2; 3869 3870 stat = inb(com->sts_port); 3871 stat2 = inb(com->in_modem_port); 3872 if ( !(stat2 & CICSCD_CD) ) msr |= TIOCM_CAR; 3873 if ( !(stat2 & CICSCD_CI) ) msr |= TIOCM_RI; 3874 if ( stat & STS8251_DSR ) msr |= TIOCM_DSR; 3875 if ( !(stat2 & CICSCD_CS) ) msr |= TIOCM_CTS; 3876#if COM_CARRIER_DETECT_EMULATE 3877 if ( msr & (TIOCM_DSR|TIOCM_CTS) ) { 3878 msr |= TIOCM_CAR; 3879 } 3880#endif 3881 } 3882 return(msr); 3883} 3884 3885static void 3886pc98_check_msr(void* chan) 3887{ 3888 int msr, delta; 3889 int s; 3890 register struct tty *tp; 3891 struct com_s *com; 3892 struct cdev *dev; 3893 3894 dev=(struct cdev *)chan; 3895 com = dev->si_drv1; 3896 tp = dev->si_tty; 3897 3898 s = spltty(); 3899 msr = pc98_get_modem_status(com); 3900 /* make change flag */ 3901 delta = msr ^ com->pc98_prev_modem_status; 3902 if ( delta & TIOCM_CAR ) { 3903 if ( com->modem_car_chg_timer ) { 3904 if ( -- com->modem_car_chg_timer ) 3905 msr ^= TIOCM_CAR; 3906 } else { 3907 if ((com->modem_car_chg_timer = (msr & TIOCM_CAR) ? 3908 DCD_ON_RECOGNITION : DCD_OFF_TOLERANCE) != 0) 3909 msr ^= TIOCM_CAR; 3910 } 3911 } else 3912 com->modem_car_chg_timer = 0; 3913 delta = ( msr ^ com->pc98_prev_modem_status ) & 3914 (TIOCM_CAR|TIOCM_RI|TIOCM_DSR|TIOCM_CTS); 3915 com->pc98_prev_modem_status = msr; 3916 delta = ( com->pc98_modem_delta |= delta ); 3917 splx(s); 3918 if ( com->modem_checking || (tp->t_state & (TS_ISOPEN)) ) { 3919 if ( delta ) { 3920 commint(dev); 3921 } 3922 timeout(pc98_check_msr, (caddr_t)dev, 3923 PC98_CHECK_MODEM_INTERVAL); 3924 } else { 3925 com->modem_checking = 0; 3926 } 3927} 3928 3929static void 3930pc98_msrint_start(struct cdev *dev) 3931{ 3932 struct com_s *com; 3933 int s = spltty(); 3934 3935 com = dev->si_drv1; 3936 /* modem control line check routine envoke interval is 1/10 sec */ 3937 if ( com->modem_checking == 0 ) { 3938 com->pc98_prev_modem_status = pc98_get_modem_status(com); 3939 com->pc98_modem_delta = 0; 3940 timeout(pc98_check_msr, (caddr_t)dev, 3941 PC98_CHECK_MODEM_INTERVAL); 3942 com->modem_checking = 1; 3943 } 3944 splx(s); 3945} 3946 3947static void 3948pc98_disable_i8251_interrupt(struct com_s *com, int mod) 3949{ 3950 /* disable interrupt */ 3951 register int tmp; 3952 3953 mod |= ~(IEN_Tx|IEN_TxEMP|IEN_Rx); 3954 COM_INT_DISABLE 3955 tmp = inb( com->intr_ctrl_port ) & ~(IEN_Tx|IEN_TxEMP|IEN_Rx); 3956 outb( com->intr_ctrl_port, (com->intr_enable&=~mod) | tmp ); 3957 COM_INT_ENABLE 3958} 3959 3960static void 3961pc98_enable_i8251_interrupt(struct com_s *com, int mod) 3962{ 3963 register int tmp; 3964 3965 COM_INT_DISABLE 3966 tmp = inb( com->intr_ctrl_port ) & ~(IEN_Tx|IEN_TxEMP|IEN_Rx); 3967 outb( com->intr_ctrl_port, (com->intr_enable|=mod) | tmp ); 3968 COM_INT_ENABLE 3969} 3970 3971static int 3972pc98_check_i8251_interrupt(struct com_s *com) 3973{ 3974 return ( com->intr_enable & 0x07 ); 3975} 3976 3977static void 3978pc98_i8251_clear_cmd(struct com_s *com, int x) 3979{ 3980 int tmp; 3981 3982 COM_INT_DISABLE 3983 tmp = com->pc98_prev_siocmd & ~(x); 3984 if (com->pc98_8251fifo_enable) 3985 outb(I8251F_fcr, 0); 3986 outb(com->cmd_port, tmp); 3987 com->pc98_prev_siocmd = tmp & ~(CMD8251_ER|CMD8251_RESET|CMD8251_EH); 3988 if (com->pc98_8251fifo_enable) 3989 outb(I8251F_fcr, FIFO_ENABLE); 3990 COM_INT_ENABLE 3991} 3992 3993static void 3994pc98_i8251_or_cmd(struct com_s *com, int x) 3995{ 3996 int tmp; 3997 3998 COM_INT_DISABLE 3999 if (com->pc98_8251fifo_enable) 4000 outb(I8251F_fcr, 0); 4001 tmp = com->pc98_prev_siocmd | (x); 4002 outb(com->cmd_port, tmp); 4003 com->pc98_prev_siocmd = tmp & ~(CMD8251_ER|CMD8251_RESET|CMD8251_EH); 4004 if (com->pc98_8251fifo_enable) 4005 outb(I8251F_fcr, FIFO_ENABLE); 4006 COM_INT_ENABLE 4007} 4008 4009static void 4010pc98_i8251_set_cmd(struct com_s *com, int x) 4011{ 4012 int tmp; 4013 4014 COM_INT_DISABLE 4015 if (com->pc98_8251fifo_enable) 4016 outb(I8251F_fcr, 0); 4017 tmp = (x); 4018 outb(com->cmd_port, tmp); 4019 com->pc98_prev_siocmd = tmp & ~(CMD8251_ER|CMD8251_RESET|CMD8251_EH); 4020 if (com->pc98_8251fifo_enable) 4021 outb(I8251F_fcr, FIFO_ENABLE); 4022 COM_INT_ENABLE 4023} 4024 4025static void 4026pc98_i8251_clear_or_cmd(struct com_s *com, int clr, int x) 4027{ 4028 int tmp; 4029 COM_INT_DISABLE 4030 if (com->pc98_8251fifo_enable) 4031 outb(I8251F_fcr, 0); 4032 tmp = com->pc98_prev_siocmd & ~(clr); 4033 tmp |= (x); 4034 outb(com->cmd_port, tmp); 4035 com->pc98_prev_siocmd = tmp & ~(CMD8251_ER|CMD8251_RESET|CMD8251_EH); 4036 if (com->pc98_8251fifo_enable) 4037 outb(I8251F_fcr, FIFO_ENABLE); 4038 COM_INT_ENABLE 4039} 4040 4041static int 4042pc98_i8251_get_cmd(struct com_s *com) 4043{ 4044 return com->pc98_prev_siocmd; 4045} 4046 4047static int 4048pc98_i8251_get_mod(struct com_s *com) 4049{ 4050 return com->pc98_prev_siomod; 4051} 4052 4053static void 4054pc98_i8251_reset(struct com_s *com, int mode, int command) 4055{ 4056 if (com->pc98_8251fifo_enable) 4057 outb(I8251F_fcr, 0); 4058 outb(com->cmd_port, 0); /* dummy */ 4059 DELAY(2); 4060 outb(com->cmd_port, 0); /* dummy */ 4061 DELAY(2); 4062 outb(com->cmd_port, 0); /* dummy */ 4063 DELAY(2); 4064 outb(com->cmd_port, CMD8251_RESET); /* internal reset */ 4065 DELAY(2); 4066 outb(com->cmd_port, mode ); /* mode register */ 4067 com->pc98_prev_siomod = mode; 4068 DELAY(2); 4069 pc98_i8251_set_cmd( com, (command|CMD8251_ER) ); 4070 DELAY(10); 4071 if (com->pc98_8251fifo_enable) 4072 outb(I8251F_fcr, FIFO_ENABLE | FIFO_XMT_RST | FIFO_RCV_RST); 4073} 4074 4075static void 4076pc98_check_sysclock(void) 4077{ 4078 /* get system clock from port */ 4079 if ( pc98_machine_type & M_8M ) { 4080 /* 8 MHz system & H98 */ 4081 sysclock = 8; 4082 } else { 4083 /* 5 MHz system */ 4084 sysclock = 5; 4085 } 4086} 4087 4088static void 4089com_cflag_and_speed_set( struct com_s *com, int cflag, int speed) 4090{ 4091 int cfcr=0; 4092 int previnterrupt; 4093 int tmp; 4094 u_int count; 4095 4096 if (pc98_ttspeedtab(com, speed, &count) != 0) 4097 return; 4098 4099 previnterrupt = pc98_check_i8251_interrupt(com); 4100 pc98_disable_i8251_interrupt( com, IEN_Tx|IEN_TxEMP|IEN_Rx ); 4101 4102 switch ( cflag&CSIZE ) { 4103 case CS5: 4104 cfcr = MOD8251_5BITS; break; 4105 case CS6: 4106 cfcr = MOD8251_6BITS; break; 4107 case CS7: 4108 cfcr = MOD8251_7BITS; break; 4109 case CS8: 4110 cfcr = MOD8251_8BITS; break; 4111 } 4112 if ( cflag&PARENB ) { 4113 if ( cflag&PARODD ) 4114 cfcr |= MOD8251_PENAB; 4115 else 4116 cfcr |= MOD8251_PENAB | MOD8251_PEVEN; 4117 } 4118 4119 if ( cflag&CSTOPB ) 4120 cfcr |= MOD8251_STOP2; 4121 else 4122 cfcr |= MOD8251_STOP1; 4123 4124 if ( count & 0x10000 ) 4125 cfcr |= MOD8251_CLKx1; 4126 else 4127 cfcr |= MOD8251_CLKx16; 4128 4129 while (!((tmp = inb(com->sts_port)) & STS8251_TxEMP)) 4130 ; 4131 4132 /* set baud rate from ospeed */ 4133 pc98_set_baud_rate( com, count ); 4134 4135 if ( cfcr != pc98_i8251_get_mod(com) ) 4136 pc98_i8251_reset(com, cfcr, pc98_i8251_get_cmd(com) ); 4137 4138 pc98_enable_i8251_interrupt( com, previnterrupt ); 4139} 4140 4141static int 4142pc98_ttspeedtab(struct com_s *com, int speed, u_int *divisor) 4143{ 4144 int if_type, effect_sp, count = -1, mod; 4145 4146 if_type = com->pc98_if_type & 0x0f; 4147 4148 switch (com->pc98_if_type) { 4149 case COM_IF_INTERNAL: 4150 if (PC98SIO_baud_rate_port(if_type) != -1) { 4151 count = ttspeedtab(speed, if_8251_type[if_type].speedtab); 4152 if (count > 0) { 4153 count |= COM1_EXT_CLOCK; 4154 break; 4155 } 4156 } 4157 4158 /* for *1CLK asynchronous! mode, TEFUTEFU */ 4159 mod = (sysclock == 5) ? 2457600 : 1996800; 4160 effect_sp = ttspeedtab( speed, pc98speedtab ); 4161 if ( effect_sp < 0 ) /* XXX */ 4162 effect_sp = ttspeedtab( (speed - 1), pc98speedtab ); 4163 if ( effect_sp <= 0 ) 4164 return effect_sp; 4165 if ( effect_sp == speed ) 4166 mod /= 16; 4167 if ( mod % effect_sp ) 4168 return(-1); 4169 count = mod / effect_sp; 4170 if ( count > 65535 ) 4171 return(-1); 4172 if ( effect_sp != speed ) 4173 count |= 0x10000; 4174 break; 4175 case COM_IF_PC9861K_1: 4176 case COM_IF_PC9861K_2: 4177 count = 1; 4178 break; 4179 case COM_IF_IND_SS_1: 4180 case COM_IF_IND_SS_2: 4181 case COM_IF_PIO9032B_1: 4182 case COM_IF_PIO9032B_2: 4183 count = ttspeedtab( speed, if_8251_type[if_type].speedtab ); 4184 break; 4185 case COM_IF_B98_01_1: 4186 case COM_IF_B98_01_2: 4187 count = ttspeedtab( speed, if_8251_type[if_type].speedtab ); 4188#ifdef B98_01_OLD 4189 if (count == 0 || count == 1) { 4190 count += 4; 4191 count |= 0x20000; /* x1 mode for 76800 and 153600 */ 4192 } 4193#endif 4194 break; 4195 } 4196 4197 if (count < 0) 4198 return count; 4199 4200 *divisor = (u_int) count; 4201 return 0; 4202} 4203 4204static void 4205pc98_set_baud_rate( struct com_s *com, u_int count ) 4206{ 4207 int if_type, io, s; 4208 4209 if_type = com->pc98_if_type & 0x0f; 4210 io = rman_get_start(com->ioportres) & 0xff00; 4211 4212 switch (com->pc98_if_type) { 4213 case COM_IF_INTERNAL: 4214 if (PC98SIO_baud_rate_port(if_type) != -1) { 4215 if (count & COM1_EXT_CLOCK) { 4216 outb((Port_t)PC98SIO_baud_rate_port(if_type), count & 0xff); 4217 break; 4218 } else { 4219 outb((Port_t)PC98SIO_baud_rate_port(if_type), 0x09); 4220 } 4221 } 4222 4223 if (count == 0) 4224 return; 4225 4226 /* set i8253 */ 4227 s = splclock(); 4228 if (count != 3) 4229 outb( 0x77, 0xb6 ); 4230 else 4231 outb( 0x77, 0xb4 ); 4232 outb( 0x5f, 0); 4233 outb( 0x75, count & 0xff ); 4234 outb( 0x5f, 0); 4235 outb( 0x75, (count >> 8) & 0xff ); 4236 splx(s); 4237 break; 4238 case COM_IF_IND_SS_1: 4239 case COM_IF_IND_SS_2: 4240 outb(io | PC98SIO_intr_ctrl_port(if_type), 0); 4241 outb(io | PC98SIO_baud_rate_port(if_type), 0); 4242 outb(io | PC98SIO_baud_rate_port(if_type), 0xc0); 4243 outb(io | PC98SIO_baud_rate_port(if_type), (count >> 8) | 0x80); 4244 outb(io | PC98SIO_baud_rate_port(if_type), count & 0xff); 4245 break; 4246 case COM_IF_PIO9032B_1: 4247 case COM_IF_PIO9032B_2: 4248 outb(io | PC98SIO_baud_rate_port(if_type), count); 4249 break; 4250 case COM_IF_B98_01_1: 4251 case COM_IF_B98_01_2: 4252 outb(io | PC98SIO_baud_rate_port(if_type), count & 0x0f); 4253#ifdef B98_01_OLD 4254 /* 4255 * Some old B98_01 board should be controlled 4256 * in different way, but this hasn't been tested yet. 4257 */ 4258 outb(io | PC98SIO_func_port(if_type), 4259 (count & 0x20000) ? 0xf0 : 0xf2); 4260#endif 4261 break; 4262 } 4263} 4264static int 4265pc98_check_if_type(device_t dev, struct siodev *iod) 4266{ 4267 int irr, io, if_type, tmp; 4268 static short irq_tab[2][8] = { 4269 { 3, 5, 6, 9, 10, 12, 13, -1}, 4270 { 3, 10, 12, 13, 5, 6, 9, -1} 4271 }; 4272 4273 if_type = iod->if_type & 0x0f; 4274 iod->irq = 0; 4275 io = isa_get_port(dev) & 0xff00; 4276 4277 if (IS_8251(iod->if_type)) { 4278 if (PC98SIO_func_port(if_type) != -1) { 4279 outb(io | PC98SIO_func_port(if_type), 0xf2); 4280 tmp = ttspeedtab(9600, if_8251_type[if_type].speedtab); 4281 if (tmp != -1 && PC98SIO_baud_rate_port(if_type) != -1) 4282 outb(io | PC98SIO_baud_rate_port(if_type), tmp); 4283 } 4284 4285 iod->cmd = io | PC98SIO_cmd_port(if_type); 4286 iod->sts = io | PC98SIO_sts_port(if_type); 4287 iod->mod = io | PC98SIO_in_modem_port(if_type); 4288 iod->ctrl = io | PC98SIO_intr_ctrl_port(if_type); 4289 4290 if (iod->if_type == COM_IF_INTERNAL) { 4291 iod->irq = 4; 4292 4293 if (pc98_check_8251vfast()) { 4294 PC98SIO_baud_rate_port(if_type) = I8251F_div; 4295 if_8251_type[if_type].speedtab = pc98fast_speedtab; 4296 } 4297 } else { 4298 tmp = inb( iod->mod ) & if_8251_type[if_type].irr_mask; 4299 if ((isa_get_port(dev) & 0xff) == IO_COM2) 4300 iod->irq = irq_tab[0][tmp]; 4301 else 4302 iod->irq = irq_tab[1][tmp]; 4303 } 4304 } else { 4305 irr = if_16550a_type[if_type].irr_read; 4306#ifdef COM_MULTIPORT 4307 if (!COM_ISMULTIPORT(device_get_flags(dev)) || 4308 device_get_unit(dev) == COM_MPMASTER(device_get_flags(dev))) 4309#endif 4310 if (irr != -1) { 4311 tmp = inb(io | irr); 4312 if (isa_get_port(dev) & 0x01) /* XXX depend on RSB-384 */ 4313 iod->irq = irq_tab[1][tmp >> 3]; 4314 else 4315 iod->irq = irq_tab[0][tmp & 0x07]; 4316 } 4317 iod->cmd = 0; 4318 iod->sts = 0; 4319 iod->mod = 0; 4320 iod->ctrl = 0; 4321 } 4322 if ( iod->irq == -1 ) return -1; 4323 4324 return 0; 4325} 4326static void 4327pc98_set_ioport(struct com_s *com) 4328{ 4329 int if_type = com->pc98_if_type & 0x0f; 4330 Port_t io = rman_get_start(com->ioportres) & 0xff00; 4331 4332 pc98_check_sysclock(); 4333 com->data_port = io | PC98SIO_data_port(if_type); 4334 com->cmd_port = io | PC98SIO_cmd_port(if_type); 4335 com->sts_port = io | PC98SIO_sts_port(if_type); 4336 com->in_modem_port = io | PC98SIO_in_modem_port(if_type); 4337 com->intr_ctrl_port = io | PC98SIO_intr_ctrl_port(if_type); 4338} 4339static int 4340pc98_check_8251vfast(void) 4341{ 4342 int i; 4343 4344 outb(I8251F_div, 0x8c); 4345 DELAY(10); 4346 for (i = 0; i < 100; i++) { 4347 if ((inb(I8251F_div) & 0x80) != 0) { 4348 i = 0; 4349 break; 4350 } 4351 DELAY(1); 4352 } 4353 outb(I8251F_div, 0); 4354 DELAY(10); 4355 for (; i < 100; i++) { 4356 if ((inb(I8251F_div) & 0x80) == 0) 4357 return 1; 4358 DELAY(1); 4359 } 4360 4361 return 0; 4362} 4363static int 4364pc98_check_8251fifo(void) 4365{ 4366 u_char tmp1, tmp2; 4367 4368 tmp1 = inb(I8251F_iir); 4369 DELAY(10); 4370 tmp2 = inb(I8251F_iir); 4371 if (((tmp1 ^ tmp2) & 0x40) != 0 && ((tmp1 | tmp2) & 0x20) == 0) 4372 return 1; 4373 4374 return 0; 4375} 4376#endif /* PC98 defined */ 4377