sio.c revision 146049
1/*- 2 * Copyright (c) 1991 The Regents of the University of California. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 4. Neither the name of the University nor the names of its contributors 14 * may be used to endorse or promote products derived from this software 15 * without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * $FreeBSD: head/sys/pc98/cbus/sio.c 146049 2005-05-10 12:02:18Z nyan $ 30 * from: @(#)com.c 7.5 (Berkeley) 5/16/91 31 * from: i386/isa sio.c,v 1.234 32 */ 33 34#include "opt_comconsole.h" 35#include "opt_compat.h" 36#include "opt_gdb.h" 37#include "opt_kdb.h" 38#include "opt_sio.h" 39 40/* 41 * Serial driver, based on 386BSD-0.1 com driver. 42 * Mostly rewritten to use pseudo-DMA. 43 * Works for National Semiconductor NS8250-NS16550AF UARTs. 44 * COM driver, based on HP dca driver. 45 * 46 * Changes for PC-Card integration: 47 * - Added PC-Card driver table and handlers 48 */ 49/*=============================================================== 50 * 386BSD(98),FreeBSD-1.1x(98) com driver. 51 * ----- 52 * modified for PC9801 by M.Ishii 53 * Kyoto University Microcomputer Club (KMC) 54 * Chou "TEFUTEFU" Hirotomi 55 * Kyoto Univ. the faculty of medicine 56 *=============================================================== 57 * FreeBSD-2.0.1(98) sio driver. 58 * ----- 59 * modified for pc98 Internal i8251 and MICRO CORE MC16550II 60 * T.Koike(hfc01340@niftyserve.or.jp) 61 * implement kernel device configuration 62 * aizu@orient.center.nitech.ac.jp 63 * 64 * Notes. 65 * ----- 66 * PC98 localization based on 386BSD(98) com driver. Using its PC98 local 67 * functions. 68 * This driver is under debugging,has bugs. 69 */ 70/* 71 * modified for AIWA B98-01 72 * by T.Hatanou <hatanou@yasuda.comm.waseda.ac.jp> last update: 15 Sep.1995 73 */ 74/* 75 * Modified by Y.Takahashi of Kogakuin University. 76 */ 77/* 78 * modified for 8251(FIFO) by Seigo TANIMURA <tanimura@FreeBSD.org> 79 */ 80 81#include <sys/param.h> 82#include <sys/systm.h> 83#include <sys/bus.h> 84#include <sys/conf.h> 85#include <sys/fcntl.h> 86#include <sys/interrupt.h> 87#include <sys/kdb.h> 88#include <sys/kernel.h> 89#include <sys/limits.h> 90#include <sys/lock.h> 91#include <sys/malloc.h> 92#include <sys/module.h> 93#include <sys/mutex.h> 94#include <sys/proc.h> 95#include <sys/reboot.h> 96#include <sys/serial.h> 97#include <sys/sysctl.h> 98#include <sys/syslog.h> 99#include <sys/tty.h> 100#include <machine/bus.h> 101#include <sys/rman.h> 102#include <sys/timepps.h> 103#include <sys/uio.h> 104#include <sys/cons.h> 105 106#include <isa/isavar.h> 107 108#include <machine/resource.h> 109 110#include <dev/sio/sioreg.h> 111#include <dev/sio/siovar.h> 112 113#ifdef PC98 114#include <pc98/cbus/cbus.h> 115#include <pc98/pc98/pc98_machdep.h> 116#endif 117 118#ifdef COM_ESP 119#include <dev/ic/esp.h> 120#endif 121#include <dev/ic/ns16550.h> 122#ifdef PC98 123#include <dev/ic/i8251.h> 124#include <dev/ic/rsa.h> 125#endif 126 127#define LOTS_OF_EVENTS 64 /* helps separate urgent events from input */ 128 129/* 130 * Meaning of flags: 131 * 132 * 0x00000001 shared IRQs 133 * 0x00000002 disable FIFO 134 * 0x00000008 recover sooner from lost output interrupts 135 * 0x00000010 device is potential system console 136 * 0x00000020 device is forced to become system console 137 * 0x00000040 device is reserved for low-level IO 138 * 0x00000080 use this port for remote kernel debugging 139 * 0x0000??00 minor number of master port 140 * 0x00010000 PPS timestamping on CTS instead of DCD 141 * 0x00080000 IIR_TXRDY bug 142 * 0x00400000 If no comconsole found then mark as a comconsole 143 * 0x1?000000 interface type 144 */ 145 146#ifdef COM_MULTIPORT 147/* checks in flags for multiport and which is multiport "master chip" 148 * for a given card 149 */ 150#define COM_ISMULTIPORT(flags) ((flags) & 0x01) 151#define COM_MPMASTER(flags) (((flags) >> 8) & 0x0ff) 152#ifndef PC98 153#define COM_NOTAST4(flags) ((flags) & 0x04) 154#endif 155#else 156#define COM_ISMULTIPORT(flags) (0) 157#endif /* COM_MULTIPORT */ 158 159#define COM_C_IIR_TXRDYBUG 0x80000 160#define COM_CONSOLE(flags) ((flags) & 0x10) 161#define COM_DEBUGGER(flags) ((flags) & 0x80) 162#ifndef PC98 163#define COM_FIFOSIZE(flags) (((flags) & 0xff000000) >> 24) 164#endif 165#define COM_FORCECONSOLE(flags) ((flags) & 0x20) 166#define COM_IIR_TXRDYBUG(flags) ((flags) & COM_C_IIR_TXRDYBUG) 167#define COM_LLCONSOLE(flags) ((flags) & 0x40) 168#define COM_LOSESOUTINTS(flags) ((flags) & 0x08) 169#define COM_NOFIFO(flags) ((flags) & 0x02) 170#ifndef PC98 171#define COM_NOSCR(flags) ((flags) & 0x100000) 172#endif 173#define COM_PPSCTS(flags) ((flags) & 0x10000) 174#ifndef PC98 175#define COM_ST16650A(flags) ((flags) & 0x20000) 176#define COM_TI16754(flags) ((flags) & 0x200000) 177#endif 178 179#define sio_getreg(com, off) \ 180 (bus_space_read_1((com)->bst, (com)->bsh, (off))) 181#define sio_setreg(com, off, value) \ 182 (bus_space_write_1((com)->bst, (com)->bsh, (off), (value))) 183 184/* 185 * com state bits. 186 * (CS_BUSY | CS_TTGO) and (CS_BUSY | CS_TTGO | CS_ODEVREADY) must be higher 187 * than the other bits so that they can be tested as a group without masking 188 * off the low bits. 189 * 190 * The following com and tty flags correspond closely: 191 * CS_BUSY = TS_BUSY (maintained by comstart(), siopoll() and 192 * comstop()) 193 * CS_TTGO = ~TS_TTSTOP (maintained by comparam() and comstart()) 194 * CS_CTS_OFLOW = CCTS_OFLOW (maintained by comparam()) 195 * CS_RTS_IFLOW = CRTS_IFLOW (maintained by comparam()) 196 * TS_FLUSH is not used. 197 * XXX I think TIOCSETA doesn't clear TS_TTSTOP when it clears IXON. 198 * XXX CS_*FLOW should be CF_*FLOW in com->flags (control flags not state). 199 */ 200#define CS_BUSY 0x80 /* output in progress */ 201#define CS_TTGO 0x40 /* output not stopped by XOFF */ 202#define CS_ODEVREADY 0x20 /* external device h/w ready (CTS) */ 203#define CS_CHECKMSR 1 /* check of MSR scheduled */ 204#define CS_CTS_OFLOW 2 /* use CTS output flow control */ 205#define CS_ODONE 4 /* output completed */ 206#define CS_RTS_IFLOW 8 /* use RTS input flow control */ 207#define CSE_BUSYCHECK 1 /* siobusycheck() scheduled */ 208 209static char const * const error_desc[] = { 210#define CE_OVERRUN 0 211 "silo overflow", 212#define CE_INTERRUPT_BUF_OVERFLOW 1 213 "interrupt-level buffer overflow", 214#define CE_TTY_BUF_OVERFLOW 2 215 "tty-level buffer overflow", 216}; 217 218#define CE_NTYPES 3 219#define CE_RECORD(com, errnum) (++(com)->delta_error_counts[errnum]) 220 221/* types. XXX - should be elsewhere */ 222typedef u_int Port_t; /* hardware port */ 223typedef u_char bool_t; /* boolean */ 224 225/* queue of linear buffers */ 226struct lbq { 227 u_char *l_head; /* next char to process */ 228 u_char *l_tail; /* one past the last char to process */ 229 struct lbq *l_next; /* next in queue */ 230 bool_t l_queued; /* nonzero if queued */ 231}; 232 233/* com device structure */ 234struct com_s { 235 u_char state; /* miscellaneous flag bits */ 236 u_char cfcr_image; /* copy of value written to CFCR */ 237#ifdef COM_ESP 238 bool_t esp; /* is this unit a hayes esp board? */ 239#endif 240 u_char extra_state; /* more flag bits, separate for order trick */ 241 u_char fifo_image; /* copy of value written to FIFO */ 242 bool_t hasfifo; /* nonzero for 16550 UARTs */ 243 bool_t loses_outints; /* nonzero if device loses output interrupts */ 244 u_char mcr_image; /* copy of value written to MCR */ 245#ifdef COM_MULTIPORT 246 bool_t multiport; /* is this unit part of a multiport device? */ 247#endif /* COM_MULTIPORT */ 248 bool_t no_irq; /* nonzero if irq is not attached */ 249 bool_t gone; /* hardware disappeared */ 250 bool_t poll; /* nonzero if polling is required */ 251 bool_t poll_output; /* nonzero if polling for output is required */ 252 bool_t st16650a; /* nonzero if Startech 16650A compatible */ 253 int unit; /* unit number */ 254 u_int flags; /* copy of device flags */ 255 u_int tx_fifo_size; 256 257 /* 258 * The high level of the driver never reads status registers directly 259 * because there would be too many side effects to handle conveniently. 260 * Instead, it reads copies of the registers stored here by the 261 * interrupt handler. 262 */ 263 u_char last_modem_status; /* last MSR read by intr handler */ 264 u_char prev_modem_status; /* last MSR handled by high level */ 265 266 u_char *ibuf; /* start of input buffer */ 267 u_char *ibufend; /* end of input buffer */ 268 u_char *ibufold; /* old input buffer, to be freed */ 269 u_char *ihighwater; /* threshold in input buffer */ 270 u_char *iptr; /* next free spot in input buffer */ 271 int ibufsize; /* size of ibuf (not include error bytes) */ 272 int ierroff; /* offset of error bytes in ibuf */ 273 274 struct lbq obufq; /* head of queue of output buffers */ 275 struct lbq obufs[2]; /* output buffers */ 276 277 bus_space_tag_t bst; 278 bus_space_handle_t bsh; 279 280#ifdef PC98 281 Port_t cmd_port; 282 Port_t sts_port; 283 Port_t in_modem_port; 284 Port_t intr_ctrl_port; 285 Port_t rsabase; /* Iobase address of an I/O-DATA RSA board. */ 286 int intr_enable; 287 int pc98_prev_modem_status; 288 int pc98_modem_delta; 289 int modem_car_chg_timer; 290 int pc98_prev_siocmd; 291 int pc98_prev_siomod; 292 int modem_checking; 293 int pc98_if_type; 294 295 bool_t pc98_8251fifo; 296 bool_t pc98_8251fifo_enable; 297#endif /* PC98 */ 298 Port_t data_port; /* i/o ports */ 299#ifdef COM_ESP 300 Port_t esp_port; 301#endif 302 Port_t int_ctl_port; 303 Port_t int_id_port; 304 Port_t modem_ctl_port; 305 Port_t line_status_port; 306 Port_t modem_status_port; 307 308 struct tty *tp; /* cross reference */ 309 310 struct pps_state pps; 311 int pps_bit; 312#ifdef ALT_BREAK_TO_DEBUGGER 313 int alt_brk_state; 314#endif 315 316 u_long bytes_in; /* statistics */ 317 u_long bytes_out; 318 u_int delta_error_counts[CE_NTYPES]; 319 u_long error_counts[CE_NTYPES]; 320 321 u_long rclk; 322 323 struct resource *irqres; 324 struct resource *ioportres; 325 int ioportrid; 326 void *cookie; 327 328 /* 329 * Data area for output buffers. Someday we should build the output 330 * buffer queue without copying data. 331 */ 332#ifdef PC98 333 int obufsize; 334 u_char *obuf1; 335 u_char *obuf2; 336#else 337 u_char obuf1[256]; 338 u_char obuf2[256]; 339#endif 340}; 341 342#ifdef COM_ESP 343static int espattach(struct com_s *com, Port_t esp_port); 344#endif 345 346static void combreak(struct tty *tp, int sig); 347static timeout_t siobusycheck; 348static u_int siodivisor(u_long rclk, speed_t speed); 349static void comclose(struct tty *tp); 350static int comopen(struct tty *tp, struct cdev *dev); 351static void sioinput(struct com_s *com); 352static void siointr1(struct com_s *com); 353static void siointr(void *arg); 354static int commodem(struct tty *tp, int sigon, int sigoff); 355static int comparam(struct tty *tp, struct termios *t); 356static void siopoll(void *); 357static void siosettimeout(void); 358static int siosetwater(struct com_s *com, speed_t speed); 359static void comstart(struct tty *tp); 360static void comstop(struct tty *tp, int rw); 361static timeout_t comwakeup; 362 363char sio_driver_name[] = "sio"; 364static struct mtx sio_lock; 365static int sio_inited; 366 367/* table and macro for fast conversion from a unit number to its com struct */ 368devclass_t sio_devclass; 369#define com_addr(unit) ((struct com_s *) \ 370 devclass_get_softc(sio_devclass, unit)) /* XXX */ 371 372int comconsole = -1; 373static volatile speed_t comdefaultrate = CONSPEED; 374static u_long comdefaultrclk = DEFAULT_RCLK; 375SYSCTL_ULONG(_machdep, OID_AUTO, conrclk, CTLFLAG_RW, &comdefaultrclk, 0, ""); 376static speed_t gdbdefaultrate = GDBSPEED; 377SYSCTL_UINT(_machdep, OID_AUTO, gdbspeed, CTLFLAG_RW, 378 &gdbdefaultrate, GDBSPEED, ""); 379static u_int com_events; /* input chars + weighted output completions */ 380static Port_t siocniobase; 381static int siocnunit = -1; 382static void *sio_slow_ih; 383static void *sio_fast_ih; 384static int sio_timeout; 385static int sio_timeouts_until_log; 386static struct callout_handle sio_timeout_handle 387 = CALLOUT_HANDLE_INITIALIZER(&sio_timeout_handle); 388static int sio_numunits; 389 390#ifdef PC98 391struct siodev { 392 short if_type; 393 short irq; 394 Port_t cmd, sts, ctrl, mod; 395}; 396static int sysclock; 397 398#define COM_INT_DISABLE {int previpri; previpri=spltty(); 399#define COM_INT_ENABLE splx(previpri);} 400#define IEN_TxFLAG IEN_Tx 401 402#define COM_CARRIER_DETECT_EMULATE 0 403#define PC98_CHECK_MODEM_INTERVAL (hz/10) 404#define DCD_OFF_TOLERANCE 2 405#define DCD_ON_RECOGNITION 2 406#define IS_8251(if_type) (!(if_type & 0x10)) 407#define COM1_EXT_CLOCK 0x40000 408 409static void commint(struct cdev *dev); 410static void com_tiocm_bis(struct com_s *com, int msr); 411static void com_tiocm_bic(struct com_s *com, int msr); 412static int com_tiocm_get(struct com_s *com); 413static int com_tiocm_get_delta(struct com_s *com); 414static void pc98_msrint_start(struct cdev *dev); 415static void com_cflag_and_speed_set(struct com_s *com, int cflag, int speed); 416static int pc98_ttspeedtab(struct com_s *com, int speed, u_int *divisor); 417static int pc98_get_modem_status(struct com_s *com); 418static timeout_t pc98_check_msr; 419static void pc98_set_baud_rate(struct com_s *com, u_int count); 420static void pc98_i8251_reset(struct com_s *com, int mode, int command); 421static void pc98_disable_i8251_interrupt(struct com_s *com, int mod); 422static void pc98_enable_i8251_interrupt(struct com_s *com, int mod); 423static int pc98_check_i8251_interrupt(struct com_s *com); 424static int pc98_i8251_get_cmd(struct com_s *com); 425static int pc98_i8251_get_mod(struct com_s *com); 426static void pc98_i8251_set_cmd(struct com_s *com, int x); 427static void pc98_i8251_or_cmd(struct com_s *com, int x); 428static void pc98_i8251_clear_cmd(struct com_s *com, int x); 429static void pc98_i8251_clear_or_cmd(struct com_s *com, int clr, int x); 430static int pc98_check_if_type(device_t dev, struct siodev *iod); 431static int pc98_check_8251vfast(void); 432static int pc98_check_8251fifo(void); 433static void pc98_check_sysclock(void); 434static void pc98_set_ioport(struct com_s *com); 435 436#define com_int_Tx_disable(com) \ 437 pc98_disable_i8251_interrupt(com,IEN_Tx|IEN_TxEMP) 438#define com_int_Tx_enable(com) \ 439 pc98_enable_i8251_interrupt(com,IEN_TxFLAG) 440#define com_int_Rx_disable(com) \ 441 pc98_disable_i8251_interrupt(com,IEN_Rx) 442#define com_int_Rx_enable(com) \ 443 pc98_enable_i8251_interrupt(com,IEN_Rx) 444#define com_int_TxRx_disable(com) \ 445 pc98_disable_i8251_interrupt(com,IEN_Tx|IEN_TxEMP|IEN_Rx) 446#define com_int_TxRx_enable(com) \ 447 pc98_enable_i8251_interrupt(com,IEN_TxFLAG|IEN_Rx) 448#define com_send_break_on(com) \ 449 (IS_8251((com)->pc98_if_type) ? \ 450 pc98_i8251_or_cmd((com), CMD8251_SBRK) : \ 451 sio_setreg((com), com_cfcr, (com)->cfcr_image |= CFCR_SBREAK)) 452#define com_send_break_off(com) \ 453 (IS_8251((com)->pc98_if_type) ? \ 454 pc98_i8251_clear_cmd((com), CMD8251_SBRK) : \ 455 sio_setreg((com), com_cfcr, (com)->cfcr_image &= ~CFCR_SBREAK)) 456 457static struct speedtab pc98speedtab[] = { /* internal RS232C interface */ 458 { 0, 0, }, 459 { 50, 50, }, 460 { 75, 75, }, 461 { 150, 150, }, 462 { 200, 200, }, 463 { 300, 300, }, 464 { 600, 600, }, 465 { 1200, 1200, }, 466 { 2400, 2400, }, 467 { 4800, 4800, }, 468 { 9600, 9600, }, 469 { 19200, 19200, }, 470 { 38400, 38400, }, 471 { 51200, 51200, }, 472 { 76800, 76800, }, 473 { 20800, 20800, }, 474 { 31200, 31200, }, 475 { 41600, 41600, }, 476 { 62400, 62400, }, 477 { -1, -1 } 478}; 479static struct speedtab pc98fast_speedtab[] = { 480 { 9600, 0x80 | (DEFAULT_RCLK / (16 * (9600))), }, 481 { 19200, 0x80 | (DEFAULT_RCLK / (16 * (19200))), }, 482 { 38400, 0x80 | (DEFAULT_RCLK / (16 * (38400))), }, 483 { 57600, 0x80 | (DEFAULT_RCLK / (16 * (57600))), }, 484 { 115200, 0x80 | (DEFAULT_RCLK / (16 * (115200))), }, 485 { -1, -1 } 486}; 487static struct speedtab comspeedtab_pio9032b[] = { 488 { 300, 6, }, 489 { 600, 5, }, 490 { 1200, 4, }, 491 { 2400, 3, }, 492 { 4800, 2, }, 493 { 9600, 1, }, 494 { 19200, 0, }, 495 { 38400, 7, }, 496 { -1, -1 } 497}; 498static struct speedtab comspeedtab_b98_01[] = { 499 { 75, 11, }, 500 { 150, 10, }, 501 { 300, 9, }, 502 { 600, 8, }, 503 { 1200, 7, }, 504 { 2400, 6, }, 505 { 4800, 5, }, 506 { 9600, 4, }, 507 { 19200, 3, }, 508 { 38400, 2, }, 509 { 76800, 1, }, 510 { 153600, 0, }, 511 { -1, -1 } 512}; 513static struct speedtab comspeedtab_ind[] = { 514 { 300, 1536, }, 515 { 600, 768, }, 516 { 1200, 384, }, 517 { 2400, 192, }, 518 { 4800, 96, }, 519 { 9600, 48, }, 520 { 19200, 24, }, 521 { 38400, 12, }, 522 { 57600, 8, }, 523 { 115200, 4, }, 524 { 153600, 3, }, 525 { 230400, 2, }, 526 { 460800, 1, }, 527 { -1, -1 } 528}; 529 530struct { 531 char *name; 532 short port_table[7]; 533 short irr_mask; 534 struct speedtab *speedtab; 535 short check_irq; 536} if_8251_type[] = { 537 /* COM_IF_INTERNAL */ 538 { " (internal)", {0x30, 0x32, 0x32, 0x33, 0x35, -1, -1}, 539 -1, pc98speedtab, 1 }, 540 /* COM_IF_PC9861K_1 */ 541 { " (PC9861K)", {0xb1, 0xb3, 0xb3, 0xb0, 0xb0, -1, -1}, 542 3, NULL, 1 }, 543 /* COM_IF_PC9861K_2 */ 544 { " (PC9861K)", {0xb9, 0xbb, 0xbb, 0xb2, 0xb2, -1, -1}, 545 3, NULL, 1 }, 546 /* COM_IF_IND_SS_1 */ 547 { " (IND-SS)", {0xb1, 0xb3, 0xb3, 0xb0, 0xb0, 0xb3, -1}, 548 3, comspeedtab_ind, 1 }, 549 /* COM_IF_IND_SS_2 */ 550 { " (IND-SS)", {0xb9, 0xbb, 0xbb, 0xb2, 0xb2, 0xbb, -1}, 551 3, comspeedtab_ind, 1 }, 552 /* COM_IF_PIO9032B_1 */ 553 { " (PIO9032B)", {0xb1, 0xb3, 0xb3, 0xb0, 0xb0, 0xb8, -1}, 554 7, comspeedtab_pio9032b, 1 }, 555 /* COM_IF_PIO9032B_2 */ 556 { " (PIO9032B)", {0xb9, 0xbb, 0xbb, 0xb2, 0xb2, 0xba, -1}, 557 7, comspeedtab_pio9032b, 1 }, 558 /* COM_IF_B98_01_1 */ 559 { " (B98-01)", {0xb1, 0xb3, 0xb3, 0xb0, 0xb0, 0xd1, 0xd3}, 560 7, comspeedtab_b98_01, 0 }, 561 /* COM_IF_B98_01_2 */ 562 { " (B98-01)", {0xb9, 0xbb, 0xbb, 0xb2, 0xb2, 0xd5, 0xd7}, 563 7, comspeedtab_b98_01, 0 }, 564}; 565#define PC98SIO_data_port(type) (if_8251_type[type].port_table[0]) 566#define PC98SIO_cmd_port(type) (if_8251_type[type].port_table[1]) 567#define PC98SIO_sts_port(type) (if_8251_type[type].port_table[2]) 568#define PC98SIO_in_modem_port(type) (if_8251_type[type].port_table[3]) 569#define PC98SIO_intr_ctrl_port(type) (if_8251_type[type].port_table[4]) 570#define PC98SIO_baud_rate_port(type) (if_8251_type[type].port_table[5]) 571#define PC98SIO_func_port(type) (if_8251_type[type].port_table[6]) 572 573#define I8251F_data 0x130 574#define I8251F_lsr 0x132 575#define I8251F_msr 0x134 576#define I8251F_iir 0x136 577#define I8251F_fcr 0x138 578#define I8251F_div 0x13a 579 580 581static bus_addr_t port_table_0[] = 582 {0x000, 0x001, 0x002, 0x003, 0x004, 0x005, 0x006, 0x007}; 583static bus_addr_t port_table_1[] = 584 {0x000, 0x002, 0x004, 0x006, 0x008, 0x00a, 0x00c, 0x00e}; 585static bus_addr_t port_table_8[] = 586 {0x000, 0x100, 0x200, 0x300, 0x400, 0x500, 0x600, 0x700}; 587static bus_addr_t port_table_rsa[] = { 588 0x008, 0x009, 0x00a, 0x00b, 0x00c, 0x00d, 0x00e, 0x00f, 589 0x000, 0x001, 0x002, 0x003, 0x004, 0x005, 0x006, 0x007 590}; 591 592struct { 593 char *name; 594 short irr_read; 595 short irr_write; 596 bus_addr_t *iat; 597 bus_size_t iatsz; 598 u_long rclk; 599} if_16550a_type[] = { 600 /* COM_IF_RSA98 */ 601 {" (RSA-98)", -1, -1, port_table_0, IO_COMSIZE, DEFAULT_RCLK}, 602 /* COM_IF_NS16550 */ 603 {"", -1, -1, port_table_0, IO_COMSIZE, DEFAULT_RCLK}, 604 /* COM_IF_SECOND_CCU */ 605 {"", -1, -1, port_table_0, IO_COMSIZE, DEFAULT_RCLK}, 606 /* COM_IF_MC16550II */ 607 {" (MC16550II)", -1, 0x1000, port_table_8, IO_COMSIZE, 608 DEFAULT_RCLK * 4}, 609 /* COM_IF_MCRS98 */ 610 {" (MC-RS98)", -1, 0x1000, port_table_8, IO_COMSIZE, DEFAULT_RCLK * 4}, 611 /* COM_IF_RSB3000 */ 612 {" (RSB-3000)", 0xbf, -1, port_table_1, IO_COMSIZE, DEFAULT_RCLK * 10}, 613 /* COM_IF_RSB384 */ 614 {" (RSB-384)", 0xbf, -1, port_table_1, IO_COMSIZE, DEFAULT_RCLK * 10}, 615 /* COM_IF_MODEM_CARD */ 616 {"", -1, -1, port_table_0, IO_COMSIZE, DEFAULT_RCLK}, 617 /* COM_IF_RSA98III */ 618 {" (RSA-98III)", -1, -1, port_table_rsa, 16, DEFAULT_RCLK * 8}, 619 /* COM_IF_ESP98 */ 620 {" (ESP98)", -1, -1, port_table_1, IO_COMSIZE, DEFAULT_RCLK * 4}, 621}; 622#endif /* PC98 */ 623 624#ifdef GDB 625static Port_t siogdbiobase = 0; 626#endif 627 628#ifdef COM_ESP 629#ifdef PC98 630 631/* XXX configure this properly. */ 632/* XXX quite broken for new-bus. */ 633static Port_t likely_com_ports[] = { 0, 0xb0, 0xb1, 0 }; 634static Port_t likely_esp_ports[] = { 0xc0d0, 0 }; 635 636#define ESP98_CMD1 (ESP_CMD1 * 0x100) 637#define ESP98_CMD2 (ESP_CMD2 * 0x100) 638#define ESP98_STATUS1 (ESP_STATUS1 * 0x100) 639#define ESP98_STATUS2 (ESP_STATUS2 * 0x100) 640 641#else /* PC98 */ 642 643/* XXX configure this properly. */ 644static Port_t likely_com_ports[] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8, }; 645static Port_t likely_esp_ports[] = { 0x140, 0x180, 0x280, 0 }; 646 647#endif /* PC98 */ 648#endif 649 650/* 651 * handle sysctl read/write requests for console speed 652 * 653 * In addition to setting comdefaultrate for I/O through /dev/console, 654 * also set the initial and lock values for the /dev/ttyXX device 655 * if there is one associated with the console. Finally, if the /dev/tty 656 * device has already been open, change the speed on the open running port 657 * itself. 658 */ 659 660static int 661sysctl_machdep_comdefaultrate(SYSCTL_HANDLER_ARGS) 662{ 663 int error, s; 664 speed_t newspeed; 665 struct com_s *com; 666 struct tty *tp; 667 668 newspeed = comdefaultrate; 669 670 error = sysctl_handle_opaque(oidp, &newspeed, sizeof newspeed, req); 671 if (error || !req->newptr) 672 return (error); 673 674 comdefaultrate = newspeed; 675 676 if (comconsole < 0) /* serial console not selected? */ 677 return (0); 678 679 com = com_addr(comconsole); 680 if (com == NULL) 681 return (ENXIO); 682 683 tp = com->tp; 684 if (tp == NULL) 685 return (ENXIO); 686 687 /* 688 * set the initial and lock rates for /dev/ttydXX and /dev/cuaXX 689 * (note, the lock rates really are boolean -- if non-zero, disallow 690 * speed changes) 691 */ 692 tp->t_init_in.c_ispeed = tp->t_init_in.c_ospeed = 693 tp->t_lock_in.c_ispeed = tp->t_lock_in.c_ospeed = 694 tp->t_init_out.c_ispeed = tp->t_init_out.c_ospeed = 695 tp->t_lock_out.c_ispeed = tp->t_lock_out.c_ospeed = comdefaultrate; 696 697 if (tp->t_state & TS_ISOPEN) { 698 tp->t_termios.c_ispeed = 699 tp->t_termios.c_ospeed = comdefaultrate; 700 s = spltty(); 701 error = comparam(tp, &tp->t_termios); 702 splx(s); 703 } 704 return error; 705} 706 707SYSCTL_PROC(_machdep, OID_AUTO, conspeed, CTLTYPE_INT | CTLFLAG_RW, 708 0, 0, sysctl_machdep_comdefaultrate, "I", ""); 709 710/* 711 * Unload the driver and clear the table. 712 * XXX this is mostly wrong. 713 * XXX TODO: 714 * This is usually called when the card is ejected, but 715 * can be caused by a kldunload of a controller driver. 716 * The idea is to reset the driver's view of the device 717 * and ensure that any driver entry points such as 718 * read and write do not hang. 719 */ 720int 721siodetach(device_t dev) 722{ 723 struct com_s *com; 724 725 com = (struct com_s *) device_get_softc(dev); 726 if (com == NULL) { 727 device_printf(dev, "NULL com in siounload\n"); 728 return (0); 729 } 730 com->gone = TRUE; 731 if (com->tp) 732 ttyfree(com->tp); 733 if (com->irqres) { 734 bus_teardown_intr(dev, com->irqres, com->cookie); 735 bus_release_resource(dev, SYS_RES_IRQ, 0, com->irqres); 736 } 737 if (com->ioportres) 738 bus_release_resource(dev, SYS_RES_IOPORT, com->ioportrid, 739 com->ioportres); 740 if (com->ibuf != NULL) 741 free(com->ibuf, M_DEVBUF); 742#ifdef PC98 743 if (com->obuf1 != NULL) 744 free(com->obuf1, M_DEVBUF); 745#endif 746 747 device_set_softc(dev, NULL); 748 free(com, M_DEVBUF); 749 return (0); 750} 751 752int 753sioprobe(dev, xrid, rclk, noprobe) 754 device_t dev; 755 int xrid; 756 u_long rclk; 757 int noprobe; 758{ 759#if 0 760 static bool_t already_init; 761 device_t xdev; 762#endif 763 struct com_s *com; 764 u_int divisor; 765 bool_t failures[10]; 766 int fn; 767 device_t idev; 768 Port_t iobase; 769 intrmask_t irqmap[4]; 770 intrmask_t irqs; 771 u_char mcr_image; 772 int result; 773 u_long xirq; 774 u_int flags = device_get_flags(dev); 775 int rid; 776 struct resource *port; 777#ifdef PC98 778 int tmp; 779 struct siodev iod; 780#endif 781 782#ifdef PC98 783 iod.if_type = GET_IFTYPE(flags); 784 if ((iod.if_type < 0 || iod.if_type > COM_IF_END1) && 785 (iod.if_type < 0x10 || iod.if_type > COM_IF_END2)) 786 return ENXIO; 787#endif 788 789 rid = xrid; 790#ifdef PC98 791 if (IS_8251(iod.if_type)) { 792 port = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid, 793 RF_ACTIVE); 794 } else if (iod.if_type == COM_IF_MODEM_CARD || 795 iod.if_type == COM_IF_RSA98III || 796 isa_get_vendorid(dev)) { 797 port = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 0, ~0, 798 if_16550a_type[iod.if_type & 0x0f].iatsz, RF_ACTIVE); 799 } else { 800 port = isa_alloc_resourcev(dev, SYS_RES_IOPORT, &rid, 801 if_16550a_type[iod.if_type & 0x0f].iat, 802 if_16550a_type[iod.if_type & 0x0f].iatsz, RF_ACTIVE); 803 } 804#else 805 port = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 806 0, ~0, IO_COMSIZE, RF_ACTIVE); 807#endif 808 if (!port) 809 return (ENXIO); 810#ifdef PC98 811 if (!IS_8251(iod.if_type)) { 812 if (isa_load_resourcev(port, 813 if_16550a_type[iod.if_type & 0x0f].iat, 814 if_16550a_type[iod.if_type & 0x0f].iatsz) != 0) { 815 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 816 return ENXIO; 817 } 818 } 819#endif 820 821 com = malloc(sizeof(*com), M_DEVBUF, M_NOWAIT | M_ZERO); 822 if (com == NULL) { 823 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 824 return (ENOMEM); 825 } 826 device_set_softc(dev, com); 827 com->bst = rman_get_bustag(port); 828 com->bsh = rman_get_bushandle(port); 829#ifdef PC98 830 if (!IS_8251(iod.if_type) && rclk == 0) 831 rclk = if_16550a_type[iod.if_type & 0x0f].rclk; 832#else 833 if (rclk == 0) 834 rclk = DEFAULT_RCLK; 835#endif 836 com->rclk = rclk; 837 838 while (sio_inited != 2) 839 if (atomic_cmpset_int(&sio_inited, 0, 1)) { 840 mtx_init(&sio_lock, sio_driver_name, NULL, 841 (comconsole != -1) ? 842 MTX_SPIN | MTX_QUIET : MTX_SPIN); 843 atomic_store_rel_int(&sio_inited, 2); 844 } 845 846#if 0 847 /* 848 * XXX this is broken - when we are first called, there are no 849 * previously configured IO ports. We could hard code 850 * 0x3f8, 0x2f8, 0x3e8, 0x2e8 etc but that's probably worse. 851 * This code has been doing nothing since the conversion since 852 * "count" is zero the first time around. 853 */ 854 if (!already_init) { 855 /* 856 * Turn off MCR_IENABLE for all likely serial ports. An unused 857 * port with its MCR_IENABLE gate open will inhibit interrupts 858 * from any used port that shares the interrupt vector. 859 * XXX the gate enable is elsewhere for some multiports. 860 */ 861 device_t *devs; 862 int count, i, xioport; 863#ifdef PC98 864 int xiftype; 865#endif 866 867 devclass_get_devices(sio_devclass, &devs, &count); 868#ifdef PC98 869 for (i = 0; i < count; i++) { 870 xdev = devs[i]; 871 xioport = bus_get_resource_start(xdev, SYS_RES_IOPORT, 0); 872 xiftype = GET_IFTYPE(device_get_flags(xdev)); 873 if (device_is_enabled(xdev) && xioport > 0) { 874 if (IS_8251(xiftype)) 875 outb((xioport & 0xff00) | PC98SIO_cmd_port(xiftype & 0x0f), 0xf2); 876 else 877 outb(xioport + if_16550a_type[xiftype & 0x0f].iat[com_mcr], 0); 878 } 879 } 880#else 881 for (i = 0; i < count; i++) { 882 xdev = devs[i]; 883 if (device_is_enabled(xdev) && 884 bus_get_resource(xdev, SYS_RES_IOPORT, 0, &xioport, 885 NULL) == 0) 886 outb(xioport + com_mcr, 0); 887 } 888#endif 889 free(devs, M_TEMP); 890 already_init = TRUE; 891 } 892#endif 893 894 if (COM_LLCONSOLE(flags)) { 895 printf("sio%d: reserved for low-level i/o\n", 896 device_get_unit(dev)); 897 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 898 device_set_softc(dev, NULL); 899 free(com, M_DEVBUF); 900 return (ENXIO); 901 } 902 903#ifdef PC98 904 DELAY(10); 905 906 /* 907 * If the port is i8251 UART (internal, B98_01) 908 */ 909 if (pc98_check_if_type(dev, &iod) == -1) { 910 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 911 device_set_softc(dev, NULL); 912 free(com, M_DEVBUF); 913 return (ENXIO); 914 } 915 if (iod.irq > 0) 916 bus_set_resource(dev, SYS_RES_IRQ, 0, iod.irq, 1); 917 if (IS_8251(iod.if_type)) { 918 outb(iod.cmd, 0); 919 DELAY(10); 920 outb(iod.cmd, 0); 921 DELAY(10); 922 outb(iod.cmd, 0); 923 DELAY(10); 924 outb(iod.cmd, CMD8251_RESET); 925 DELAY(1000); /* for a while...*/ 926 outb(iod.cmd, 0xf2); /* MODE (dummy) */ 927 DELAY(10); 928 outb(iod.cmd, 0x01); /* CMD (dummy) */ 929 DELAY(1000); /* for a while...*/ 930 if (( inb(iod.sts) & STS8251_TxEMP ) == 0 ) { 931 result = (ENXIO); 932 } 933 if (if_8251_type[iod.if_type & 0x0f].check_irq) { 934 COM_INT_DISABLE 935 tmp = ( inb( iod.ctrl ) & ~(IEN_Rx|IEN_TxEMP|IEN_Tx)); 936 outb( iod.ctrl, tmp|IEN_TxEMP ); 937 DELAY(10); 938 result = isa_irq_pending() ? 0 : ENXIO; 939 outb( iod.ctrl, tmp ); 940 COM_INT_ENABLE 941 } else { 942 /* 943 * B98_01 doesn't activate TxEMP interrupt line 944 * when being reset, so we can't check irq pending. 945 */ 946 result = 0; 947 } 948 if (epson_machine_id==0x20) { /* XXX */ 949 result = 0; 950 } 951 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 952 if (result) { 953 device_set_softc(dev, NULL); 954 free(com, M_DEVBUF); 955 } 956 return result; 957 } 958#endif /* PC98 */ 959 /* 960 * If the device is on a multiport card and has an AST/4 961 * compatible interrupt control register, initialize this 962 * register and prepare to leave MCR_IENABLE clear in the mcr. 963 * Otherwise, prepare to set MCR_IENABLE in the mcr. 964 * Point idev to the device struct giving the correct id_irq. 965 * This is the struct for the master device if there is one. 966 */ 967 idev = dev; 968 mcr_image = MCR_IENABLE; 969#ifdef COM_MULTIPORT 970 if (COM_ISMULTIPORT(flags)) { 971#ifndef PC98 972 Port_t xiobase; 973 u_long io; 974#endif 975 976 idev = devclass_get_device(sio_devclass, COM_MPMASTER(flags)); 977 if (idev == NULL) { 978 printf("sio%d: master device %d not configured\n", 979 device_get_unit(dev), COM_MPMASTER(flags)); 980 idev = dev; 981 } 982#ifndef PC98 983 if (!COM_NOTAST4(flags)) { 984 if (bus_get_resource(idev, SYS_RES_IOPORT, 0, &io, 985 NULL) == 0) { 986 xiobase = io; 987 if (bus_get_resource(idev, SYS_RES_IRQ, 0, 988 NULL, NULL) == 0) 989 outb(xiobase + com_scr, 0x80); 990 else 991 outb(xiobase + com_scr, 0); 992 } 993 mcr_image = 0; 994 } 995#endif 996 } 997#endif /* COM_MULTIPORT */ 998 if (bus_get_resource(idev, SYS_RES_IRQ, 0, NULL, NULL) != 0) 999 mcr_image = 0; 1000 1001 bzero(failures, sizeof failures); 1002 iobase = rman_get_start(port); 1003 1004#ifdef PC98 1005 if (iod.if_type == COM_IF_RSA98III) { 1006 mcr_image = 0; 1007 1008 outb(iobase + rsa_msr, 0x04); 1009 outb(iobase + rsa_frr, 0x00); 1010 if ((inb(iobase + rsa_srr) & 0x36) != 0x36) { 1011 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 1012 device_set_softc(dev, NULL); 1013 free(com, M_DEVBUF); 1014 return (ENXIO); 1015 } 1016 outb(iobase + rsa_ier, 0x00); 1017 outb(iobase + rsa_frr, 0x00); 1018 outb(iobase + rsa_tivsr, 0x00); 1019 outb(iobase + rsa_tcr, 0x00); 1020 } 1021 1022 tmp = if_16550a_type[iod.if_type & 0x0f].irr_write; 1023 if (tmp != -1) { 1024 /* MC16550II */ 1025 int irqout; 1026 switch (isa_get_irq(idev)) { 1027 case 3: irqout = 4; break; 1028 case 5: irqout = 5; break; 1029 case 6: irqout = 6; break; 1030 case 12: irqout = 7; break; 1031 default: 1032 printf("sio%d: irq configuration error\n", 1033 device_get_unit(dev)); 1034 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 1035 device_set_softc(dev, NULL); 1036 free(com, M_DEVBUF); 1037 return (ENXIO); 1038 } 1039 outb((iobase & 0x00ff) | tmp, irqout); 1040 } 1041#endif 1042 1043 /* 1044 * We don't want to get actual interrupts, just masked ones. 1045 * Interrupts from this line should already be masked in the ICU, 1046 * but mask them in the processor as well in case there are some 1047 * (misconfigured) shared interrupts. 1048 */ 1049 mtx_lock_spin(&sio_lock); 1050/* EXTRA DELAY? */ 1051 1052 /* 1053 * Initialize the speed and the word size and wait long enough to 1054 * drain the maximum of 16 bytes of junk in device output queues. 1055 * The speed is undefined after a master reset and must be set 1056 * before relying on anything related to output. There may be 1057 * junk after a (very fast) soft reboot and (apparently) after 1058 * master reset. 1059 * XXX what about the UART bug avoided by waiting in comparam()? 1060 * We don't want to to wait long enough to drain at 2 bps. 1061 */ 1062 if (iobase == siocniobase) 1063 DELAY((16 + 1) * 1000000 / (comdefaultrate / 10)); 1064 else { 1065 sio_setreg(com, com_cfcr, CFCR_DLAB | CFCR_8BITS); 1066 divisor = siodivisor(rclk, SIO_TEST_SPEED); 1067 sio_setreg(com, com_dlbl, divisor & 0xff); 1068 sio_setreg(com, com_dlbh, divisor >> 8); 1069 sio_setreg(com, com_cfcr, CFCR_8BITS); 1070 DELAY((16 + 1) * 1000000 / (SIO_TEST_SPEED / 10)); 1071 } 1072 1073 /* 1074 * Enable the interrupt gate and disable device interupts. This 1075 * should leave the device driving the interrupt line low and 1076 * guarantee an edge trigger if an interrupt can be generated. 1077 */ 1078/* EXTRA DELAY? */ 1079 sio_setreg(com, com_mcr, mcr_image); 1080 sio_setreg(com, com_ier, 0); 1081 DELAY(1000); /* XXX */ 1082 irqmap[0] = isa_irq_pending(); 1083 1084 /* 1085 * Attempt to set loopback mode so that we can send a null byte 1086 * without annoying any external device. 1087 */ 1088/* EXTRA DELAY? */ 1089 sio_setreg(com, com_mcr, mcr_image | MCR_LOOPBACK); 1090 1091 /* 1092 * Attempt to generate an output interrupt. On 8250's, setting 1093 * IER_ETXRDY generates an interrupt independent of the current 1094 * setting and independent of whether the THR is empty. On 16450's, 1095 * setting IER_ETXRDY generates an interrupt independent of the 1096 * current setting. On 16550A's, setting IER_ETXRDY only 1097 * generates an interrupt when IER_ETXRDY is not already set. 1098 */ 1099 sio_setreg(com, com_ier, IER_ETXRDY); 1100#ifdef PC98 1101 if (iod.if_type == COM_IF_RSA98III) 1102 outb(iobase + rsa_ier, 0x04); 1103#endif 1104 1105 /* 1106 * On some 16x50 incompatibles, setting IER_ETXRDY doesn't generate 1107 * an interrupt. They'd better generate one for actually doing 1108 * output. Loopback may be broken on the same incompatibles but 1109 * it's unlikely to do more than allow the null byte out. 1110 */ 1111 sio_setreg(com, com_data, 0); 1112 if (iobase == siocniobase) 1113 DELAY((1 + 2) * 1000000 / (comdefaultrate / 10)); 1114 else 1115 DELAY((1 + 2) * 1000000 / (SIO_TEST_SPEED / 10)); 1116 1117 /* 1118 * Turn off loopback mode so that the interrupt gate works again 1119 * (MCR_IENABLE was hidden). This should leave the device driving 1120 * an interrupt line high. It doesn't matter if the interrupt 1121 * line oscillates while we are not looking at it, since interrupts 1122 * are disabled. 1123 */ 1124/* EXTRA DELAY? */ 1125 sio_setreg(com, com_mcr, mcr_image); 1126 1127 /* 1128 * It seems my Xircom CBEM56G Cardbus modem wants to be reset 1129 * to 8 bits *again*, or else probe test 0 will fail. 1130 * gwk@sgi.com, 4/19/2001 1131 */ 1132 sio_setreg(com, com_cfcr, CFCR_8BITS); 1133 1134 /* 1135 * Some PCMCIA cards (Palido 321s, DC-1S, ...) have the "TXRDY bug", 1136 * so we probe for a buggy IIR_TXRDY implementation even in the 1137 * noprobe case. We don't probe for it in the !noprobe case because 1138 * noprobe is always set for PCMCIA cards and the problem is not 1139 * known to affect any other cards. 1140 */ 1141 if (noprobe) { 1142 /* Read IIR a few times. */ 1143 for (fn = 0; fn < 2; fn ++) { 1144 DELAY(10000); 1145 failures[6] = sio_getreg(com, com_iir); 1146 } 1147 1148 /* IIR_TXRDY should be clear. Is it? */ 1149 result = 0; 1150 if (failures[6] & IIR_TXRDY) { 1151 /* 1152 * No. We seem to have the bug. Does our fix for 1153 * it work? 1154 */ 1155 sio_setreg(com, com_ier, 0); 1156 if (sio_getreg(com, com_iir) & IIR_NOPEND) { 1157 /* Yes. We discovered the TXRDY bug! */ 1158 SET_FLAG(dev, COM_C_IIR_TXRDYBUG); 1159 } else { 1160 /* No. Just fail. XXX */ 1161 result = ENXIO; 1162 sio_setreg(com, com_mcr, 0); 1163 } 1164 } else { 1165 /* Yes. No bug. */ 1166 CLR_FLAG(dev, COM_C_IIR_TXRDYBUG); 1167 } 1168 sio_setreg(com, com_ier, 0); 1169 sio_setreg(com, com_cfcr, CFCR_8BITS); 1170 mtx_unlock_spin(&sio_lock); 1171 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 1172 if (iobase == siocniobase) 1173 result = 0; 1174 if (result != 0) { 1175 device_set_softc(dev, NULL); 1176 free(com, M_DEVBUF); 1177 } 1178 return (result); 1179 } 1180 1181 /* 1182 * Check that 1183 * o the CFCR, IER and MCR in UART hold the values written to them 1184 * (the values happen to be all distinct - this is good for 1185 * avoiding false positive tests from bus echoes). 1186 * o an output interrupt is generated and its vector is correct. 1187 * o the interrupt goes away when the IIR in the UART is read. 1188 */ 1189/* EXTRA DELAY? */ 1190 failures[0] = sio_getreg(com, com_cfcr) - CFCR_8BITS; 1191 failures[1] = sio_getreg(com, com_ier) - IER_ETXRDY; 1192 failures[2] = sio_getreg(com, com_mcr) - mcr_image; 1193 DELAY(10000); /* Some internal modems need this time */ 1194 irqmap[1] = isa_irq_pending(); 1195 failures[4] = (sio_getreg(com, com_iir) & IIR_IMASK) - IIR_TXRDY; 1196#ifdef PC98 1197 if (iod.if_type == COM_IF_RSA98III) 1198 inb(iobase + rsa_srr); 1199#endif 1200 DELAY(1000); /* XXX */ 1201 irqmap[2] = isa_irq_pending(); 1202 failures[6] = (sio_getreg(com, com_iir) & IIR_IMASK) - IIR_NOPEND; 1203#ifdef PC98 1204 if (iod.if_type == COM_IF_RSA98III) 1205 inb(iobase + rsa_srr); 1206#endif 1207 1208 /* 1209 * Turn off all device interrupts and check that they go off properly. 1210 * Leave MCR_IENABLE alone. For ports without a master port, it gates 1211 * the OUT2 output of the UART to 1212 * the ICU input. Closing the gate would give a floating ICU input 1213 * (unless there is another device driving it) and spurious interrupts. 1214 * (On the system that this was first tested on, the input floats high 1215 * and gives a (masked) interrupt as soon as the gate is closed.) 1216 */ 1217 sio_setreg(com, com_ier, 0); 1218 sio_setreg(com, com_cfcr, CFCR_8BITS); /* dummy to avoid bus echo */ 1219 failures[7] = sio_getreg(com, com_ier); 1220#ifdef PC98 1221 if (iod.if_type == COM_IF_RSA98III) 1222 outb(iobase + rsa_ier, 0x00); 1223#endif 1224 DELAY(1000); /* XXX */ 1225 irqmap[3] = isa_irq_pending(); 1226 failures[9] = (sio_getreg(com, com_iir) & IIR_IMASK) - IIR_NOPEND; 1227#ifdef PC98 1228 if (iod.if_type == COM_IF_RSA98III) { 1229 inb(iobase + rsa_srr); 1230 outb(iobase + rsa_frr, 0x00); 1231 } 1232#endif 1233 1234 mtx_unlock_spin(&sio_lock); 1235 1236 irqs = irqmap[1] & ~irqmap[0]; 1237 if (bus_get_resource(idev, SYS_RES_IRQ, 0, &xirq, NULL) == 0 && 1238 ((1 << xirq) & irqs) == 0) { 1239 printf( 1240 "sio%d: configured irq %ld not in bitmap of probed irqs %#x\n", 1241 device_get_unit(dev), xirq, irqs); 1242 printf( 1243 "sio%d: port may not be enabled\n", 1244 device_get_unit(dev)); 1245 } 1246 if (bootverbose) 1247 printf("sio%d: irq maps: %#x %#x %#x %#x\n", 1248 device_get_unit(dev), 1249 irqmap[0], irqmap[1], irqmap[2], irqmap[3]); 1250 1251 result = 0; 1252 for (fn = 0; fn < sizeof failures; ++fn) 1253 if (failures[fn]) { 1254 sio_setreg(com, com_mcr, 0); 1255 result = ENXIO; 1256 if (bootverbose) { 1257 printf("sio%d: probe failed test(s):", 1258 device_get_unit(dev)); 1259 for (fn = 0; fn < sizeof failures; ++fn) 1260 if (failures[fn]) 1261 printf(" %d", fn); 1262 printf("\n"); 1263 } 1264 break; 1265 } 1266 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 1267 if (iobase == siocniobase) 1268 result = 0; 1269 if (result != 0) { 1270 device_set_softc(dev, NULL); 1271 free(com, M_DEVBUF); 1272 } 1273 return (result); 1274} 1275 1276#ifdef COM_ESP 1277static int 1278espattach(com, esp_port) 1279 struct com_s *com; 1280 Port_t esp_port; 1281{ 1282 u_char dips; 1283 u_char val; 1284 1285 /* 1286 * Check the ESP-specific I/O port to see if we're an ESP 1287 * card. If not, return failure immediately. 1288 */ 1289 if ((inb(esp_port) & 0xf3) == 0) { 1290 printf(" port 0x%x is not an ESP board?\n", esp_port); 1291 return (0); 1292 } 1293 1294 /* 1295 * We've got something that claims to be a Hayes ESP card. 1296 * Let's hope so. 1297 */ 1298 1299 /* Get the dip-switch configuration */ 1300#ifdef PC98 1301 outb(esp_port + ESP98_CMD1, ESP_GETDIPS); 1302 dips = inb(esp_port + ESP98_STATUS1); 1303#else 1304 outb(esp_port + ESP_CMD1, ESP_GETDIPS); 1305 dips = inb(esp_port + ESP_STATUS1); 1306#endif 1307 1308 /* 1309 * Bits 0,1 of dips say which COM port we are. 1310 */ 1311#ifdef PC98 1312 if ((rman_get_start(com->ioportres) & 0xff) == 1313 likely_com_ports[dips & 0x03]) 1314#else 1315 if (rman_get_start(com->ioportres) == likely_com_ports[dips & 0x03]) 1316#endif 1317 printf(" : ESP"); 1318 else { 1319 printf(" esp_port has com %d\n", dips & 0x03); 1320 return (0); 1321 } 1322 1323 /* 1324 * Check for ESP version 2.0 or later: bits 4,5,6 = 010. 1325 */ 1326#ifdef PC98 1327 outb(esp_port + ESP98_CMD1, ESP_GETTEST); 1328 val = inb(esp_port + ESP98_STATUS1); /* clear reg 1 */ 1329 val = inb(esp_port + ESP98_STATUS2); 1330#else 1331 outb(esp_port + ESP_CMD1, ESP_GETTEST); 1332 val = inb(esp_port + ESP_STATUS1); /* clear reg 1 */ 1333 val = inb(esp_port + ESP_STATUS2); 1334#endif 1335 if ((val & 0x70) < 0x20) { 1336 printf("-old (%o)", val & 0x70); 1337 return (0); 1338 } 1339 1340 /* 1341 * Check for ability to emulate 16550: bit 7 == 1 1342 */ 1343 if ((dips & 0x80) == 0) { 1344 printf(" slave"); 1345 return (0); 1346 } 1347 1348 /* 1349 * Okay, we seem to be a Hayes ESP card. Whee. 1350 */ 1351 com->esp = TRUE; 1352 com->esp_port = esp_port; 1353 return (1); 1354} 1355#endif /* COM_ESP */ 1356 1357int 1358sioattach(dev, xrid, rclk) 1359 device_t dev; 1360 int xrid; 1361 u_long rclk; 1362{ 1363 struct com_s *com; 1364#ifdef COM_ESP 1365 Port_t *espp; 1366#endif 1367 Port_t iobase; 1368 int unit; 1369 u_int flags; 1370 int rid; 1371 struct resource *port; 1372 int ret; 1373 int error; 1374 struct tty *tp; 1375#ifdef PC98 1376 u_char *obuf; 1377 u_long obufsize; 1378 int if_type = GET_IFTYPE(device_get_flags(dev)); 1379#endif 1380 1381 rid = xrid; 1382#ifdef PC98 1383 if (IS_8251(if_type)) { 1384 port = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid, 1385 RF_ACTIVE); 1386 } else if (if_type == COM_IF_MODEM_CARD || 1387 if_type == COM_IF_RSA98III || 1388 isa_get_vendorid(dev)) { 1389 port = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 0, ~0, 1390 if_16550a_type[if_type & 0x0f].iatsz, RF_ACTIVE); 1391 } else { 1392 port = isa_alloc_resourcev(dev, SYS_RES_IOPORT, &rid, 1393 if_16550a_type[if_type & 0x0f].iat, 1394 if_16550a_type[if_type & 0x0f].iatsz, RF_ACTIVE); 1395 } 1396#else 1397 port = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 1398 0, ~0, IO_COMSIZE, RF_ACTIVE); 1399#endif 1400 if (!port) 1401 return (ENXIO); 1402#ifdef PC98 1403 if (!IS_8251(if_type)) { 1404 if (isa_load_resourcev(port, 1405 if_16550a_type[if_type & 0x0f].iat, 1406 if_16550a_type[if_type & 0x0f].iatsz) != 0) { 1407 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 1408 return ENXIO; 1409 } 1410 } 1411#endif 1412 1413 iobase = rman_get_start(port); 1414 unit = device_get_unit(dev); 1415 com = device_get_softc(dev); 1416 flags = device_get_flags(dev); 1417 1418 if (unit >= sio_numunits) 1419 sio_numunits = unit + 1; 1420 1421#ifdef PC98 1422 obufsize = 256; 1423 if (if_type == COM_IF_RSA98III) 1424 obufsize = 2048; 1425 if ((obuf = malloc(obufsize * 2, M_DEVBUF, M_NOWAIT)) == NULL) { 1426 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 1427 return ENXIO; 1428 } 1429 bzero(obuf, obufsize * 2); 1430#endif 1431 1432 /* 1433 * sioprobe() has initialized the device registers as follows: 1434 * o cfcr = CFCR_8BITS. 1435 * It is most important that CFCR_DLAB is off, so that the 1436 * data port is not hidden when we enable interrupts. 1437 * o ier = 0. 1438 * Interrupts are only enabled when the line is open. 1439 * o mcr = MCR_IENABLE, or 0 if the port has AST/4 compatible 1440 * interrupt control register or the config specifies no irq. 1441 * Keeping MCR_DTR and MCR_RTS off might stop the external 1442 * device from sending before we are ready. 1443 */ 1444 bzero(com, sizeof *com); 1445 com->unit = unit; 1446 com->ioportres = port; 1447 com->ioportrid = rid; 1448 com->bst = rman_get_bustag(port); 1449 com->bsh = rman_get_bushandle(port); 1450 com->cfcr_image = CFCR_8BITS; 1451 com->loses_outints = COM_LOSESOUTINTS(flags) != 0; 1452 com->no_irq = bus_get_resource(dev, SYS_RES_IRQ, 0, NULL, NULL) != 0; 1453 com->tx_fifo_size = 1; 1454#ifdef PC98 1455 com->obufsize = obufsize; 1456 com->obuf1 = obuf; 1457 com->obuf2 = obuf + obufsize; 1458#endif 1459 com->obufs[0].l_head = com->obuf1; 1460 com->obufs[1].l_head = com->obuf2; 1461 1462#ifdef PC98 1463 com->pc98_if_type = if_type; 1464 1465 if (IS_8251(if_type)) { 1466 pc98_set_ioport(com); 1467 1468 if (if_type == COM_IF_INTERNAL && pc98_check_8251fifo()) { 1469 com->pc98_8251fifo = 1; 1470 com->pc98_8251fifo_enable = 0; 1471 } 1472 } else { 1473 bus_addr_t *iat = if_16550a_type[if_type & 0x0f].iat; 1474 1475 com->data_port = iobase + iat[com_data]; 1476 com->int_ctl_port = iobase + iat[com_ier]; 1477 com->int_id_port = iobase + iat[com_iir]; 1478 com->modem_ctl_port = iobase + iat[com_mcr]; 1479 com->mcr_image = inb(com->modem_ctl_port); 1480 com->line_status_port = iobase + iat[com_lsr]; 1481 com->modem_status_port = iobase + iat[com_msr]; 1482 } 1483#else /* not PC98 */ 1484 com->data_port = iobase + com_data; 1485 com->int_ctl_port = iobase + com_ier; 1486 com->int_id_port = iobase + com_iir; 1487 com->modem_ctl_port = iobase + com_mcr; 1488 com->mcr_image = inb(com->modem_ctl_port); 1489 com->line_status_port = iobase + com_lsr; 1490 com->modem_status_port = iobase + com_msr; 1491#endif 1492 1493 tp = com->tp = ttyalloc(); 1494 tp->t_oproc = comstart; 1495 tp->t_param = comparam; 1496 tp->t_stop = comstop; 1497 tp->t_modem = commodem; 1498 tp->t_break = combreak; 1499 tp->t_close = comclose; 1500 tp->t_open = comopen; 1501 tp->t_sc = com; 1502 1503#ifdef PC98 1504 if (!IS_8251(if_type) && rclk == 0) 1505 rclk = if_16550a_type[if_type & 0x0f].rclk; 1506#else 1507 if (rclk == 0) 1508 rclk = DEFAULT_RCLK; 1509#endif 1510 com->rclk = rclk; 1511 1512 if (unit == comconsole) 1513 ttyconsolemode(tp, comdefaultrate); 1514 error = siosetwater(com, tp->t_init_in.c_ispeed); 1515 mtx_unlock_spin(&sio_lock); 1516 if (error) { 1517 /* 1518 * Leave i/o resources allocated if this is a `cn'-level 1519 * console, so that other devices can't snarf them. 1520 */ 1521 if (iobase != siocniobase) 1522 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 1523 return (ENOMEM); 1524 } 1525 1526 /* attempt to determine UART type */ 1527 printf("sio%d: type", unit); 1528 1529#ifndef PC98 1530 if (!COM_ISMULTIPORT(flags) && 1531 !COM_IIR_TXRDYBUG(flags) && !COM_NOSCR(flags)) { 1532 u_char scr; 1533 u_char scr1; 1534 u_char scr2; 1535 1536 scr = sio_getreg(com, com_scr); 1537 sio_setreg(com, com_scr, 0xa5); 1538 scr1 = sio_getreg(com, com_scr); 1539 sio_setreg(com, com_scr, 0x5a); 1540 scr2 = sio_getreg(com, com_scr); 1541 sio_setreg(com, com_scr, scr); 1542 if (scr1 != 0xa5 || scr2 != 0x5a) { 1543 printf(" 8250 or not responding"); 1544 goto determined_type; 1545 } 1546 } 1547#endif /* !PC98 */ 1548#ifdef PC98 1549 if (IS_8251(com->pc98_if_type)) { 1550 if (com->pc98_8251fifo && !COM_NOFIFO(flags)) 1551 com->tx_fifo_size = 16; 1552 com_int_TxRx_disable( com ); 1553 com_cflag_and_speed_set( com, tp->t_init_in.c_cflag, comdefaultrate ); 1554 com_tiocm_bic( com, TIOCM_DTR|TIOCM_RTS|TIOCM_LE ); 1555 com_send_break_off( com ); 1556 1557 if (com->pc98_if_type == COM_IF_INTERNAL) { 1558 printf(" (internal%s%s)", 1559 com->pc98_8251fifo ? " fifo" : "", 1560 PC98SIO_baud_rate_port(com->pc98_if_type) != -1 ? 1561 " v-fast" : ""); 1562 } else { 1563 printf(" 8251%s", if_8251_type[com->pc98_if_type & 0x0f].name); 1564 } 1565 } else { 1566#endif /* PC98 */ 1567 sio_setreg(com, com_fifo, FIFO_ENABLE | FIFO_RX_HIGH); 1568 DELAY(100); 1569 switch (inb(com->int_id_port) & IIR_FIFO_MASK) { 1570 case FIFO_RX_LOW: 1571 printf(" 16450"); 1572 break; 1573 case FIFO_RX_MEDL: 1574 printf(" 16450?"); 1575 break; 1576 case FIFO_RX_MEDH: 1577 printf(" 16550?"); 1578 break; 1579 case FIFO_RX_HIGH: 1580 if (COM_NOFIFO(flags)) { 1581 printf(" 16550A fifo disabled"); 1582 break; 1583 } 1584 com->hasfifo = TRUE; 1585#ifdef PC98 1586 if (com->pc98_if_type == COM_IF_RSA98III) { 1587 com->tx_fifo_size = 2048; 1588 com->rsabase = iobase; 1589 outb(com->rsabase + rsa_ier, 0x00); 1590 outb(com->rsabase + rsa_frr, 0x00); 1591 } 1592#else 1593 if (COM_ST16650A(flags)) { 1594 printf(" ST16650A"); 1595 com->st16650a = TRUE; 1596 com->tx_fifo_size = 32; 1597 break; 1598 } 1599 if (COM_TI16754(flags)) { 1600 printf(" TI16754"); 1601 com->tx_fifo_size = 64; 1602 break; 1603 } 1604#endif 1605 printf(" 16550A"); 1606#ifdef COM_ESP 1607#ifdef PC98 1608 if (com->pc98_if_type == COM_IF_ESP98) 1609#endif 1610 for (espp = likely_esp_ports; *espp != 0; espp++) 1611 if (espattach(com, *espp)) { 1612 com->tx_fifo_size = 1024; 1613 break; 1614 } 1615 if (com->esp) 1616 break; 1617#endif 1618#ifdef PC98 1619 com->tx_fifo_size = 16; 1620#else 1621 com->tx_fifo_size = COM_FIFOSIZE(flags); 1622 if (com->tx_fifo_size == 0) 1623 com->tx_fifo_size = 16; 1624 else 1625 printf(" lookalike with %u bytes FIFO", 1626 com->tx_fifo_size); 1627#endif 1628 break; 1629 } 1630 1631#ifdef PC98 1632 if (com->pc98_if_type == COM_IF_RSB3000) { 1633 /* Set RSB-2000/3000 Extended Buffer mode. */ 1634 u_char lcr; 1635 lcr = sio_getreg(com, com_cfcr); 1636 sio_setreg(com, com_cfcr, lcr | CFCR_DLAB); 1637 sio_setreg(com, com_emr, EMR_EXBUFF | EMR_EFMODE); 1638 sio_setreg(com, com_cfcr, lcr); 1639 } 1640#endif 1641 1642#ifdef COM_ESP 1643 if (com->esp) { 1644 /* 1645 * Set 16550 compatibility mode. 1646 * We don't use the ESP_MODE_SCALE bit to increase the 1647 * fifo trigger levels because we can't handle large 1648 * bursts of input. 1649 * XXX flow control should be set in comparam(), not here. 1650 */ 1651#ifdef PC98 1652 outb(com->esp_port + ESP98_CMD1, ESP_SETMODE); 1653 outb(com->esp_port + ESP98_CMD2, ESP_MODE_RTS | ESP_MODE_FIFO); 1654#else 1655 outb(com->esp_port + ESP_CMD1, ESP_SETMODE); 1656 outb(com->esp_port + ESP_CMD2, ESP_MODE_RTS | ESP_MODE_FIFO); 1657#endif 1658 1659 /* Set RTS/CTS flow control. */ 1660#ifdef PC98 1661 outb(com->esp_port + ESP98_CMD1, ESP_SETFLOWTYPE); 1662 outb(com->esp_port + ESP98_CMD2, ESP_FLOW_RTS); 1663 outb(com->esp_port + ESP98_CMD2, ESP_FLOW_CTS); 1664#else 1665 outb(com->esp_port + ESP_CMD1, ESP_SETFLOWTYPE); 1666 outb(com->esp_port + ESP_CMD2, ESP_FLOW_RTS); 1667 outb(com->esp_port + ESP_CMD2, ESP_FLOW_CTS); 1668#endif 1669 1670 /* Set flow-control levels. */ 1671#ifdef PC98 1672 outb(com->esp_port + ESP98_CMD1, ESP_SETRXFLOW); 1673 outb(com->esp_port + ESP98_CMD2, HIBYTE(768)); 1674 outb(com->esp_port + ESP98_CMD2, LOBYTE(768)); 1675 outb(com->esp_port + ESP98_CMD2, HIBYTE(512)); 1676 outb(com->esp_port + ESP98_CMD2, LOBYTE(512)); 1677#else 1678 outb(com->esp_port + ESP_CMD1, ESP_SETRXFLOW); 1679 outb(com->esp_port + ESP_CMD2, HIBYTE(768)); 1680 outb(com->esp_port + ESP_CMD2, LOBYTE(768)); 1681 outb(com->esp_port + ESP_CMD2, HIBYTE(512)); 1682 outb(com->esp_port + ESP_CMD2, LOBYTE(512)); 1683#endif 1684 1685#ifdef PC98 1686 /* Set UART clock prescaler. */ 1687 outb(com->esp_port + ESP98_CMD1, ESP_SETCLOCK); 1688 outb(com->esp_port + ESP98_CMD2, 2); /* 4 times */ 1689#endif 1690 } 1691#endif /* COM_ESP */ 1692 sio_setreg(com, com_fifo, 0); 1693#ifdef PC98 1694 printf("%s", if_16550a_type[com->pc98_if_type & 0x0f].name); 1695#else 1696determined_type: ; 1697#endif 1698 1699#ifdef COM_MULTIPORT 1700 if (COM_ISMULTIPORT(flags)) { 1701 device_t masterdev; 1702 1703 com->multiport = TRUE; 1704 printf(" (multiport"); 1705 if (unit == COM_MPMASTER(flags)) 1706 printf(" master"); 1707 printf(")"); 1708 masterdev = devclass_get_device(sio_devclass, 1709 COM_MPMASTER(flags)); 1710 com->no_irq = (masterdev == NULL || bus_get_resource(masterdev, 1711 SYS_RES_IRQ, 0, NULL, NULL) != 0); 1712 } 1713#endif /* COM_MULTIPORT */ 1714#ifdef PC98 1715 } 1716#endif 1717 if (unit == comconsole) 1718 printf(", console"); 1719 if (COM_IIR_TXRDYBUG(flags)) 1720 printf(" with a buggy IIR_TXRDY implementation"); 1721 printf("\n"); 1722 1723 if (sio_fast_ih == NULL) { 1724 swi_add(&tty_ithd, "sio", siopoll, NULL, SWI_TTY, 0, 1725 &sio_fast_ih); 1726 swi_add(&clk_ithd, "sio", siopoll, NULL, SWI_CLOCK, 0, 1727 &sio_slow_ih); 1728 } 1729 1730 com->flags = flags; 1731 com->pps.ppscap = PPS_CAPTUREASSERT | PPS_CAPTURECLEAR; 1732 tp->t_pps = &com->pps; 1733 1734 if (COM_PPSCTS(flags)) 1735 com->pps_bit = MSR_CTS; 1736 else 1737 com->pps_bit = MSR_DCD; 1738 pps_init(&com->pps); 1739 1740 rid = 0; 1741 com->irqres = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, RF_ACTIVE); 1742 if (com->irqres) { 1743 ret = BUS_SETUP_INTR(device_get_parent(dev), dev, com->irqres, 1744 INTR_TYPE_TTY | INTR_FAST, 1745 siointr, com, &com->cookie); 1746 if (ret) { 1747 ret = BUS_SETUP_INTR(device_get_parent(dev), dev, 1748 com->irqres, INTR_TYPE_TTY, 1749 siointr, com, &com->cookie); 1750 if (ret == 0) 1751 device_printf(dev, "unable to activate interrupt in fast mode - using normal mode\n"); 1752 } 1753 if (ret) 1754 device_printf(dev, "could not activate interrupt\n"); 1755#if defined(KDB) && (defined(BREAK_TO_DEBUGGER) || \ 1756 defined(ALT_BREAK_TO_DEBUGGER)) 1757 /* 1758 * Enable interrupts for early break-to-debugger support 1759 * on the console. 1760 */ 1761 if (ret == 0 && unit == comconsole) 1762 outb(siocniobase + com_ier, IER_ERXRDY | IER_ERLS | 1763 IER_EMSC); 1764#endif 1765 } 1766 1767 /* We're ready, open the doors... */ 1768 ttycreate(tp, NULL, unit, MINOR_CALLOUT, "d%r", unit); 1769 1770 return (0); 1771} 1772 1773static int 1774comopen(struct tty *tp, struct cdev *dev) 1775{ 1776 struct com_s *com; 1777 int i; 1778 1779 com = tp->t_sc; 1780 com->poll = com->no_irq; 1781 com->poll_output = com->loses_outints; 1782#ifdef PC98 1783 if (IS_8251(com->pc98_if_type)) { 1784 com_tiocm_bis(com, TIOCM_DTR|TIOCM_RTS); 1785 pc98_msrint_start(dev); 1786 if (com->pc98_8251fifo) { 1787 com->pc98_8251fifo_enable = 1; 1788 outb(I8251F_fcr, CTRL8251F_ENABLE | 1789 CTRL8251F_XMT_RST | CTRL8251F_RCV_RST); 1790 } 1791 } 1792#endif 1793 if (com->hasfifo) { 1794 /* 1795 * (Re)enable and drain fifos. 1796 * 1797 * Certain SMC chips cause problems if the fifos 1798 * are enabled while input is ready. Turn off the 1799 * fifo if necessary to clear the input. We test 1800 * the input ready bit after enabling the fifos 1801 * since we've already enabled them in comparam() 1802 * and to handle races between enabling and fresh 1803 * input. 1804 */ 1805 for (i = 0; i < 500; i++) { 1806 sio_setreg(com, com_fifo, 1807 FIFO_RCV_RST | FIFO_XMT_RST 1808 | com->fifo_image); 1809#ifdef PC98 1810 if (com->pc98_if_type == COM_IF_RSA98III) 1811 outb(com->rsabase + rsa_frr , 0x00); 1812#endif 1813 /* 1814 * XXX the delays are for superstitious 1815 * historical reasons. It must be less than 1816 * the character time at the maximum 1817 * supported speed (87 usec at 115200 bps 1818 * 8N1). Otherwise we might loop endlessly 1819 * if data is streaming in. We used to use 1820 * delays of 100. That usually worked 1821 * because DELAY(100) used to usually delay 1822 * for about 85 usec instead of 100. 1823 */ 1824 DELAY(50); 1825#ifdef PC98 1826 if (com->pc98_if_type == COM_IF_RSA98III ? 1827 !(inb(com->rsabase + rsa_srr) & 0x08) : 1828 !(inb(com->line_status_port) & LSR_RXRDY)) 1829 break; 1830#else 1831 if (!(inb(com->line_status_port) & LSR_RXRDY)) 1832 break; 1833#endif 1834 sio_setreg(com, com_fifo, 0); 1835 DELAY(50); 1836 (void) inb(com->data_port); 1837 } 1838 if (i == 500) 1839 return (EIO); 1840 } 1841 1842 mtx_lock_spin(&sio_lock); 1843#ifdef PC98 1844 if (IS_8251(com->pc98_if_type)) { 1845 com_tiocm_bis(com, TIOCM_LE); 1846 com->pc98_prev_modem_status = pc98_get_modem_status(com); 1847 com_int_Rx_enable(com); 1848 } else { 1849#endif 1850 (void) inb(com->line_status_port); 1851 (void) inb(com->data_port); 1852 com->prev_modem_status = com->last_modem_status 1853 = inb(com->modem_status_port); 1854 outb(com->int_ctl_port, 1855 IER_ERXRDY | IER_ERLS | IER_EMSC 1856 | (COM_IIR_TXRDYBUG(com->flags) ? 0 : IER_ETXRDY)); 1857#ifdef PC98 1858 if (com->pc98_if_type == COM_IF_RSA98III) { 1859 outb(com->rsabase + rsa_ier, 0x1d); 1860 outb(com->int_ctl_port, IER_ERLS | IER_EMSC); 1861 } 1862#endif 1863#ifdef PC98 1864 } 1865#endif 1866 mtx_unlock_spin(&sio_lock); 1867 siosettimeout(); 1868 /* XXX: should be generic ? */ 1869#ifdef PC98 1870 if ((IS_8251(com->pc98_if_type) && 1871 (pc98_get_modem_status(com) & TIOCM_CAR)) || 1872 (!IS_8251(com->pc98_if_type) && 1873 (com->prev_modem_status & MSR_DCD)) || 1874 ISCALLOUT(dev)) 1875 ttyld_modem(tp, 1); 1876#else 1877 if (com->prev_modem_status & MSR_DCD || ISCALLOUT(dev)) 1878 ttyld_modem(tp, 1); 1879#endif 1880 return (0); 1881} 1882 1883static void 1884comclose(tp) 1885 struct tty *tp; 1886{ 1887 int s; 1888 struct com_s *com; 1889 1890 s = spltty(); 1891 com = tp->t_sc; 1892 com->poll = FALSE; 1893 com->poll_output = FALSE; 1894#ifdef PC98 1895 com_send_break_off(com); 1896#else 1897 sio_setreg(com, com_cfcr, com->cfcr_image &= ~CFCR_SBREAK); 1898#endif 1899 1900#if defined(KDB) && (defined(BREAK_TO_DEBUGGER) || \ 1901 defined(ALT_BREAK_TO_DEBUGGER)) 1902 /* 1903 * Leave interrupts enabled and don't clear DTR if this is the 1904 * console. This allows us to detect break-to-debugger events 1905 * while the console device is closed. 1906 */ 1907 if (com->unit != comconsole) 1908#endif 1909 { 1910#ifdef PC98 1911 int tmp; 1912 if (IS_8251(com->pc98_if_type)) 1913 com_int_TxRx_disable(com); 1914 else 1915 sio_setreg(com, com_ier, 0); 1916 if (com->pc98_if_type == COM_IF_RSA98III) 1917 outb(com->rsabase + rsa_ier, 0x00); 1918 if (IS_8251(com->pc98_if_type)) 1919 tmp = pc98_get_modem_status(com) & TIOCM_CAR; 1920 else 1921 tmp = com->prev_modem_status & MSR_DCD; 1922#else 1923 sio_setreg(com, com_ier, 0); 1924#endif 1925 if (tp->t_cflag & HUPCL 1926 /* 1927 * XXX we will miss any carrier drop between here and the 1928 * next open. Perhaps we should watch DCD even when the 1929 * port is closed; it is not sufficient to check it at 1930 * the next open because it might go up and down while 1931 * we're not watching. 1932 */ 1933 || (!tp->t_actout 1934#ifdef PC98 1935 && !(tmp) 1936#else 1937 && !(com->prev_modem_status & MSR_DCD) 1938#endif 1939 && !(tp->t_init_in.c_cflag & CLOCAL)) 1940 || !(tp->t_state & TS_ISOPEN)) { 1941#ifdef PC98 1942 if (IS_8251(com->pc98_if_type)) 1943 com_tiocm_bic(com, TIOCM_DTR|TIOCM_RTS|TIOCM_LE); 1944 else 1945#endif 1946 (void)commodem(tp, 0, SER_DTR); 1947 ttydtrwaitstart(tp); 1948 } 1949#ifdef PC98 1950 else { 1951 if (IS_8251(com->pc98_if_type)) 1952 com_tiocm_bic(com, TIOCM_LE); 1953 } 1954#endif 1955 } 1956#ifdef PC98 1957 if (com->pc98_8251fifo) { 1958 if (com->pc98_8251fifo_enable) 1959 outb(I8251F_fcr, CTRL8251F_XMT_RST | CTRL8251F_RCV_RST); 1960 com->pc98_8251fifo_enable = 0; 1961 } 1962#endif 1963 if (com->hasfifo) { 1964 /* 1965 * Disable fifos so that they are off after controlled 1966 * reboots. Some BIOSes fail to detect 16550s when the 1967 * fifos are enabled. 1968 */ 1969 sio_setreg(com, com_fifo, 0); 1970 } 1971 tp->t_actout = FALSE; 1972 wakeup(&tp->t_actout); 1973 wakeup(TSA_CARR_ON(tp)); /* restart any wopeners */ 1974 siosettimeout(); 1975 splx(s); 1976} 1977 1978static void 1979siobusycheck(chan) 1980 void *chan; 1981{ 1982 struct com_s *com; 1983 int s; 1984 1985 com = (struct com_s *)chan; 1986 1987 /* 1988 * Clear TS_BUSY if low-level output is complete. 1989 * spl locking is sufficient because siointr1() does not set CS_BUSY. 1990 * If siointr1() clears CS_BUSY after we look at it, then we'll get 1991 * called again. Reading the line status port outside of siointr1() 1992 * is safe because CS_BUSY is clear so there are no output interrupts 1993 * to lose. 1994 */ 1995 s = spltty(); 1996 if (com->state & CS_BUSY) 1997 com->extra_state &= ~CSE_BUSYCHECK; /* False alarm. */ 1998#ifdef PC98 1999 else if ((IS_8251(com->pc98_if_type) && 2000 ((com->pc98_8251fifo_enable && 2001 (inb(I8251F_lsr) & (STS8251F_TxRDY | STS8251F_TxEMP)) 2002 == (STS8251F_TxRDY | STS8251F_TxEMP)) || 2003 (!com->pc98_8251fifo_enable && 2004 (inb(com->sts_port) & (STS8251_TxRDY | STS8251_TxEMP)) 2005 == (STS8251_TxRDY | STS8251_TxEMP)))) || 2006 ((inb(com->line_status_port) & (LSR_TSRE | LSR_TXRDY)) 2007 == (LSR_TSRE | LSR_TXRDY))) { 2008#else 2009 else if ((inb(com->line_status_port) & (LSR_TSRE | LSR_TXRDY)) 2010 == (LSR_TSRE | LSR_TXRDY)) { 2011#endif 2012 com->tp->t_state &= ~TS_BUSY; 2013 ttwwakeup(com->tp); 2014 com->extra_state &= ~CSE_BUSYCHECK; 2015 } else 2016 timeout(siobusycheck, com, hz / 100); 2017 splx(s); 2018} 2019 2020static u_int 2021siodivisor(rclk, speed) 2022 u_long rclk; 2023 speed_t speed; 2024{ 2025 long actual_speed; 2026 u_int divisor; 2027 int error; 2028 2029 if (speed == 0) 2030 return (0); 2031#if UINT_MAX > (ULONG_MAX - 1) / 8 2032 if (speed > (ULONG_MAX - 1) / 8) 2033 return (0); 2034#endif 2035 divisor = (rclk / (8UL * speed) + 1) / 2; 2036 if (divisor == 0 || divisor >= 65536) 2037 return (0); 2038 actual_speed = rclk / (16UL * divisor); 2039 2040 /* 10 times error in percent: */ 2041 error = ((actual_speed - (long)speed) * 2000 / (long)speed + 1) / 2; 2042 2043 /* 3.0% maximum error tolerance: */ 2044 if (error < -30 || error > 30) 2045 return (0); 2046 2047 return (divisor); 2048} 2049 2050/* 2051 * Call this function with the sio_lock mutex held. It will return with the 2052 * lock still held. 2053 */ 2054static void 2055sioinput(com) 2056 struct com_s *com; 2057{ 2058 u_char *buf; 2059 int incc; 2060 u_char line_status; 2061 int recv_data; 2062 struct tty *tp; 2063 2064 buf = com->ibuf; 2065 tp = com->tp; 2066 if (!(tp->t_state & TS_ISOPEN) || !(tp->t_cflag & CREAD)) { 2067 com_events -= (com->iptr - com->ibuf); 2068 com->iptr = com->ibuf; 2069 return; 2070 } 2071 if (tp->t_state & TS_CAN_BYPASS_L_RINT) { 2072 /* 2073 * Avoid the grotesquely inefficient lineswitch routine 2074 * (ttyinput) in "raw" mode. It usually takes about 450 2075 * instructions (that's without canonical processing or echo!). 2076 * slinput is reasonably fast (usually 40 instructions plus 2077 * call overhead). 2078 */ 2079 do { 2080 /* 2081 * This may look odd, but it is using save-and-enable 2082 * semantics instead of the save-and-disable semantics 2083 * that are used everywhere else. 2084 */ 2085 mtx_unlock_spin(&sio_lock); 2086 incc = com->iptr - buf; 2087 if (tp->t_rawq.c_cc + incc > tp->t_ihiwat 2088 && (com->state & CS_RTS_IFLOW 2089 || tp->t_iflag & IXOFF) 2090 && !(tp->t_state & TS_TBLOCK)) 2091 ttyblock(tp); 2092 com->delta_error_counts[CE_TTY_BUF_OVERFLOW] 2093 += b_to_q((char *)buf, incc, &tp->t_rawq); 2094 buf += incc; 2095 tk_nin += incc; 2096 tk_rawcc += incc; 2097 tp->t_rawcc += incc; 2098 ttwakeup(tp); 2099 if (tp->t_state & TS_TTSTOP 2100 && (tp->t_iflag & IXANY 2101 || tp->t_cc[VSTART] == tp->t_cc[VSTOP])) { 2102 tp->t_state &= ~TS_TTSTOP; 2103 tp->t_lflag &= ~FLUSHO; 2104 comstart(tp); 2105 } 2106 mtx_lock_spin(&sio_lock); 2107 } while (buf < com->iptr); 2108 } else { 2109 do { 2110 /* 2111 * This may look odd, but it is using save-and-enable 2112 * semantics instead of the save-and-disable semantics 2113 * that are used everywhere else. 2114 */ 2115 mtx_unlock_spin(&sio_lock); 2116 line_status = buf[com->ierroff]; 2117 recv_data = *buf++; 2118 if (line_status 2119 & (LSR_BI | LSR_FE | LSR_OE | LSR_PE)) { 2120 if (line_status & LSR_BI) 2121 recv_data |= TTY_BI; 2122 if (line_status & LSR_FE) 2123 recv_data |= TTY_FE; 2124 if (line_status & LSR_OE) 2125 recv_data |= TTY_OE; 2126 if (line_status & LSR_PE) 2127 recv_data |= TTY_PE; 2128 } 2129 ttyld_rint(tp, recv_data); 2130 mtx_lock_spin(&sio_lock); 2131 } while (buf < com->iptr); 2132 } 2133 com_events -= (com->iptr - com->ibuf); 2134 com->iptr = com->ibuf; 2135 2136 /* 2137 * There is now room for another low-level buffer full of input, 2138 * so enable RTS if it is now disabled and there is room in the 2139 * high-level buffer. 2140 */ 2141#ifdef PC98 2142 if (IS_8251(com->pc98_if_type)) { 2143 if ((com->state & CS_RTS_IFLOW) && 2144 !(com_tiocm_get(com) & TIOCM_RTS) && 2145 !(tp->t_state & TS_TBLOCK)) 2146 com_tiocm_bis(com, TIOCM_RTS); 2147 } else { 2148 if ((com->state & CS_RTS_IFLOW) && 2149 !(com->mcr_image & MCR_RTS) && 2150 !(tp->t_state & TS_TBLOCK)) 2151 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS); 2152 } 2153#else 2154 if ((com->state & CS_RTS_IFLOW) && !(com->mcr_image & MCR_RTS) && 2155 !(tp->t_state & TS_TBLOCK)) 2156 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS); 2157#endif 2158} 2159 2160static void 2161siointr(arg) 2162 void *arg; 2163{ 2164 struct com_s *com; 2165#if defined(PC98) && defined(COM_MULTIPORT) 2166 u_char rsa_buf_status; 2167#endif 2168 2169#ifndef COM_MULTIPORT 2170 com = (struct com_s *)arg; 2171 2172 mtx_lock_spin(&sio_lock); 2173 siointr1(com); 2174 mtx_unlock_spin(&sio_lock); 2175#else /* COM_MULTIPORT */ 2176 bool_t possibly_more_intrs; 2177 int unit; 2178 2179 /* 2180 * Loop until there is no activity on any port. This is necessary 2181 * to get an interrupt edge more than to avoid another interrupt. 2182 * If the IRQ signal is just an OR of the IRQ signals from several 2183 * devices, then the edge from one may be lost because another is 2184 * on. 2185 */ 2186 mtx_lock_spin(&sio_lock); 2187 do { 2188 possibly_more_intrs = FALSE; 2189 for (unit = 0; unit < sio_numunits; ++unit) { 2190 com = com_addr(unit); 2191 /* 2192 * XXX COM_LOCK(); 2193 * would it work here, or be counter-productive? 2194 */ 2195#ifdef PC98 2196 if (com != NULL 2197 && !com->gone 2198 && IS_8251(com->pc98_if_type)) { 2199 siointr1(com); 2200 } else if (com != NULL 2201 && !com->gone 2202 && com->pc98_if_type == COM_IF_RSA98III) { 2203 rsa_buf_status = 2204 inb(com->rsabase + rsa_srr) & 0xc9; 2205 if ((rsa_buf_status & 0xc8) 2206 || !(rsa_buf_status & 0x01)) { 2207 siointr1(com); 2208 if (rsa_buf_status != 2209 (inb(com->rsabase + rsa_srr) & 0xc9)) 2210 possibly_more_intrs = TRUE; 2211 } 2212 } else 2213#endif 2214 if (com != NULL 2215 && !com->gone 2216 && (inb(com->int_id_port) & IIR_IMASK) 2217 != IIR_NOPEND) { 2218 siointr1(com); 2219 possibly_more_intrs = TRUE; 2220 } 2221 /* XXX COM_UNLOCK(); */ 2222 } 2223 } while (possibly_more_intrs); 2224 mtx_unlock_spin(&sio_lock); 2225#endif /* COM_MULTIPORT */ 2226} 2227 2228static struct timespec siots[8]; 2229static int siotso; 2230static int volatile siotsunit = -1; 2231 2232static int 2233sysctl_siots(SYSCTL_HANDLER_ARGS) 2234{ 2235 char buf[128]; 2236 long long delta; 2237 size_t len; 2238 int error, i, tso; 2239 2240 for (i = 1, tso = siotso; i < tso; i++) { 2241 delta = (long long)(siots[i].tv_sec - siots[i - 1].tv_sec) * 2242 1000000000 + 2243 (siots[i].tv_nsec - siots[i - 1].tv_nsec); 2244 len = sprintf(buf, "%lld\n", delta); 2245 if (delta >= 110000) 2246 len += sprintf(buf + len - 1, ": *** %ld.%09ld\n", 2247 (long)siots[i].tv_sec, siots[i].tv_nsec) - 1; 2248 if (i == tso - 1) 2249 buf[len - 1] = '\0'; 2250 error = SYSCTL_OUT(req, buf, len); 2251 if (error != 0) 2252 return (error); 2253 uio_yield(); 2254 } 2255 return (0); 2256} 2257 2258SYSCTL_PROC(_machdep, OID_AUTO, siots, CTLTYPE_STRING | CTLFLAG_RD, 2259 0, 0, sysctl_siots, "A", "sio timestamps"); 2260 2261static void 2262siointr1(com) 2263 struct com_s *com; 2264{ 2265 u_char int_ctl; 2266 u_char int_ctl_new; 2267 u_char line_status; 2268 u_char modem_status; 2269 u_char *ioptr; 2270 u_char recv_data; 2271 2272#ifdef PC98 2273 u_char tmp = 0; 2274 u_char rsa_buf_status = 0; 2275 int rsa_tx_fifo_size = 0; 2276#endif /* PC98 */ 2277 2278 if (COM_IIR_TXRDYBUG(com->flags)) { 2279 int_ctl = inb(com->int_ctl_port); 2280 int_ctl_new = int_ctl; 2281 } else { 2282 int_ctl = 0; 2283 int_ctl_new = 0; 2284 } 2285 2286 while (!com->gone) { 2287#ifdef PC98 2288status_read:; 2289 if (IS_8251(com->pc98_if_type)) { 2290 if (com->pc98_8251fifo_enable) 2291 tmp = inb(I8251F_lsr); 2292 else 2293 tmp = inb(com->sts_port); 2294more_intr: 2295 line_status = 0; 2296 if (com->pc98_8251fifo_enable) { 2297 if (tmp & STS8251F_TxRDY) line_status |= LSR_TXRDY; 2298 if (tmp & STS8251F_RxRDY) line_status |= LSR_RXRDY; 2299 if (tmp & STS8251F_TxEMP) line_status |= LSR_TSRE; 2300 if (tmp & STS8251F_PE) line_status |= LSR_PE; 2301 if (tmp & STS8251F_OE) line_status |= LSR_OE; 2302 if (tmp & STS8251F_BD_SD) line_status |= LSR_BI; 2303 } else { 2304 if (tmp & STS8251_TxRDY) line_status |= LSR_TXRDY; 2305 if (tmp & STS8251_RxRDY) line_status |= LSR_RXRDY; 2306 if (tmp & STS8251_TxEMP) line_status |= LSR_TSRE; 2307 if (tmp & STS8251_PE) line_status |= LSR_PE; 2308 if (tmp & STS8251_OE) line_status |= LSR_OE; 2309 if (tmp & STS8251_FE) line_status |= LSR_FE; 2310 if (tmp & STS8251_BD_SD) line_status |= LSR_BI; 2311 } 2312 } else { 2313#endif /* PC98 */ 2314 if (com->pps.ppsparam.mode & PPS_CAPTUREBOTH) { 2315 modem_status = inb(com->modem_status_port); 2316 if ((modem_status ^ com->last_modem_status) & 2317 com->pps_bit) { 2318 pps_capture(&com->pps); 2319 pps_event(&com->pps, 2320 (modem_status & com->pps_bit) ? 2321 PPS_CAPTUREASSERT : PPS_CAPTURECLEAR); 2322 } 2323 } 2324 line_status = inb(com->line_status_port); 2325#ifdef PC98 2326 } 2327 if (com->pc98_if_type == COM_IF_RSA98III) 2328 rsa_buf_status = inb(com->rsabase + rsa_srr); 2329#endif /* PC98 */ 2330 2331 /* input event? (check first to help avoid overruns) */ 2332#ifndef PC98 2333 while (line_status & LSR_RCV_MASK) { 2334#else 2335 while ((line_status & LSR_RCV_MASK) 2336 || (com->pc98_if_type == COM_IF_RSA98III 2337 && (rsa_buf_status & 0x08))) { 2338#endif /* PC98 */ 2339 /* break/unnattached error bits or real input? */ 2340#ifdef PC98 2341 if (IS_8251(com->pc98_if_type)) { 2342 if (com->pc98_8251fifo_enable) { 2343 recv_data = inb(I8251F_data); 2344 if (tmp & (STS8251F_PE | STS8251F_OE | 2345 STS8251F_BD_SD)) { 2346 pc98_i8251_or_cmd(com, CMD8251_ER); 2347 recv_data = 0; 2348 } 2349 } else { 2350 recv_data = inb(com->data_port); 2351 if (tmp & (STS8251_PE | STS8251_OE | 2352 STS8251_FE | STS8251_BD_SD)) { 2353 pc98_i8251_or_cmd(com, CMD8251_ER); 2354 recv_data = 0; 2355 } 2356 } 2357 } else if (com->pc98_if_type == COM_IF_RSA98III) { 2358 if (!(rsa_buf_status & 0x08)) 2359 recv_data = 0; 2360 else 2361 recv_data = inb(com->data_port); 2362 } else 2363#endif 2364 if (!(line_status & LSR_RXRDY)) 2365 recv_data = 0; 2366 else 2367 recv_data = inb(com->data_port); 2368#ifdef KDB 2369#ifdef ALT_BREAK_TO_DEBUGGER 2370 if (com->unit == comconsole && 2371 kdb_alt_break(recv_data, &com->alt_brk_state) != 0) 2372 kdb_enter("Break sequence on console"); 2373#endif /* ALT_BREAK_TO_DEBUGGER */ 2374#endif /* KDB */ 2375 if (line_status & (LSR_BI | LSR_FE | LSR_PE)) { 2376 /* 2377 * Don't store BI if IGNBRK or FE/PE if IGNPAR. 2378 * Otherwise, push the work to a higher level 2379 * (to handle PARMRK) if we're bypassing. 2380 * Otherwise, convert BI/FE and PE+INPCK to 0. 2381 * 2382 * This makes bypassing work right in the 2383 * usual "raw" case (IGNBRK set, and IGNPAR 2384 * and INPCK clear). 2385 * 2386 * Note: BI together with FE/PE means just BI. 2387 */ 2388 if (line_status & LSR_BI) { 2389#if defined(KDB) && defined(BREAK_TO_DEBUGGER) 2390 if (com->unit == comconsole) { 2391 kdb_enter("Line break on console"); 2392 goto cont; 2393 } 2394#endif 2395 if (com->tp == NULL 2396 || com->tp->t_iflag & IGNBRK) 2397 goto cont; 2398 } else { 2399 if (com->tp == NULL 2400 || com->tp->t_iflag & IGNPAR) 2401 goto cont; 2402 } 2403 if (com->tp->t_state & TS_CAN_BYPASS_L_RINT 2404 && (line_status & (LSR_BI | LSR_FE) 2405 || com->tp->t_iflag & INPCK)) 2406 recv_data = 0; 2407 } 2408 ++com->bytes_in; 2409 if (com->tp != NULL && 2410 com->tp->t_hotchar != 0 && recv_data == com->tp->t_hotchar) 2411 swi_sched(sio_fast_ih, 0); 2412 ioptr = com->iptr; 2413 if (ioptr >= com->ibufend) 2414 CE_RECORD(com, CE_INTERRUPT_BUF_OVERFLOW); 2415 else { 2416 if (com->tp != NULL && com->tp->t_do_timestamp) 2417 microtime(&com->tp->t_timestamp); 2418 ++com_events; 2419 swi_sched(sio_slow_ih, SWI_DELAY); 2420#if 0 /* for testing input latency vs efficiency */ 2421if (com->iptr - com->ibuf == 8) 2422 swi_sched(sio_fast_ih, 0); 2423#endif 2424 ioptr[0] = recv_data; 2425 ioptr[com->ierroff] = line_status; 2426 com->iptr = ++ioptr; 2427 if (ioptr == com->ihighwater 2428 && com->state & CS_RTS_IFLOW) 2429#ifdef PC98 2430 IS_8251(com->pc98_if_type) ? 2431 com_tiocm_bic(com, TIOCM_RTS) : 2432#endif 2433 outb(com->modem_ctl_port, 2434 com->mcr_image &= ~MCR_RTS); 2435 if (line_status & LSR_OE) 2436 CE_RECORD(com, CE_OVERRUN); 2437 } 2438cont: 2439 if (line_status & LSR_TXRDY 2440 && com->state >= (CS_BUSY | CS_TTGO | CS_ODEVREADY)) 2441 goto txrdy; 2442 2443 /* 2444 * "& 0x7F" is to avoid the gcc-1.40 generating a slow 2445 * jump from the top of the loop to here 2446 */ 2447#ifdef PC98 2448 if (IS_8251(com->pc98_if_type)) 2449 goto status_read; 2450 else 2451#endif 2452 line_status = inb(com->line_status_port) & 0x7F; 2453#ifdef PC98 2454 if (com->pc98_if_type == COM_IF_RSA98III) 2455 rsa_buf_status = inb(com->rsabase + rsa_srr); 2456#endif /* PC98 */ 2457 } 2458 2459 /* modem status change? (always check before doing output) */ 2460#ifdef PC98 2461 if (!IS_8251(com->pc98_if_type)) { 2462#endif 2463 modem_status = inb(com->modem_status_port); 2464 if (modem_status != com->last_modem_status) { 2465 /* 2466 * Schedule high level to handle DCD changes. Note 2467 * that we don't use the delta bits anywhere. Some 2468 * UARTs mess them up, and it's easy to remember the 2469 * previous bits and calculate the delta. 2470 */ 2471 com->last_modem_status = modem_status; 2472 if (!(com->state & CS_CHECKMSR)) { 2473 com_events += LOTS_OF_EVENTS; 2474 com->state |= CS_CHECKMSR; 2475 swi_sched(sio_fast_ih, 0); 2476 } 2477 2478 /* handle CTS change immediately for crisp flow ctl */ 2479 if (com->state & CS_CTS_OFLOW) { 2480 if (modem_status & MSR_CTS) 2481 com->state |= CS_ODEVREADY; 2482 else 2483 com->state &= ~CS_ODEVREADY; 2484 } 2485 } 2486#ifdef PC98 2487 } 2488#endif 2489 2490txrdy: 2491 /* output queued and everything ready? */ 2492#ifndef PC98 2493 if (line_status & LSR_TXRDY 2494 && com->state >= (CS_BUSY | CS_TTGO | CS_ODEVREADY)) { 2495#else 2496 if (((com->pc98_if_type == COM_IF_RSA98III) 2497 ? (rsa_buf_status & 0x02) 2498 : (line_status & LSR_TXRDY)) 2499 && com->state >= (CS_BUSY | CS_TTGO | CS_ODEVREADY)) { 2500#endif 2501#ifdef PC98 2502 Port_t tmp_data_port; 2503 2504 if (IS_8251(com->pc98_if_type) && 2505 com->pc98_8251fifo_enable) 2506 tmp_data_port = I8251F_data; 2507 else 2508 tmp_data_port = com->data_port; 2509#endif 2510 2511 ioptr = com->obufq.l_head; 2512 if (com->tx_fifo_size > 1 && com->unit != siotsunit) { 2513 u_int ocount; 2514 2515 ocount = com->obufq.l_tail - ioptr; 2516#ifdef PC98 2517 if (com->pc98_if_type == COM_IF_RSA98III) { 2518 rsa_buf_status = inb(com->rsabase + rsa_srr); 2519 rsa_tx_fifo_size = 1024; 2520 if (!(rsa_buf_status & 0x01)) 2521 rsa_tx_fifo_size = 2048; 2522 if (ocount > rsa_tx_fifo_size) 2523 ocount = rsa_tx_fifo_size; 2524 } else 2525#endif 2526 if (ocount > com->tx_fifo_size) 2527 ocount = com->tx_fifo_size; 2528 com->bytes_out += ocount; 2529 do 2530#ifdef PC98 2531 outb(tmp_data_port, *ioptr++); 2532#else 2533 outb(com->data_port, *ioptr++); 2534#endif 2535 while (--ocount != 0); 2536 } else { 2537#ifdef PC98 2538 outb(tmp_data_port, *ioptr++); 2539#else 2540 outb(com->data_port, *ioptr++); 2541#endif 2542 ++com->bytes_out; 2543 if (com->unit == siotsunit 2544 && siotso < sizeof siots / sizeof siots[0]) 2545 nanouptime(&siots[siotso++]); 2546 } 2547#ifdef PC98 2548 if (IS_8251(com->pc98_if_type)) 2549 if (!(pc98_check_i8251_interrupt(com) & IEN_TxFLAG)) 2550 com_int_Tx_enable(com); 2551#endif 2552 com->obufq.l_head = ioptr; 2553 if (COM_IIR_TXRDYBUG(com->flags)) 2554 int_ctl_new = int_ctl | IER_ETXRDY; 2555 if (ioptr >= com->obufq.l_tail) { 2556 struct lbq *qp; 2557 2558 qp = com->obufq.l_next; 2559 qp->l_queued = FALSE; 2560 qp = qp->l_next; 2561 if (qp != NULL) { 2562 com->obufq.l_head = qp->l_head; 2563 com->obufq.l_tail = qp->l_tail; 2564 com->obufq.l_next = qp; 2565 } else { 2566 /* output just completed */ 2567 if (COM_IIR_TXRDYBUG(com->flags)) 2568 int_ctl_new = int_ctl 2569 & ~IER_ETXRDY; 2570 com->state &= ~CS_BUSY; 2571#if defined(PC98) 2572 if (IS_8251(com->pc98_if_type) && 2573 pc98_check_i8251_interrupt(com) & IEN_TxFLAG) 2574 com_int_Tx_disable(com); 2575#endif 2576 } 2577 if (!(com->state & CS_ODONE)) { 2578 com_events += LOTS_OF_EVENTS; 2579 com->state |= CS_ODONE; 2580 /* handle at high level ASAP */ 2581 swi_sched(sio_fast_ih, 0); 2582 } 2583 } 2584#ifdef PC98 2585 if (COM_IIR_TXRDYBUG(com->flags) 2586 && int_ctl != int_ctl_new) { 2587 if (com->pc98_if_type == COM_IF_RSA98III) { 2588 int_ctl_new &= ~(IER_ETXRDY | IER_ERXRDY); 2589 outb(com->int_ctl_port, int_ctl_new); 2590 outb(com->rsabase + rsa_ier, 0x1d); 2591 } else 2592 outb(com->int_ctl_port, int_ctl_new); 2593 } 2594#else 2595 if (COM_IIR_TXRDYBUG(com->flags) 2596 && int_ctl != int_ctl_new) 2597 outb(com->int_ctl_port, int_ctl_new); 2598#endif 2599 } 2600#ifdef PC98 2601 else if (line_status & LSR_TXRDY) { 2602 if (IS_8251(com->pc98_if_type)) 2603 if (pc98_check_i8251_interrupt(com) & IEN_TxFLAG) 2604 com_int_Tx_disable(com); 2605 } 2606 if (IS_8251(com->pc98_if_type)) { 2607 if (com->pc98_8251fifo_enable) { 2608 if ((tmp = inb(I8251F_lsr)) & STS8251F_RxRDY) 2609 goto more_intr; 2610 } else { 2611 if ((tmp = inb(com->sts_port)) & STS8251_RxRDY) 2612 goto more_intr; 2613 } 2614 } 2615#endif 2616 2617 /* finished? */ 2618#ifndef COM_MULTIPORT 2619#ifdef PC98 2620 if (IS_8251(com->pc98_if_type)) 2621 return; 2622#endif 2623 if ((inb(com->int_id_port) & IIR_IMASK) == IIR_NOPEND) 2624#endif /* COM_MULTIPORT */ 2625 return; 2626 } 2627} 2628 2629/* software interrupt handler for SWI_TTY */ 2630static void 2631siopoll(void *dummy) 2632{ 2633 int unit; 2634 2635 if (com_events == 0) 2636 return; 2637repeat: 2638 for (unit = 0; unit < sio_numunits; ++unit) { 2639 struct com_s *com; 2640 int incc; 2641 struct tty *tp; 2642 2643 com = com_addr(unit); 2644 if (com == NULL) 2645 continue; 2646 tp = com->tp; 2647 if (tp == NULL || com->gone) { 2648 /* 2649 * Discard any events related to never-opened or 2650 * going-away devices. 2651 */ 2652 mtx_lock_spin(&sio_lock); 2653 incc = com->iptr - com->ibuf; 2654 com->iptr = com->ibuf; 2655 if (com->state & CS_CHECKMSR) { 2656 incc += LOTS_OF_EVENTS; 2657 com->state &= ~CS_CHECKMSR; 2658 } 2659 com_events -= incc; 2660 mtx_unlock_spin(&sio_lock); 2661 continue; 2662 } 2663 if (com->iptr != com->ibuf) { 2664 mtx_lock_spin(&sio_lock); 2665 sioinput(com); 2666 mtx_unlock_spin(&sio_lock); 2667 } 2668 if (com->state & CS_CHECKMSR) { 2669 u_char delta_modem_status; 2670 2671#ifdef PC98 2672 if (!IS_8251(com->pc98_if_type)) { 2673#endif 2674 mtx_lock_spin(&sio_lock); 2675 delta_modem_status = com->last_modem_status 2676 ^ com->prev_modem_status; 2677 com->prev_modem_status = com->last_modem_status; 2678 com_events -= LOTS_OF_EVENTS; 2679 com->state &= ~CS_CHECKMSR; 2680 mtx_unlock_spin(&sio_lock); 2681 if (delta_modem_status & MSR_DCD) 2682 ttyld_modem(tp, 2683 com->prev_modem_status & MSR_DCD); 2684#ifdef PC98 2685 } 2686#endif 2687 } 2688 if (com->state & CS_ODONE) { 2689 mtx_lock_spin(&sio_lock); 2690 com_events -= LOTS_OF_EVENTS; 2691 com->state &= ~CS_ODONE; 2692 mtx_unlock_spin(&sio_lock); 2693 if (!(com->state & CS_BUSY) 2694 && !(com->extra_state & CSE_BUSYCHECK)) { 2695 timeout(siobusycheck, com, hz / 100); 2696 com->extra_state |= CSE_BUSYCHECK; 2697 } 2698 ttyld_start(tp); 2699 } 2700 if (com_events == 0) 2701 break; 2702 } 2703 if (com_events >= LOTS_OF_EVENTS) 2704 goto repeat; 2705} 2706 2707static void 2708combreak(tp, sig) 2709 struct tty *tp; 2710 int sig; 2711{ 2712 struct com_s *com; 2713 2714 com = tp->t_sc; 2715 2716#ifdef PC98 2717 if (sig) 2718 com_send_break_on(com); 2719 else 2720 com_send_break_off(com); 2721#else 2722 if (sig) 2723 sio_setreg(com, com_cfcr, com->cfcr_image |= CFCR_SBREAK); 2724 else 2725 sio_setreg(com, com_cfcr, com->cfcr_image &= ~CFCR_SBREAK); 2726#endif 2727} 2728 2729static int 2730comparam(tp, t) 2731 struct tty *tp; 2732 struct termios *t; 2733{ 2734 u_int cfcr; 2735 int cflag; 2736 struct com_s *com; 2737 u_int divisor; 2738 u_char dlbh; 2739 u_char dlbl; 2740 u_char efr_flowbits; 2741 int s; 2742#ifdef PC98 2743 u_char param = 0; 2744#endif 2745 2746 com = tp->t_sc; 2747 if (com == NULL) 2748 return (ENODEV); 2749 2750#ifdef PC98 2751 cfcr = 0; 2752 2753 if (IS_8251(com->pc98_if_type)) { 2754 if (pc98_ttspeedtab(com, t->c_ospeed, &divisor) != 0) 2755 return (EINVAL); 2756 } else { 2757#endif 2758 /* check requested parameters */ 2759 if (t->c_ispeed != (t->c_ospeed != 0 ? t->c_ospeed : tp->t_ospeed)) 2760 return (EINVAL); 2761 divisor = siodivisor(com->rclk, t->c_ispeed); 2762 if (divisor == 0) 2763 return (EINVAL); 2764#ifdef PC98 2765 } 2766#endif 2767 2768 /* parameters are OK, convert them to the com struct and the device */ 2769 s = spltty(); 2770#ifdef PC98 2771 if (IS_8251(com->pc98_if_type)) { 2772 if (t->c_ospeed == 0) 2773 com_tiocm_bic(com, TIOCM_DTR|TIOCM_RTS|TIOCM_LE); 2774 else 2775 com_tiocm_bis(com, TIOCM_DTR|TIOCM_RTS|TIOCM_LE); 2776 } else 2777#endif 2778 if (t->c_ospeed == 0) 2779 (void)commodem(tp, 0, SER_DTR); /* hang up line */ 2780 else 2781 (void)commodem(tp, SER_DTR, 0); 2782 cflag = t->c_cflag; 2783#ifdef PC98 2784 if (!IS_8251(com->pc98_if_type)) { 2785#endif 2786 switch (cflag & CSIZE) { 2787 case CS5: 2788 cfcr = CFCR_5BITS; 2789 break; 2790 case CS6: 2791 cfcr = CFCR_6BITS; 2792 break; 2793 case CS7: 2794 cfcr = CFCR_7BITS; 2795 break; 2796 default: 2797 cfcr = CFCR_8BITS; 2798 break; 2799 } 2800 if (cflag & PARENB) { 2801 cfcr |= CFCR_PENAB; 2802 if (!(cflag & PARODD)) 2803 cfcr |= CFCR_PEVEN; 2804 } 2805 if (cflag & CSTOPB) 2806 cfcr |= CFCR_STOPB; 2807 2808 if (com->hasfifo) { 2809 /* 2810 * Use a fifo trigger level low enough so that the input 2811 * latency from the fifo is less than about 16 msec and 2812 * the total latency is less than about 30 msec. These 2813 * latencies are reasonable for humans. Serial comms 2814 * protocols shouldn't expect anything better since modem 2815 * latencies are larger. 2816 * 2817 * The fifo trigger level cannot be set at RX_HIGH for high 2818 * speed connections without further work on reducing 2819 * interrupt disablement times in other parts of the system, 2820 * without producing silo overflow errors. 2821 */ 2822 com->fifo_image = com->unit == siotsunit ? 0 2823 : t->c_ispeed <= 4800 2824 ? FIFO_ENABLE : FIFO_ENABLE | FIFO_RX_MEDH; 2825#ifdef COM_ESP 2826 /* 2827 * The Hayes ESP card needs the fifo DMA mode bit set 2828 * in compatibility mode. If not, it will interrupt 2829 * for each character received. 2830 */ 2831 if (com->esp) 2832 com->fifo_image |= FIFO_DMA_MODE; 2833#endif 2834 sio_setreg(com, com_fifo, com->fifo_image); 2835 } 2836#ifdef PC98 2837 } 2838#endif 2839 2840 /* 2841 * This returns with interrupts disabled so that we can complete 2842 * the speed change atomically. Keeping interrupts disabled is 2843 * especially important while com_data is hidden. 2844 */ 2845 (void) siosetwater(com, t->c_ispeed); 2846 2847#ifdef PC98 2848 if (IS_8251(com->pc98_if_type)) 2849 com_cflag_and_speed_set(com, cflag, t->c_ospeed); 2850 else { 2851#endif 2852 sio_setreg(com, com_cfcr, cfcr | CFCR_DLAB); 2853 /* 2854 * Only set the divisor registers if they would change, since on 2855 * some 16550 incompatibles (UMC8669F), setting them while input 2856 * is arriving loses sync until data stops arriving. 2857 */ 2858 dlbl = divisor & 0xFF; 2859 if (sio_getreg(com, com_dlbl) != dlbl) 2860 sio_setreg(com, com_dlbl, dlbl); 2861 dlbh = divisor >> 8; 2862 if (sio_getreg(com, com_dlbh) != dlbh) 2863 sio_setreg(com, com_dlbh, dlbh); 2864#ifdef PC98 2865 } 2866#endif 2867 2868 efr_flowbits = 0; 2869 2870 if (cflag & CRTS_IFLOW) { 2871 com->state |= CS_RTS_IFLOW; 2872 efr_flowbits |= EFR_AUTORTS; 2873 /* 2874 * If CS_RTS_IFLOW just changed from off to on, the change 2875 * needs to be propagated to MCR_RTS. This isn't urgent, 2876 * so do it later by calling comstart() instead of repeating 2877 * a lot of code from comstart() here. 2878 */ 2879 } else if (com->state & CS_RTS_IFLOW) { 2880 com->state &= ~CS_RTS_IFLOW; 2881 /* 2882 * CS_RTS_IFLOW just changed from on to off. Force MCR_RTS 2883 * on here, since comstart() won't do it later. 2884 */ 2885#ifdef PC98 2886 if (IS_8251(com->pc98_if_type)) 2887 com_tiocm_bis(com, TIOCM_RTS); 2888 else 2889 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS); 2890#else 2891 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS); 2892#endif 2893 } 2894 2895 /* 2896 * Set up state to handle output flow control. 2897 * XXX - worth handling MDMBUF (DCD) flow control at the lowest level? 2898 * Now has 10+ msec latency, while CTS flow has 50- usec latency. 2899 */ 2900 com->state |= CS_ODEVREADY; 2901 com->state &= ~CS_CTS_OFLOW; 2902#ifdef PC98 2903 if (com->pc98_if_type == COM_IF_RSA98III) { 2904 param = inb(com->rsabase + rsa_msr); 2905 outb(com->rsabase + rsa_msr, param & 0x14); 2906 } 2907#endif 2908 if (cflag & CCTS_OFLOW) { 2909 com->state |= CS_CTS_OFLOW; 2910 efr_flowbits |= EFR_AUTOCTS; 2911#ifdef PC98 2912 if (IS_8251(com->pc98_if_type)) { 2913 if (!(pc98_get_modem_status(com) & TIOCM_CTS)) 2914 com->state &= ~CS_ODEVREADY; 2915 } else if (com->pc98_if_type == COM_IF_RSA98III) { 2916 /* Set automatic flow control mode */ 2917 outb(com->rsabase + rsa_msr, param | 0x08); 2918 } else 2919#endif 2920 if (!(com->last_modem_status & MSR_CTS)) 2921 com->state &= ~CS_ODEVREADY; 2922 } 2923 2924#ifdef PC98 2925 if (!IS_8251(com->pc98_if_type)) 2926 sio_setreg(com, com_cfcr, com->cfcr_image = cfcr); 2927#else 2928 if (com->st16650a) { 2929 sio_setreg(com, com_lcr, LCR_EFR_ENABLE); 2930 sio_setreg(com, com_efr, 2931 (sio_getreg(com, com_efr) 2932 & ~(EFR_AUTOCTS | EFR_AUTORTS)) | efr_flowbits); 2933 } 2934 sio_setreg(com, com_cfcr, com->cfcr_image = cfcr); 2935#endif 2936 2937 /* XXX shouldn't call functions while intrs are disabled. */ 2938 ttyldoptim(tp); 2939 2940 mtx_unlock_spin(&sio_lock); 2941 splx(s); 2942 comstart(tp); 2943 if (com->ibufold != NULL) { 2944 free(com->ibufold, M_DEVBUF); 2945 com->ibufold = NULL; 2946 } 2947 return (0); 2948} 2949 2950/* 2951 * This function must be called with the sio_lock mutex released and will 2952 * return with it obtained. 2953 */ 2954static int 2955siosetwater(com, speed) 2956 struct com_s *com; 2957 speed_t speed; 2958{ 2959 int cp4ticks; 2960 u_char *ibuf; 2961 int ibufsize; 2962 struct tty *tp; 2963 2964 /* 2965 * Make the buffer size large enough to handle a softtty interrupt 2966 * latency of about 2 ticks without loss of throughput or data 2967 * (about 3 ticks if input flow control is not used or not honoured, 2968 * but a bit less for CS5-CS7 modes). 2969 */ 2970 cp4ticks = speed / 10 / hz * 4; 2971 for (ibufsize = 128; ibufsize < cp4ticks;) 2972 ibufsize <<= 1; 2973#ifdef PC98 2974 if (com->pc98_if_type == COM_IF_RSA98III) 2975 ibufsize = 2048; 2976#endif 2977 if (ibufsize == com->ibufsize) { 2978 mtx_lock_spin(&sio_lock); 2979 return (0); 2980 } 2981 2982 /* 2983 * Allocate input buffer. The extra factor of 2 in the size is 2984 * to allow for an error byte for each input byte. 2985 */ 2986 ibuf = malloc(2 * ibufsize, M_DEVBUF, M_NOWAIT); 2987 if (ibuf == NULL) { 2988 mtx_lock_spin(&sio_lock); 2989 return (ENOMEM); 2990 } 2991 2992 /* Initialize non-critical variables. */ 2993 com->ibufold = com->ibuf; 2994 com->ibufsize = ibufsize; 2995 tp = com->tp; 2996 if (tp != NULL) { 2997 tp->t_ififosize = 2 * ibufsize; 2998 tp->t_ispeedwat = (speed_t)-1; 2999 tp->t_ospeedwat = (speed_t)-1; 3000 } 3001 3002 /* 3003 * Read current input buffer, if any. Continue with interrupts 3004 * disabled. 3005 */ 3006 mtx_lock_spin(&sio_lock); 3007 if (com->iptr != com->ibuf) 3008 sioinput(com); 3009 3010 /*- 3011 * Initialize critical variables, including input buffer watermarks. 3012 * The external device is asked to stop sending when the buffer 3013 * exactly reaches high water, or when the high level requests it. 3014 * The high level is notified immediately (rather than at a later 3015 * clock tick) when this watermark is reached. 3016 * The buffer size is chosen so the watermark should almost never 3017 * be reached. 3018 * The low watermark is invisibly 0 since the buffer is always 3019 * emptied all at once. 3020 */ 3021 com->iptr = com->ibuf = ibuf; 3022 com->ibufend = ibuf + ibufsize; 3023 com->ierroff = ibufsize; 3024 com->ihighwater = ibuf + 3 * ibufsize / 4; 3025 return (0); 3026} 3027 3028static void 3029comstart(tp) 3030 struct tty *tp; 3031{ 3032 struct com_s *com; 3033 int s; 3034 3035 com = tp->t_sc; 3036 if (com == NULL) 3037 return; 3038 s = spltty(); 3039 mtx_lock_spin(&sio_lock); 3040 if (tp->t_state & TS_TTSTOP) 3041 com->state &= ~CS_TTGO; 3042 else 3043 com->state |= CS_TTGO; 3044 if (tp->t_state & TS_TBLOCK) { 3045#ifdef PC98 3046 if (IS_8251(com->pc98_if_type)) { 3047 if ((com_tiocm_get(com) & TIOCM_RTS) && 3048 (com->state & CS_RTS_IFLOW)) 3049 com_tiocm_bic(com, TIOCM_RTS); 3050 } else { 3051 if ((com->mcr_image & MCR_RTS) && 3052 (com->state & CS_RTS_IFLOW)) 3053 outb(com->modem_ctl_port, com->mcr_image &= ~MCR_RTS); 3054 } 3055#else 3056 if (com->mcr_image & MCR_RTS && com->state & CS_RTS_IFLOW) 3057 outb(com->modem_ctl_port, com->mcr_image &= ~MCR_RTS); 3058#endif 3059 } else { 3060#ifdef PC98 3061 if (IS_8251(com->pc98_if_type)) { 3062 if (!(com_tiocm_get(com) & TIOCM_RTS) && 3063 com->iptr < com->ihighwater && 3064 com->state & CS_RTS_IFLOW) 3065 com_tiocm_bis(com, TIOCM_RTS); 3066 } else { 3067 if (!(com->mcr_image & MCR_RTS) && 3068 com->iptr < com->ihighwater && 3069 com->state & CS_RTS_IFLOW) 3070 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS); 3071 } 3072#else 3073 if (!(com->mcr_image & MCR_RTS) && com->iptr < com->ihighwater 3074 && com->state & CS_RTS_IFLOW) 3075 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS); 3076#endif 3077 } 3078 mtx_unlock_spin(&sio_lock); 3079 if (tp->t_state & (TS_TIMEOUT | TS_TTSTOP)) { 3080 ttwwakeup(tp); 3081 splx(s); 3082 return; 3083 } 3084 if (tp->t_outq.c_cc != 0) { 3085 struct lbq *qp; 3086 struct lbq *next; 3087 3088 if (!com->obufs[0].l_queued) { 3089 com->obufs[0].l_tail 3090 = com->obuf1 + q_to_b(&tp->t_outq, com->obuf1, 3091#ifdef PC98 3092 com->obufsize); 3093#else 3094 sizeof com->obuf1); 3095#endif 3096 com->obufs[0].l_next = NULL; 3097 com->obufs[0].l_queued = TRUE; 3098 mtx_lock_spin(&sio_lock); 3099 if (com->state & CS_BUSY) { 3100 qp = com->obufq.l_next; 3101 while ((next = qp->l_next) != NULL) 3102 qp = next; 3103 qp->l_next = &com->obufs[0]; 3104 } else { 3105 com->obufq.l_head = com->obufs[0].l_head; 3106 com->obufq.l_tail = com->obufs[0].l_tail; 3107 com->obufq.l_next = &com->obufs[0]; 3108 com->state |= CS_BUSY; 3109 } 3110 mtx_unlock_spin(&sio_lock); 3111 } 3112 if (tp->t_outq.c_cc != 0 && !com->obufs[1].l_queued) { 3113 com->obufs[1].l_tail 3114 = com->obuf2 + q_to_b(&tp->t_outq, com->obuf2, 3115#ifdef PC98 3116 com->obufsize); 3117#else 3118 sizeof com->obuf2); 3119#endif 3120 com->obufs[1].l_next = NULL; 3121 com->obufs[1].l_queued = TRUE; 3122 mtx_lock_spin(&sio_lock); 3123 if (com->state & CS_BUSY) { 3124 qp = com->obufq.l_next; 3125 while ((next = qp->l_next) != NULL) 3126 qp = next; 3127 qp->l_next = &com->obufs[1]; 3128 } else { 3129 com->obufq.l_head = com->obufs[1].l_head; 3130 com->obufq.l_tail = com->obufs[1].l_tail; 3131 com->obufq.l_next = &com->obufs[1]; 3132 com->state |= CS_BUSY; 3133 } 3134 mtx_unlock_spin(&sio_lock); 3135 } 3136 tp->t_state |= TS_BUSY; 3137 } 3138 mtx_lock_spin(&sio_lock); 3139 if (com->state >= (CS_BUSY | CS_TTGO)) 3140 siointr1(com); /* fake interrupt to start output */ 3141 mtx_unlock_spin(&sio_lock); 3142 ttwwakeup(tp); 3143 splx(s); 3144} 3145 3146static void 3147comstop(tp, rw) 3148 struct tty *tp; 3149 int rw; 3150{ 3151 struct com_s *com; 3152#ifdef PC98 3153 int rsa98_tmp = 0; 3154#endif 3155 3156 com = tp->t_sc; 3157 if (com == NULL || com->gone) 3158 return; 3159 mtx_lock_spin(&sio_lock); 3160 if (rw & FWRITE) { 3161#ifdef PC98 3162 if (!IS_8251(com->pc98_if_type)) { 3163#endif 3164 if (com->hasfifo) 3165#ifdef COM_ESP 3166 /* XXX avoid h/w bug. */ 3167 if (!com->esp) 3168#endif 3169 sio_setreg(com, com_fifo, 3170 FIFO_XMT_RST | com->fifo_image); 3171#ifdef PC98 3172 if (com->pc98_if_type == COM_IF_RSA98III) 3173 for (rsa98_tmp = 0; rsa98_tmp < 2048; rsa98_tmp++) 3174 sio_setreg(com, com_fifo, 3175 FIFO_XMT_RST | com->fifo_image); 3176 } 3177#endif 3178 com->obufs[0].l_queued = FALSE; 3179 com->obufs[1].l_queued = FALSE; 3180 if (com->state & CS_ODONE) 3181 com_events -= LOTS_OF_EVENTS; 3182 com->state &= ~(CS_ODONE | CS_BUSY); 3183 com->tp->t_state &= ~TS_BUSY; 3184 } 3185 if (rw & FREAD) { 3186#ifdef PC98 3187 if (!IS_8251(com->pc98_if_type)) { 3188 if (com->pc98_if_type == COM_IF_RSA98III) 3189 for (rsa98_tmp = 0; rsa98_tmp < 2048; rsa98_tmp++) 3190 sio_getreg(com, com_data); 3191#endif 3192 if (com->hasfifo) 3193#ifdef COM_ESP 3194 /* XXX avoid h/w bug. */ 3195 if (!com->esp) 3196#endif 3197 sio_setreg(com, com_fifo, 3198 FIFO_RCV_RST | com->fifo_image); 3199#ifdef PC98 3200 } 3201#endif 3202 com_events -= (com->iptr - com->ibuf); 3203 com->iptr = com->ibuf; 3204 } 3205 mtx_unlock_spin(&sio_lock); 3206 comstart(tp); 3207} 3208 3209static int 3210commodem(struct tty *tp, int sigon, int sigoff) 3211{ 3212 struct com_s *com; 3213 int bitand, bitor, msr; 3214#ifdef PC98 3215 int clr, set; 3216#endif 3217 3218 com = tp->t_sc; 3219 if (com->gone) 3220 return(0); 3221 if (sigon != 0 || sigoff != 0) { 3222#ifdef PC98 3223 if (IS_8251(com->pc98_if_type)) { 3224 bitand = bitor = 0; 3225 clr = set = 0; 3226 if (sigoff & SER_DTR) { 3227 bitand |= TIOCM_DTR; 3228 clr |= CMD8251_DTR; 3229 } 3230 if (sigoff & SER_RTS) { 3231 bitand |= TIOCM_RTS; 3232 clr |= CMD8251_RxEN | CMD8251_RTS; 3233 } 3234 if (sigon & SER_DTR) { 3235 bitor |= TIOCM_DTR; 3236 set |= CMD8251_TxEN | CMD8251_RxEN | 3237 CMD8251_DTR; 3238 } 3239 if (sigon & SER_RTS) { 3240 bitor |= TIOCM_RTS; 3241 set |= CMD8251_TxEN | CMD8251_RxEN | 3242 CMD8251_RTS; 3243 } 3244 bitand = ~bitand; 3245 mtx_lock_spin(&sio_lock); 3246 com->pc98_prev_modem_status &= bitand; 3247 com->pc98_prev_modem_status |= bitor; 3248 pc98_i8251_clear_or_cmd(com, clr, set); 3249 mtx_unlock_spin(&sio_lock); 3250 return (0); 3251 } else { 3252#endif 3253 bitand = bitor = 0; 3254 if (sigoff & SER_DTR) 3255 bitand |= MCR_DTR; 3256 if (sigoff & SER_RTS) 3257 bitand |= MCR_RTS; 3258 if (sigon & SER_DTR) 3259 bitor |= MCR_DTR; 3260 if (sigon & SER_RTS) 3261 bitor |= MCR_RTS; 3262 bitand = ~bitand; 3263 mtx_lock_spin(&sio_lock); 3264 com->mcr_image &= bitand; 3265 com->mcr_image |= bitor; 3266 outb(com->modem_ctl_port, com->mcr_image); 3267 mtx_unlock_spin(&sio_lock); 3268 return (0); 3269#ifdef PC98 3270 } 3271#endif 3272 } else { 3273#ifdef PC98 3274 if (IS_8251(com->pc98_if_type)) 3275 return (com_tiocm_get(com)); 3276 else { 3277#endif 3278 bitor = 0; 3279 if (com->mcr_image & MCR_DTR) 3280 bitor |= SER_DTR; 3281 if (com->mcr_image & MCR_RTS) 3282 bitor |= SER_RTS; 3283 msr = com->prev_modem_status; 3284 if (msr & MSR_CTS) 3285 bitor |= SER_CTS; 3286 if (msr & MSR_DCD) 3287 bitor |= SER_DCD; 3288 if (msr & MSR_DSR) 3289 bitor |= SER_DSR; 3290 if (msr & MSR_DSR) 3291 bitor |= SER_DSR; 3292 if (msr & (MSR_RI | MSR_TERI)) 3293 bitor |= SER_RI; 3294 return (bitor); 3295#ifdef PC98 3296 } 3297#endif 3298 } 3299} 3300 3301static void 3302siosettimeout() 3303{ 3304 struct com_s *com; 3305 bool_t someopen; 3306 int unit; 3307 3308 /* 3309 * Set our timeout period to 1 second if no polled devices are open. 3310 * Otherwise set it to max(1/200, 1/hz). 3311 * Enable timeouts iff some device is open. 3312 */ 3313 untimeout(comwakeup, (void *)NULL, sio_timeout_handle); 3314 sio_timeout = hz; 3315 someopen = FALSE; 3316 for (unit = 0; unit < sio_numunits; ++unit) { 3317 com = com_addr(unit); 3318 if (com != NULL && com->tp != NULL 3319 && com->tp->t_state & TS_ISOPEN && !com->gone) { 3320 someopen = TRUE; 3321 if (com->poll || com->poll_output) { 3322 sio_timeout = hz > 200 ? hz / 200 : 1; 3323 break; 3324 } 3325 } 3326 } 3327 if (someopen) { 3328 sio_timeouts_until_log = hz / sio_timeout; 3329 sio_timeout_handle = timeout(comwakeup, (void *)NULL, 3330 sio_timeout); 3331 } else { 3332 /* Flush error messages, if any. */ 3333 sio_timeouts_until_log = 1; 3334 comwakeup((void *)NULL); 3335 untimeout(comwakeup, (void *)NULL, sio_timeout_handle); 3336 } 3337} 3338 3339static void 3340comwakeup(chan) 3341 void *chan; 3342{ 3343 struct com_s *com; 3344 int unit; 3345 3346 sio_timeout_handle = timeout(comwakeup, (void *)NULL, sio_timeout); 3347 3348 /* 3349 * Recover from lost output interrupts. 3350 * Poll any lines that don't use interrupts. 3351 */ 3352 for (unit = 0; unit < sio_numunits; ++unit) { 3353 com = com_addr(unit); 3354 if (com != NULL && !com->gone 3355 && (com->state >= (CS_BUSY | CS_TTGO) || com->poll)) { 3356 mtx_lock_spin(&sio_lock); 3357 siointr1(com); 3358 mtx_unlock_spin(&sio_lock); 3359 } 3360 } 3361 3362 /* 3363 * Check for and log errors, but not too often. 3364 */ 3365 if (--sio_timeouts_until_log > 0) 3366 return; 3367 sio_timeouts_until_log = hz / sio_timeout; 3368 for (unit = 0; unit < sio_numunits; ++unit) { 3369 int errnum; 3370 3371 com = com_addr(unit); 3372 if (com == NULL) 3373 continue; 3374 if (com->gone) 3375 continue; 3376 for (errnum = 0; errnum < CE_NTYPES; ++errnum) { 3377 u_int delta; 3378 u_long total; 3379 3380 mtx_lock_spin(&sio_lock); 3381 delta = com->delta_error_counts[errnum]; 3382 com->delta_error_counts[errnum] = 0; 3383 mtx_unlock_spin(&sio_lock); 3384 if (delta == 0) 3385 continue; 3386 total = com->error_counts[errnum] += delta; 3387 log(LOG_ERR, "sio%d: %u more %s%s (total %lu)\n", 3388 unit, delta, error_desc[errnum], 3389 delta == 1 ? "" : "s", total); 3390 } 3391 } 3392} 3393 3394#ifdef PC98 3395/* commint is called when modem control line changes */ 3396static void 3397commint(struct cdev *dev) 3398{ 3399 register struct tty *tp; 3400 int stat,delta; 3401 struct com_s *com; 3402 3403 com = dev->si_drv1; 3404 tp = com->tp; 3405 3406 stat = com_tiocm_get(com); 3407 delta = com_tiocm_get_delta(com); 3408 3409 if (com->state & CS_CTS_OFLOW) { 3410 if (stat & TIOCM_CTS) 3411 com->state |= CS_ODEVREADY; 3412 else 3413 com->state &= ~CS_ODEVREADY; 3414 } 3415 if ((delta & TIOCM_CAR) && (ISCALLOUT(dev)) == 0) { 3416 if (stat & TIOCM_CAR ) 3417 (void)ttyld_modem(tp, 1); 3418 else if (ttyld_modem(tp, 0) == 0) { 3419 /* negate DTR, RTS */ 3420 com_tiocm_bic(com, (tp->t_cflag & HUPCL) ? 3421 TIOCM_DTR|TIOCM_RTS|TIOCM_LE : TIOCM_LE ); 3422 /* disable IENABLE */ 3423 com_int_TxRx_disable( com ); 3424 } 3425 } 3426} 3427#endif 3428 3429/* 3430 * Following are all routines needed for SIO to act as console 3431 */ 3432struct siocnstate { 3433 u_char dlbl; 3434 u_char dlbh; 3435 u_char ier; 3436 u_char cfcr; 3437 u_char mcr; 3438}; 3439 3440/* 3441 * This is a function in order to not replicate "ttyd%d" more 3442 * places than absolutely necessary. 3443 */ 3444static void 3445siocnset(struct consdev *cd, int unit) 3446{ 3447 3448 cd->cn_unit = unit; 3449 sprintf(cd->cn_name, "ttyd%d", unit); 3450} 3451 3452static speed_t siocngetspeed(Port_t, u_long rclk); 3453static void siocnclose(struct siocnstate *sp, Port_t iobase); 3454static void siocnopen(struct siocnstate *sp, Port_t iobase, int speed); 3455static void siocntxwait(Port_t iobase); 3456 3457static cn_probe_t siocnprobe; 3458static cn_init_t siocninit; 3459static cn_term_t siocnterm; 3460static cn_checkc_t siocncheckc; 3461static cn_getc_t siocngetc; 3462static cn_putc_t siocnputc; 3463 3464CONS_DRIVER(sio, siocnprobe, siocninit, siocnterm, siocngetc, siocncheckc, 3465 siocnputc, NULL); 3466 3467static void 3468siocntxwait(iobase) 3469 Port_t iobase; 3470{ 3471 int timo; 3472 3473 /* 3474 * Wait for any pending transmission to finish. Required to avoid 3475 * the UART lockup bug when the speed is changed, and for normal 3476 * transmits. 3477 */ 3478 timo = 100000; 3479 while ((inb(iobase + com_lsr) & (LSR_TSRE | LSR_TXRDY)) 3480 != (LSR_TSRE | LSR_TXRDY) && --timo != 0) 3481 ; 3482} 3483 3484/* 3485 * Read the serial port specified and try to figure out what speed 3486 * it's currently running at. We're assuming the serial port has 3487 * been initialized and is basicly idle. This routine is only intended 3488 * to be run at system startup. 3489 * 3490 * If the value read from the serial port doesn't make sense, return 0. 3491 */ 3492 3493static speed_t 3494siocngetspeed(iobase, rclk) 3495 Port_t iobase; 3496 u_long rclk; 3497{ 3498 u_int divisor; 3499 u_char dlbh; 3500 u_char dlbl; 3501 u_char cfcr; 3502 3503 cfcr = inb(iobase + com_cfcr); 3504 outb(iobase + com_cfcr, CFCR_DLAB | cfcr); 3505 3506 dlbl = inb(iobase + com_dlbl); 3507 dlbh = inb(iobase + com_dlbh); 3508 3509 outb(iobase + com_cfcr, cfcr); 3510 3511 divisor = dlbh << 8 | dlbl; 3512 3513 /* XXX there should be more sanity checking. */ 3514 if (divisor == 0) 3515 return (CONSPEED); 3516 return (rclk / (16UL * divisor)); 3517} 3518 3519static void 3520siocnopen(sp, iobase, speed) 3521 struct siocnstate *sp; 3522 Port_t iobase; 3523 int speed; 3524{ 3525 u_int divisor; 3526 u_char dlbh; 3527 u_char dlbl; 3528 3529 /* 3530 * Save all the device control registers except the fifo register 3531 * and set our default ones (cs8 -parenb speed=comdefaultrate). 3532 * We can't save the fifo register since it is read-only. 3533 */ 3534 sp->ier = inb(iobase + com_ier); 3535 outb(iobase + com_ier, 0); /* spltty() doesn't stop siointr() */ 3536 siocntxwait(iobase); 3537 sp->cfcr = inb(iobase + com_cfcr); 3538 outb(iobase + com_cfcr, CFCR_DLAB | CFCR_8BITS); 3539 sp->dlbl = inb(iobase + com_dlbl); 3540 sp->dlbh = inb(iobase + com_dlbh); 3541 /* 3542 * Only set the divisor registers if they would change, since on 3543 * some 16550 incompatibles (Startech), setting them clears the 3544 * data input register. This also reduces the effects of the 3545 * UMC8669F bug. 3546 */ 3547 divisor = siodivisor(comdefaultrclk, speed); 3548 dlbl = divisor & 0xFF; 3549 if (sp->dlbl != dlbl) 3550 outb(iobase + com_dlbl, dlbl); 3551 dlbh = divisor >> 8; 3552 if (sp->dlbh != dlbh) 3553 outb(iobase + com_dlbh, dlbh); 3554 outb(iobase + com_cfcr, CFCR_8BITS); 3555 sp->mcr = inb(iobase + com_mcr); 3556 /* 3557 * We don't want interrupts, but must be careful not to "disable" 3558 * them by clearing the MCR_IENABLE bit, since that might cause 3559 * an interrupt by floating the IRQ line. 3560 */ 3561 outb(iobase + com_mcr, (sp->mcr & MCR_IENABLE) | MCR_DTR | MCR_RTS); 3562} 3563 3564static void 3565siocnclose(sp, iobase) 3566 struct siocnstate *sp; 3567 Port_t iobase; 3568{ 3569 /* 3570 * Restore the device control registers. 3571 */ 3572 siocntxwait(iobase); 3573 outb(iobase + com_cfcr, CFCR_DLAB | CFCR_8BITS); 3574 if (sp->dlbl != inb(iobase + com_dlbl)) 3575 outb(iobase + com_dlbl, sp->dlbl); 3576 if (sp->dlbh != inb(iobase + com_dlbh)) 3577 outb(iobase + com_dlbh, sp->dlbh); 3578 outb(iobase + com_cfcr, sp->cfcr); 3579 /* 3580 * XXX damp oscillations of MCR_DTR and MCR_RTS by not restoring them. 3581 */ 3582 outb(iobase + com_mcr, sp->mcr | MCR_DTR | MCR_RTS); 3583 outb(iobase + com_ier, sp->ier); 3584} 3585 3586static void 3587siocnprobe(cp) 3588 struct consdev *cp; 3589{ 3590 speed_t boot_speed; 3591 u_char cfcr; 3592 u_int divisor; 3593 int s, unit; 3594 struct siocnstate sp; 3595 3596 /* 3597 * Find our first enabled console, if any. If it is a high-level 3598 * console device, then initialize it and return successfully. 3599 * If it is a low-level console device, then initialize it and 3600 * return unsuccessfully. It must be initialized in both cases 3601 * for early use by console drivers and debuggers. Initializing 3602 * the hardware is not necessary in all cases, since the i/o 3603 * routines initialize it on the fly, but it is necessary if 3604 * input might arrive while the hardware is switched back to an 3605 * uninitialized state. We can't handle multiple console devices 3606 * yet because our low-level routines don't take a device arg. 3607 * We trust the user to set the console flags properly so that we 3608 * don't need to probe. 3609 */ 3610 cp->cn_pri = CN_DEAD; 3611 3612 for (unit = 0; unit < 16; unit++) { /* XXX need to know how many */ 3613 int flags; 3614 3615 if (resource_disabled("sio", unit)) 3616 continue; 3617 if (resource_int_value("sio", unit, "flags", &flags)) 3618 continue; 3619 if (COM_CONSOLE(flags) || COM_DEBUGGER(flags)) { 3620 int port; 3621 Port_t iobase; 3622 3623 if (resource_int_value("sio", unit, "port", &port)) 3624 continue; 3625 iobase = port; 3626 s = spltty(); 3627 if (boothowto & RB_SERIAL) { 3628 boot_speed = 3629 siocngetspeed(iobase, comdefaultrclk); 3630 if (boot_speed) 3631 comdefaultrate = boot_speed; 3632 } 3633 3634 /* 3635 * Initialize the divisor latch. We can't rely on 3636 * siocnopen() to do this the first time, since it 3637 * avoids writing to the latch if the latch appears 3638 * to have the correct value. Also, if we didn't 3639 * just read the speed from the hardware, then we 3640 * need to set the speed in hardware so that 3641 * switching it later is null. 3642 */ 3643 cfcr = inb(iobase + com_cfcr); 3644 outb(iobase + com_cfcr, CFCR_DLAB | cfcr); 3645 divisor = siodivisor(comdefaultrclk, comdefaultrate); 3646 outb(iobase + com_dlbl, divisor & 0xff); 3647 outb(iobase + com_dlbh, divisor >> 8); 3648 outb(iobase + com_cfcr, cfcr); 3649 3650 siocnopen(&sp, iobase, comdefaultrate); 3651 3652 splx(s); 3653 if (COM_CONSOLE(flags) && !COM_LLCONSOLE(flags)) { 3654 siocnset(cp, unit); 3655 cp->cn_pri = COM_FORCECONSOLE(flags) 3656 || boothowto & RB_SERIAL 3657 ? CN_REMOTE : CN_NORMAL; 3658 siocniobase = iobase; 3659 siocnunit = unit; 3660 } 3661#ifdef GDB 3662 if (COM_DEBUGGER(flags)) 3663 siogdbiobase = iobase; 3664#endif 3665 } 3666 } 3667} 3668 3669static void 3670siocninit(cp) 3671 struct consdev *cp; 3672{ 3673 comconsole = cp->cn_unit; 3674} 3675 3676static void 3677siocnterm(cp) 3678 struct consdev *cp; 3679{ 3680 comconsole = -1; 3681} 3682 3683static int 3684siocncheckc(struct consdev *cd) 3685{ 3686 int c; 3687 Port_t iobase; 3688 int s; 3689 struct siocnstate sp; 3690 speed_t speed; 3691 3692 if (cd != NULL && cd->cn_unit == siocnunit) { 3693 iobase = siocniobase; 3694 speed = comdefaultrate; 3695 } else { 3696#ifdef GDB 3697 iobase = siogdbiobase; 3698 speed = gdbdefaultrate; 3699#else 3700 return (-1); 3701#endif 3702 } 3703 s = spltty(); 3704 siocnopen(&sp, iobase, speed); 3705 if (inb(iobase + com_lsr) & LSR_RXRDY) 3706 c = inb(iobase + com_data); 3707 else 3708 c = -1; 3709 siocnclose(&sp, iobase); 3710 splx(s); 3711 return (c); 3712} 3713 3714static int 3715siocngetc(struct consdev *cd) 3716{ 3717 int c; 3718 Port_t iobase; 3719 int s; 3720 struct siocnstate sp; 3721 speed_t speed; 3722 3723 if (cd != NULL && cd->cn_unit == siocnunit) { 3724 iobase = siocniobase; 3725 speed = comdefaultrate; 3726 } else { 3727#ifdef GDB 3728 iobase = siogdbiobase; 3729 speed = gdbdefaultrate; 3730#else 3731 return (-1); 3732#endif 3733 } 3734 s = spltty(); 3735 siocnopen(&sp, iobase, speed); 3736 while (!(inb(iobase + com_lsr) & LSR_RXRDY)) 3737 ; 3738 c = inb(iobase + com_data); 3739 siocnclose(&sp, iobase); 3740 splx(s); 3741 return (c); 3742} 3743 3744static void 3745siocnputc(struct consdev *cd, int c) 3746{ 3747 int need_unlock; 3748 int s; 3749 struct siocnstate sp; 3750 Port_t iobase; 3751 speed_t speed; 3752 3753 if (cd != NULL && cd->cn_unit == siocnunit) { 3754 iobase = siocniobase; 3755 speed = comdefaultrate; 3756 } else { 3757#ifdef GDB 3758 iobase = siogdbiobase; 3759 speed = gdbdefaultrate; 3760#else 3761 return; 3762#endif 3763 } 3764 s = spltty(); 3765 need_unlock = 0; 3766 if (!kdb_active && sio_inited == 2 && !mtx_owned(&sio_lock)) { 3767 mtx_lock_spin(&sio_lock); 3768 need_unlock = 1; 3769 } 3770 siocnopen(&sp, iobase, speed); 3771 siocntxwait(iobase); 3772 outb(iobase + com_data, c); 3773 siocnclose(&sp, iobase); 3774 if (need_unlock) 3775 mtx_unlock_spin(&sio_lock); 3776 splx(s); 3777} 3778 3779/* 3780 * Remote gdb(1) support. 3781 */ 3782 3783#if defined(GDB) 3784 3785#include <gdb/gdb.h> 3786 3787static gdb_probe_f siogdbprobe; 3788static gdb_init_f siogdbinit; 3789static gdb_term_f siogdbterm; 3790static gdb_getc_f siogdbgetc; 3791static gdb_checkc_f siogdbcheckc; 3792static gdb_putc_f siogdbputc; 3793 3794GDB_DBGPORT(sio, siogdbprobe, siogdbinit, siogdbterm, siogdbcheckc, 3795 siogdbgetc, siogdbputc); 3796 3797static int 3798siogdbprobe(void) 3799{ 3800 return ((siogdbiobase != 0) ? 0 : -1); 3801} 3802 3803static void 3804siogdbinit(void) 3805{ 3806} 3807 3808static void 3809siogdbterm(void) 3810{ 3811} 3812 3813static void 3814siogdbputc(int c) 3815{ 3816 siocnputc(NULL, c); 3817} 3818 3819static int 3820siogdbcheckc(void) 3821{ 3822 return (siocncheckc(NULL)); 3823} 3824 3825static int 3826siogdbgetc(void) 3827{ 3828 return (siocngetc(NULL)); 3829} 3830 3831#endif 3832 3833#ifdef PC98 3834/* 3835 * pc98 local function 3836 */ 3837static void 3838com_tiocm_bis(struct com_s *com, int msr) 3839{ 3840 int s; 3841 int tmp = 0; 3842 3843 s=spltty(); 3844 com->pc98_prev_modem_status |= ( msr & (TIOCM_LE|TIOCM_DTR|TIOCM_RTS) ); 3845 tmp |= CMD8251_TxEN|CMD8251_RxEN; 3846 if ( msr & TIOCM_DTR ) tmp |= CMD8251_DTR; 3847 if ( msr & TIOCM_RTS ) tmp |= CMD8251_RTS; 3848 3849 pc98_i8251_or_cmd( com, tmp ); 3850 splx(s); 3851} 3852 3853static void 3854com_tiocm_bic(struct com_s *com, int msr) 3855{ 3856 int s; 3857 int tmp = msr; 3858 3859 s=spltty(); 3860 com->pc98_prev_modem_status &= ~( msr & (TIOCM_LE|TIOCM_DTR|TIOCM_RTS) ); 3861 if ( msr & TIOCM_DTR ) tmp |= CMD8251_DTR; 3862 if ( msr & TIOCM_RTS ) tmp |= CMD8251_RTS; 3863 3864 pc98_i8251_clear_cmd( com, tmp ); 3865 splx(s); 3866} 3867 3868static int 3869com_tiocm_get(struct com_s *com) 3870{ 3871 return( com->pc98_prev_modem_status ); 3872} 3873 3874static int 3875com_tiocm_get_delta(struct com_s *com) 3876{ 3877 int tmp; 3878 3879 tmp = com->pc98_modem_delta; 3880 com->pc98_modem_delta = 0; 3881 return( tmp ); 3882} 3883 3884/* convert to TIOCM_?? ( ioctl.h ) */ 3885static int 3886pc98_get_modem_status(struct com_s *com) 3887{ 3888 register int msr; 3889 3890 msr = com->pc98_prev_modem_status 3891 & ~(TIOCM_CAR|TIOCM_RI|TIOCM_DSR|TIOCM_CTS); 3892 if (com->pc98_8251fifo_enable) { 3893 int stat2; 3894 3895 stat2 = inb(I8251F_msr); 3896 if ( stat2 & CICSCDF_CD ) msr |= TIOCM_CAR; 3897 if ( stat2 & CICSCDF_CI ) msr |= TIOCM_RI; 3898 if ( stat2 & CICSCDF_DR ) msr |= TIOCM_DSR; 3899 if ( stat2 & CICSCDF_CS ) msr |= TIOCM_CTS; 3900#if COM_CARRIER_DETECT_EMULATE 3901 if ( msr & (TIOCM_DSR|TIOCM_CTS) ) { 3902 msr |= TIOCM_CAR; 3903 } 3904#endif 3905 } else { 3906 int stat, stat2; 3907 3908 stat = inb(com->sts_port); 3909 stat2 = inb(com->in_modem_port); 3910 if ( !(stat2 & CICSCD_CD) ) msr |= TIOCM_CAR; 3911 if ( !(stat2 & CICSCD_CI) ) msr |= TIOCM_RI; 3912 if ( stat & STS8251_DSR ) msr |= TIOCM_DSR; 3913 if ( !(stat2 & CICSCD_CS) ) msr |= TIOCM_CTS; 3914#if COM_CARRIER_DETECT_EMULATE 3915 if ( msr & (TIOCM_DSR|TIOCM_CTS) ) { 3916 msr |= TIOCM_CAR; 3917 } 3918#endif 3919 } 3920 return(msr); 3921} 3922 3923static void 3924pc98_check_msr(void* chan) 3925{ 3926 int msr, delta; 3927 int s; 3928 register struct tty *tp; 3929 struct com_s *com; 3930 struct cdev *dev; 3931 3932 dev=(struct cdev *)chan; 3933 com = dev->si_drv1; 3934 tp = dev->si_tty; 3935 3936 s = spltty(); 3937 msr = pc98_get_modem_status(com); 3938 /* make change flag */ 3939 delta = msr ^ com->pc98_prev_modem_status; 3940 if ( delta & TIOCM_CAR ) { 3941 if ( com->modem_car_chg_timer ) { 3942 if ( -- com->modem_car_chg_timer ) 3943 msr ^= TIOCM_CAR; 3944 } else { 3945 if ((com->modem_car_chg_timer = (msr & TIOCM_CAR) ? 3946 DCD_ON_RECOGNITION : DCD_OFF_TOLERANCE) != 0) 3947 msr ^= TIOCM_CAR; 3948 } 3949 } else 3950 com->modem_car_chg_timer = 0; 3951 delta = ( msr ^ com->pc98_prev_modem_status ) & 3952 (TIOCM_CAR|TIOCM_RI|TIOCM_DSR|TIOCM_CTS); 3953 com->pc98_prev_modem_status = msr; 3954 delta = ( com->pc98_modem_delta |= delta ); 3955 splx(s); 3956 if ( com->modem_checking || (tp->t_state & (TS_ISOPEN)) ) { 3957 if ( delta ) { 3958 commint(dev); 3959 } 3960 timeout(pc98_check_msr, (caddr_t)dev, 3961 PC98_CHECK_MODEM_INTERVAL); 3962 } else { 3963 com->modem_checking = 0; 3964 } 3965} 3966 3967static void 3968pc98_msrint_start(struct cdev *dev) 3969{ 3970 struct com_s *com; 3971 int s = spltty(); 3972 3973 com = dev->si_drv1; 3974 /* modem control line check routine envoke interval is 1/10 sec */ 3975 if ( com->modem_checking == 0 ) { 3976 com->pc98_prev_modem_status = pc98_get_modem_status(com); 3977 com->pc98_modem_delta = 0; 3978 timeout(pc98_check_msr, (caddr_t)dev, 3979 PC98_CHECK_MODEM_INTERVAL); 3980 com->modem_checking = 1; 3981 } 3982 splx(s); 3983} 3984 3985static void 3986pc98_disable_i8251_interrupt(struct com_s *com, int mod) 3987{ 3988 /* disable interrupt */ 3989 register int tmp; 3990 3991 mod |= ~(IEN_Tx|IEN_TxEMP|IEN_Rx); 3992 COM_INT_DISABLE 3993 tmp = inb( com->intr_ctrl_port ) & ~(IEN_Tx|IEN_TxEMP|IEN_Rx); 3994 outb( com->intr_ctrl_port, (com->intr_enable&=~mod) | tmp ); 3995 COM_INT_ENABLE 3996} 3997 3998static void 3999pc98_enable_i8251_interrupt(struct com_s *com, int mod) 4000{ 4001 register int tmp; 4002 4003 COM_INT_DISABLE 4004 tmp = inb( com->intr_ctrl_port ) & ~(IEN_Tx|IEN_TxEMP|IEN_Rx); 4005 outb( com->intr_ctrl_port, (com->intr_enable|=mod) | tmp ); 4006 COM_INT_ENABLE 4007} 4008 4009static int 4010pc98_check_i8251_interrupt(struct com_s *com) 4011{ 4012 return ( com->intr_enable & 0x07 ); 4013} 4014 4015static void 4016pc98_i8251_clear_cmd(struct com_s *com, int x) 4017{ 4018 int tmp; 4019 4020 COM_INT_DISABLE 4021 tmp = com->pc98_prev_siocmd & ~(x); 4022 if (com->pc98_8251fifo_enable) 4023 outb(I8251F_fcr, 0); 4024 outb(com->cmd_port, tmp); 4025 com->pc98_prev_siocmd = tmp & ~(CMD8251_ER|CMD8251_RESET|CMD8251_EH); 4026 if (com->pc98_8251fifo_enable) 4027 outb(I8251F_fcr, CTRL8251F_ENABLE); 4028 COM_INT_ENABLE 4029} 4030 4031static void 4032pc98_i8251_or_cmd(struct com_s *com, int x) 4033{ 4034 int tmp; 4035 4036 COM_INT_DISABLE 4037 if (com->pc98_8251fifo_enable) 4038 outb(I8251F_fcr, 0); 4039 tmp = com->pc98_prev_siocmd | (x); 4040 outb(com->cmd_port, tmp); 4041 com->pc98_prev_siocmd = tmp & ~(CMD8251_ER|CMD8251_RESET|CMD8251_EH); 4042 if (com->pc98_8251fifo_enable) 4043 outb(I8251F_fcr, CTRL8251F_ENABLE); 4044 COM_INT_ENABLE 4045} 4046 4047static void 4048pc98_i8251_set_cmd(struct com_s *com, int x) 4049{ 4050 int tmp; 4051 4052 COM_INT_DISABLE 4053 if (com->pc98_8251fifo_enable) 4054 outb(I8251F_fcr, 0); 4055 tmp = (x); 4056 outb(com->cmd_port, tmp); 4057 com->pc98_prev_siocmd = tmp & ~(CMD8251_ER|CMD8251_RESET|CMD8251_EH); 4058 if (com->pc98_8251fifo_enable) 4059 outb(I8251F_fcr, CTRL8251F_ENABLE); 4060 COM_INT_ENABLE 4061} 4062 4063static void 4064pc98_i8251_clear_or_cmd(struct com_s *com, int clr, int x) 4065{ 4066 int tmp; 4067 COM_INT_DISABLE 4068 if (com->pc98_8251fifo_enable) 4069 outb(I8251F_fcr, 0); 4070 tmp = com->pc98_prev_siocmd & ~(clr); 4071 tmp |= (x); 4072 outb(com->cmd_port, tmp); 4073 com->pc98_prev_siocmd = tmp & ~(CMD8251_ER|CMD8251_RESET|CMD8251_EH); 4074 if (com->pc98_8251fifo_enable) 4075 outb(I8251F_fcr, CTRL8251F_ENABLE); 4076 COM_INT_ENABLE 4077} 4078 4079static int 4080pc98_i8251_get_cmd(struct com_s *com) 4081{ 4082 return com->pc98_prev_siocmd; 4083} 4084 4085static int 4086pc98_i8251_get_mod(struct com_s *com) 4087{ 4088 return com->pc98_prev_siomod; 4089} 4090 4091static void 4092pc98_i8251_reset(struct com_s *com, int mode, int command) 4093{ 4094 if (com->pc98_8251fifo_enable) 4095 outb(I8251F_fcr, 0); 4096 outb(com->cmd_port, 0); /* dummy */ 4097 DELAY(2); 4098 outb(com->cmd_port, 0); /* dummy */ 4099 DELAY(2); 4100 outb(com->cmd_port, 0); /* dummy */ 4101 DELAY(2); 4102 outb(com->cmd_port, CMD8251_RESET); /* internal reset */ 4103 DELAY(2); 4104 outb(com->cmd_port, mode ); /* mode register */ 4105 com->pc98_prev_siomod = mode; 4106 DELAY(2); 4107 pc98_i8251_set_cmd( com, (command|CMD8251_ER) ); 4108 DELAY(10); 4109 if (com->pc98_8251fifo_enable) 4110 outb(I8251F_fcr, CTRL8251F_ENABLE | 4111 CTRL8251F_XMT_RST | CTRL8251F_RCV_RST); 4112} 4113 4114static void 4115pc98_check_sysclock(void) 4116{ 4117 /* get system clock from port */ 4118 if ( pc98_machine_type & M_8M ) { 4119 /* 8 MHz system & H98 */ 4120 sysclock = 8; 4121 } else { 4122 /* 5 MHz system */ 4123 sysclock = 5; 4124 } 4125} 4126 4127static void 4128com_cflag_and_speed_set( struct com_s *com, int cflag, int speed) 4129{ 4130 int cfcr=0; 4131 int previnterrupt; 4132 u_int count; 4133 4134 if (pc98_ttspeedtab(com, speed, &count) != 0) 4135 return; 4136 4137 previnterrupt = pc98_check_i8251_interrupt(com); 4138 pc98_disable_i8251_interrupt( com, IEN_Tx|IEN_TxEMP|IEN_Rx ); 4139 4140 switch ( cflag&CSIZE ) { 4141 case CS5: 4142 cfcr = MOD8251_5BITS; break; 4143 case CS6: 4144 cfcr = MOD8251_6BITS; break; 4145 case CS7: 4146 cfcr = MOD8251_7BITS; break; 4147 case CS8: 4148 cfcr = MOD8251_8BITS; break; 4149 } 4150 if ( cflag&PARENB ) { 4151 if ( cflag&PARODD ) 4152 cfcr |= MOD8251_PODD; 4153 else 4154 cfcr |= MOD8251_PEVEN; 4155 } else 4156 cfcr |= MOD8251_PDISAB; 4157 4158 if ( cflag&CSTOPB ) 4159 cfcr |= MOD8251_STOP2; 4160 else 4161 cfcr |= MOD8251_STOP1; 4162 4163 if ( count & 0x10000 ) 4164 cfcr |= MOD8251_CLKX1; 4165 else 4166 cfcr |= MOD8251_CLKX16; 4167 4168 if (epson_machine_id != 0x20) { /* XXX */ 4169 int tmp; 4170 while (!((tmp = inb(com->sts_port)) & STS8251_TxEMP)) 4171 ; 4172 } 4173 /* set baud rate from ospeed */ 4174 pc98_set_baud_rate( com, count ); 4175 4176 if ( cfcr != pc98_i8251_get_mod(com) ) 4177 pc98_i8251_reset(com, cfcr, pc98_i8251_get_cmd(com) ); 4178 4179 pc98_enable_i8251_interrupt( com, previnterrupt ); 4180} 4181 4182static int 4183pc98_ttspeedtab(struct com_s *com, int speed, u_int *divisor) 4184{ 4185 int if_type, effect_sp, count = -1, mod; 4186 4187 if_type = com->pc98_if_type & 0x0f; 4188 4189 switch (com->pc98_if_type) { 4190 case COM_IF_INTERNAL: 4191 if (PC98SIO_baud_rate_port(if_type) != -1) { 4192 count = ttspeedtab(speed, if_8251_type[if_type].speedtab); 4193 if (count > 0) { 4194 count |= COM1_EXT_CLOCK; 4195 break; 4196 } 4197 } 4198 4199 /* for *1CLK asynchronous! mode, TEFUTEFU */ 4200 mod = (sysclock == 5) ? 2457600 : 1996800; 4201 effect_sp = ttspeedtab( speed, pc98speedtab ); 4202 if ( effect_sp < 0 ) /* XXX */ 4203 effect_sp = ttspeedtab( (speed - 1), pc98speedtab ); 4204 if ( effect_sp <= 0 ) 4205 return effect_sp; 4206 if ( effect_sp == speed ) 4207 mod /= 16; 4208 if ( mod % effect_sp ) 4209 return(-1); 4210 count = mod / effect_sp; 4211 if ( count > 65535 ) 4212 return(-1); 4213 if ( effect_sp != speed ) 4214 count |= 0x10000; 4215 break; 4216 case COM_IF_PC9861K_1: 4217 case COM_IF_PC9861K_2: 4218 count = 1; 4219 break; 4220 case COM_IF_IND_SS_1: 4221 case COM_IF_IND_SS_2: 4222 case COM_IF_PIO9032B_1: 4223 case COM_IF_PIO9032B_2: 4224 count = ttspeedtab( speed, if_8251_type[if_type].speedtab ); 4225 break; 4226 case COM_IF_B98_01_1: 4227 case COM_IF_B98_01_2: 4228 count = ttspeedtab( speed, if_8251_type[if_type].speedtab ); 4229#ifdef B98_01_OLD 4230 if (count == 0 || count == 1) { 4231 count += 4; 4232 count |= 0x20000; /* x1 mode for 76800 and 153600 */ 4233 } 4234#endif 4235 break; 4236 } 4237 4238 if (count < 0) 4239 return count; 4240 4241 *divisor = (u_int) count; 4242 return 0; 4243} 4244 4245static void 4246pc98_set_baud_rate( struct com_s *com, u_int count ) 4247{ 4248 int if_type, io, s; 4249 4250 if_type = com->pc98_if_type & 0x0f; 4251 io = rman_get_start(com->ioportres) & 0xff00; 4252 4253 switch (com->pc98_if_type) { 4254 case COM_IF_INTERNAL: 4255 if (PC98SIO_baud_rate_port(if_type) != -1) { 4256 if (count & COM1_EXT_CLOCK) { 4257 outb((Port_t)PC98SIO_baud_rate_port(if_type), count & 0xff); 4258 break; 4259 } else { 4260 outb((Port_t)PC98SIO_baud_rate_port(if_type), 0x09); 4261 } 4262 } 4263 4264 if (count == 0) 4265 return; 4266 4267 /* set i8253 */ 4268 s = splclock(); 4269 if (count != 3) 4270 outb( 0x77, 0xb6 ); 4271 else 4272 outb( 0x77, 0xb4 ); 4273 outb( 0x5f, 0); 4274 outb( 0x75, count & 0xff ); 4275 outb( 0x5f, 0); 4276 outb( 0x75, (count >> 8) & 0xff ); 4277 splx(s); 4278 break; 4279 case COM_IF_IND_SS_1: 4280 case COM_IF_IND_SS_2: 4281 outb(io | PC98SIO_intr_ctrl_port(if_type), 0); 4282 outb(io | PC98SIO_baud_rate_port(if_type), 0); 4283 outb(io | PC98SIO_baud_rate_port(if_type), 0xc0); 4284 outb(io | PC98SIO_baud_rate_port(if_type), (count >> 8) | 0x80); 4285 outb(io | PC98SIO_baud_rate_port(if_type), count & 0xff); 4286 break; 4287 case COM_IF_PIO9032B_1: 4288 case COM_IF_PIO9032B_2: 4289 outb(io | PC98SIO_baud_rate_port(if_type), count); 4290 break; 4291 case COM_IF_B98_01_1: 4292 case COM_IF_B98_01_2: 4293 outb(io | PC98SIO_baud_rate_port(if_type), count & 0x0f); 4294#ifdef B98_01_OLD 4295 /* 4296 * Some old B98_01 board should be controlled 4297 * in different way, but this hasn't been tested yet. 4298 */ 4299 outb(io | PC98SIO_func_port(if_type), 4300 (count & 0x20000) ? 0xf0 : 0xf2); 4301#endif 4302 break; 4303 } 4304} 4305static int 4306pc98_check_if_type(device_t dev, struct siodev *iod) 4307{ 4308 int irr, io, if_type, tmp; 4309 static short irq_tab[2][8] = { 4310 { 3, 5, 6, 9, 10, 12, 13, -1}, 4311 { 3, 10, 12, 13, 5, 6, 9, -1} 4312 }; 4313 4314 if_type = iod->if_type & 0x0f; 4315 iod->irq = 0; 4316 io = isa_get_port(dev) & 0xff00; 4317 4318 if (IS_8251(iod->if_type)) { 4319 if (PC98SIO_func_port(if_type) != -1) { 4320 outb(io | PC98SIO_func_port(if_type), 0xf2); 4321 tmp = ttspeedtab(9600, if_8251_type[if_type].speedtab); 4322 if (tmp != -1 && PC98SIO_baud_rate_port(if_type) != -1) 4323 outb(io | PC98SIO_baud_rate_port(if_type), tmp); 4324 } 4325 4326 iod->cmd = io | PC98SIO_cmd_port(if_type); 4327 iod->sts = io | PC98SIO_sts_port(if_type); 4328 iod->mod = io | PC98SIO_in_modem_port(if_type); 4329 iod->ctrl = io | PC98SIO_intr_ctrl_port(if_type); 4330 4331 if (iod->if_type == COM_IF_INTERNAL) { 4332 iod->irq = 4; 4333 4334 if (pc98_check_8251vfast()) { 4335 PC98SIO_baud_rate_port(if_type) = I8251F_div; 4336 if_8251_type[if_type].speedtab = pc98fast_speedtab; 4337 } 4338 } else { 4339 tmp = inb( iod->mod ) & if_8251_type[if_type].irr_mask; 4340 if ((isa_get_port(dev) & 0xff) == IO_COM2) 4341 iod->irq = irq_tab[0][tmp]; 4342 else 4343 iod->irq = irq_tab[1][tmp]; 4344 } 4345 } else { 4346 irr = if_16550a_type[if_type].irr_read; 4347#ifdef COM_MULTIPORT 4348 if (!COM_ISMULTIPORT(device_get_flags(dev)) || 4349 device_get_unit(dev) == COM_MPMASTER(device_get_flags(dev))) 4350#endif 4351 if (irr != -1) { 4352 tmp = inb(io | irr); 4353 if (isa_get_port(dev) & 0x01) /* XXX depend on RSB-384 */ 4354 iod->irq = irq_tab[1][tmp >> 3]; 4355 else 4356 iod->irq = irq_tab[0][tmp & 0x07]; 4357 } 4358 } 4359 if ( iod->irq == -1 ) return -1; 4360 4361 return 0; 4362} 4363static void 4364pc98_set_ioport(struct com_s *com) 4365{ 4366 int if_type = com->pc98_if_type & 0x0f; 4367 Port_t io = rman_get_start(com->ioportres) & 0xff00; 4368 4369 pc98_check_sysclock(); 4370 com->data_port = io | PC98SIO_data_port(if_type); 4371 com->cmd_port = io | PC98SIO_cmd_port(if_type); 4372 com->sts_port = io | PC98SIO_sts_port(if_type); 4373 com->in_modem_port = io | PC98SIO_in_modem_port(if_type); 4374 com->intr_ctrl_port = io | PC98SIO_intr_ctrl_port(if_type); 4375} 4376static int 4377pc98_check_8251vfast(void) 4378{ 4379 int i; 4380 4381 outb(I8251F_div, 0x8c); 4382 DELAY(10); 4383 for (i = 0; i < 100; i++) { 4384 if ((inb(I8251F_div) & 0x80) != 0) { 4385 i = 0; 4386 break; 4387 } 4388 DELAY(1); 4389 } 4390 outb(I8251F_div, 0); 4391 DELAY(10); 4392 for (; i < 100; i++) { 4393 if ((inb(I8251F_div) & 0x80) == 0) 4394 return 1; 4395 DELAY(1); 4396 } 4397 4398 return 0; 4399} 4400static int 4401pc98_check_8251fifo(void) 4402{ 4403 u_char tmp1, tmp2; 4404 4405 tmp1 = inb(I8251F_iir); 4406 DELAY(10); 4407 tmp2 = inb(I8251F_iir); 4408 if (((tmp1 ^ tmp2) & 0x40) != 0 && ((tmp1 | tmp2) & 0x20) == 0) 4409 return 1; 4410 4411 return 0; 4412} 4413#endif /* PC98 defined */ 4414