sio.c revision 135517
11844Swollman/*- 250476Speter * Copyright (c) 1991 The Regents of the University of California. 31638Srgrimes * All rights reserved. 494940Sru * 51638Srgrimes * Redistribution and use in source and binary forms, with or without 6103713Smarkm * modification, are permitted provided that the following conditions 71638Srgrimes * are met: 8119607Sru * 1. Redistributions of source code must retain the above copyright 9119607Sru * notice, this list of conditions and the following disclaimer. 10119607Sru * 2. Redistributions in binary form must reproduce the above copyright 11119607Sru * notice, this list of conditions and the following disclaimer in the 12119607Sru * documentation and/or other materials provided with the distribution. 13119607Sru * 4. Neither the name of the University nor the names of its contributors 14119607Sru * may be used to endorse or promote products derived from this software 15119607Sru * without specific prior written permission. 16119607Sru * 17117034Sgordon * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 18119607Sru * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 191638Srgrimes * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 202827Sjkh * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 211638Srgrimes * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 222827Sjkh * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 231638Srgrimes * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24125474Sru * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 251844Swollman * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 261844Swollman * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 271638Srgrimes * SUCH DAMAGE. 2894424Sru * 2994424Sru * $FreeBSD: head/sys/pc98/cbus/sio.c 135517 2004-09-20 14:01:38Z nyan $ 3094424Sru * from: @(#)com.c 7.5 (Berkeley) 5/16/91 3194424Sru * from: i386/isa sio.c,v 1.234 321638Srgrimes */ 331638Srgrimes 341638Srgrimes#include "opt_comconsole.h" 3536054Sbde#include "opt_compat.h" 36125119Sru#include "opt_gdb.h" 3736054Sbde#include "opt_kdb.h" 3836054Sbde#include "opt_sio.h" 3936054Sbde 4036054Sbde/* 411844Swollman * Serial driver, based on 386BSD-0.1 com driver. 421638Srgrimes * Mostly rewritten to use pseudo-DMA. 4394518Sru * Works for National Semiconductor NS8250-NS16550AF UARTs. 4494518Sru * COM driver, based on HP dca driver. 4594518Sru * 4694518Sru * Changes for PC-Card integration: 4794518Sru * - Added PC-Card driver table and handlers 4894518Sru */ 4994518Sru/*=============================================================== 508321Sbde * 386BSD(98),FreeBSD-1.1x(98) com driver. 511844Swollman * ----- 5294518Sru * modified for PC9801 by M.Ishii 5394424Sru * Kyoto University Microcomputer Club (KMC) 5494424Sru * Chou "TEFUTEFU" Hirotomi 5594424Sru * Kyoto Univ. the faculty of medicine 562351Sbde *=============================================================== 5794424Sru * FreeBSD-2.0.1(98) sio driver. 581638Srgrimes * ----- 592351Sbde * modified for pc98 Internal i8251 and MICRO CORE MC16550II 602351Sbde * T.Koike(hfc01340@niftyserve.or.jp) 612351Sbde * implement kernel device configuration 622351Sbde * aizu@orient.center.nitech.ac.jp 632351Sbde * 642351Sbde * Notes. 6533624Seivind * ----- 6634081Sbde * PC98 localization based on 386BSD(98) com driver. Using its PC98 local 6794497Sru * functions. 6894497Sru * This driver is under debugging,has bugs. 6994497Sru */ 7094410Sru/* 7133624Seivind * modified for AIWA B98-01 7294518Sru * by T.Hatanou <hatanou@yasuda.comm.waseda.ac.jp> last update: 15 Sep.1995 731638Srgrimes */ 741638Srgrimes/* 751638Srgrimes * Modified by Y.Takahashi of Kogakuin University. 7674806Sru */ 7774806Sru/* 781638Srgrimes * modified for 8251(FIFO) by Seigo TANIMURA <tanimura@FreeBSD.org> 7958493Sru */ 8074806Sru 8174941Sru#include <sys/param.h> 8274941Sru#include <sys/systm.h> 831638Srgrimes#include <sys/bus.h> 841638Srgrimes#include <sys/conf.h> 851638Srgrimes#include <sys/fcntl.h> 8697769Sru#include <sys/interrupt.h> 8774806Sru#include <sys/kdb.h> 8896164Sru#include <sys/kernel.h> 8974806Sru#include <sys/limits.h> 901638Srgrimes#include <sys/lock.h> 91119607Sru#include <sys/malloc.h> 92119607Sru#include <sys/module.h> 93119607Sru#include <sys/mutex.h> 941638Srgrimes#include <sys/proc.h> 95119607Sru#include <sys/reboot.h> 96119607Sru#include <sys/serial.h> 97119607Sru#include <sys/sysctl.h> 98119607Sru#include <sys/syslog.h> 99125620Sru#include <sys/tty.h> 100125620Sru#include <machine/bus.h> 10155670Sbde#include <sys/rman.h> 10224750Sbde#include <sys/timepps.h> 103125620Sru#include <sys/uio.h> 104125620Sru#include <sys/cons.h> 105125620Sru 106125620Sru#include <isa/isavar.h> 107125620Sru 10846541Sbde#include <machine/resource.h> 10994497Sru 11094497Sru#include <dev/sio/sioreg.h> 11124750Sbde#include <dev/sio/siovar.h> 11228945Speter 113125620Sru#ifdef PC98 11424750Sbde#include <pc98/pc98/pc98.h> 1151638Srgrimes#include <pc98/pc98/pc98_machdep.h> 1161638Srgrimes#endif 11749328Shoek 11849328Shoek#ifdef COM_ESP 11949328Shoek#include <dev/ic/esp.h> 12049328Shoek#endif 12149328Shoek#include <dev/ic/ns16550.h> 122125620Sru#ifdef PC98 12396163Sru#include <dev/ic/i8251.h> 12499343Sru#include <dev/ic/rsa.h> 12596163Sru#endif 1261638Srgrimes 12775083Sru#define LOTS_OF_EVENTS 64 /* helps separate urgent events from input */ 128100872Sru 12975083Sru#define CALLOUT_MASK 0x80 13075083Sru#define CONTROL_MASK 0x60 131100872Sru#define CONTROL_INIT_STATE 0x20 13249328Shoek#define CONTROL_LOCK_STATE 0x40 1331638Srgrimes#define DEV_TO_UNIT(dev) (MINOR_TO_UNIT(minor(dev))) 13475083Sru#define MINOR_TO_UNIT(mynor) ((((mynor) & ~0xffffU) >> (8 + 3)) \ 13595734Sru | ((mynor) & 0x1f)) 1361638Srgrimes#define UNIT_TO_MINOR(unit) ((((unit) & ~0x1fU) << (8 + 3)) \ 13775284Sru | ((unit) & 0x1f)) 13875284Sru 13999343Sru/* 14075284Sru * Meaning of flags: 14175284Sru * 14275284Sru * 0x00000001 shared IRQs 14375284Sru * 0x00000002 disable FIFO 14475284Sru * 0x00000008 recover sooner from lost output interrupts 14575284Sru * 0x00000010 device is potential system console 14675284Sru * 0x00000020 device is forced to become system console 14775284Sru * 0x00000040 device is reserved for low-level IO 14875284Sru * 0x00000080 use this port for remote kernel debugging 14975284Sru * 0x0000??00 minor number of master port 15075284Sru * 0x00010000 PPS timestamping on CTS instead of DCD 15175284Sru * 0x00080000 IIR_TXRDY bug 15275284Sru * 0x00400000 If no comconsole found then mark as a comconsole 15375284Sru * 0x1?000000 interface type 15475284Sru */ 15575284Sru 15688055Sru#ifdef COM_MULTIPORT 15788055Sru/* checks in flags for multiport and which is multiport "master chip" 158100872Sru * for a given card 15975284Sru */ 16094954Sru#define COM_ISMULTIPORT(flags) ((flags) & 0x01) 16175284Sru#define COM_MPMASTER(flags) (((flags) >> 8) & 0x0ff) 16275284Sru#ifndef PC98 16375284Sru#define COM_NOTAST4(flags) ((flags) & 0x04) 16475284Sru#endif 16599257Sru#else 16699257Sru#define COM_ISMULTIPORT(flags) (0) 16799257Sru#endif /* COM_MULTIPORT */ 16897769Sru 16996668Sru#define COM_C_IIR_TXRDYBUG 0x80000 17099256Sru#define COM_CONSOLE(flags) ((flags) & 0x10) 17196462Sru#define COM_DEBUGGER(flags) ((flags) & 0x80) 17296163Sru#ifndef PC98 17396164Sru#define COM_FIFOSIZE(flags) (((flags) & 0xff000000) >> 24) 17499343Sru#endif 17596163Sru#define COM_FORCECONSOLE(flags) ((flags) & 0x20) 17696163Sru#define COM_IIR_TXRDYBUG(flags) ((flags) & COM_C_IIR_TXRDYBUG) 1771844Swollman#define COM_LLCONSOLE(flags) ((flags) & 0x40) 1781638Srgrimes#define COM_LOSESOUTINTS(flags) ((flags) & 0x08) 1791638Srgrimes#define COM_NOFIFO(flags) ((flags) & 0x02) 180103713Smarkm#ifndef PC98 1811638Srgrimes#define COM_NOSCR(flags) ((flags) & 0x100000) 182103713Smarkm#endif 1831638Srgrimes#define COM_PPSCTS(flags) ((flags) & 0x10000) 1841638Srgrimes#ifndef PC98 1851638Srgrimes#define COM_ST16650A(flags) ((flags) & 0x20000) 1861638Srgrimes#define COM_TI16754(flags) ((flags) & 0x200000) 1871638Srgrimes#endif 18874842Sru 1891844Swollman#define sio_getreg(com, off) \ 1901844Swollman (bus_space_read_1((com)->bst, (com)->bsh, (off))) 19134081Sbde#define sio_setreg(com, off, value) \ 19294113Sru (bus_space_write_1((com)->bst, (com)->bsh, (off), (value))) 19334087Sbde 19434081Sbde/* 19534081Sbde * com state bits. 19616663Sjkh * (CS_BUSY | CS_TTGO) and (CS_BUSY | CS_TTGO | CS_ODEVREADY) must be higher 19776861Skris * than the other bits so that they can be tested as a group without masking 19876861Skris * off the low bits. 199 * 200 * The following com and tty flags correspond closely: 201 * CS_BUSY = TS_BUSY (maintained by comstart(), siopoll() and 202 * comstop()) 203 * CS_TTGO = ~TS_TTSTOP (maintained by comparam() and comstart()) 204 * CS_CTS_OFLOW = CCTS_OFLOW (maintained by comparam()) 205 * CS_RTS_IFLOW = CRTS_IFLOW (maintained by comparam()) 206 * TS_FLUSH is not used. 207 * XXX I think TIOCSETA doesn't clear TS_TTSTOP when it clears IXON. 208 * XXX CS_*FLOW should be CF_*FLOW in com->flags (control flags not state). 209 */ 210#define CS_BUSY 0x80 /* output in progress */ 211#define CS_TTGO 0x40 /* output not stopped by XOFF */ 212#define CS_ODEVREADY 0x20 /* external device h/w ready (CTS) */ 213#define CS_CHECKMSR 1 /* check of MSR scheduled */ 214#define CS_CTS_OFLOW 2 /* use CTS output flow control */ 215#define CS_ODONE 4 /* output completed */ 216#define CS_RTS_IFLOW 8 /* use RTS input flow control */ 217#define CSE_BUSYCHECK 1 /* siobusycheck() scheduled */ 218 219static char const * const error_desc[] = { 220#define CE_OVERRUN 0 221 "silo overflow", 222#define CE_INTERRUPT_BUF_OVERFLOW 1 223 "interrupt-level buffer overflow", 224#define CE_TTY_BUF_OVERFLOW 2 225 "tty-level buffer overflow", 226}; 227 228#define CE_NTYPES 3 229#define CE_RECORD(com, errnum) (++(com)->delta_error_counts[errnum]) 230 231/* types. XXX - should be elsewhere */ 232typedef u_int Port_t; /* hardware port */ 233typedef u_char bool_t; /* boolean */ 234 235/* queue of linear buffers */ 236struct lbq { 237 u_char *l_head; /* next char to process */ 238 u_char *l_tail; /* one past the last char to process */ 239 struct lbq *l_next; /* next in queue */ 240 bool_t l_queued; /* nonzero if queued */ 241}; 242 243/* com device structure */ 244struct com_s { 245 u_char state; /* miscellaneous flag bits */ 246 bool_t active_out; /* nonzero if the callout device is open */ 247 u_char cfcr_image; /* copy of value written to CFCR */ 248#ifdef COM_ESP 249 bool_t esp; /* is this unit a hayes esp board? */ 250#endif 251 u_char extra_state; /* more flag bits, separate for order trick */ 252 u_char fifo_image; /* copy of value written to FIFO */ 253 bool_t hasfifo; /* nonzero for 16550 UARTs */ 254 bool_t loses_outints; /* nonzero if device loses output interrupts */ 255 u_char mcr_image; /* copy of value written to MCR */ 256#ifdef COM_MULTIPORT 257 bool_t multiport; /* is this unit part of a multiport device? */ 258#endif /* COM_MULTIPORT */ 259 bool_t no_irq; /* nonzero if irq is not attached */ 260 bool_t gone; /* hardware disappeared */ 261 bool_t poll; /* nonzero if polling is required */ 262 bool_t poll_output; /* nonzero if polling for output is required */ 263 bool_t st16650a; /* nonzero if Startech 16650A compatible */ 264 int unit; /* unit number */ 265 u_int flags; /* copy of device flags */ 266 u_int tx_fifo_size; 267 u_int wopeners; /* # processes waiting for DCD in open() */ 268 269 /* 270 * The high level of the driver never reads status registers directly 271 * because there would be too many side effects to handle conveniently. 272 * Instead, it reads copies of the registers stored here by the 273 * interrupt handler. 274 */ 275 u_char last_modem_status; /* last MSR read by intr handler */ 276 u_char prev_modem_status; /* last MSR handled by high level */ 277 278 u_char *ibuf; /* start of input buffer */ 279 u_char *ibufend; /* end of input buffer */ 280 u_char *ibufold; /* old input buffer, to be freed */ 281 u_char *ihighwater; /* threshold in input buffer */ 282 u_char *iptr; /* next free spot in input buffer */ 283 int ibufsize; /* size of ibuf (not include error bytes) */ 284 int ierroff; /* offset of error bytes in ibuf */ 285 286 struct lbq obufq; /* head of queue of output buffers */ 287 struct lbq obufs[2]; /* output buffers */ 288 289 bus_space_tag_t bst; 290 bus_space_handle_t bsh; 291 292#ifdef PC98 293 Port_t cmd_port; 294 Port_t sts_port; 295 Port_t in_modem_port; 296 Port_t intr_ctrl_port; 297 Port_t rsabase; /* Iobase address of an I/O-DATA RSA board. */ 298 int intr_enable; 299 int pc98_prev_modem_status; 300 int pc98_modem_delta; 301 int modem_car_chg_timer; 302 int pc98_prev_siocmd; 303 int pc98_prev_siomod; 304 int modem_checking; 305 int pc98_if_type; 306 307 bool_t pc98_8251fifo; 308 bool_t pc98_8251fifo_enable; 309#endif /* PC98 */ 310 Port_t data_port; /* i/o ports */ 311#ifdef COM_ESP 312 Port_t esp_port; 313#endif 314 Port_t int_ctl_port; 315 Port_t int_id_port; 316 Port_t modem_ctl_port; 317 Port_t line_status_port; 318 Port_t modem_status_port; 319 320 struct tty *tp; /* cross reference */ 321 322 bool_t do_timestamp; 323 struct timeval timestamp; 324 struct pps_state pps; 325 int pps_bit; 326#ifdef ALT_BREAK_TO_DEBUGGER 327 int alt_brk_state; 328#endif 329 330 u_long bytes_in; /* statistics */ 331 u_long bytes_out; 332 u_int delta_error_counts[CE_NTYPES]; 333 u_long error_counts[CE_NTYPES]; 334 335 u_long rclk; 336 337 struct resource *irqres; 338 struct resource *ioportres; 339 int ioportrid; 340 void *cookie; 341 struct cdev *devs[6]; 342 343 /* 344 * Data area for output buffers. Someday we should build the output 345 * buffer queue without copying data. 346 */ 347#ifdef PC98 348 int obufsize; 349 u_char *obuf1; 350 u_char *obuf2; 351#else 352 u_char obuf1[256]; 353 u_char obuf2[256]; 354#endif 355}; 356 357#ifdef COM_ESP 358static int espattach(struct com_s *com, Port_t esp_port); 359#endif 360 361static void combreak(struct tty *tp, int sig); 362static timeout_t siobusycheck; 363static u_int siodivisor(u_long rclk, speed_t speed); 364static void comhardclose(struct com_s *com); 365static void sioinput(struct com_s *com); 366static void siointr1(struct com_s *com); 367static void siointr(void *arg); 368static int commodem(struct tty *tp, int sigon, int sigoff); 369static int comparam(struct tty *tp, struct termios *t); 370static void siopoll(void *); 371static void siosettimeout(void); 372static int siosetwater(struct com_s *com, speed_t speed); 373static void comstart(struct tty *tp); 374static void comstop(struct tty *tp, int rw); 375static timeout_t comwakeup; 376 377char sio_driver_name[] = "sio"; 378static struct mtx sio_lock; 379static int sio_inited; 380 381/* table and macro for fast conversion from a unit number to its com struct */ 382devclass_t sio_devclass; 383#define com_addr(unit) ((struct com_s *) \ 384 devclass_get_softc(sio_devclass, unit)) /* XXX */ 385 386static d_open_t sioopen; 387static d_close_t sioclose; 388static d_read_t sioread; 389static d_write_t siowrite; 390static d_ioctl_t sioioctl; 391 392static struct cdevsw sio_cdevsw = { 393 .d_version = D_VERSION, 394 .d_open = sioopen, 395 .d_close = sioclose, 396 .d_read = sioread, 397 .d_write = siowrite, 398 .d_ioctl = sioioctl, 399 .d_name = sio_driver_name, 400 .d_flags = D_TTY | D_NEEDGIANT, 401}; 402 403static d_open_t siocopen; 404static d_close_t siocclose; 405static d_read_t siocrdwr; 406static d_ioctl_t siocioctl; 407 408static struct cdevsw sioc_cdevsw = { 409 .d_version = D_VERSION, 410 .d_open = siocopen, 411 .d_close = siocclose, 412 .d_read = siocrdwr, 413 .d_write = siocrdwr, 414 .d_ioctl = siocioctl, 415 .d_name = sio_driver_name, 416 .d_flags = D_TTY | D_NEEDGIANT, 417}; 418 419int comconsole = -1; 420static volatile speed_t comdefaultrate = CONSPEED; 421static u_long comdefaultrclk = DEFAULT_RCLK; 422SYSCTL_ULONG(_machdep, OID_AUTO, conrclk, CTLFLAG_RW, &comdefaultrclk, 0, ""); 423static speed_t gdbdefaultrate = GDBSPEED; 424SYSCTL_UINT(_machdep, OID_AUTO, gdbspeed, CTLFLAG_RW, 425 &gdbdefaultrate, GDBSPEED, ""); 426static u_int com_events; /* input chars + weighted output completions */ 427static Port_t siocniobase; 428static int siocnunit = -1; 429static void *sio_slow_ih; 430static void *sio_fast_ih; 431static int sio_timeout; 432static int sio_timeouts_until_log; 433static struct callout_handle sio_timeout_handle 434 = CALLOUT_HANDLE_INITIALIZER(&sio_timeout_handle); 435static int sio_numunits; 436 437#ifdef PC98 438struct siodev { 439 short if_type; 440 short irq; 441 Port_t cmd, sts, ctrl, mod; 442}; 443static int sysclock; 444 445#define COM_INT_DISABLE {int previpri; previpri=spltty(); 446#define COM_INT_ENABLE splx(previpri);} 447#define IEN_TxFLAG IEN_Tx 448 449#define COM_CARRIER_DETECT_EMULATE 0 450#define PC98_CHECK_MODEM_INTERVAL (hz/10) 451#define DCD_OFF_TOLERANCE 2 452#define DCD_ON_RECOGNITION 2 453#define IS_8251(if_type) (!(if_type & 0x10)) 454#define COM1_EXT_CLOCK 0x40000 455 456static void commint(struct cdev *dev); 457static void com_tiocm_bis(struct com_s *com, int msr); 458static void com_tiocm_bic(struct com_s *com, int msr); 459static int com_tiocm_get(struct com_s *com); 460static int com_tiocm_get_delta(struct com_s *com); 461static void pc98_msrint_start(struct cdev *dev); 462static void com_cflag_and_speed_set(struct com_s *com, int cflag, int speed); 463static int pc98_ttspeedtab(struct com_s *com, int speed, u_int *divisor); 464static int pc98_get_modem_status(struct com_s *com); 465static timeout_t pc98_check_msr; 466static void pc98_set_baud_rate(struct com_s *com, u_int count); 467static void pc98_i8251_reset(struct com_s *com, int mode, int command); 468static void pc98_disable_i8251_interrupt(struct com_s *com, int mod); 469static void pc98_enable_i8251_interrupt(struct com_s *com, int mod); 470static int pc98_check_i8251_interrupt(struct com_s *com); 471static int pc98_i8251_get_cmd(struct com_s *com); 472static int pc98_i8251_get_mod(struct com_s *com); 473static void pc98_i8251_set_cmd(struct com_s *com, int x); 474static void pc98_i8251_or_cmd(struct com_s *com, int x); 475static void pc98_i8251_clear_cmd(struct com_s *com, int x); 476static void pc98_i8251_clear_or_cmd(struct com_s *com, int clr, int x); 477static int pc98_check_if_type(device_t dev, struct siodev *iod); 478static int pc98_check_8251vfast(void); 479static int pc98_check_8251fifo(void); 480static void pc98_check_sysclock(void); 481static void pc98_set_ioport(struct com_s *com); 482 483#define com_int_Tx_disable(com) \ 484 pc98_disable_i8251_interrupt(com,IEN_Tx|IEN_TxEMP) 485#define com_int_Tx_enable(com) \ 486 pc98_enable_i8251_interrupt(com,IEN_TxFLAG) 487#define com_int_Rx_disable(com) \ 488 pc98_disable_i8251_interrupt(com,IEN_Rx) 489#define com_int_Rx_enable(com) \ 490 pc98_enable_i8251_interrupt(com,IEN_Rx) 491#define com_int_TxRx_disable(com) \ 492 pc98_disable_i8251_interrupt(com,IEN_Tx|IEN_TxEMP|IEN_Rx) 493#define com_int_TxRx_enable(com) \ 494 pc98_enable_i8251_interrupt(com,IEN_TxFLAG|IEN_Rx) 495#define com_send_break_on(com) \ 496 (IS_8251((com)->pc98_if_type) ? \ 497 pc98_i8251_or_cmd((com), CMD8251_SBRK) : \ 498 sio_setreg((com), com_cfcr, (com)->cfcr_image |= CFCR_SBREAK)) 499#define com_send_break_off(com) \ 500 (IS_8251((com)->pc98_if_type) ? \ 501 pc98_i8251_clear_cmd((com), CMD8251_SBRK) : \ 502 sio_setreg((com), com_cfcr, (com)->cfcr_image &= ~CFCR_SBREAK)) 503 504static struct speedtab pc98speedtab[] = { /* internal RS232C interface */ 505 { 0, 0, }, 506 { 50, 50, }, 507 { 75, 75, }, 508 { 150, 150, }, 509 { 200, 200, }, 510 { 300, 300, }, 511 { 600, 600, }, 512 { 1200, 1200, }, 513 { 2400, 2400, }, 514 { 4800, 4800, }, 515 { 9600, 9600, }, 516 { 19200, 19200, }, 517 { 38400, 38400, }, 518 { 51200, 51200, }, 519 { 76800, 76800, }, 520 { 20800, 20800, }, 521 { 31200, 31200, }, 522 { 41600, 41600, }, 523 { 62400, 62400, }, 524 { -1, -1 } 525}; 526static struct speedtab pc98fast_speedtab[] = { 527 { 9600, 0x80 | (DEFAULT_RCLK / (16 * (9600))), }, 528 { 19200, 0x80 | (DEFAULT_RCLK / (16 * (19200))), }, 529 { 38400, 0x80 | (DEFAULT_RCLK / (16 * (38400))), }, 530 { 57600, 0x80 | (DEFAULT_RCLK / (16 * (57600))), }, 531 { 115200, 0x80 | (DEFAULT_RCLK / (16 * (115200))), }, 532 { -1, -1 } 533}; 534static struct speedtab comspeedtab_pio9032b[] = { 535 { 300, 6, }, 536 { 600, 5, }, 537 { 1200, 4, }, 538 { 2400, 3, }, 539 { 4800, 2, }, 540 { 9600, 1, }, 541 { 19200, 0, }, 542 { 38400, 7, }, 543 { -1, -1 } 544}; 545static struct speedtab comspeedtab_b98_01[] = { 546 { 75, 11, }, 547 { 150, 10, }, 548 { 300, 9, }, 549 { 600, 8, }, 550 { 1200, 7, }, 551 { 2400, 6, }, 552 { 4800, 5, }, 553 { 9600, 4, }, 554 { 19200, 3, }, 555 { 38400, 2, }, 556 { 76800, 1, }, 557 { 153600, 0, }, 558 { -1, -1 } 559}; 560static struct speedtab comspeedtab_ind[] = { 561 { 300, 1536, }, 562 { 600, 768, }, 563 { 1200, 384, }, 564 { 2400, 192, }, 565 { 4800, 96, }, 566 { 9600, 48, }, 567 { 19200, 24, }, 568 { 38400, 12, }, 569 { 57600, 8, }, 570 { 115200, 4, }, 571 { 153600, 3, }, 572 { 230400, 2, }, 573 { 460800, 1, }, 574 { -1, -1 } 575}; 576 577struct { 578 char *name; 579 short port_table[7]; 580 short irr_mask; 581 struct speedtab *speedtab; 582 short check_irq; 583} if_8251_type[] = { 584 /* COM_IF_INTERNAL */ 585 { " (internal)", {0x30, 0x32, 0x32, 0x33, 0x35, -1, -1}, 586 -1, pc98speedtab, 1 }, 587 /* COM_IF_PC9861K_1 */ 588 { " (PC9861K)", {0xb1, 0xb3, 0xb3, 0xb0, 0xb0, -1, -1}, 589 3, NULL, 1 }, 590 /* COM_IF_PC9861K_2 */ 591 { " (PC9861K)", {0xb9, 0xbb, 0xbb, 0xb2, 0xb2, -1, -1}, 592 3, NULL, 1 }, 593 /* COM_IF_IND_SS_1 */ 594 { " (IND-SS)", {0xb1, 0xb3, 0xb3, 0xb0, 0xb0, 0xb3, -1}, 595 3, comspeedtab_ind, 1 }, 596 /* COM_IF_IND_SS_2 */ 597 { " (IND-SS)", {0xb9, 0xbb, 0xbb, 0xb2, 0xb2, 0xbb, -1}, 598 3, comspeedtab_ind, 1 }, 599 /* COM_IF_PIO9032B_1 */ 600 { " (PIO9032B)", {0xb1, 0xb3, 0xb3, 0xb0, 0xb0, 0xb8, -1}, 601 7, comspeedtab_pio9032b, 1 }, 602 /* COM_IF_PIO9032B_2 */ 603 { " (PIO9032B)", {0xb9, 0xbb, 0xbb, 0xb2, 0xb2, 0xba, -1}, 604 7, comspeedtab_pio9032b, 1 }, 605 /* COM_IF_B98_01_1 */ 606 { " (B98-01)", {0xb1, 0xb3, 0xb3, 0xb0, 0xb0, 0xd1, 0xd3}, 607 7, comspeedtab_b98_01, 0 }, 608 /* COM_IF_B98_01_2 */ 609 { " (B98-01)", {0xb9, 0xbb, 0xbb, 0xb2, 0xb2, 0xd5, 0xd7}, 610 7, comspeedtab_b98_01, 0 }, 611}; 612#define PC98SIO_data_port(type) (if_8251_type[type].port_table[0]) 613#define PC98SIO_cmd_port(type) (if_8251_type[type].port_table[1]) 614#define PC98SIO_sts_port(type) (if_8251_type[type].port_table[2]) 615#define PC98SIO_in_modem_port(type) (if_8251_type[type].port_table[3]) 616#define PC98SIO_intr_ctrl_port(type) (if_8251_type[type].port_table[4]) 617#define PC98SIO_baud_rate_port(type) (if_8251_type[type].port_table[5]) 618#define PC98SIO_func_port(type) (if_8251_type[type].port_table[6]) 619 620#define I8251F_data 0x130 621#define I8251F_lsr 0x132 622#define I8251F_msr 0x134 623#define I8251F_iir 0x136 624#define I8251F_fcr 0x138 625#define I8251F_div 0x13a 626 627 628static bus_addr_t port_table_0[] = 629 {0x000, 0x001, 0x002, 0x003, 0x004, 0x005, 0x006, 0x007}; 630static bus_addr_t port_table_1[] = 631 {0x000, 0x002, 0x004, 0x006, 0x008, 0x00a, 0x00c, 0x00e}; 632static bus_addr_t port_table_8[] = 633 {0x000, 0x100, 0x200, 0x300, 0x400, 0x500, 0x600, 0x700}; 634static bus_addr_t port_table_rsa[] = { 635 0x008, 0x009, 0x00a, 0x00b, 0x00c, 0x00d, 0x00e, 0x00f, 636 0x000, 0x001, 0x002, 0x003, 0x004, 0x005, 0x006, 0x007 637}; 638 639struct { 640 char *name; 641 short irr_read; 642 short irr_write; 643 bus_addr_t *iat; 644 bus_size_t iatsz; 645 u_long rclk; 646} if_16550a_type[] = { 647 /* COM_IF_RSA98 */ 648 {" (RSA-98)", -1, -1, port_table_0, IO_COMSIZE, DEFAULT_RCLK}, 649 /* COM_IF_NS16550 */ 650 {"", -1, -1, port_table_0, IO_COMSIZE, DEFAULT_RCLK}, 651 /* COM_IF_SECOND_CCU */ 652 {"", -1, -1, port_table_0, IO_COMSIZE, DEFAULT_RCLK}, 653 /* COM_IF_MC16550II */ 654 {" (MC16550II)", -1, 0x1000, port_table_8, IO_COMSIZE, 655 DEFAULT_RCLK * 4}, 656 /* COM_IF_MCRS98 */ 657 {" (MC-RS98)", -1, 0x1000, port_table_8, IO_COMSIZE, DEFAULT_RCLK * 4}, 658 /* COM_IF_RSB3000 */ 659 {" (RSB-3000)", 0xbf, -1, port_table_1, IO_COMSIZE, DEFAULT_RCLK * 10}, 660 /* COM_IF_RSB384 */ 661 {" (RSB-384)", 0xbf, -1, port_table_1, IO_COMSIZE, DEFAULT_RCLK * 10}, 662 /* COM_IF_MODEM_CARD */ 663 {"", -1, -1, port_table_0, IO_COMSIZE, DEFAULT_RCLK}, 664 /* COM_IF_RSA98III */ 665 {" (RSA-98III)", -1, -1, port_table_rsa, 16, DEFAULT_RCLK * 8}, 666 /* COM_IF_ESP98 */ 667 {" (ESP98)", -1, -1, port_table_1, IO_COMSIZE, DEFAULT_RCLK * 4}, 668}; 669#endif /* PC98 */ 670 671#ifdef GDB 672static Port_t siogdbiobase = 0; 673#endif 674 675#ifdef COM_ESP 676#ifdef PC98 677 678/* XXX configure this properly. */ 679/* XXX quite broken for new-bus. */ 680static Port_t likely_com_ports[] = { 0, 0xb0, 0xb1, 0 }; 681static Port_t likely_esp_ports[] = { 0xc0d0, 0 }; 682 683#define ESP98_CMD1 (ESP_CMD1 * 0x100) 684#define ESP98_CMD2 (ESP_CMD2 * 0x100) 685#define ESP98_STATUS1 (ESP_STATUS1 * 0x100) 686#define ESP98_STATUS2 (ESP_STATUS2 * 0x100) 687 688#else /* PC98 */ 689 690/* XXX configure this properly. */ 691static Port_t likely_com_ports[] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8, }; 692static Port_t likely_esp_ports[] = { 0x140, 0x180, 0x280, 0 }; 693 694#endif /* PC98 */ 695#endif 696 697/* 698 * handle sysctl read/write requests for console speed 699 * 700 * In addition to setting comdefaultrate for I/O through /dev/console, 701 * also set the initial and lock values for the /dev/ttyXX device 702 * if there is one associated with the console. Finally, if the /dev/tty 703 * device has already been open, change the speed on the open running port 704 * itself. 705 */ 706 707static int 708sysctl_machdep_comdefaultrate(SYSCTL_HANDLER_ARGS) 709{ 710 int error, s; 711 speed_t newspeed; 712 struct com_s *com; 713 struct tty *tp; 714 715 newspeed = comdefaultrate; 716 717 error = sysctl_handle_opaque(oidp, &newspeed, sizeof newspeed, req); 718 if (error || !req->newptr) 719 return (error); 720 721 comdefaultrate = newspeed; 722 723 if (comconsole < 0) /* serial console not selected? */ 724 return (0); 725 726 com = com_addr(comconsole); 727 if (com == NULL) 728 return (ENXIO); 729 730 tp = com->tp; 731 if (tp == NULL) 732 return (ENXIO); 733 734 /* 735 * set the initial and lock rates for /dev/ttydXX and /dev/cuaXX 736 * (note, the lock rates really are boolean -- if non-zero, disallow 737 * speed changes) 738 */ 739 tp->t_init_in.c_ispeed = tp->t_init_in.c_ospeed = 740 tp->t_lock_in.c_ispeed = tp->t_lock_in.c_ospeed = 741 tp->t_init_out.c_ispeed = tp->t_init_out.c_ospeed = 742 tp->t_lock_out.c_ispeed = tp->t_lock_out.c_ospeed = comdefaultrate; 743 744 /* 745 * if we're open, change the running rate too 746 */ 747 if (tp->t_state & TS_ISOPEN) { 748 tp->t_termios.c_ispeed = 749 tp->t_termios.c_ospeed = comdefaultrate; 750 s = spltty(); 751 error = comparam(tp, &tp->t_termios); 752 splx(s); 753 } 754 return error; 755} 756 757SYSCTL_PROC(_machdep, OID_AUTO, conspeed, CTLTYPE_INT | CTLFLAG_RW, 758 0, 0, sysctl_machdep_comdefaultrate, "I", ""); 759 760/* 761 * Unload the driver and clear the table. 762 * XXX this is mostly wrong. 763 * XXX TODO: 764 * This is usually called when the card is ejected, but 765 * can be caused by a kldunload of a controller driver. 766 * The idea is to reset the driver's view of the device 767 * and ensure that any driver entry points such as 768 * read and write do not hang. 769 */ 770int 771siodetach(dev) 772 device_t dev; 773{ 774 struct com_s *com; 775 int i; 776 777 com = (struct com_s *) device_get_softc(dev); 778 if (com == NULL) { 779 device_printf(dev, "NULL com in siounload\n"); 780 return (0); 781 } 782 com->gone = TRUE; 783 if (com->tp) 784 ttygone(com->tp); 785 for (i = 0 ; i < 6; i++) 786 destroy_dev(com->devs[i]); 787 if (com->irqres) { 788 bus_teardown_intr(dev, com->irqres, com->cookie); 789 bus_release_resource(dev, SYS_RES_IRQ, 0, com->irqres); 790 } 791 if (com->ioportres) 792 bus_release_resource(dev, SYS_RES_IOPORT, com->ioportrid, 793 com->ioportres); 794 if (com->tp && (com->tp->t_state & TS_ISOPEN)) { 795 device_printf(dev, "still open, forcing close\n"); 796 ttyld_close(com->tp, 0); 797 tty_close(com->tp); 798 } else { 799 if (com->ibuf != NULL) 800 free(com->ibuf, M_DEVBUF); 801#ifdef PC98 802 if (com->obuf1 != NULL) 803 free(com->obuf1, M_DEVBUF); 804#endif 805 device_set_softc(dev, NULL); 806 free(com, M_DEVBUF); 807 } 808 return (0); 809} 810 811int 812sioprobe(dev, xrid, rclk, noprobe) 813 device_t dev; 814 int xrid; 815 u_long rclk; 816 int noprobe; 817{ 818#if 0 819 static bool_t already_init; 820 device_t xdev; 821#endif 822 struct com_s *com; 823 u_int divisor; 824 bool_t failures[10]; 825 int fn; 826 device_t idev; 827 Port_t iobase; 828 intrmask_t irqmap[4]; 829 intrmask_t irqs; 830 u_char mcr_image; 831 int result; 832 u_long xirq; 833 u_int flags = device_get_flags(dev); 834 int rid; 835 struct resource *port; 836#ifdef PC98 837 int tmp; 838 struct siodev iod; 839#endif 840 841#ifdef PC98 842 iod.if_type = GET_IFTYPE(flags); 843 if ((iod.if_type < 0 || iod.if_type > COM_IF_END1) && 844 (iod.if_type < 0x10 || iod.if_type > COM_IF_END2)) 845 return ENXIO; 846#endif 847 848 rid = xrid; 849#ifdef PC98 850 if (IS_8251(iod.if_type)) { 851 port = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid, 852 RF_ACTIVE); 853 } else if (iod.if_type == COM_IF_MODEM_CARD || 854 iod.if_type == COM_IF_RSA98III || 855 isa_get_vendorid(dev)) { 856 port = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 0, ~0, 857 if_16550a_type[iod.if_type & 0x0f].iatsz, RF_ACTIVE); 858 } else { 859 port = isa_alloc_resourcev(dev, SYS_RES_IOPORT, &rid, 860 if_16550a_type[iod.if_type & 0x0f].iat, 861 if_16550a_type[iod.if_type & 0x0f].iatsz, RF_ACTIVE); 862 } 863#else 864 port = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 865 0, ~0, IO_COMSIZE, RF_ACTIVE); 866#endif 867 if (!port) 868 return (ENXIO); 869#ifdef PC98 870 if (!IS_8251(iod.if_type)) { 871 if (isa_load_resourcev(port, 872 if_16550a_type[iod.if_type & 0x0f].iat, 873 if_16550a_type[iod.if_type & 0x0f].iatsz) != 0) { 874 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 875 return ENXIO; 876 } 877 } 878#endif 879 880 com = malloc(sizeof(*com), M_DEVBUF, M_NOWAIT | M_ZERO); 881 if (com == NULL) { 882 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 883 return (ENOMEM); 884 } 885 device_set_softc(dev, com); 886 com->bst = rman_get_bustag(port); 887 com->bsh = rman_get_bushandle(port); 888#ifdef PC98 889 if (!IS_8251(iod.if_type) && rclk == 0) 890 rclk = if_16550a_type[iod.if_type & 0x0f].rclk; 891#else 892 if (rclk == 0) 893 rclk = DEFAULT_RCLK; 894#endif 895 com->rclk = rclk; 896 897 while (sio_inited != 2) 898 if (atomic_cmpset_int(&sio_inited, 0, 1)) { 899 mtx_init(&sio_lock, sio_driver_name, NULL, 900 (comconsole != -1) ? 901 MTX_SPIN | MTX_QUIET : MTX_SPIN); 902 atomic_store_rel_int(&sio_inited, 2); 903 } 904 905#if 0 906 /* 907 * XXX this is broken - when we are first called, there are no 908 * previously configured IO ports. We could hard code 909 * 0x3f8, 0x2f8, 0x3e8, 0x2e8 etc but that's probably worse. 910 * This code has been doing nothing since the conversion since 911 * "count" is zero the first time around. 912 */ 913 if (!already_init) { 914 /* 915 * Turn off MCR_IENABLE for all likely serial ports. An unused 916 * port with its MCR_IENABLE gate open will inhibit interrupts 917 * from any used port that shares the interrupt vector. 918 * XXX the gate enable is elsewhere for some multiports. 919 */ 920 device_t *devs; 921 int count, i, xioport; 922#ifdef PC98 923 int xiftype; 924#endif 925 926 devclass_get_devices(sio_devclass, &devs, &count); 927#ifdef PC98 928 for (i = 0; i < count; i++) { 929 xdev = devs[i]; 930 xioport = bus_get_resource_start(xdev, SYS_RES_IOPORT, 0); 931 xiftype = GET_IFTYPE(device_get_flags(xdev)); 932 if (device_is_enabled(xdev) && xioport > 0) { 933 if (IS_8251(xiftype)) 934 outb((xioport & 0xff00) | PC98SIO_cmd_port(xiftype & 0x0f), 0xf2); 935 else 936 outb(xioport + if_16550a_type[xiftype & 0x0f].iat[com_mcr], 0); 937 } 938 } 939#else 940 for (i = 0; i < count; i++) { 941 xdev = devs[i]; 942 if (device_is_enabled(xdev) && 943 bus_get_resource(xdev, SYS_RES_IOPORT, 0, &xioport, 944 NULL) == 0) 945 outb(xioport + com_mcr, 0); 946 } 947#endif 948 free(devs, M_TEMP); 949 already_init = TRUE; 950 } 951#endif 952 953 if (COM_LLCONSOLE(flags)) { 954 printf("sio%d: reserved for low-level i/o\n", 955 device_get_unit(dev)); 956 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 957 device_set_softc(dev, NULL); 958 free(com, M_DEVBUF); 959 return (ENXIO); 960 } 961 962#ifdef PC98 963 DELAY(10); 964 965 /* 966 * If the port is i8251 UART (internal, B98_01) 967 */ 968 if (pc98_check_if_type(dev, &iod) == -1) { 969 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 970 device_set_softc(dev, NULL); 971 free(com, M_DEVBUF); 972 return (ENXIO); 973 } 974 if (iod.irq > 0) 975 bus_set_resource(dev, SYS_RES_IRQ, 0, iod.irq, 1); 976 if (IS_8251(iod.if_type)) { 977 outb(iod.cmd, 0); 978 DELAY(10); 979 outb(iod.cmd, 0); 980 DELAY(10); 981 outb(iod.cmd, 0); 982 DELAY(10); 983 outb(iod.cmd, CMD8251_RESET); 984 DELAY(1000); /* for a while...*/ 985 outb(iod.cmd, 0xf2); /* MODE (dummy) */ 986 DELAY(10); 987 outb(iod.cmd, 0x01); /* CMD (dummy) */ 988 DELAY(1000); /* for a while...*/ 989 if (( inb(iod.sts) & STS8251_TxEMP ) == 0 ) { 990 result = (ENXIO); 991 } 992 if (if_8251_type[iod.if_type & 0x0f].check_irq) { 993 COM_INT_DISABLE 994 tmp = ( inb( iod.ctrl ) & ~(IEN_Rx|IEN_TxEMP|IEN_Tx)); 995 outb( iod.ctrl, tmp|IEN_TxEMP ); 996 DELAY(10); 997 result = isa_irq_pending() ? 0 : ENXIO; 998 outb( iod.ctrl, tmp ); 999 COM_INT_ENABLE 1000 } else { 1001 /* 1002 * B98_01 doesn't activate TxEMP interrupt line 1003 * when being reset, so we can't check irq pending. 1004 */ 1005 result = 0; 1006 } 1007 if (epson_machine_id==0x20) { /* XXX */ 1008 result = 0; 1009 } 1010 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 1011 if (result) { 1012 device_set_softc(dev, NULL); 1013 free(com, M_DEVBUF); 1014 } 1015 return result; 1016 } 1017#endif /* PC98 */ 1018 /* 1019 * If the device is on a multiport card and has an AST/4 1020 * compatible interrupt control register, initialize this 1021 * register and prepare to leave MCR_IENABLE clear in the mcr. 1022 * Otherwise, prepare to set MCR_IENABLE in the mcr. 1023 * Point idev to the device struct giving the correct id_irq. 1024 * This is the struct for the master device if there is one. 1025 */ 1026 idev = dev; 1027 mcr_image = MCR_IENABLE; 1028#ifdef COM_MULTIPORT 1029 if (COM_ISMULTIPORT(flags)) { 1030#ifndef PC98 1031 Port_t xiobase; 1032 u_long io; 1033#endif 1034 1035 idev = devclass_get_device(sio_devclass, COM_MPMASTER(flags)); 1036 if (idev == NULL) { 1037 printf("sio%d: master device %d not configured\n", 1038 device_get_unit(dev), COM_MPMASTER(flags)); 1039 idev = dev; 1040 } 1041#ifndef PC98 1042 if (!COM_NOTAST4(flags)) { 1043 if (bus_get_resource(idev, SYS_RES_IOPORT, 0, &io, 1044 NULL) == 0) { 1045 xiobase = io; 1046 if (bus_get_resource(idev, SYS_RES_IRQ, 0, 1047 NULL, NULL) == 0) 1048 outb(xiobase + com_scr, 0x80); 1049 else 1050 outb(xiobase + com_scr, 0); 1051 } 1052 mcr_image = 0; 1053 } 1054#endif 1055 } 1056#endif /* COM_MULTIPORT */ 1057 if (bus_get_resource(idev, SYS_RES_IRQ, 0, NULL, NULL) != 0) 1058 mcr_image = 0; 1059 1060 bzero(failures, sizeof failures); 1061 iobase = rman_get_start(port); 1062 1063#ifdef PC98 1064 if (iod.if_type == COM_IF_RSA98III) { 1065 mcr_image = 0; 1066 1067 outb(iobase + rsa_msr, 0x04); 1068 outb(iobase + rsa_frr, 0x00); 1069 if ((inb(iobase + rsa_srr) & 0x36) != 0x36) { 1070 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 1071 device_set_softc(dev, NULL); 1072 free(com, M_DEVBUF); 1073 return (ENXIO); 1074 } 1075 outb(iobase + rsa_ier, 0x00); 1076 outb(iobase + rsa_frr, 0x00); 1077 outb(iobase + rsa_tivsr, 0x00); 1078 outb(iobase + rsa_tcr, 0x00); 1079 } 1080 1081 tmp = if_16550a_type[iod.if_type & 0x0f].irr_write; 1082 if (tmp != -1) { 1083 /* MC16550II */ 1084 int irqout; 1085 switch (isa_get_irq(idev)) { 1086 case 3: irqout = 4; break; 1087 case 5: irqout = 5; break; 1088 case 6: irqout = 6; break; 1089 case 12: irqout = 7; break; 1090 default: 1091 printf("sio%d: irq configuration error\n", 1092 device_get_unit(dev)); 1093 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 1094 device_set_softc(dev, NULL); 1095 free(com, M_DEVBUF); 1096 return (ENXIO); 1097 } 1098 outb((iobase & 0x00ff) | tmp, irqout); 1099 } 1100#endif 1101 1102 /* 1103 * We don't want to get actual interrupts, just masked ones. 1104 * Interrupts from this line should already be masked in the ICU, 1105 * but mask them in the processor as well in case there are some 1106 * (misconfigured) shared interrupts. 1107 */ 1108 mtx_lock_spin(&sio_lock); 1109/* EXTRA DELAY? */ 1110 1111 /* 1112 * Initialize the speed and the word size and wait long enough to 1113 * drain the maximum of 16 bytes of junk in device output queues. 1114 * The speed is undefined after a master reset and must be set 1115 * before relying on anything related to output. There may be 1116 * junk after a (very fast) soft reboot and (apparently) after 1117 * master reset. 1118 * XXX what about the UART bug avoided by waiting in comparam()? 1119 * We don't want to to wait long enough to drain at 2 bps. 1120 */ 1121 if (iobase == siocniobase) 1122 DELAY((16 + 1) * 1000000 / (comdefaultrate / 10)); 1123 else { 1124 sio_setreg(com, com_cfcr, CFCR_DLAB | CFCR_8BITS); 1125 divisor = siodivisor(rclk, SIO_TEST_SPEED); 1126 sio_setreg(com, com_dlbl, divisor & 0xff); 1127 sio_setreg(com, com_dlbh, divisor >> 8); 1128 sio_setreg(com, com_cfcr, CFCR_8BITS); 1129 DELAY((16 + 1) * 1000000 / (SIO_TEST_SPEED / 10)); 1130 } 1131 1132 /* 1133 * Enable the interrupt gate and disable device interupts. This 1134 * should leave the device driving the interrupt line low and 1135 * guarantee an edge trigger if an interrupt can be generated. 1136 */ 1137/* EXTRA DELAY? */ 1138 sio_setreg(com, com_mcr, mcr_image); 1139 sio_setreg(com, com_ier, 0); 1140 DELAY(1000); /* XXX */ 1141 irqmap[0] = isa_irq_pending(); 1142 1143 /* 1144 * Attempt to set loopback mode so that we can send a null byte 1145 * without annoying any external device. 1146 */ 1147/* EXTRA DELAY? */ 1148 sio_setreg(com, com_mcr, mcr_image | MCR_LOOPBACK); 1149 1150 /* 1151 * Attempt to generate an output interrupt. On 8250's, setting 1152 * IER_ETXRDY generates an interrupt independent of the current 1153 * setting and independent of whether the THR is empty. On 16450's, 1154 * setting IER_ETXRDY generates an interrupt independent of the 1155 * current setting. On 16550A's, setting IER_ETXRDY only 1156 * generates an interrupt when IER_ETXRDY is not already set. 1157 */ 1158 sio_setreg(com, com_ier, IER_ETXRDY); 1159#ifdef PC98 1160 if (iod.if_type == COM_IF_RSA98III) 1161 outb(iobase + rsa_ier, 0x04); 1162#endif 1163 1164 /* 1165 * On some 16x50 incompatibles, setting IER_ETXRDY doesn't generate 1166 * an interrupt. They'd better generate one for actually doing 1167 * output. Loopback may be broken on the same incompatibles but 1168 * it's unlikely to do more than allow the null byte out. 1169 */ 1170 sio_setreg(com, com_data, 0); 1171 if (iobase == siocniobase) 1172 DELAY((1 + 2) * 1000000 / (comdefaultrate / 10)); 1173 else 1174 DELAY((1 + 2) * 1000000 / (SIO_TEST_SPEED / 10)); 1175 1176 /* 1177 * Turn off loopback mode so that the interrupt gate works again 1178 * (MCR_IENABLE was hidden). This should leave the device driving 1179 * an interrupt line high. It doesn't matter if the interrupt 1180 * line oscillates while we are not looking at it, since interrupts 1181 * are disabled. 1182 */ 1183/* EXTRA DELAY? */ 1184 sio_setreg(com, com_mcr, mcr_image); 1185 1186 /* 1187 * It seems my Xircom CBEM56G Cardbus modem wants to be reset 1188 * to 8 bits *again*, or else probe test 0 will fail. 1189 * gwk@sgi.com, 4/19/2001 1190 */ 1191 sio_setreg(com, com_cfcr, CFCR_8BITS); 1192 1193 /* 1194 * Some PCMCIA cards (Palido 321s, DC-1S, ...) have the "TXRDY bug", 1195 * so we probe for a buggy IIR_TXRDY implementation even in the 1196 * noprobe case. We don't probe for it in the !noprobe case because 1197 * noprobe is always set for PCMCIA cards and the problem is not 1198 * known to affect any other cards. 1199 */ 1200 if (noprobe) { 1201 /* Read IIR a few times. */ 1202 for (fn = 0; fn < 2; fn ++) { 1203 DELAY(10000); 1204 failures[6] = sio_getreg(com, com_iir); 1205 } 1206 1207 /* IIR_TXRDY should be clear. Is it? */ 1208 result = 0; 1209 if (failures[6] & IIR_TXRDY) { 1210 /* 1211 * No. We seem to have the bug. Does our fix for 1212 * it work? 1213 */ 1214 sio_setreg(com, com_ier, 0); 1215 if (sio_getreg(com, com_iir) & IIR_NOPEND) { 1216 /* Yes. We discovered the TXRDY bug! */ 1217 SET_FLAG(dev, COM_C_IIR_TXRDYBUG); 1218 } else { 1219 /* No. Just fail. XXX */ 1220 result = ENXIO; 1221 sio_setreg(com, com_mcr, 0); 1222 } 1223 } else { 1224 /* Yes. No bug. */ 1225 CLR_FLAG(dev, COM_C_IIR_TXRDYBUG); 1226 } 1227 sio_setreg(com, com_ier, 0); 1228 sio_setreg(com, com_cfcr, CFCR_8BITS); 1229 mtx_unlock_spin(&sio_lock); 1230 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 1231 if (iobase == siocniobase) 1232 result = 0; 1233 if (result != 0) { 1234 device_set_softc(dev, NULL); 1235 free(com, M_DEVBUF); 1236 } 1237 return (result); 1238 } 1239 1240 /* 1241 * Check that 1242 * o the CFCR, IER and MCR in UART hold the values written to them 1243 * (the values happen to be all distinct - this is good for 1244 * avoiding false positive tests from bus echoes). 1245 * o an output interrupt is generated and its vector is correct. 1246 * o the interrupt goes away when the IIR in the UART is read. 1247 */ 1248/* EXTRA DELAY? */ 1249 failures[0] = sio_getreg(com, com_cfcr) - CFCR_8BITS; 1250 failures[1] = sio_getreg(com, com_ier) - IER_ETXRDY; 1251 failures[2] = sio_getreg(com, com_mcr) - mcr_image; 1252 DELAY(10000); /* Some internal modems need this time */ 1253 irqmap[1] = isa_irq_pending(); 1254 failures[4] = (sio_getreg(com, com_iir) & IIR_IMASK) - IIR_TXRDY; 1255#ifdef PC98 1256 if (iod.if_type == COM_IF_RSA98III) 1257 inb(iobase + rsa_srr); 1258#endif 1259 DELAY(1000); /* XXX */ 1260 irqmap[2] = isa_irq_pending(); 1261 failures[6] = (sio_getreg(com, com_iir) & IIR_IMASK) - IIR_NOPEND; 1262#ifdef PC98 1263 if (iod.if_type == COM_IF_RSA98III) 1264 inb(iobase + rsa_srr); 1265#endif 1266 1267 /* 1268 * Turn off all device interrupts and check that they go off properly. 1269 * Leave MCR_IENABLE alone. For ports without a master port, it gates 1270 * the OUT2 output of the UART to 1271 * the ICU input. Closing the gate would give a floating ICU input 1272 * (unless there is another device driving it) and spurious interrupts. 1273 * (On the system that this was first tested on, the input floats high 1274 * and gives a (masked) interrupt as soon as the gate is closed.) 1275 */ 1276 sio_setreg(com, com_ier, 0); 1277 sio_setreg(com, com_cfcr, CFCR_8BITS); /* dummy to avoid bus echo */ 1278 failures[7] = sio_getreg(com, com_ier); 1279#ifdef PC98 1280 if (iod.if_type == COM_IF_RSA98III) 1281 outb(iobase + rsa_ier, 0x00); 1282#endif 1283 DELAY(1000); /* XXX */ 1284 irqmap[3] = isa_irq_pending(); 1285 failures[9] = (sio_getreg(com, com_iir) & IIR_IMASK) - IIR_NOPEND; 1286#ifdef PC98 1287 if (iod.if_type == COM_IF_RSA98III) { 1288 inb(iobase + rsa_srr); 1289 outb(iobase + rsa_frr, 0x00); 1290 } 1291#endif 1292 1293 mtx_unlock_spin(&sio_lock); 1294 1295 irqs = irqmap[1] & ~irqmap[0]; 1296 if (bus_get_resource(idev, SYS_RES_IRQ, 0, &xirq, NULL) == 0 && 1297 ((1 << xirq) & irqs) == 0) { 1298 printf( 1299 "sio%d: configured irq %ld not in bitmap of probed irqs %#x\n", 1300 device_get_unit(dev), xirq, irqs); 1301 printf( 1302 "sio%d: port may not be enabled\n", 1303 device_get_unit(dev)); 1304 } 1305 if (bootverbose) 1306 printf("sio%d: irq maps: %#x %#x %#x %#x\n", 1307 device_get_unit(dev), 1308 irqmap[0], irqmap[1], irqmap[2], irqmap[3]); 1309 1310 result = 0; 1311 for (fn = 0; fn < sizeof failures; ++fn) 1312 if (failures[fn]) { 1313 sio_setreg(com, com_mcr, 0); 1314 result = ENXIO; 1315 if (bootverbose) { 1316 printf("sio%d: probe failed test(s):", 1317 device_get_unit(dev)); 1318 for (fn = 0; fn < sizeof failures; ++fn) 1319 if (failures[fn]) 1320 printf(" %d", fn); 1321 printf("\n"); 1322 } 1323 break; 1324 } 1325 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 1326 if (iobase == siocniobase) 1327 result = 0; 1328 if (result != 0) { 1329 device_set_softc(dev, NULL); 1330 free(com, M_DEVBUF); 1331 } 1332 return (result); 1333} 1334 1335#ifdef COM_ESP 1336static int 1337espattach(com, esp_port) 1338 struct com_s *com; 1339 Port_t esp_port; 1340{ 1341 u_char dips; 1342 u_char val; 1343 1344 /* 1345 * Check the ESP-specific I/O port to see if we're an ESP 1346 * card. If not, return failure immediately. 1347 */ 1348 if ((inb(esp_port) & 0xf3) == 0) { 1349 printf(" port 0x%x is not an ESP board?\n", esp_port); 1350 return (0); 1351 } 1352 1353 /* 1354 * We've got something that claims to be a Hayes ESP card. 1355 * Let's hope so. 1356 */ 1357 1358 /* Get the dip-switch configuration */ 1359#ifdef PC98 1360 outb(esp_port + ESP98_CMD1, ESP_GETDIPS); 1361 dips = inb(esp_port + ESP98_STATUS1); 1362#else 1363 outb(esp_port + ESP_CMD1, ESP_GETDIPS); 1364 dips = inb(esp_port + ESP_STATUS1); 1365#endif 1366 1367 /* 1368 * Bits 0,1 of dips say which COM port we are. 1369 */ 1370#ifdef PC98 1371 if ((rman_get_start(com->ioportres) & 0xff) == 1372 likely_com_ports[dips & 0x03]) 1373#else 1374 if (rman_get_start(com->ioportres) == likely_com_ports[dips & 0x03]) 1375#endif 1376 printf(" : ESP"); 1377 else { 1378 printf(" esp_port has com %d\n", dips & 0x03); 1379 return (0); 1380 } 1381 1382 /* 1383 * Check for ESP version 2.0 or later: bits 4,5,6 = 010. 1384 */ 1385#ifdef PC98 1386 outb(esp_port + ESP98_CMD1, ESP_GETTEST); 1387 val = inb(esp_port + ESP98_STATUS1); /* clear reg 1 */ 1388 val = inb(esp_port + ESP98_STATUS2); 1389#else 1390 outb(esp_port + ESP_CMD1, ESP_GETTEST); 1391 val = inb(esp_port + ESP_STATUS1); /* clear reg 1 */ 1392 val = inb(esp_port + ESP_STATUS2); 1393#endif 1394 if ((val & 0x70) < 0x20) { 1395 printf("-old (%o)", val & 0x70); 1396 return (0); 1397 } 1398 1399 /* 1400 * Check for ability to emulate 16550: bit 7 == 1 1401 */ 1402 if ((dips & 0x80) == 0) { 1403 printf(" slave"); 1404 return (0); 1405 } 1406 1407 /* 1408 * Okay, we seem to be a Hayes ESP card. Whee. 1409 */ 1410 com->esp = TRUE; 1411 com->esp_port = esp_port; 1412 return (1); 1413} 1414#endif /* COM_ESP */ 1415 1416int 1417sioattach(dev, xrid, rclk) 1418 device_t dev; 1419 int xrid; 1420 u_long rclk; 1421{ 1422 struct com_s *com; 1423#ifdef COM_ESP 1424 Port_t *espp; 1425#endif 1426 Port_t iobase; 1427 int minorbase; 1428 int unit; 1429 u_int flags; 1430 int rid; 1431 struct resource *port; 1432 int ret; 1433 struct tty *tp; 1434#ifdef PC98 1435 u_char *obuf; 1436 u_long obufsize; 1437 int if_type = GET_IFTYPE(device_get_flags(dev)); 1438#endif 1439 1440 rid = xrid; 1441#ifdef PC98 1442 if (IS_8251(if_type)) { 1443 port = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid, 1444 RF_ACTIVE); 1445 } else if (if_type == COM_IF_MODEM_CARD || 1446 if_type == COM_IF_RSA98III || 1447 isa_get_vendorid(dev)) { 1448 port = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 0, ~0, 1449 if_16550a_type[if_type & 0x0f].iatsz, RF_ACTIVE); 1450 } else { 1451 port = isa_alloc_resourcev(dev, SYS_RES_IOPORT, &rid, 1452 if_16550a_type[if_type & 0x0f].iat, 1453 if_16550a_type[if_type & 0x0f].iatsz, RF_ACTIVE); 1454 } 1455#else 1456 port = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 1457 0, ~0, IO_COMSIZE, RF_ACTIVE); 1458#endif 1459 if (!port) 1460 return (ENXIO); 1461#ifdef PC98 1462 if (!IS_8251(if_type)) { 1463 if (isa_load_resourcev(port, 1464 if_16550a_type[if_type & 0x0f].iat, 1465 if_16550a_type[if_type & 0x0f].iatsz) != 0) { 1466 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 1467 return ENXIO; 1468 } 1469 } 1470#endif 1471 1472 iobase = rman_get_start(port); 1473 unit = device_get_unit(dev); 1474 com = device_get_softc(dev); 1475 flags = device_get_flags(dev); 1476 1477 if (unit >= sio_numunits) 1478 sio_numunits = unit + 1; 1479 1480#ifdef PC98 1481 obufsize = 256; 1482 if (if_type == COM_IF_RSA98III) 1483 obufsize = 2048; 1484 if ((obuf = malloc(obufsize * 2, M_DEVBUF, M_NOWAIT)) == NULL) { 1485 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 1486 return ENXIO; 1487 } 1488 bzero(obuf, obufsize * 2); 1489#endif 1490 1491 /* 1492 * sioprobe() has initialized the device registers as follows: 1493 * o cfcr = CFCR_8BITS. 1494 * It is most important that CFCR_DLAB is off, so that the 1495 * data port is not hidden when we enable interrupts. 1496 * o ier = 0. 1497 * Interrupts are only enabled when the line is open. 1498 * o mcr = MCR_IENABLE, or 0 if the port has AST/4 compatible 1499 * interrupt control register or the config specifies no irq. 1500 * Keeping MCR_DTR and MCR_RTS off might stop the external 1501 * device from sending before we are ready. 1502 */ 1503 bzero(com, sizeof *com); 1504 com->unit = unit; 1505 com->ioportres = port; 1506 com->ioportrid = rid; 1507 com->bst = rman_get_bustag(port); 1508 com->bsh = rman_get_bushandle(port); 1509 com->cfcr_image = CFCR_8BITS; 1510 com->loses_outints = COM_LOSESOUTINTS(flags) != 0; 1511 com->no_irq = bus_get_resource(dev, SYS_RES_IRQ, 0, NULL, NULL) != 0; 1512 com->tx_fifo_size = 1; 1513#ifdef PC98 1514 com->obufsize = obufsize; 1515 com->obuf1 = obuf; 1516 com->obuf2 = obuf + obufsize; 1517#endif 1518 com->obufs[0].l_head = com->obuf1; 1519 com->obufs[1].l_head = com->obuf2; 1520 1521#ifdef PC98 1522 com->pc98_if_type = if_type; 1523 1524 if (IS_8251(if_type)) { 1525 pc98_set_ioport(com); 1526 1527 if (if_type == COM_IF_INTERNAL && pc98_check_8251fifo()) { 1528 com->pc98_8251fifo = 1; 1529 com->pc98_8251fifo_enable = 0; 1530 } 1531 } else { 1532 bus_addr_t *iat = if_16550a_type[if_type & 0x0f].iat; 1533 1534 com->data_port = iobase + iat[com_data]; 1535 com->int_ctl_port = iobase + iat[com_ier]; 1536 com->int_id_port = iobase + iat[com_iir]; 1537 com->modem_ctl_port = iobase + iat[com_mcr]; 1538 com->mcr_image = inb(com->modem_ctl_port); 1539 com->line_status_port = iobase + iat[com_lsr]; 1540 com->modem_status_port = iobase + iat[com_msr]; 1541 } 1542#else /* not PC98 */ 1543 com->data_port = iobase + com_data; 1544 com->int_ctl_port = iobase + com_ier; 1545 com->int_id_port = iobase + com_iir; 1546 com->modem_ctl_port = iobase + com_mcr; 1547 com->mcr_image = inb(com->modem_ctl_port); 1548 com->line_status_port = iobase + com_lsr; 1549 com->modem_status_port = iobase + com_msr; 1550#endif 1551 1552 tp = com->tp = ttyalloc(); 1553 tp->t_oproc = comstart; 1554 tp->t_param = comparam; 1555 tp->t_stop = comstop; 1556 tp->t_modem = commodem; 1557 tp->t_break = combreak; 1558 tp->t_sc = com; 1559 1560#ifdef PC98 1561 if (!IS_8251(if_type) && rclk == 0) 1562 rclk = if_16550a_type[if_type & 0x0f].rclk; 1563#else 1564 if (rclk == 0) 1565 rclk = DEFAULT_RCLK; 1566#endif 1567 com->rclk = rclk; 1568 1569 /* 1570 * We don't use all the flags from <sys/ttydefaults.h> since they 1571 * are only relevant for logins. It's important to have echo off 1572 * initially so that the line doesn't start blathering before the 1573 * echo flag can be turned off. 1574 */ 1575 tp->t_init_in.c_iflag = 0; 1576 tp->t_init_in.c_oflag = 0; 1577 tp->t_init_in.c_cflag = TTYDEF_CFLAG; 1578 tp->t_init_in.c_lflag = 0; 1579 if (unit == comconsole) { 1580#ifdef PC98 1581 if (IS_8251(com->pc98_if_type)) 1582 DELAY(100000); 1583#endif 1584 tp->t_init_in.c_iflag = TTYDEF_IFLAG; 1585 tp->t_init_in.c_oflag = TTYDEF_OFLAG; 1586 tp->t_init_in.c_cflag = TTYDEF_CFLAG | CLOCAL; 1587 tp->t_init_in.c_lflag = TTYDEF_LFLAG; 1588 tp->t_lock_out.c_cflag = tp->t_lock_in.c_cflag = CLOCAL; 1589 tp->t_lock_out.c_ispeed = tp->t_lock_out.c_ospeed = 1590 tp->t_lock_in.c_ispeed = tp->t_lock_in.c_ospeed = 1591 tp->t_init_in.c_ispeed = tp->t_init_in.c_ospeed = comdefaultrate; 1592 } else 1593 tp->t_init_in.c_ispeed = tp->t_init_in.c_ospeed = TTYDEF_SPEED; 1594 if (siosetwater(com, tp->t_init_in.c_ispeed) != 0) { 1595 mtx_unlock_spin(&sio_lock); 1596 /* 1597 * Leave i/o resources allocated if this is a `cn'-level 1598 * console, so that other devices can't snarf them. 1599 */ 1600 if (iobase != siocniobase) 1601 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 1602 return (ENOMEM); 1603 } 1604 mtx_unlock_spin(&sio_lock); 1605 termioschars(&tp->t_init_in); 1606 tp->t_init_out = tp->t_init_in; 1607 1608 /* attempt to determine UART type */ 1609 printf("sio%d: type", unit); 1610 1611 1612#ifndef PC98 1613 if (!COM_ISMULTIPORT(flags) && 1614 !COM_IIR_TXRDYBUG(flags) && !COM_NOSCR(flags)) { 1615 u_char scr; 1616 u_char scr1; 1617 u_char scr2; 1618 1619 scr = sio_getreg(com, com_scr); 1620 sio_setreg(com, com_scr, 0xa5); 1621 scr1 = sio_getreg(com, com_scr); 1622 sio_setreg(com, com_scr, 0x5a); 1623 scr2 = sio_getreg(com, com_scr); 1624 sio_setreg(com, com_scr, scr); 1625 if (scr1 != 0xa5 || scr2 != 0x5a) { 1626 printf(" 8250 or not responding"); 1627 goto determined_type; 1628 } 1629 } 1630#endif /* !PC98 */ 1631#ifdef PC98 1632 if (IS_8251(com->pc98_if_type)) { 1633 if (com->pc98_8251fifo && !COM_NOFIFO(flags)) 1634 com->tx_fifo_size = 16; 1635 com_int_TxRx_disable( com ); 1636 com_cflag_and_speed_set( com, tp->t_init_in.c_cflag, comdefaultrate ); 1637 com_tiocm_bic( com, TIOCM_DTR|TIOCM_RTS|TIOCM_LE ); 1638 com_send_break_off( com ); 1639 1640 if (com->pc98_if_type == COM_IF_INTERNAL) { 1641 printf(" (internal%s%s)", 1642 com->pc98_8251fifo ? " fifo" : "", 1643 PC98SIO_baud_rate_port(com->pc98_if_type) != -1 ? 1644 " v-fast" : ""); 1645 } else { 1646 printf(" 8251%s", if_8251_type[com->pc98_if_type & 0x0f].name); 1647 } 1648 } else { 1649#endif /* PC98 */ 1650 sio_setreg(com, com_fifo, FIFO_ENABLE | FIFO_RX_HIGH); 1651 DELAY(100); 1652 switch (inb(com->int_id_port) & IIR_FIFO_MASK) { 1653 case FIFO_RX_LOW: 1654 printf(" 16450"); 1655 break; 1656 case FIFO_RX_MEDL: 1657 printf(" 16450?"); 1658 break; 1659 case FIFO_RX_MEDH: 1660 printf(" 16550?"); 1661 break; 1662 case FIFO_RX_HIGH: 1663 if (COM_NOFIFO(flags)) { 1664 printf(" 16550A fifo disabled"); 1665 break; 1666 } 1667 com->hasfifo = TRUE; 1668#ifdef PC98 1669 if (com->pc98_if_type == COM_IF_RSA98III) { 1670 com->tx_fifo_size = 2048; 1671 com->rsabase = iobase; 1672 outb(com->rsabase + rsa_ier, 0x00); 1673 outb(com->rsabase + rsa_frr, 0x00); 1674 } 1675#else 1676 if (COM_ST16650A(flags)) { 1677 printf(" ST16650A"); 1678 com->st16650a = TRUE; 1679 com->tx_fifo_size = 32; 1680 break; 1681 } 1682 if (COM_TI16754(flags)) { 1683 printf(" TI16754"); 1684 com->tx_fifo_size = 64; 1685 break; 1686 } 1687#endif 1688 printf(" 16550A"); 1689#ifdef COM_ESP 1690#ifdef PC98 1691 if (com->pc98_if_type == COM_IF_ESP98) 1692#endif 1693 for (espp = likely_esp_ports; *espp != 0; espp++) 1694 if (espattach(com, *espp)) { 1695 com->tx_fifo_size = 1024; 1696 break; 1697 } 1698 if (com->esp) 1699 break; 1700#endif 1701#ifdef PC98 1702 com->tx_fifo_size = 16; 1703#else 1704 com->tx_fifo_size = COM_FIFOSIZE(flags); 1705 if (com->tx_fifo_size == 0) 1706 com->tx_fifo_size = 16; 1707 else 1708 printf(" lookalike with %u bytes FIFO", 1709 com->tx_fifo_size); 1710#endif 1711 break; 1712 } 1713 1714#ifdef PC98 1715 if (com->pc98_if_type == COM_IF_RSB3000) { 1716 /* Set RSB-2000/3000 Extended Buffer mode. */ 1717 u_char lcr; 1718 lcr = sio_getreg(com, com_cfcr); 1719 sio_setreg(com, com_cfcr, lcr | CFCR_DLAB); 1720 sio_setreg(com, com_emr, EMR_EXBUFF | EMR_EFMODE); 1721 sio_setreg(com, com_cfcr, lcr); 1722 } 1723#endif 1724 1725#ifdef COM_ESP 1726 if (com->esp) { 1727 /* 1728 * Set 16550 compatibility mode. 1729 * We don't use the ESP_MODE_SCALE bit to increase the 1730 * fifo trigger levels because we can't handle large 1731 * bursts of input. 1732 * XXX flow control should be set in comparam(), not here. 1733 */ 1734#ifdef PC98 1735 outb(com->esp_port + ESP98_CMD1, ESP_SETMODE); 1736 outb(com->esp_port + ESP98_CMD2, ESP_MODE_RTS | ESP_MODE_FIFO); 1737#else 1738 outb(com->esp_port + ESP_CMD1, ESP_SETMODE); 1739 outb(com->esp_port + ESP_CMD2, ESP_MODE_RTS | ESP_MODE_FIFO); 1740#endif 1741 1742 /* Set RTS/CTS flow control. */ 1743#ifdef PC98 1744 outb(com->esp_port + ESP98_CMD1, ESP_SETFLOWTYPE); 1745 outb(com->esp_port + ESP98_CMD2, ESP_FLOW_RTS); 1746 outb(com->esp_port + ESP98_CMD2, ESP_FLOW_CTS); 1747#else 1748 outb(com->esp_port + ESP_CMD1, ESP_SETFLOWTYPE); 1749 outb(com->esp_port + ESP_CMD2, ESP_FLOW_RTS); 1750 outb(com->esp_port + ESP_CMD2, ESP_FLOW_CTS); 1751#endif 1752 1753 /* Set flow-control levels. */ 1754#ifdef PC98 1755 outb(com->esp_port + ESP98_CMD1, ESP_SETRXFLOW); 1756 outb(com->esp_port + ESP98_CMD2, HIBYTE(768)); 1757 outb(com->esp_port + ESP98_CMD2, LOBYTE(768)); 1758 outb(com->esp_port + ESP98_CMD2, HIBYTE(512)); 1759 outb(com->esp_port + ESP98_CMD2, LOBYTE(512)); 1760#else 1761 outb(com->esp_port + ESP_CMD1, ESP_SETRXFLOW); 1762 outb(com->esp_port + ESP_CMD2, HIBYTE(768)); 1763 outb(com->esp_port + ESP_CMD2, LOBYTE(768)); 1764 outb(com->esp_port + ESP_CMD2, HIBYTE(512)); 1765 outb(com->esp_port + ESP_CMD2, LOBYTE(512)); 1766#endif 1767 1768#ifdef PC98 1769 /* Set UART clock prescaler. */ 1770 outb(com->esp_port + ESP98_CMD1, ESP_SETCLOCK); 1771 outb(com->esp_port + ESP98_CMD2, 2); /* 4 times */ 1772#endif 1773 } 1774#endif /* COM_ESP */ 1775 sio_setreg(com, com_fifo, 0); 1776#ifdef PC98 1777 printf("%s", if_16550a_type[com->pc98_if_type & 0x0f].name); 1778#else 1779determined_type: ; 1780#endif 1781 1782#ifdef COM_MULTIPORT 1783 if (COM_ISMULTIPORT(flags)) { 1784 device_t masterdev; 1785 1786 com->multiport = TRUE; 1787 printf(" (multiport"); 1788 if (unit == COM_MPMASTER(flags)) 1789 printf(" master"); 1790 printf(")"); 1791 masterdev = devclass_get_device(sio_devclass, 1792 COM_MPMASTER(flags)); 1793 com->no_irq = (masterdev == NULL || bus_get_resource(masterdev, 1794 SYS_RES_IRQ, 0, NULL, NULL) != 0); 1795 } 1796#endif /* COM_MULTIPORT */ 1797#ifdef PC98 1798 } 1799#endif 1800 if (unit == comconsole) 1801 printf(", console"); 1802 if (COM_IIR_TXRDYBUG(flags)) 1803 printf(" with a buggy IIR_TXRDY implementation"); 1804 printf("\n"); 1805 1806 if (sio_fast_ih == NULL) { 1807 swi_add(&tty_ithd, "sio", siopoll, NULL, SWI_TTY, 0, 1808 &sio_fast_ih); 1809 swi_add(&clk_ithd, "sio", siopoll, NULL, SWI_CLOCK, 0, 1810 &sio_slow_ih); 1811 } 1812 minorbase = UNIT_TO_MINOR(unit); 1813 com->devs[0] = make_dev(&sio_cdevsw, minorbase, 1814 UID_ROOT, GID_WHEEL, 0600, "ttyd%r", unit); 1815 com->devs[1] = make_dev(&sioc_cdevsw, minorbase | CONTROL_INIT_STATE, 1816 UID_ROOT, GID_WHEEL, 0600, "ttyid%r", unit); 1817 com->devs[2] = make_dev(&sioc_cdevsw, minorbase | CONTROL_LOCK_STATE, 1818 UID_ROOT, GID_WHEEL, 0600, "ttyld%r", unit); 1819 com->devs[3] = make_dev(&sio_cdevsw, minorbase | CALLOUT_MASK, 1820 UID_UUCP, GID_DIALER, 0660, "cuaa%r", unit); 1821 com->devs[4] = make_dev(&sioc_cdevsw, 1822 minorbase | CALLOUT_MASK | CONTROL_INIT_STATE, 1823 UID_UUCP, GID_DIALER, 0660, "cuaia%r", unit); 1824 com->devs[5] = make_dev(&sioc_cdevsw, 1825 minorbase | CALLOUT_MASK | CONTROL_LOCK_STATE, 1826 UID_UUCP, GID_DIALER, 0660, "cuala%r", unit); 1827 for (rid = 0; rid < 6; rid++) { 1828 com->devs[rid]->si_drv1 = com; 1829 com->devs[rid]->si_tty = tp; 1830 } 1831 com->flags = flags; 1832 com->pps.ppscap = PPS_CAPTUREASSERT | PPS_CAPTURECLEAR; 1833 1834 if (COM_PPSCTS(flags)) 1835 com->pps_bit = MSR_CTS; 1836 else 1837 com->pps_bit = MSR_DCD; 1838 pps_init(&com->pps); 1839 1840 rid = 0; 1841 com->irqres = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, RF_ACTIVE); 1842 if (com->irqres) { 1843 ret = BUS_SETUP_INTR(device_get_parent(dev), dev, com->irqres, 1844 INTR_TYPE_TTY | INTR_FAST, 1845 siointr, com, &com->cookie); 1846 if (ret) { 1847 ret = BUS_SETUP_INTR(device_get_parent(dev), dev, 1848 com->irqres, INTR_TYPE_TTY, 1849 siointr, com, &com->cookie); 1850 if (ret == 0) 1851 device_printf(dev, "unable to activate interrupt in fast mode - using normal mode\n"); 1852 } 1853 if (ret) 1854 device_printf(dev, "could not activate interrupt\n"); 1855#if defined(KDB) && (defined(BREAK_TO_DEBUGGER) || \ 1856 defined(ALT_BREAK_TO_DEBUGGER)) 1857 /* 1858 * Enable interrupts for early break-to-debugger support 1859 * on the console. 1860 */ 1861 if (ret == 0 && unit == comconsole) 1862 outb(siocniobase + com_ier, IER_ERXRDY | IER_ERLS | 1863 IER_EMSC); 1864#endif 1865 } 1866 1867 return (0); 1868} 1869 1870static int 1871siocopen(dev, flag, mode, td) 1872 struct cdev *dev; 1873 int flag; 1874 int mode; 1875 struct thread *td; 1876{ 1877 struct com_s *com; 1878 1879 com = dev->si_drv1; 1880 if (com == NULL) 1881 return (ENXIO); 1882 if (com->gone) 1883 return (ENXIO); 1884 return (0); 1885} 1886 1887static int 1888sioopen(dev, flag, mode, td) 1889 struct cdev *dev; 1890 int flag; 1891 int mode; 1892 struct thread *td; 1893{ 1894 struct com_s *com; 1895 int error; 1896 int mynor; 1897 int s; 1898 struct tty *tp; 1899 int unit; 1900 1901 mynor = minor(dev); 1902 unit = MINOR_TO_UNIT(mynor); 1903 com = dev->si_drv1; 1904 if (com == NULL) 1905 return (ENXIO); 1906 if (com->gone) 1907 return (ENXIO); 1908 tp = dev->si_tty = com->tp; 1909 s = spltty(); 1910 /* 1911 * We jump to this label after all non-interrupted sleeps to pick 1912 * up any changes of the device state. 1913 */ 1914open_top: 1915 error = ttydtrwaitsleep(tp); 1916 if (error != 0) 1917 goto out; 1918 if (tp->t_state & TS_ISOPEN) { 1919 /* 1920 * The device is open, so everything has been initialized. 1921 * Handle conflicts. 1922 */ 1923 if (mynor & CALLOUT_MASK) { 1924 if (!com->active_out) { 1925 error = EBUSY; 1926 goto out; 1927 } 1928 } else { 1929 if (com->active_out) { 1930 if (flag & O_NONBLOCK) { 1931 error = EBUSY; 1932 goto out; 1933 } 1934 error = tsleep(&com->active_out, 1935 TTIPRI | PCATCH, "siobi", 0); 1936 if (com_addr(unit) == NULL) 1937 return (ENXIO); 1938 if (error != 0 || com->gone) 1939 goto out; 1940 goto open_top; 1941 } 1942 } 1943 if (tp->t_state & TS_XCLUDE && 1944 suser(td)) { 1945 error = EBUSY; 1946 goto out; 1947 } 1948 } else { 1949 /* 1950 * The device isn't open, so there are no conflicts. 1951 * Initialize it. Initialization is done twice in many 1952 * cases: to preempt sleeping callin opens if we are 1953 * callout, and to complete a callin open after DCD rises. 1954 */ 1955 tp->t_dev = dev; 1956 tp->t_termios = mynor & CALLOUT_MASK 1957 ? tp->t_init_out : tp->t_init_in; 1958#ifdef PC98 1959 if (!IS_8251(com->pc98_if_type)) 1960#endif 1961 (void)commodem(tp, SER_DTR | SER_RTS, 0); 1962 com->poll = com->no_irq; 1963 com->poll_output = com->loses_outints; 1964 ++com->wopeners; 1965 error = comparam(tp, &tp->t_termios); 1966 --com->wopeners; 1967 if (error != 0) 1968 goto out; 1969#ifdef PC98 1970 if (IS_8251(com->pc98_if_type)) { 1971 com_tiocm_bis(com, TIOCM_DTR|TIOCM_RTS); 1972 pc98_msrint_start(dev); 1973 if (com->pc98_8251fifo) { 1974 com->pc98_8251fifo_enable = 1; 1975 outb(I8251F_fcr, CTRL8251F_ENABLE | 1976 CTRL8251F_XMT_RST | CTRL8251F_RCV_RST); 1977 } 1978 } 1979#endif 1980 /* 1981 * XXX we should goto open_top if comparam() slept. 1982 */ 1983 if (com->hasfifo) { 1984 int i; 1985 /* 1986 * (Re)enable and drain fifos. 1987 * 1988 * Certain SMC chips cause problems if the fifos 1989 * are enabled while input is ready. Turn off the 1990 * fifo if necessary to clear the input. We test 1991 * the input ready bit after enabling the fifos 1992 * since we've already enabled them in comparam() 1993 * and to handle races between enabling and fresh 1994 * input. 1995 */ 1996 for (i = 0; i < 500; i++) { 1997 sio_setreg(com, com_fifo, 1998 FIFO_RCV_RST | FIFO_XMT_RST 1999 | com->fifo_image); 2000#ifdef PC98 2001 if (com->pc98_if_type == COM_IF_RSA98III) 2002 outb(com->rsabase + rsa_frr , 0x00); 2003#endif 2004 /* 2005 * XXX the delays are for superstitious 2006 * historical reasons. It must be less than 2007 * the character time at the maximum 2008 * supported speed (87 usec at 115200 bps 2009 * 8N1). Otherwise we might loop endlessly 2010 * if data is streaming in. We used to use 2011 * delays of 100. That usually worked 2012 * because DELAY(100) used to usually delay 2013 * for about 85 usec instead of 100. 2014 */ 2015 DELAY(50); 2016#ifdef PC98 2017 if (com->pc98_if_type == COM_IF_RSA98III ? 2018 !(inb(com->rsabase + rsa_srr) & 0x08) : 2019 !(inb(com->line_status_port) & LSR_RXRDY)) 2020 break; 2021#else 2022 if (!(inb(com->line_status_port) & LSR_RXRDY)) 2023 break; 2024#endif 2025 sio_setreg(com, com_fifo, 0); 2026 DELAY(50); 2027 (void) inb(com->data_port); 2028 } 2029 if (i == 500) { 2030 error = EIO; 2031 goto out; 2032 } 2033 } 2034 2035 mtx_lock_spin(&sio_lock); 2036#ifdef PC98 2037 if (IS_8251(com->pc98_if_type)) { 2038 com_tiocm_bis(com, TIOCM_LE); 2039 com->pc98_prev_modem_status = pc98_get_modem_status(com); 2040 com_int_Rx_enable(com); 2041 } else { 2042#endif 2043 (void) inb(com->line_status_port); 2044 (void) inb(com->data_port); 2045 com->prev_modem_status = com->last_modem_status 2046 = inb(com->modem_status_port); 2047 outb(com->int_ctl_port, 2048 IER_ERXRDY | IER_ERLS | IER_EMSC 2049 | (COM_IIR_TXRDYBUG(com->flags) ? 0 : IER_ETXRDY)); 2050#ifdef PC98 2051 if (com->pc98_if_type == COM_IF_RSA98III) { 2052 outb(com->rsabase + rsa_ier, 0x1d); 2053 outb(com->int_ctl_port, IER_ERLS | IER_EMSC); 2054 } 2055#endif 2056#ifdef PC98 2057 } 2058#endif 2059 mtx_unlock_spin(&sio_lock); 2060 /* 2061 * Handle initial DCD. Callout devices get a fake initial 2062 * DCD (trapdoor DCD). If we are callout, then any sleeping 2063 * callin opens get woken up and resume sleeping on "siobi" 2064 * instead of "siodcd". 2065 */ 2066 /* 2067 * XXX `mynor & CALLOUT_MASK' should be 2068 * `tp->t_cflag & (SOFT_CARRIER | TRAPDOOR_CARRIER) where 2069 * TRAPDOOR_CARRIER is the default initial state for callout 2070 * devices and SOFT_CARRIER is like CLOCAL except it hides 2071 * the true carrier. 2072 */ 2073#ifdef PC98 2074 if ((IS_8251(com->pc98_if_type) && 2075 (pc98_get_modem_status(com) & TIOCM_CAR)) || 2076 (!IS_8251(com->pc98_if_type) && 2077 (com->prev_modem_status & MSR_DCD)) || 2078 mynor & CALLOUT_MASK) 2079 ttyld_modem(tp, 1); 2080#else 2081 if (com->prev_modem_status & MSR_DCD || mynor & CALLOUT_MASK) 2082 ttyld_modem(tp, 1); 2083#endif 2084 } 2085 /* 2086 * Wait for DCD if necessary. 2087 */ 2088 if (!(tp->t_state & TS_CARR_ON) && !(mynor & CALLOUT_MASK) 2089 && !(tp->t_cflag & CLOCAL) && !(flag & O_NONBLOCK)) { 2090 ++com->wopeners; 2091 error = tsleep(TSA_CARR_ON(tp), TTIPRI | PCATCH, "siodcd", 0); 2092 if (com_addr(unit) == NULL) 2093 return (ENXIO); 2094 --com->wopeners; 2095 if (error != 0 || com->gone) 2096 goto out; 2097 goto open_top; 2098 } 2099 error = ttyld_open(tp, dev); 2100 ttyldoptim(tp); 2101 if (tp->t_state & TS_ISOPEN && mynor & CALLOUT_MASK) 2102 com->active_out = TRUE; 2103 siosettimeout(); 2104out: 2105 splx(s); 2106 if (!(tp->t_state & TS_ISOPEN) && com->wopeners == 0) 2107 comhardclose(com); 2108 return (error); 2109} 2110 2111static int 2112siocclose(dev, flag, mode, td) 2113 struct cdev *dev; 2114 int flag; 2115 int mode; 2116 struct thread *td; 2117{ 2118 2119 return (0); 2120} 2121 2122static int 2123sioclose(dev, flag, mode, td) 2124 struct cdev *dev; 2125 int flag; 2126 int mode; 2127 struct thread *td; 2128{ 2129 struct com_s *com; 2130 int s; 2131 struct tty *tp; 2132 2133 com = dev->si_drv1; 2134 if (com == NULL) 2135 return (ENODEV); 2136 tp = com->tp; 2137 s = spltty(); 2138 ttyld_close(tp, flag); 2139#ifdef PC98 2140 com->modem_checking = 0; 2141#endif 2142 ttyldoptim(tp); 2143 comhardclose(com); 2144 tty_close(tp); 2145 siosettimeout(); 2146 splx(s); 2147 if (com->gone) { 2148 printf("sio%d: gone\n", com->unit); 2149 s = spltty(); 2150 if (com->ibuf != NULL) 2151 free(com->ibuf, M_DEVBUF); 2152 bzero(tp, sizeof *tp); 2153 splx(s); 2154 } 2155 return (0); 2156} 2157 2158static void 2159comhardclose(com) 2160 struct com_s *com; 2161{ 2162 int s; 2163 struct tty *tp; 2164 2165 s = spltty(); 2166 com->poll = FALSE; 2167 com->poll_output = FALSE; 2168 com->do_timestamp = FALSE; 2169 com->pps.ppsparam.mode = 0; 2170#ifdef PC98 2171 com_send_break_off(com); 2172#else 2173 sio_setreg(com, com_cfcr, com->cfcr_image &= ~CFCR_SBREAK); 2174#endif 2175 tp = com->tp; 2176 2177#if defined(KDB) && (defined(BREAK_TO_DEBUGGER) || \ 2178 defined(ALT_BREAK_TO_DEBUGGER)) 2179 /* 2180 * Leave interrupts enabled and don't clear DTR if this is the 2181 * console. This allows us to detect break-to-debugger events 2182 * while the console device is closed. 2183 */ 2184 if (com->unit != comconsole) 2185#endif 2186 { 2187#ifdef PC98 2188 int tmp; 2189 if (IS_8251(com->pc98_if_type)) 2190 com_int_TxRx_disable(com); 2191 else 2192 sio_setreg(com, com_ier, 0); 2193 if (com->pc98_if_type == COM_IF_RSA98III) 2194 outb(com->rsabase + rsa_ier, 0x00); 2195 if (IS_8251(com->pc98_if_type)) 2196 tmp = pc98_get_modem_status(com) & TIOCM_CAR; 2197 else 2198 tmp = com->prev_modem_status & MSR_DCD; 2199#else 2200 sio_setreg(com, com_ier, 0); 2201#endif 2202 if (tp->t_cflag & HUPCL 2203 /* 2204 * XXX we will miss any carrier drop between here and the 2205 * next open. Perhaps we should watch DCD even when the 2206 * port is closed; it is not sufficient to check it at 2207 * the next open because it might go up and down while 2208 * we're not watching. 2209 */ 2210 || (!com->active_out 2211#ifdef PC98 2212 && !(tmp) 2213#else 2214 && !(com->prev_modem_status & MSR_DCD) 2215#endif 2216 && !(tp->t_init_in.c_cflag & CLOCAL)) 2217 || !(tp->t_state & TS_ISOPEN)) { 2218#ifdef PC98 2219 if (IS_8251(com->pc98_if_type)) 2220 com_tiocm_bic(com, TIOCM_DTR|TIOCM_RTS|TIOCM_LE); 2221 else 2222#endif 2223 (void)commodem(tp, 0, SER_DTR); 2224 ttydtrwaitstart(tp); 2225 } 2226#ifdef PC98 2227 else { 2228 if (IS_8251(com->pc98_if_type)) 2229 com_tiocm_bic(com, TIOCM_LE); 2230 } 2231#endif 2232 } 2233#ifdef PC98 2234 if (com->pc98_8251fifo) { 2235 if (com->pc98_8251fifo_enable) 2236 outb(I8251F_fcr, CTRL8251F_XMT_RST | CTRL8251F_RCV_RST); 2237 com->pc98_8251fifo_enable = 0; 2238 } 2239#endif 2240 if (com->hasfifo) { 2241 /* 2242 * Disable fifos so that they are off after controlled 2243 * reboots. Some BIOSes fail to detect 16550s when the 2244 * fifos are enabled. 2245 */ 2246 sio_setreg(com, com_fifo, 0); 2247 } 2248 com->active_out = FALSE; 2249 wakeup(&com->active_out); 2250 wakeup(TSA_CARR_ON(tp)); /* restart any wopeners */ 2251 splx(s); 2252} 2253 2254static int 2255siocrdwr(dev, uio, flag) 2256 struct cdev *dev; 2257 struct uio *uio; 2258 int flag; 2259{ 2260 2261 return (ENODEV); 2262} 2263 2264static int 2265sioread(dev, uio, flag) 2266 struct cdev *dev; 2267 struct uio *uio; 2268 int flag; 2269{ 2270 struct com_s *com; 2271 2272 com = dev->si_drv1; 2273 if (com == NULL || com->gone) 2274 return (ENODEV); 2275 return (ttyld_read(com->tp, uio, flag)); 2276} 2277 2278static int 2279siowrite(dev, uio, flag) 2280 struct cdev *dev; 2281 struct uio *uio; 2282 int flag; 2283{ 2284 int mynor; 2285 struct com_s *com; 2286 int unit; 2287 2288 mynor = minor(dev); 2289 2290 unit = MINOR_TO_UNIT(mynor); 2291 com = dev->si_drv1; 2292 if (com == NULL || com->gone) 2293 return (ENODEV); 2294 /* 2295 * (XXX) We disallow virtual consoles if the physical console is 2296 * a serial port. This is in case there is a display attached that 2297 * is not the console. In that situation we don't need/want the X 2298 * server taking over the console. 2299 */ 2300 if (constty != NULL && unit == comconsole) 2301 constty = NULL; 2302 return (ttyld_write(com->tp, uio, flag)); 2303} 2304 2305static void 2306siobusycheck(chan) 2307 void *chan; 2308{ 2309 struct com_s *com; 2310 int s; 2311 2312 com = (struct com_s *)chan; 2313 2314 /* 2315 * Clear TS_BUSY if low-level output is complete. 2316 * spl locking is sufficient because siointr1() does not set CS_BUSY. 2317 * If siointr1() clears CS_BUSY after we look at it, then we'll get 2318 * called again. Reading the line status port outside of siointr1() 2319 * is safe because CS_BUSY is clear so there are no output interrupts 2320 * to lose. 2321 */ 2322 s = spltty(); 2323 if (com->state & CS_BUSY) 2324 com->extra_state &= ~CSE_BUSYCHECK; /* False alarm. */ 2325#ifdef PC98 2326 else if ((IS_8251(com->pc98_if_type) && 2327 ((com->pc98_8251fifo_enable && 2328 (inb(I8251F_lsr) & (STS8251F_TxRDY | STS8251F_TxEMP)) 2329 == (STS8251F_TxRDY | STS8251F_TxEMP)) || 2330 (!com->pc98_8251fifo_enable && 2331 (inb(com->sts_port) & (STS8251_TxRDY | STS8251_TxEMP)) 2332 == (STS8251_TxRDY | STS8251_TxEMP)))) || 2333 ((inb(com->line_status_port) & (LSR_TSRE | LSR_TXRDY)) 2334 == (LSR_TSRE | LSR_TXRDY))) { 2335#else 2336 else if ((inb(com->line_status_port) & (LSR_TSRE | LSR_TXRDY)) 2337 == (LSR_TSRE | LSR_TXRDY)) { 2338#endif 2339 com->tp->t_state &= ~TS_BUSY; 2340 ttwwakeup(com->tp); 2341 com->extra_state &= ~CSE_BUSYCHECK; 2342 } else 2343 timeout(siobusycheck, com, hz / 100); 2344 splx(s); 2345} 2346 2347static u_int 2348siodivisor(rclk, speed) 2349 u_long rclk; 2350 speed_t speed; 2351{ 2352 long actual_speed; 2353 u_int divisor; 2354 int error; 2355 2356 if (speed == 0) 2357 return (0); 2358#if UINT_MAX > (ULONG_MAX - 1) / 8 2359 if (speed > (ULONG_MAX - 1) / 8) 2360 return (0); 2361#endif 2362 divisor = (rclk / (8UL * speed) + 1) / 2; 2363 if (divisor == 0 || divisor >= 65536) 2364 return (0); 2365 actual_speed = rclk / (16UL * divisor); 2366 2367 /* 10 times error in percent: */ 2368 error = ((actual_speed - (long)speed) * 2000 / (long)speed + 1) / 2; 2369 2370 /* 3.0% maximum error tolerance: */ 2371 if (error < -30 || error > 30) 2372 return (0); 2373 2374 return (divisor); 2375} 2376 2377/* 2378 * Call this function with the sio_lock mutex held. It will return with the 2379 * lock still held. 2380 */ 2381static void 2382sioinput(com) 2383 struct com_s *com; 2384{ 2385 u_char *buf; 2386 int incc; 2387 u_char line_status; 2388 int recv_data; 2389 struct tty *tp; 2390 2391 buf = com->ibuf; 2392 tp = com->tp; 2393 if (!(tp->t_state & TS_ISOPEN) || !(tp->t_cflag & CREAD)) { 2394 com_events -= (com->iptr - com->ibuf); 2395 com->iptr = com->ibuf; 2396 return; 2397 } 2398 if (tp->t_state & TS_CAN_BYPASS_L_RINT) { 2399 /* 2400 * Avoid the grotesquely inefficient lineswitch routine 2401 * (ttyinput) in "raw" mode. It usually takes about 450 2402 * instructions (that's without canonical processing or echo!). 2403 * slinput is reasonably fast (usually 40 instructions plus 2404 * call overhead). 2405 */ 2406 do { 2407 /* 2408 * This may look odd, but it is using save-and-enable 2409 * semantics instead of the save-and-disable semantics 2410 * that are used everywhere else. 2411 */ 2412 mtx_unlock_spin(&sio_lock); 2413 incc = com->iptr - buf; 2414 if (tp->t_rawq.c_cc + incc > tp->t_ihiwat 2415 && (com->state & CS_RTS_IFLOW 2416 || tp->t_iflag & IXOFF) 2417 && !(tp->t_state & TS_TBLOCK)) 2418 ttyblock(tp); 2419 com->delta_error_counts[CE_TTY_BUF_OVERFLOW] 2420 += b_to_q((char *)buf, incc, &tp->t_rawq); 2421 buf += incc; 2422 tk_nin += incc; 2423 tk_rawcc += incc; 2424 tp->t_rawcc += incc; 2425 ttwakeup(tp); 2426 if (tp->t_state & TS_TTSTOP 2427 && (tp->t_iflag & IXANY 2428 || tp->t_cc[VSTART] == tp->t_cc[VSTOP])) { 2429 tp->t_state &= ~TS_TTSTOP; 2430 tp->t_lflag &= ~FLUSHO; 2431 comstart(tp); 2432 } 2433 mtx_lock_spin(&sio_lock); 2434 } while (buf < com->iptr); 2435 } else { 2436 do { 2437 /* 2438 * This may look odd, but it is using save-and-enable 2439 * semantics instead of the save-and-disable semantics 2440 * that are used everywhere else. 2441 */ 2442 mtx_unlock_spin(&sio_lock); 2443 line_status = buf[com->ierroff]; 2444 recv_data = *buf++; 2445 if (line_status 2446 & (LSR_BI | LSR_FE | LSR_OE | LSR_PE)) { 2447 if (line_status & LSR_BI) 2448 recv_data |= TTY_BI; 2449 if (line_status & LSR_FE) 2450 recv_data |= TTY_FE; 2451 if (line_status & LSR_OE) 2452 recv_data |= TTY_OE; 2453 if (line_status & LSR_PE) 2454 recv_data |= TTY_PE; 2455 } 2456 ttyld_rint(tp, recv_data); 2457 mtx_lock_spin(&sio_lock); 2458 } while (buf < com->iptr); 2459 } 2460 com_events -= (com->iptr - com->ibuf); 2461 com->iptr = com->ibuf; 2462 2463 /* 2464 * There is now room for another low-level buffer full of input, 2465 * so enable RTS if it is now disabled and there is room in the 2466 * high-level buffer. 2467 */ 2468#ifdef PC98 2469 if (IS_8251(com->pc98_if_type)) { 2470 if ((com->state & CS_RTS_IFLOW) && 2471 !(com_tiocm_get(com) & TIOCM_RTS) && 2472 !(tp->t_state & TS_TBLOCK)) 2473 com_tiocm_bis(com, TIOCM_RTS); 2474 } else { 2475 if ((com->state & CS_RTS_IFLOW) && 2476 !(com->mcr_image & MCR_RTS) && 2477 !(tp->t_state & TS_TBLOCK)) 2478 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS); 2479 } 2480#else 2481 if ((com->state & CS_RTS_IFLOW) && !(com->mcr_image & MCR_RTS) && 2482 !(tp->t_state & TS_TBLOCK)) 2483 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS); 2484#endif 2485} 2486 2487static void 2488siointr(arg) 2489 void *arg; 2490{ 2491 struct com_s *com; 2492#if defined(PC98) && defined(COM_MULTIPORT) 2493 u_char rsa_buf_status; 2494#endif 2495 2496#ifndef COM_MULTIPORT 2497 com = (struct com_s *)arg; 2498 2499 mtx_lock_spin(&sio_lock); 2500 siointr1(com); 2501 mtx_unlock_spin(&sio_lock); 2502#else /* COM_MULTIPORT */ 2503 bool_t possibly_more_intrs; 2504 int unit; 2505 2506 /* 2507 * Loop until there is no activity on any port. This is necessary 2508 * to get an interrupt edge more than to avoid another interrupt. 2509 * If the IRQ signal is just an OR of the IRQ signals from several 2510 * devices, then the edge from one may be lost because another is 2511 * on. 2512 */ 2513 mtx_lock_spin(&sio_lock); 2514 do { 2515 possibly_more_intrs = FALSE; 2516 for (unit = 0; unit < sio_numunits; ++unit) { 2517 com = com_addr(unit); 2518 /* 2519 * XXX COM_LOCK(); 2520 * would it work here, or be counter-productive? 2521 */ 2522#ifdef PC98 2523 if (com != NULL 2524 && !com->gone 2525 && IS_8251(com->pc98_if_type)) { 2526 siointr1(com); 2527 } else if (com != NULL 2528 && !com->gone 2529 && com->pc98_if_type == COM_IF_RSA98III) { 2530 rsa_buf_status = 2531 inb(com->rsabase + rsa_srr) & 0xc9; 2532 if ((rsa_buf_status & 0xc8) 2533 || !(rsa_buf_status & 0x01)) { 2534 siointr1(com); 2535 if (rsa_buf_status != 2536 (inb(com->rsabase + rsa_srr) & 0xc9)) 2537 possibly_more_intrs = TRUE; 2538 } 2539 } else 2540#endif 2541 if (com != NULL 2542 && !com->gone 2543 && (inb(com->int_id_port) & IIR_IMASK) 2544 != IIR_NOPEND) { 2545 siointr1(com); 2546 possibly_more_intrs = TRUE; 2547 } 2548 /* XXX COM_UNLOCK(); */ 2549 } 2550 } while (possibly_more_intrs); 2551 mtx_unlock_spin(&sio_lock); 2552#endif /* COM_MULTIPORT */ 2553} 2554 2555static struct timespec siots[8]; 2556static int siotso; 2557static int volatile siotsunit = -1; 2558 2559static int 2560sysctl_siots(SYSCTL_HANDLER_ARGS) 2561{ 2562 char buf[128]; 2563 long long delta; 2564 size_t len; 2565 int error, i, tso; 2566 2567 for (i = 1, tso = siotso; i < tso; i++) { 2568 delta = (long long)(siots[i].tv_sec - siots[i - 1].tv_sec) * 2569 1000000000 + 2570 (siots[i].tv_nsec - siots[i - 1].tv_nsec); 2571 len = sprintf(buf, "%lld\n", delta); 2572 if (delta >= 110000) 2573 len += sprintf(buf + len - 1, ": *** %ld.%09ld\n", 2574 (long)siots[i].tv_sec, siots[i].tv_nsec) - 1; 2575 if (i == tso - 1) 2576 buf[len - 1] = '\0'; 2577 error = SYSCTL_OUT(req, buf, len); 2578 if (error != 0) 2579 return (error); 2580 uio_yield(); 2581 } 2582 return (0); 2583} 2584 2585SYSCTL_PROC(_machdep, OID_AUTO, siots, CTLTYPE_STRING | CTLFLAG_RD, 2586 0, 0, sysctl_siots, "A", "sio timestamps"); 2587 2588static void 2589siointr1(com) 2590 struct com_s *com; 2591{ 2592 u_char int_ctl; 2593 u_char int_ctl_new; 2594 u_char line_status; 2595 u_char modem_status; 2596 u_char *ioptr; 2597 u_char recv_data; 2598 2599#ifdef PC98 2600 u_char tmp = 0; 2601 u_char rsa_buf_status = 0; 2602 int rsa_tx_fifo_size = 0; 2603#endif /* PC98 */ 2604 2605 if (COM_IIR_TXRDYBUG(com->flags)) { 2606 int_ctl = inb(com->int_ctl_port); 2607 int_ctl_new = int_ctl; 2608 } else { 2609 int_ctl = 0; 2610 int_ctl_new = 0; 2611 } 2612 2613 while (!com->gone) { 2614#ifdef PC98 2615status_read:; 2616 if (IS_8251(com->pc98_if_type)) { 2617 if (com->pc98_8251fifo_enable) 2618 tmp = inb(I8251F_lsr); 2619 else 2620 tmp = inb(com->sts_port); 2621more_intr: 2622 line_status = 0; 2623 if (com->pc98_8251fifo_enable) { 2624 if (tmp & STS8251F_TxRDY) line_status |= LSR_TXRDY; 2625 if (tmp & STS8251F_RxRDY) line_status |= LSR_RXRDY; 2626 if (tmp & STS8251F_TxEMP) line_status |= LSR_TSRE; 2627 if (tmp & STS8251F_PE) line_status |= LSR_PE; 2628 if (tmp & STS8251F_OE) line_status |= LSR_OE; 2629 if (tmp & STS8251F_BD_SD) line_status |= LSR_BI; 2630 } else { 2631 if (tmp & STS8251_TxRDY) line_status |= LSR_TXRDY; 2632 if (tmp & STS8251_RxRDY) line_status |= LSR_RXRDY; 2633 if (tmp & STS8251_TxEMP) line_status |= LSR_TSRE; 2634 if (tmp & STS8251_PE) line_status |= LSR_PE; 2635 if (tmp & STS8251_OE) line_status |= LSR_OE; 2636 if (tmp & STS8251_FE) line_status |= LSR_FE; 2637 if (tmp & STS8251_BD_SD) line_status |= LSR_BI; 2638 } 2639 } else { 2640#endif /* PC98 */ 2641 if (com->pps.ppsparam.mode & PPS_CAPTUREBOTH) { 2642 modem_status = inb(com->modem_status_port); 2643 if ((modem_status ^ com->last_modem_status) & 2644 com->pps_bit) { 2645 pps_capture(&com->pps); 2646 pps_event(&com->pps, 2647 (modem_status & com->pps_bit) ? 2648 PPS_CAPTUREASSERT : PPS_CAPTURECLEAR); 2649 } 2650 } 2651 line_status = inb(com->line_status_port); 2652#ifdef PC98 2653 } 2654 if (com->pc98_if_type == COM_IF_RSA98III) 2655 rsa_buf_status = inb(com->rsabase + rsa_srr); 2656#endif /* PC98 */ 2657 2658 /* input event? (check first to help avoid overruns) */ 2659#ifndef PC98 2660 while (line_status & LSR_RCV_MASK) { 2661#else 2662 while ((line_status & LSR_RCV_MASK) 2663 || (com->pc98_if_type == COM_IF_RSA98III 2664 && (rsa_buf_status & 0x08))) { 2665#endif /* PC98 */ 2666 /* break/unnattached error bits or real input? */ 2667#ifdef PC98 2668 if (IS_8251(com->pc98_if_type)) { 2669 if (com->pc98_8251fifo_enable) { 2670 recv_data = inb(I8251F_data); 2671 if (tmp & (STS8251F_PE | STS8251F_OE | 2672 STS8251F_BD_SD)) { 2673 pc98_i8251_or_cmd(com, CMD8251_ER); 2674 recv_data = 0; 2675 } 2676 } else { 2677 recv_data = inb(com->data_port); 2678 if (tmp & (STS8251_PE | STS8251_OE | 2679 STS8251_FE | STS8251_BD_SD)) { 2680 pc98_i8251_or_cmd(com, CMD8251_ER); 2681 recv_data = 0; 2682 } 2683 } 2684 } else if (com->pc98_if_type == COM_IF_RSA98III) { 2685 if (!(rsa_buf_status & 0x08)) 2686 recv_data = 0; 2687 else 2688 recv_data = inb(com->data_port); 2689 } else 2690#endif 2691 if (!(line_status & LSR_RXRDY)) 2692 recv_data = 0; 2693 else 2694 recv_data = inb(com->data_port); 2695#ifdef KDB 2696#ifdef ALT_BREAK_TO_DEBUGGER 2697 if (com->unit == comconsole && 2698 kdb_alt_break(recv_data, &com->alt_brk_state) != 0) 2699 kdb_enter("Break sequence on console"); 2700#endif /* ALT_BREAK_TO_DEBUGGER */ 2701#endif /* KDB */ 2702 if (line_status & (LSR_BI | LSR_FE | LSR_PE)) { 2703 /* 2704 * Don't store BI if IGNBRK or FE/PE if IGNPAR. 2705 * Otherwise, push the work to a higher level 2706 * (to handle PARMRK) if we're bypassing. 2707 * Otherwise, convert BI/FE and PE+INPCK to 0. 2708 * 2709 * This makes bypassing work right in the 2710 * usual "raw" case (IGNBRK set, and IGNPAR 2711 * and INPCK clear). 2712 * 2713 * Note: BI together with FE/PE means just BI. 2714 */ 2715 if (line_status & LSR_BI) { 2716#if defined(KDB) && defined(BREAK_TO_DEBUGGER) 2717 if (com->unit == comconsole) { 2718 kdb_enter("Line break on console"); 2719 goto cont; 2720 } 2721#endif 2722 if (com->tp == NULL 2723 || com->tp->t_iflag & IGNBRK) 2724 goto cont; 2725 } else { 2726 if (com->tp == NULL 2727 || com->tp->t_iflag & IGNPAR) 2728 goto cont; 2729 } 2730 if (com->tp->t_state & TS_CAN_BYPASS_L_RINT 2731 && (line_status & (LSR_BI | LSR_FE) 2732 || com->tp->t_iflag & INPCK)) 2733 recv_data = 0; 2734 } 2735 ++com->bytes_in; 2736 if (com->tp != NULL && 2737 com->tp->t_hotchar != 0 && recv_data == com->tp->t_hotchar) 2738 swi_sched(sio_fast_ih, 0); 2739 ioptr = com->iptr; 2740 if (ioptr >= com->ibufend) 2741 CE_RECORD(com, CE_INTERRUPT_BUF_OVERFLOW); 2742 else { 2743 if (com->do_timestamp) 2744 microtime(&com->timestamp); 2745 ++com_events; 2746 swi_sched(sio_slow_ih, SWI_DELAY); 2747#if 0 /* for testing input latency vs efficiency */ 2748if (com->iptr - com->ibuf == 8) 2749 swi_sched(sio_fast_ih, 0); 2750#endif 2751 ioptr[0] = recv_data; 2752 ioptr[com->ierroff] = line_status; 2753 com->iptr = ++ioptr; 2754 if (ioptr == com->ihighwater 2755 && com->state & CS_RTS_IFLOW) 2756#ifdef PC98 2757 IS_8251(com->pc98_if_type) ? 2758 com_tiocm_bic(com, TIOCM_RTS) : 2759#endif 2760 outb(com->modem_ctl_port, 2761 com->mcr_image &= ~MCR_RTS); 2762 if (line_status & LSR_OE) 2763 CE_RECORD(com, CE_OVERRUN); 2764 } 2765cont: 2766 if (line_status & LSR_TXRDY 2767 && com->state >= (CS_BUSY | CS_TTGO | CS_ODEVREADY)) 2768 goto txrdy; 2769 2770 /* 2771 * "& 0x7F" is to avoid the gcc-1.40 generating a slow 2772 * jump from the top of the loop to here 2773 */ 2774#ifdef PC98 2775 if (IS_8251(com->pc98_if_type)) 2776 goto status_read; 2777 else 2778#endif 2779 line_status = inb(com->line_status_port) & 0x7F; 2780#ifdef PC98 2781 if (com->pc98_if_type == COM_IF_RSA98III) 2782 rsa_buf_status = inb(com->rsabase + rsa_srr); 2783#endif /* PC98 */ 2784 } 2785 2786 /* modem status change? (always check before doing output) */ 2787#ifdef PC98 2788 if (!IS_8251(com->pc98_if_type)) { 2789#endif 2790 modem_status = inb(com->modem_status_port); 2791 if (modem_status != com->last_modem_status) { 2792 /* 2793 * Schedule high level to handle DCD changes. Note 2794 * that we don't use the delta bits anywhere. Some 2795 * UARTs mess them up, and it's easy to remember the 2796 * previous bits and calculate the delta. 2797 */ 2798 com->last_modem_status = modem_status; 2799 if (!(com->state & CS_CHECKMSR)) { 2800 com_events += LOTS_OF_EVENTS; 2801 com->state |= CS_CHECKMSR; 2802 swi_sched(sio_fast_ih, 0); 2803 } 2804 2805 /* handle CTS change immediately for crisp flow ctl */ 2806 if (com->state & CS_CTS_OFLOW) { 2807 if (modem_status & MSR_CTS) 2808 com->state |= CS_ODEVREADY; 2809 else 2810 com->state &= ~CS_ODEVREADY; 2811 } 2812 } 2813#ifdef PC98 2814 } 2815#endif 2816 2817txrdy: 2818 /* output queued and everything ready? */ 2819#ifndef PC98 2820 if (line_status & LSR_TXRDY 2821 && com->state >= (CS_BUSY | CS_TTGO | CS_ODEVREADY)) { 2822#else 2823 if (((com->pc98_if_type == COM_IF_RSA98III) 2824 ? (rsa_buf_status & 0x02) 2825 : (line_status & LSR_TXRDY)) 2826 && com->state >= (CS_BUSY | CS_TTGO | CS_ODEVREADY)) { 2827#endif 2828#ifdef PC98 2829 Port_t tmp_data_port; 2830 2831 if (IS_8251(com->pc98_if_type) && 2832 com->pc98_8251fifo_enable) 2833 tmp_data_port = I8251F_data; 2834 else 2835 tmp_data_port = com->data_port; 2836#endif 2837 2838 ioptr = com->obufq.l_head; 2839 if (com->tx_fifo_size > 1 && com->unit != siotsunit) { 2840 u_int ocount; 2841 2842 ocount = com->obufq.l_tail - ioptr; 2843#ifdef PC98 2844 if (com->pc98_if_type == COM_IF_RSA98III) { 2845 rsa_buf_status = inb(com->rsabase + rsa_srr); 2846 rsa_tx_fifo_size = 1024; 2847 if (!(rsa_buf_status & 0x01)) 2848 rsa_tx_fifo_size = 2048; 2849 if (ocount > rsa_tx_fifo_size) 2850 ocount = rsa_tx_fifo_size; 2851 } else 2852#endif 2853 if (ocount > com->tx_fifo_size) 2854 ocount = com->tx_fifo_size; 2855 com->bytes_out += ocount; 2856 do 2857#ifdef PC98 2858 outb(tmp_data_port, *ioptr++); 2859#else 2860 outb(com->data_port, *ioptr++); 2861#endif 2862 while (--ocount != 0); 2863 } else { 2864#ifdef PC98 2865 outb(tmp_data_port, *ioptr++); 2866#else 2867 outb(com->data_port, *ioptr++); 2868#endif 2869 ++com->bytes_out; 2870 if (com->unit == siotsunit 2871 && siotso < sizeof siots / sizeof siots[0]) 2872 nanouptime(&siots[siotso++]); 2873 } 2874#ifdef PC98 2875 if (IS_8251(com->pc98_if_type)) 2876 if (!(pc98_check_i8251_interrupt(com) & IEN_TxFLAG)) 2877 com_int_Tx_enable(com); 2878#endif 2879 com->obufq.l_head = ioptr; 2880 if (COM_IIR_TXRDYBUG(com->flags)) 2881 int_ctl_new = int_ctl | IER_ETXRDY; 2882 if (ioptr >= com->obufq.l_tail) { 2883 struct lbq *qp; 2884 2885 qp = com->obufq.l_next; 2886 qp->l_queued = FALSE; 2887 qp = qp->l_next; 2888 if (qp != NULL) { 2889 com->obufq.l_head = qp->l_head; 2890 com->obufq.l_tail = qp->l_tail; 2891 com->obufq.l_next = qp; 2892 } else { 2893 /* output just completed */ 2894 if (COM_IIR_TXRDYBUG(com->flags)) 2895 int_ctl_new = int_ctl 2896 & ~IER_ETXRDY; 2897 com->state &= ~CS_BUSY; 2898#if defined(PC98) 2899 if (IS_8251(com->pc98_if_type) && 2900 pc98_check_i8251_interrupt(com) & IEN_TxFLAG) 2901 com_int_Tx_disable(com); 2902#endif 2903 } 2904 if (!(com->state & CS_ODONE)) { 2905 com_events += LOTS_OF_EVENTS; 2906 com->state |= CS_ODONE; 2907 /* handle at high level ASAP */ 2908 swi_sched(sio_fast_ih, 0); 2909 } 2910 } 2911#ifdef PC98 2912 if (COM_IIR_TXRDYBUG(com->flags) 2913 && int_ctl != int_ctl_new) { 2914 if (com->pc98_if_type == COM_IF_RSA98III) { 2915 int_ctl_new &= ~(IER_ETXRDY | IER_ERXRDY); 2916 outb(com->int_ctl_port, int_ctl_new); 2917 outb(com->rsabase + rsa_ier, 0x1d); 2918 } else 2919 outb(com->int_ctl_port, int_ctl_new); 2920 } 2921#else 2922 if (COM_IIR_TXRDYBUG(com->flags) 2923 && int_ctl != int_ctl_new) 2924 outb(com->int_ctl_port, int_ctl_new); 2925#endif 2926 } 2927#ifdef PC98 2928 else if (line_status & LSR_TXRDY) { 2929 if (IS_8251(com->pc98_if_type)) 2930 if (pc98_check_i8251_interrupt(com) & IEN_TxFLAG) 2931 com_int_Tx_disable(com); 2932 } 2933 if (IS_8251(com->pc98_if_type)) { 2934 if (com->pc98_8251fifo_enable) { 2935 if ((tmp = inb(I8251F_lsr)) & STS8251F_RxRDY) 2936 goto more_intr; 2937 } else { 2938 if ((tmp = inb(com->sts_port)) & STS8251_RxRDY) 2939 goto more_intr; 2940 } 2941 } 2942#endif 2943 2944 /* finished? */ 2945#ifndef COM_MULTIPORT 2946#ifdef PC98 2947 if (IS_8251(com->pc98_if_type)) 2948 return; 2949#endif 2950 if ((inb(com->int_id_port) & IIR_IMASK) == IIR_NOPEND) 2951#endif /* COM_MULTIPORT */ 2952 return; 2953 } 2954} 2955 2956static int 2957siocioctl(dev, cmd, data, flag, td) 2958 struct cdev *dev; 2959 u_long cmd; 2960 caddr_t data; 2961 int flag; 2962 struct thread *td; 2963{ 2964 struct com_s *com; 2965 struct tty *tp; 2966 int error; 2967 int mynor; 2968 struct termios *ct; 2969 2970 mynor = minor(dev); 2971 com = dev->si_drv1; 2972 if (com == NULL || com->gone) 2973 return (ENODEV); 2974 tp = com->tp; 2975 2976 switch (mynor & CONTROL_MASK) { 2977 case CONTROL_INIT_STATE: 2978 ct = mynor & CALLOUT_MASK ? &tp->t_init_out : &tp->t_init_in; 2979 break; 2980 case CONTROL_LOCK_STATE: 2981 ct = mynor & CALLOUT_MASK ? &tp->t_lock_out : &tp->t_lock_in; 2982 break; 2983 default: 2984 return (ENODEV); /* /dev/nodev */ 2985 } 2986 switch (cmd) { 2987 case TIOCSETA: 2988 error = suser(td); 2989 if (error != 0) 2990 return (error); 2991 *ct = *(struct termios *)data; 2992 return (0); 2993 case TIOCGETA: 2994 *(struct termios *)data = *ct; 2995 return (0); 2996 case TIOCGETD: 2997 *(int *)data = TTYDISC; 2998 return (0); 2999 case TIOCGWINSZ: 3000 bzero(data, sizeof(struct winsize)); 3001 return (0); 3002 default: 3003 return (ENOTTY); 3004 } 3005} 3006 3007static int 3008sioioctl(dev, cmd, data, flag, td) 3009 struct cdev *dev; 3010 u_long cmd; 3011 caddr_t data; 3012 int flag; 3013 struct thread *td; 3014{ 3015 struct com_s *com; 3016 int error; 3017 int mynor; 3018 int s; 3019 struct tty *tp; 3020#ifndef BURN_BRIDGES 3021#if defined(COMPAT_43) 3022 u_long oldcmd; 3023 struct termios term; 3024#endif 3025#endif 3026 3027 mynor = minor(dev); 3028 com = dev->si_drv1; 3029 if (com == NULL || com->gone) 3030 return (ENODEV); 3031 tp = com->tp; 3032#ifndef BURN_BRIDGES 3033#if defined(COMPAT_43) 3034 term = tp->t_termios; 3035 oldcmd = cmd; 3036 error = ttsetcompat(tp, &cmd, data, &term); 3037 if (error != 0) 3038 return (error); 3039 if (cmd != oldcmd) 3040 data = (caddr_t)&term; 3041#endif 3042#endif 3043 if (cmd == TIOCSETA || cmd == TIOCSETAW || cmd == TIOCSETAF) { 3044 int cc; 3045 struct termios *dt = (struct termios *)data; 3046 struct termios *lt = mynor & CALLOUT_MASK 3047 ? &tp->t_lock_out : &tp->t_lock_in; 3048 3049 dt->c_iflag = (tp->t_iflag & lt->c_iflag) 3050 | (dt->c_iflag & ~lt->c_iflag); 3051 dt->c_oflag = (tp->t_oflag & lt->c_oflag) 3052 | (dt->c_oflag & ~lt->c_oflag); 3053 dt->c_cflag = (tp->t_cflag & lt->c_cflag) 3054 | (dt->c_cflag & ~lt->c_cflag); 3055 dt->c_lflag = (tp->t_lflag & lt->c_lflag) 3056 | (dt->c_lflag & ~lt->c_lflag); 3057 for (cc = 0; cc < NCCS; ++cc) 3058 if (lt->c_cc[cc] != 0) 3059 dt->c_cc[cc] = tp->t_cc[cc]; 3060 if (lt->c_ispeed != 0) 3061 dt->c_ispeed = tp->t_ispeed; 3062 if (lt->c_ospeed != 0) 3063 dt->c_ospeed = tp->t_ospeed; 3064 } 3065 error = ttyioctl(dev, cmd, data, flag, td); 3066 ttyldoptim(tp); 3067 if (error != ENOTTY) 3068 return (error); 3069 s = spltty(); 3070 switch (cmd) { 3071 case TIOCTIMESTAMP: 3072 com->do_timestamp = TRUE; 3073 *(struct timeval *)data = com->timestamp; 3074 break; 3075 default: 3076 splx(s); 3077 error = pps_ioctl(cmd, data, &com->pps); 3078 if (error == ENODEV) 3079 error = ENOTTY; 3080 return (error); 3081 } 3082 splx(s); 3083 return (0); 3084} 3085 3086/* software interrupt handler for SWI_TTY */ 3087static void 3088siopoll(void *dummy) 3089{ 3090 int unit; 3091 3092 if (com_events == 0) 3093 return; 3094repeat: 3095 for (unit = 0; unit < sio_numunits; ++unit) { 3096 struct com_s *com; 3097 int incc; 3098 struct tty *tp; 3099 3100 com = com_addr(unit); 3101 if (com == NULL) 3102 continue; 3103 tp = com->tp; 3104 if (tp == NULL || com->gone) { 3105 /* 3106 * Discard any events related to never-opened or 3107 * going-away devices. 3108 */ 3109 mtx_lock_spin(&sio_lock); 3110 incc = com->iptr - com->ibuf; 3111 com->iptr = com->ibuf; 3112 if (com->state & CS_CHECKMSR) { 3113 incc += LOTS_OF_EVENTS; 3114 com->state &= ~CS_CHECKMSR; 3115 } 3116 com_events -= incc; 3117 mtx_unlock_spin(&sio_lock); 3118 continue; 3119 } 3120 if (com->iptr != com->ibuf) { 3121 mtx_lock_spin(&sio_lock); 3122 sioinput(com); 3123 mtx_unlock_spin(&sio_lock); 3124 } 3125 if (com->state & CS_CHECKMSR) { 3126 u_char delta_modem_status; 3127 3128#ifdef PC98 3129 if (!IS_8251(com->pc98_if_type)) { 3130#endif 3131 mtx_lock_spin(&sio_lock); 3132 delta_modem_status = com->last_modem_status 3133 ^ com->prev_modem_status; 3134 com->prev_modem_status = com->last_modem_status; 3135 com_events -= LOTS_OF_EVENTS; 3136 com->state &= ~CS_CHECKMSR; 3137 mtx_unlock_spin(&sio_lock); 3138 if (delta_modem_status & MSR_DCD) 3139 ttyld_modem(tp, 3140 com->prev_modem_status & MSR_DCD); 3141#ifdef PC98 3142 } 3143#endif 3144 } 3145 if (com->state & CS_ODONE) { 3146 mtx_lock_spin(&sio_lock); 3147 com_events -= LOTS_OF_EVENTS; 3148 com->state &= ~CS_ODONE; 3149 mtx_unlock_spin(&sio_lock); 3150 if (!(com->state & CS_BUSY) 3151 && !(com->extra_state & CSE_BUSYCHECK)) { 3152 timeout(siobusycheck, com, hz / 100); 3153 com->extra_state |= CSE_BUSYCHECK; 3154 } 3155 ttyld_start(tp); 3156 } 3157 if (com_events == 0) 3158 break; 3159 } 3160 if (com_events >= LOTS_OF_EVENTS) 3161 goto repeat; 3162} 3163 3164static void 3165combreak(tp, sig) 3166 struct tty *tp; 3167 int sig; 3168{ 3169 struct com_s *com; 3170 3171 com = tp->t_sc; 3172 3173#ifdef PC98 3174 if (sig) 3175 com_send_break_on(com); 3176 else 3177 com_send_break_off(com); 3178#else 3179 if (sig) 3180 sio_setreg(com, com_cfcr, com->cfcr_image |= CFCR_SBREAK); 3181 else 3182 sio_setreg(com, com_cfcr, com->cfcr_image &= ~CFCR_SBREAK); 3183#endif 3184} 3185 3186static int 3187comparam(tp, t) 3188 struct tty *tp; 3189 struct termios *t; 3190{ 3191 u_int cfcr; 3192 int cflag; 3193 struct com_s *com; 3194 u_int divisor; 3195 u_char dlbh; 3196 u_char dlbl; 3197 u_char efr_flowbits; 3198 int s; 3199#ifdef PC98 3200 u_char param = 0; 3201#endif 3202 3203 com = tp->t_sc; 3204 if (com == NULL) 3205 return (ENODEV); 3206 3207#ifdef PC98 3208 cfcr = 0; 3209 3210 if (IS_8251(com->pc98_if_type)) { 3211 if (pc98_ttspeedtab(com, t->c_ospeed, &divisor) != 0) 3212 return (EINVAL); 3213 } else { 3214#endif 3215 /* check requested parameters */ 3216 if (t->c_ispeed != (t->c_ospeed != 0 ? t->c_ospeed : tp->t_ospeed)) 3217 return (EINVAL); 3218 divisor = siodivisor(com->rclk, t->c_ispeed); 3219 if (divisor == 0) 3220 return (EINVAL); 3221#ifdef PC98 3222 } 3223#endif 3224 3225 /* parameters are OK, convert them to the com struct and the device */ 3226 s = spltty(); 3227#ifdef PC98 3228 if (IS_8251(com->pc98_if_type)) { 3229 if (t->c_ospeed == 0) 3230 com_tiocm_bic(com, TIOCM_DTR|TIOCM_RTS|TIOCM_LE); 3231 else 3232 com_tiocm_bis(com, TIOCM_DTR|TIOCM_RTS|TIOCM_LE); 3233 } else 3234#endif 3235 if (t->c_ospeed == 0) 3236 (void)commodem(tp, 0, SER_DTR); /* hang up line */ 3237 else 3238 (void)commodem(tp, SER_DTR, 0); 3239 cflag = t->c_cflag; 3240#ifdef PC98 3241 if (!IS_8251(com->pc98_if_type)) { 3242#endif 3243 switch (cflag & CSIZE) { 3244 case CS5: 3245 cfcr = CFCR_5BITS; 3246 break; 3247 case CS6: 3248 cfcr = CFCR_6BITS; 3249 break; 3250 case CS7: 3251 cfcr = CFCR_7BITS; 3252 break; 3253 default: 3254 cfcr = CFCR_8BITS; 3255 break; 3256 } 3257 if (cflag & PARENB) { 3258 cfcr |= CFCR_PENAB; 3259 if (!(cflag & PARODD)) 3260 cfcr |= CFCR_PEVEN; 3261 } 3262 if (cflag & CSTOPB) 3263 cfcr |= CFCR_STOPB; 3264 3265 if (com->hasfifo) { 3266 /* 3267 * Use a fifo trigger level low enough so that the input 3268 * latency from the fifo is less than about 16 msec and 3269 * the total latency is less than about 30 msec. These 3270 * latencies are reasonable for humans. Serial comms 3271 * protocols shouldn't expect anything better since modem 3272 * latencies are larger. 3273 * 3274 * The fifo trigger level cannot be set at RX_HIGH for high 3275 * speed connections without further work on reducing 3276 * interrupt disablement times in other parts of the system, 3277 * without producing silo overflow errors. 3278 */ 3279 com->fifo_image = com->unit == siotsunit ? 0 3280 : t->c_ispeed <= 4800 3281 ? FIFO_ENABLE : FIFO_ENABLE | FIFO_RX_MEDH; 3282#ifdef COM_ESP 3283 /* 3284 * The Hayes ESP card needs the fifo DMA mode bit set 3285 * in compatibility mode. If not, it will interrupt 3286 * for each character received. 3287 */ 3288 if (com->esp) 3289 com->fifo_image |= FIFO_DMA_MODE; 3290#endif 3291 sio_setreg(com, com_fifo, com->fifo_image); 3292 } 3293#ifdef PC98 3294 } 3295#endif 3296 3297 /* 3298 * This returns with interrupts disabled so that we can complete 3299 * the speed change atomically. Keeping interrupts disabled is 3300 * especially important while com_data is hidden. 3301 */ 3302 (void) siosetwater(com, t->c_ispeed); 3303 3304#ifdef PC98 3305 if (IS_8251(com->pc98_if_type)) 3306 com_cflag_and_speed_set(com, cflag, t->c_ospeed); 3307 else { 3308#endif 3309 sio_setreg(com, com_cfcr, cfcr | CFCR_DLAB); 3310 /* 3311 * Only set the divisor registers if they would change, since on 3312 * some 16550 incompatibles (UMC8669F), setting them while input 3313 * is arriving loses sync until data stops arriving. 3314 */ 3315 dlbl = divisor & 0xFF; 3316 if (sio_getreg(com, com_dlbl) != dlbl) 3317 sio_setreg(com, com_dlbl, dlbl); 3318 dlbh = divisor >> 8; 3319 if (sio_getreg(com, com_dlbh) != dlbh) 3320 sio_setreg(com, com_dlbh, dlbh); 3321#ifdef PC98 3322 } 3323#endif 3324 3325 efr_flowbits = 0; 3326 3327 if (cflag & CRTS_IFLOW) { 3328 com->state |= CS_RTS_IFLOW; 3329 efr_flowbits |= EFR_AUTORTS; 3330 /* 3331 * If CS_RTS_IFLOW just changed from off to on, the change 3332 * needs to be propagated to MCR_RTS. This isn't urgent, 3333 * so do it later by calling comstart() instead of repeating 3334 * a lot of code from comstart() here. 3335 */ 3336 } else if (com->state & CS_RTS_IFLOW) { 3337 com->state &= ~CS_RTS_IFLOW; 3338 /* 3339 * CS_RTS_IFLOW just changed from on to off. Force MCR_RTS 3340 * on here, since comstart() won't do it later. 3341 */ 3342#ifdef PC98 3343 if (IS_8251(com->pc98_if_type)) 3344 com_tiocm_bis(com, TIOCM_RTS); 3345 else 3346 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS); 3347#else 3348 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS); 3349#endif 3350 } 3351 3352 /* 3353 * Set up state to handle output flow control. 3354 * XXX - worth handling MDMBUF (DCD) flow control at the lowest level? 3355 * Now has 10+ msec latency, while CTS flow has 50- usec latency. 3356 */ 3357 com->state |= CS_ODEVREADY; 3358 com->state &= ~CS_CTS_OFLOW; 3359#ifdef PC98 3360 if (com->pc98_if_type == COM_IF_RSA98III) { 3361 param = inb(com->rsabase + rsa_msr); 3362 outb(com->rsabase + rsa_msr, param & 0x14); 3363 } 3364#endif 3365 if (cflag & CCTS_OFLOW) { 3366 com->state |= CS_CTS_OFLOW; 3367 efr_flowbits |= EFR_AUTOCTS; 3368#ifdef PC98 3369 if (IS_8251(com->pc98_if_type)) { 3370 if (!(pc98_get_modem_status(com) & TIOCM_CTS)) 3371 com->state &= ~CS_ODEVREADY; 3372 } else if (com->pc98_if_type == COM_IF_RSA98III) { 3373 /* Set automatic flow control mode */ 3374 outb(com->rsabase + rsa_msr, param | 0x08); 3375 } else 3376#endif 3377 if (!(com->last_modem_status & MSR_CTS)) 3378 com->state &= ~CS_ODEVREADY; 3379 } 3380 3381#ifdef PC98 3382 if (!IS_8251(com->pc98_if_type)) 3383 sio_setreg(com, com_cfcr, com->cfcr_image = cfcr); 3384#else 3385 if (com->st16650a) { 3386 sio_setreg(com, com_lcr, LCR_EFR_ENABLE); 3387 sio_setreg(com, com_efr, 3388 (sio_getreg(com, com_efr) 3389 & ~(EFR_AUTOCTS | EFR_AUTORTS)) | efr_flowbits); 3390 } 3391 sio_setreg(com, com_cfcr, com->cfcr_image = cfcr); 3392#endif 3393 3394 /* XXX shouldn't call functions while intrs are disabled. */ 3395 ttyldoptim(tp); 3396 3397 mtx_unlock_spin(&sio_lock); 3398 splx(s); 3399 comstart(tp); 3400 if (com->ibufold != NULL) { 3401 free(com->ibufold, M_DEVBUF); 3402 com->ibufold = NULL; 3403 } 3404 return (0); 3405} 3406 3407/* 3408 * This function must be called with the sio_lock mutex released and will 3409 * return with it obtained. 3410 */ 3411static int 3412siosetwater(com, speed) 3413 struct com_s *com; 3414 speed_t speed; 3415{ 3416 int cp4ticks; 3417 u_char *ibuf; 3418 int ibufsize; 3419 struct tty *tp; 3420 3421 /* 3422 * Make the buffer size large enough to handle a softtty interrupt 3423 * latency of about 2 ticks without loss of throughput or data 3424 * (about 3 ticks if input flow control is not used or not honoured, 3425 * but a bit less for CS5-CS7 modes). 3426 */ 3427 cp4ticks = speed / 10 / hz * 4; 3428 for (ibufsize = 128; ibufsize < cp4ticks;) 3429 ibufsize <<= 1; 3430#ifdef PC98 3431 if (com->pc98_if_type == COM_IF_RSA98III) 3432 ibufsize = 2048; 3433#endif 3434 if (ibufsize == com->ibufsize) { 3435 mtx_lock_spin(&sio_lock); 3436 return (0); 3437 } 3438 3439 /* 3440 * Allocate input buffer. The extra factor of 2 in the size is 3441 * to allow for an error byte for each input byte. 3442 */ 3443 ibuf = malloc(2 * ibufsize, M_DEVBUF, M_NOWAIT); 3444 if (ibuf == NULL) { 3445 mtx_lock_spin(&sio_lock); 3446 return (ENOMEM); 3447 } 3448 3449 /* Initialize non-critical variables. */ 3450 com->ibufold = com->ibuf; 3451 com->ibufsize = ibufsize; 3452 tp = com->tp; 3453 if (tp != NULL) { 3454 tp->t_ififosize = 2 * ibufsize; 3455 tp->t_ispeedwat = (speed_t)-1; 3456 tp->t_ospeedwat = (speed_t)-1; 3457 } 3458 3459 /* 3460 * Read current input buffer, if any. Continue with interrupts 3461 * disabled. 3462 */ 3463 mtx_lock_spin(&sio_lock); 3464 if (com->iptr != com->ibuf) 3465 sioinput(com); 3466 3467 /*- 3468 * Initialize critical variables, including input buffer watermarks. 3469 * The external device is asked to stop sending when the buffer 3470 * exactly reaches high water, or when the high level requests it. 3471 * The high level is notified immediately (rather than at a later 3472 * clock tick) when this watermark is reached. 3473 * The buffer size is chosen so the watermark should almost never 3474 * be reached. 3475 * The low watermark is invisibly 0 since the buffer is always 3476 * emptied all at once. 3477 */ 3478 com->iptr = com->ibuf = ibuf; 3479 com->ibufend = ibuf + ibufsize; 3480 com->ierroff = ibufsize; 3481 com->ihighwater = ibuf + 3 * ibufsize / 4; 3482 return (0); 3483} 3484 3485static void 3486comstart(tp) 3487 struct tty *tp; 3488{ 3489 struct com_s *com; 3490 int s; 3491 3492 com = tp->t_sc; 3493 if (com == NULL) 3494 return; 3495 s = spltty(); 3496 mtx_lock_spin(&sio_lock); 3497 if (tp->t_state & TS_TTSTOP) 3498 com->state &= ~CS_TTGO; 3499 else 3500 com->state |= CS_TTGO; 3501 if (tp->t_state & TS_TBLOCK) { 3502#ifdef PC98 3503 if (IS_8251(com->pc98_if_type)) { 3504 if ((com_tiocm_get(com) & TIOCM_RTS) && 3505 (com->state & CS_RTS_IFLOW)) 3506 com_tiocm_bic(com, TIOCM_RTS); 3507 } else { 3508 if ((com->mcr_image & MCR_RTS) && 3509 (com->state & CS_RTS_IFLOW)) 3510 outb(com->modem_ctl_port, com->mcr_image &= ~MCR_RTS); 3511 } 3512#else 3513 if (com->mcr_image & MCR_RTS && com->state & CS_RTS_IFLOW) 3514 outb(com->modem_ctl_port, com->mcr_image &= ~MCR_RTS); 3515#endif 3516 } else { 3517#ifdef PC98 3518 if (IS_8251(com->pc98_if_type)) { 3519 if (!(com_tiocm_get(com) & TIOCM_RTS) && 3520 com->iptr < com->ihighwater && 3521 com->state & CS_RTS_IFLOW) 3522 com_tiocm_bis(com, TIOCM_RTS); 3523 } else { 3524 if (!(com->mcr_image & MCR_RTS) && 3525 com->iptr < com->ihighwater && 3526 com->state & CS_RTS_IFLOW) 3527 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS); 3528 } 3529#else 3530 if (!(com->mcr_image & MCR_RTS) && com->iptr < com->ihighwater 3531 && com->state & CS_RTS_IFLOW) 3532 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS); 3533#endif 3534 } 3535 mtx_unlock_spin(&sio_lock); 3536 if (tp->t_state & (TS_TIMEOUT | TS_TTSTOP)) { 3537 ttwwakeup(tp); 3538 splx(s); 3539 return; 3540 } 3541 if (tp->t_outq.c_cc != 0) { 3542 struct lbq *qp; 3543 struct lbq *next; 3544 3545 if (!com->obufs[0].l_queued) { 3546 com->obufs[0].l_tail 3547 = com->obuf1 + q_to_b(&tp->t_outq, com->obuf1, 3548#ifdef PC98 3549 com->obufsize); 3550#else 3551 sizeof com->obuf1); 3552#endif 3553 com->obufs[0].l_next = NULL; 3554 com->obufs[0].l_queued = TRUE; 3555 mtx_lock_spin(&sio_lock); 3556 if (com->state & CS_BUSY) { 3557 qp = com->obufq.l_next; 3558 while ((next = qp->l_next) != NULL) 3559 qp = next; 3560 qp->l_next = &com->obufs[0]; 3561 } else { 3562 com->obufq.l_head = com->obufs[0].l_head; 3563 com->obufq.l_tail = com->obufs[0].l_tail; 3564 com->obufq.l_next = &com->obufs[0]; 3565 com->state |= CS_BUSY; 3566 } 3567 mtx_unlock_spin(&sio_lock); 3568 } 3569 if (tp->t_outq.c_cc != 0 && !com->obufs[1].l_queued) { 3570 com->obufs[1].l_tail 3571 = com->obuf2 + q_to_b(&tp->t_outq, com->obuf2, 3572#ifdef PC98 3573 com->obufsize); 3574#else 3575 sizeof com->obuf2); 3576#endif 3577 com->obufs[1].l_next = NULL; 3578 com->obufs[1].l_queued = TRUE; 3579 mtx_lock_spin(&sio_lock); 3580 if (com->state & CS_BUSY) { 3581 qp = com->obufq.l_next; 3582 while ((next = qp->l_next) != NULL) 3583 qp = next; 3584 qp->l_next = &com->obufs[1]; 3585 } else { 3586 com->obufq.l_head = com->obufs[1].l_head; 3587 com->obufq.l_tail = com->obufs[1].l_tail; 3588 com->obufq.l_next = &com->obufs[1]; 3589 com->state |= CS_BUSY; 3590 } 3591 mtx_unlock_spin(&sio_lock); 3592 } 3593 tp->t_state |= TS_BUSY; 3594 } 3595 mtx_lock_spin(&sio_lock); 3596 if (com->state >= (CS_BUSY | CS_TTGO)) 3597 siointr1(com); /* fake interrupt to start output */ 3598 mtx_unlock_spin(&sio_lock); 3599 ttwwakeup(tp); 3600 splx(s); 3601} 3602 3603static void 3604comstop(tp, rw) 3605 struct tty *tp; 3606 int rw; 3607{ 3608 struct com_s *com; 3609#ifdef PC98 3610 int rsa98_tmp = 0; 3611#endif 3612 3613 com = tp->t_sc; 3614 if (com == NULL || com->gone) 3615 return; 3616 mtx_lock_spin(&sio_lock); 3617 if (rw & FWRITE) { 3618#ifdef PC98 3619 if (!IS_8251(com->pc98_if_type)) { 3620#endif 3621 if (com->hasfifo) 3622#ifdef COM_ESP 3623 /* XXX avoid h/w bug. */ 3624 if (!com->esp) 3625#endif 3626 sio_setreg(com, com_fifo, 3627 FIFO_XMT_RST | com->fifo_image); 3628#ifdef PC98 3629 if (com->pc98_if_type == COM_IF_RSA98III) 3630 for (rsa98_tmp = 0; rsa98_tmp < 2048; rsa98_tmp++) 3631 sio_setreg(com, com_fifo, 3632 FIFO_XMT_RST | com->fifo_image); 3633 } 3634#endif 3635 com->obufs[0].l_queued = FALSE; 3636 com->obufs[1].l_queued = FALSE; 3637 if (com->state & CS_ODONE) 3638 com_events -= LOTS_OF_EVENTS; 3639 com->state &= ~(CS_ODONE | CS_BUSY); 3640 com->tp->t_state &= ~TS_BUSY; 3641 } 3642 if (rw & FREAD) { 3643#ifdef PC98 3644 if (!IS_8251(com->pc98_if_type)) { 3645 if (com->pc98_if_type == COM_IF_RSA98III) 3646 for (rsa98_tmp = 0; rsa98_tmp < 2048; rsa98_tmp++) 3647 sio_getreg(com, com_data); 3648#endif 3649 if (com->hasfifo) 3650#ifdef COM_ESP 3651 /* XXX avoid h/w bug. */ 3652 if (!com->esp) 3653#endif 3654 sio_setreg(com, com_fifo, 3655 FIFO_RCV_RST | com->fifo_image); 3656#ifdef PC98 3657 } 3658#endif 3659 com_events -= (com->iptr - com->ibuf); 3660 com->iptr = com->ibuf; 3661 } 3662 mtx_unlock_spin(&sio_lock); 3663 comstart(tp); 3664} 3665 3666static int 3667commodem(tp, sigon, sigoff) 3668 struct tty *tp; 3669 int sigon, sigoff; 3670{ 3671 struct com_s *com; 3672 int bitand, bitor, msr; 3673#ifdef PC98 3674 int clr, set; 3675#endif 3676 3677 com = tp->t_sc; 3678 if (com->gone) 3679 return(0); 3680 if (sigon != 0 || sigoff != 0) { 3681#ifdef PC98 3682 if (IS_8251(com->pc98_if_type)) { 3683 bitand = bitor = 0; 3684 clr = set = 0; 3685 if (sigoff & SER_DTR) { 3686 bitand |= TIOCM_DTR; 3687 clr |= CMD8251_DTR; 3688 } 3689 if (sigoff & SER_RTS) { 3690 bitand |= TIOCM_RTS; 3691 clr |= CMD8251_RxEN | CMD8251_RTS; 3692 } 3693 if (sigon & SER_DTR) { 3694 bitor |= TIOCM_DTR; 3695 set |= CMD8251_TxEN | CMD8251_RxEN | 3696 CMD8251_DTR; 3697 } 3698 if (sigon & SER_RTS) { 3699 bitor |= TIOCM_RTS; 3700 set |= CMD8251_TxEN | CMD8251_RxEN | 3701 CMD8251_RTS; 3702 } 3703 bitand = ~bitand; 3704 mtx_lock_spin(&sio_lock); 3705 com->pc98_prev_modem_status &= bitand; 3706 com->pc98_prev_modem_status |= bitor; 3707 pc98_i8251_clear_or_cmd(com, clr, set); 3708 mtx_unlock_spin(&sio_lock); 3709 return (0); 3710 } else { 3711#endif 3712 bitand = bitor = 0; 3713 if (sigoff & SER_DTR) 3714 bitand |= MCR_DTR; 3715 if (sigoff & SER_RTS) 3716 bitand |= MCR_RTS; 3717 if (sigon & SER_DTR) 3718 bitor |= MCR_DTR; 3719 if (sigon & SER_RTS) 3720 bitor |= MCR_RTS; 3721 bitand = ~bitand; 3722 mtx_lock_spin(&sio_lock); 3723 com->mcr_image &= bitand; 3724 com->mcr_image |= bitor; 3725 outb(com->modem_ctl_port, com->mcr_image); 3726 mtx_unlock_spin(&sio_lock); 3727 return (0); 3728#ifdef PC98 3729 } 3730#endif 3731 } else { 3732#ifdef PC98 3733 if (IS_8251(com->pc98_if_type)) 3734 return (com_tiocm_get(com)); 3735 else { 3736#endif 3737 bitor = 0; 3738 if (com->mcr_image & MCR_DTR) 3739 bitor |= SER_DTR; 3740 if (com->mcr_image & MCR_RTS) 3741 bitor |= SER_RTS; 3742 msr = com->prev_modem_status; 3743 if (msr & MSR_CTS) 3744 bitor |= SER_CTS; 3745 if (msr & MSR_DCD) 3746 bitor |= SER_DCD; 3747 if (msr & MSR_DSR) 3748 bitor |= SER_DSR; 3749 if (msr & MSR_DSR) 3750 bitor |= SER_DSR; 3751 if (msr & (MSR_RI | MSR_TERI)) 3752 bitor |= SER_RI; 3753 return (bitor); 3754#ifdef PC98 3755 } 3756#endif 3757 } 3758} 3759 3760static void 3761siosettimeout() 3762{ 3763 struct com_s *com; 3764 bool_t someopen; 3765 int unit; 3766 3767 /* 3768 * Set our timeout period to 1 second if no polled devices are open. 3769 * Otherwise set it to max(1/200, 1/hz). 3770 * Enable timeouts iff some device is open. 3771 */ 3772 untimeout(comwakeup, (void *)NULL, sio_timeout_handle); 3773 sio_timeout = hz; 3774 someopen = FALSE; 3775 for (unit = 0; unit < sio_numunits; ++unit) { 3776 com = com_addr(unit); 3777 if (com != NULL && com->tp != NULL 3778 && com->tp->t_state & TS_ISOPEN && !com->gone) { 3779 someopen = TRUE; 3780 if (com->poll || com->poll_output) { 3781 sio_timeout = hz > 200 ? hz / 200 : 1; 3782 break; 3783 } 3784 } 3785 } 3786 if (someopen) { 3787 sio_timeouts_until_log = hz / sio_timeout; 3788 sio_timeout_handle = timeout(comwakeup, (void *)NULL, 3789 sio_timeout); 3790 } else { 3791 /* Flush error messages, if any. */ 3792 sio_timeouts_until_log = 1; 3793 comwakeup((void *)NULL); 3794 untimeout(comwakeup, (void *)NULL, sio_timeout_handle); 3795 } 3796} 3797 3798static void 3799comwakeup(chan) 3800 void *chan; 3801{ 3802 struct com_s *com; 3803 int unit; 3804 3805 sio_timeout_handle = timeout(comwakeup, (void *)NULL, sio_timeout); 3806 3807 /* 3808 * Recover from lost output interrupts. 3809 * Poll any lines that don't use interrupts. 3810 */ 3811 for (unit = 0; unit < sio_numunits; ++unit) { 3812 com = com_addr(unit); 3813 if (com != NULL && !com->gone 3814 && (com->state >= (CS_BUSY | CS_TTGO) || com->poll)) { 3815 mtx_lock_spin(&sio_lock); 3816 siointr1(com); 3817 mtx_unlock_spin(&sio_lock); 3818 } 3819 } 3820 3821 /* 3822 * Check for and log errors, but not too often. 3823 */ 3824 if (--sio_timeouts_until_log > 0) 3825 return; 3826 sio_timeouts_until_log = hz / sio_timeout; 3827 for (unit = 0; unit < sio_numunits; ++unit) { 3828 int errnum; 3829 3830 com = com_addr(unit); 3831 if (com == NULL) 3832 continue; 3833 if (com->gone) 3834 continue; 3835 for (errnum = 0; errnum < CE_NTYPES; ++errnum) { 3836 u_int delta; 3837 u_long total; 3838 3839 mtx_lock_spin(&sio_lock); 3840 delta = com->delta_error_counts[errnum]; 3841 com->delta_error_counts[errnum] = 0; 3842 mtx_unlock_spin(&sio_lock); 3843 if (delta == 0) 3844 continue; 3845 total = com->error_counts[errnum] += delta; 3846 log(LOG_ERR, "sio%d: %u more %s%s (total %lu)\n", 3847 unit, delta, error_desc[errnum], 3848 delta == 1 ? "" : "s", total); 3849 } 3850 } 3851} 3852 3853#ifdef PC98 3854/* commint is called when modem control line changes */ 3855static void 3856commint(struct cdev *dev) 3857{ 3858 register struct tty *tp; 3859 int stat,delta; 3860 struct com_s *com; 3861 int mynor; 3862 3863 mynor = minor(dev); 3864 com = dev->si_drv1; 3865 tp = com->tp; 3866 3867 stat = com_tiocm_get(com); 3868 delta = com_tiocm_get_delta(com); 3869 3870 if (com->state & CS_CTS_OFLOW) { 3871 if (stat & TIOCM_CTS) 3872 com->state |= CS_ODEVREADY; 3873 else 3874 com->state &= ~CS_ODEVREADY; 3875 } 3876 if ((delta & TIOCM_CAR) && (mynor & CALLOUT_MASK) == 0) { 3877 if (stat & TIOCM_CAR ) 3878 (void)ttyld_modem(tp, 1); 3879 else if (ttyld_modem(tp, 0) == 0) { 3880 /* negate DTR, RTS */ 3881 com_tiocm_bic(com, (tp->t_cflag & HUPCL) ? 3882 TIOCM_DTR|TIOCM_RTS|TIOCM_LE : TIOCM_LE ); 3883 /* disable IENABLE */ 3884 com_int_TxRx_disable( com ); 3885 } 3886 } 3887} 3888#endif 3889 3890/* 3891 * Following are all routines needed for SIO to act as console 3892 */ 3893struct siocnstate { 3894 u_char dlbl; 3895 u_char dlbh; 3896 u_char ier; 3897 u_char cfcr; 3898 u_char mcr; 3899}; 3900 3901/* 3902 * This is a function in order to not replicate "ttyd%d" more 3903 * places than absolutely necessary. 3904 */ 3905static void 3906siocnset(struct consdev *cd, int unit) 3907{ 3908 3909 cd->cn_unit = unit; 3910 sprintf(cd->cn_name, "ttyd%d", unit); 3911} 3912 3913static speed_t siocngetspeed(Port_t, u_long rclk); 3914static void siocnclose(struct siocnstate *sp, Port_t iobase); 3915static void siocnopen(struct siocnstate *sp, Port_t iobase, int speed); 3916static void siocntxwait(Port_t iobase); 3917 3918static cn_probe_t siocnprobe; 3919static cn_init_t siocninit; 3920static cn_term_t siocnterm; 3921static cn_checkc_t siocncheckc; 3922static cn_getc_t siocngetc; 3923static cn_putc_t siocnputc; 3924 3925CONS_DRIVER(sio, siocnprobe, siocninit, siocnterm, siocngetc, siocncheckc, 3926 siocnputc, NULL); 3927 3928static void 3929siocntxwait(iobase) 3930 Port_t iobase; 3931{ 3932 int timo; 3933 3934 /* 3935 * Wait for any pending transmission to finish. Required to avoid 3936 * the UART lockup bug when the speed is changed, and for normal 3937 * transmits. 3938 */ 3939 timo = 100000; 3940 while ((inb(iobase + com_lsr) & (LSR_TSRE | LSR_TXRDY)) 3941 != (LSR_TSRE | LSR_TXRDY) && --timo != 0) 3942 ; 3943} 3944 3945/* 3946 * Read the serial port specified and try to figure out what speed 3947 * it's currently running at. We're assuming the serial port has 3948 * been initialized and is basicly idle. This routine is only intended 3949 * to be run at system startup. 3950 * 3951 * If the value read from the serial port doesn't make sense, return 0. 3952 */ 3953 3954static speed_t 3955siocngetspeed(iobase, rclk) 3956 Port_t iobase; 3957 u_long rclk; 3958{ 3959 u_int divisor; 3960 u_char dlbh; 3961 u_char dlbl; 3962 u_char cfcr; 3963 3964 cfcr = inb(iobase + com_cfcr); 3965 outb(iobase + com_cfcr, CFCR_DLAB | cfcr); 3966 3967 dlbl = inb(iobase + com_dlbl); 3968 dlbh = inb(iobase + com_dlbh); 3969 3970 outb(iobase + com_cfcr, cfcr); 3971 3972 divisor = dlbh << 8 | dlbl; 3973 3974 /* XXX there should be more sanity checking. */ 3975 if (divisor == 0) 3976 return (CONSPEED); 3977 return (rclk / (16UL * divisor)); 3978} 3979 3980static void 3981siocnopen(sp, iobase, speed) 3982 struct siocnstate *sp; 3983 Port_t iobase; 3984 int speed; 3985{ 3986 u_int divisor; 3987 u_char dlbh; 3988 u_char dlbl; 3989 3990 /* 3991 * Save all the device control registers except the fifo register 3992 * and set our default ones (cs8 -parenb speed=comdefaultrate). 3993 * We can't save the fifo register since it is read-only. 3994 */ 3995 sp->ier = inb(iobase + com_ier); 3996 outb(iobase + com_ier, 0); /* spltty() doesn't stop siointr() */ 3997 siocntxwait(iobase); 3998 sp->cfcr = inb(iobase + com_cfcr); 3999 outb(iobase + com_cfcr, CFCR_DLAB | CFCR_8BITS); 4000 sp->dlbl = inb(iobase + com_dlbl); 4001 sp->dlbh = inb(iobase + com_dlbh); 4002 /* 4003 * Only set the divisor registers if they would change, since on 4004 * some 16550 incompatibles (Startech), setting them clears the 4005 * data input register. This also reduces the effects of the 4006 * UMC8669F bug. 4007 */ 4008 divisor = siodivisor(comdefaultrclk, speed); 4009 dlbl = divisor & 0xFF; 4010 if (sp->dlbl != dlbl) 4011 outb(iobase + com_dlbl, dlbl); 4012 dlbh = divisor >> 8; 4013 if (sp->dlbh != dlbh) 4014 outb(iobase + com_dlbh, dlbh); 4015 outb(iobase + com_cfcr, CFCR_8BITS); 4016 sp->mcr = inb(iobase + com_mcr); 4017 /* 4018 * We don't want interrupts, but must be careful not to "disable" 4019 * them by clearing the MCR_IENABLE bit, since that might cause 4020 * an interrupt by floating the IRQ line. 4021 */ 4022 outb(iobase + com_mcr, (sp->mcr & MCR_IENABLE) | MCR_DTR | MCR_RTS); 4023} 4024 4025static void 4026siocnclose(sp, iobase) 4027 struct siocnstate *sp; 4028 Port_t iobase; 4029{ 4030 /* 4031 * Restore the device control registers. 4032 */ 4033 siocntxwait(iobase); 4034 outb(iobase + com_cfcr, CFCR_DLAB | CFCR_8BITS); 4035 if (sp->dlbl != inb(iobase + com_dlbl)) 4036 outb(iobase + com_dlbl, sp->dlbl); 4037 if (sp->dlbh != inb(iobase + com_dlbh)) 4038 outb(iobase + com_dlbh, sp->dlbh); 4039 outb(iobase + com_cfcr, sp->cfcr); 4040 /* 4041 * XXX damp oscillations of MCR_DTR and MCR_RTS by not restoring them. 4042 */ 4043 outb(iobase + com_mcr, sp->mcr | MCR_DTR | MCR_RTS); 4044 outb(iobase + com_ier, sp->ier); 4045} 4046 4047static void 4048siocnprobe(cp) 4049 struct consdev *cp; 4050{ 4051 speed_t boot_speed; 4052 u_char cfcr; 4053 u_int divisor; 4054 int s, unit; 4055 struct siocnstate sp; 4056 4057 /* 4058 * Find our first enabled console, if any. If it is a high-level 4059 * console device, then initialize it and return successfully. 4060 * If it is a low-level console device, then initialize it and 4061 * return unsuccessfully. It must be initialized in both cases 4062 * for early use by console drivers and debuggers. Initializing 4063 * the hardware is not necessary in all cases, since the i/o 4064 * routines initialize it on the fly, but it is necessary if 4065 * input might arrive while the hardware is switched back to an 4066 * uninitialized state. We can't handle multiple console devices 4067 * yet because our low-level routines don't take a device arg. 4068 * We trust the user to set the console flags properly so that we 4069 * don't need to probe. 4070 */ 4071 cp->cn_pri = CN_DEAD; 4072 4073 for (unit = 0; unit < 16; unit++) { /* XXX need to know how many */ 4074 int flags; 4075 4076 if (resource_disabled("sio", unit)) 4077 continue; 4078 if (resource_int_value("sio", unit, "flags", &flags)) 4079 continue; 4080 if (COM_CONSOLE(flags) || COM_DEBUGGER(flags)) { 4081 int port; 4082 Port_t iobase; 4083 4084 if (resource_int_value("sio", unit, "port", &port)) 4085 continue; 4086 iobase = port; 4087 s = spltty(); 4088 if (boothowto & RB_SERIAL) { 4089 boot_speed = 4090 siocngetspeed(iobase, comdefaultrclk); 4091 if (boot_speed) 4092 comdefaultrate = boot_speed; 4093 } 4094 4095 /* 4096 * Initialize the divisor latch. We can't rely on 4097 * siocnopen() to do this the first time, since it 4098 * avoids writing to the latch if the latch appears 4099 * to have the correct value. Also, if we didn't 4100 * just read the speed from the hardware, then we 4101 * need to set the speed in hardware so that 4102 * switching it later is null. 4103 */ 4104 cfcr = inb(iobase + com_cfcr); 4105 outb(iobase + com_cfcr, CFCR_DLAB | cfcr); 4106 divisor = siodivisor(comdefaultrclk, comdefaultrate); 4107 outb(iobase + com_dlbl, divisor & 0xff); 4108 outb(iobase + com_dlbh, divisor >> 8); 4109 outb(iobase + com_cfcr, cfcr); 4110 4111 siocnopen(&sp, iobase, comdefaultrate); 4112 4113 splx(s); 4114 if (COM_CONSOLE(flags) && !COM_LLCONSOLE(flags)) { 4115 siocnset(cp, unit); 4116 cp->cn_pri = COM_FORCECONSOLE(flags) 4117 || boothowto & RB_SERIAL 4118 ? CN_REMOTE : CN_NORMAL; 4119 siocniobase = iobase; 4120 siocnunit = unit; 4121 } 4122#ifdef GDB 4123 if (COM_DEBUGGER(flags)) 4124 siogdbiobase = iobase; 4125#endif 4126 } 4127 } 4128} 4129 4130static void 4131siocninit(cp) 4132 struct consdev *cp; 4133{ 4134 comconsole = cp->cn_unit; 4135} 4136 4137static void 4138siocnterm(cp) 4139 struct consdev *cp; 4140{ 4141 comconsole = -1; 4142} 4143 4144static int 4145siocncheckc(struct consdev *cd) 4146{ 4147 int c; 4148 Port_t iobase; 4149 int s; 4150 struct siocnstate sp; 4151 speed_t speed; 4152 4153 if (cd != NULL && cd->cn_unit == siocnunit) { 4154 iobase = siocniobase; 4155 speed = comdefaultrate; 4156 } else { 4157#ifdef GDB 4158 iobase = siogdbiobase; 4159 speed = gdbdefaultrate; 4160#else 4161 return (-1); 4162#endif 4163 } 4164 s = spltty(); 4165 siocnopen(&sp, iobase, speed); 4166 if (inb(iobase + com_lsr) & LSR_RXRDY) 4167 c = inb(iobase + com_data); 4168 else 4169 c = -1; 4170 siocnclose(&sp, iobase); 4171 splx(s); 4172 return (c); 4173} 4174 4175static int 4176siocngetc(struct consdev *cd) 4177{ 4178 int c; 4179 Port_t iobase; 4180 int s; 4181 struct siocnstate sp; 4182 speed_t speed; 4183 4184 if (cd != NULL && cd->cn_unit == siocnunit) { 4185 iobase = siocniobase; 4186 speed = comdefaultrate; 4187 } else { 4188#ifdef GDB 4189 iobase = siogdbiobase; 4190 speed = gdbdefaultrate; 4191#else 4192 return (-1); 4193#endif 4194 } 4195 s = spltty(); 4196 siocnopen(&sp, iobase, speed); 4197 while (!(inb(iobase + com_lsr) & LSR_RXRDY)) 4198 ; 4199 c = inb(iobase + com_data); 4200 siocnclose(&sp, iobase); 4201 splx(s); 4202 return (c); 4203} 4204 4205static void 4206siocnputc(struct consdev *cd, int c) 4207{ 4208 int need_unlock; 4209 int s; 4210 struct siocnstate sp; 4211 Port_t iobase; 4212 speed_t speed; 4213 4214 if (cd != NULL && cd->cn_unit == siocnunit) { 4215 iobase = siocniobase; 4216 speed = comdefaultrate; 4217 } else { 4218#ifdef GDB 4219 iobase = siogdbiobase; 4220 speed = gdbdefaultrate; 4221#else 4222 return; 4223#endif 4224 } 4225 s = spltty(); 4226 need_unlock = 0; 4227 if (sio_inited == 2 && !mtx_owned(&sio_lock)) { 4228 mtx_lock_spin(&sio_lock); 4229 need_unlock = 1; 4230 } 4231 siocnopen(&sp, iobase, speed); 4232 siocntxwait(iobase); 4233 outb(iobase + com_data, c); 4234 siocnclose(&sp, iobase); 4235 if (need_unlock) 4236 mtx_unlock_spin(&sio_lock); 4237 splx(s); 4238} 4239 4240/* 4241 * Remote gdb(1) support. 4242 */ 4243 4244#if defined(GDB) 4245 4246#include <gdb/gdb.h> 4247 4248static gdb_probe_f siogdbprobe; 4249static gdb_init_f siogdbinit; 4250static gdb_term_f siogdbterm; 4251static gdb_getc_f siogdbgetc; 4252static gdb_checkc_f siogdbcheckc; 4253static gdb_putc_f siogdbputc; 4254 4255GDB_DBGPORT(sio, siogdbprobe, siogdbinit, siogdbterm, siogdbcheckc, 4256 siogdbgetc, siogdbputc); 4257 4258static int 4259siogdbprobe(void) 4260{ 4261 return ((siogdbiobase != 0) ? 0 : -1); 4262} 4263 4264static void 4265siogdbinit(void) 4266{ 4267} 4268 4269static void 4270siogdbterm(void) 4271{ 4272} 4273 4274static void 4275siogdbputc(int c) 4276{ 4277 siocnputc(NULL, c); 4278} 4279 4280static int 4281siogdbcheckc(void) 4282{ 4283 return (siocncheckc(NULL)); 4284} 4285 4286static int 4287siogdbgetc(void) 4288{ 4289 return (siocngetc(NULL)); 4290} 4291 4292#endif 4293 4294#ifdef PC98 4295/* 4296 * pc98 local function 4297 */ 4298static void 4299com_tiocm_bis(struct com_s *com, int msr) 4300{ 4301 int s; 4302 int tmp = 0; 4303 4304 s=spltty(); 4305 com->pc98_prev_modem_status |= ( msr & (TIOCM_LE|TIOCM_DTR|TIOCM_RTS) ); 4306 tmp |= CMD8251_TxEN|CMD8251_RxEN; 4307 if ( msr & TIOCM_DTR ) tmp |= CMD8251_DTR; 4308 if ( msr & TIOCM_RTS ) tmp |= CMD8251_RTS; 4309 4310 pc98_i8251_or_cmd( com, tmp ); 4311 splx(s); 4312} 4313 4314static void 4315com_tiocm_bic(struct com_s *com, int msr) 4316{ 4317 int s; 4318 int tmp = msr; 4319 4320 s=spltty(); 4321 com->pc98_prev_modem_status &= ~( msr & (TIOCM_LE|TIOCM_DTR|TIOCM_RTS) ); 4322 if ( msr & TIOCM_DTR ) tmp |= CMD8251_DTR; 4323 if ( msr & TIOCM_RTS ) tmp |= CMD8251_RTS; 4324 4325 pc98_i8251_clear_cmd( com, tmp ); 4326 splx(s); 4327} 4328 4329static int 4330com_tiocm_get(struct com_s *com) 4331{ 4332 return( com->pc98_prev_modem_status ); 4333} 4334 4335static int 4336com_tiocm_get_delta(struct com_s *com) 4337{ 4338 int tmp; 4339 4340 tmp = com->pc98_modem_delta; 4341 com->pc98_modem_delta = 0; 4342 return( tmp ); 4343} 4344 4345/* convert to TIOCM_?? ( ioctl.h ) */ 4346static int 4347pc98_get_modem_status(struct com_s *com) 4348{ 4349 register int msr; 4350 4351 msr = com->pc98_prev_modem_status 4352 & ~(TIOCM_CAR|TIOCM_RI|TIOCM_DSR|TIOCM_CTS); 4353 if (com->pc98_8251fifo_enable) { 4354 int stat2; 4355 4356 stat2 = inb(I8251F_msr); 4357 if ( stat2 & CICSCDF_CD ) msr |= TIOCM_CAR; 4358 if ( stat2 & CICSCDF_CI ) msr |= TIOCM_RI; 4359 if ( stat2 & CICSCDF_DR ) msr |= TIOCM_DSR; 4360 if ( stat2 & CICSCDF_CS ) msr |= TIOCM_CTS; 4361#if COM_CARRIER_DETECT_EMULATE 4362 if ( msr & (TIOCM_DSR|TIOCM_CTS) ) { 4363 msr |= TIOCM_CAR; 4364 } 4365#endif 4366 } else { 4367 int stat, stat2; 4368 4369 stat = inb(com->sts_port); 4370 stat2 = inb(com->in_modem_port); 4371 if ( !(stat2 & CICSCD_CD) ) msr |= TIOCM_CAR; 4372 if ( !(stat2 & CICSCD_CI) ) msr |= TIOCM_RI; 4373 if ( stat & STS8251_DSR ) msr |= TIOCM_DSR; 4374 if ( !(stat2 & CICSCD_CS) ) msr |= TIOCM_CTS; 4375#if COM_CARRIER_DETECT_EMULATE 4376 if ( msr & (TIOCM_DSR|TIOCM_CTS) ) { 4377 msr |= TIOCM_CAR; 4378 } 4379#endif 4380 } 4381 return(msr); 4382} 4383 4384static void 4385pc98_check_msr(void* chan) 4386{ 4387 int msr, delta; 4388 int s; 4389 register struct tty *tp; 4390 struct com_s *com; 4391 struct cdev *dev; 4392 4393 dev=(struct cdev *)chan; 4394 com = dev->si_drv1; 4395 tp = dev->si_tty; 4396 4397 s = spltty(); 4398 msr = pc98_get_modem_status(com); 4399 /* make change flag */ 4400 delta = msr ^ com->pc98_prev_modem_status; 4401 if ( delta & TIOCM_CAR ) { 4402 if ( com->modem_car_chg_timer ) { 4403 if ( -- com->modem_car_chg_timer ) 4404 msr ^= TIOCM_CAR; 4405 } else { 4406 if ((com->modem_car_chg_timer = (msr & TIOCM_CAR) ? 4407 DCD_ON_RECOGNITION : DCD_OFF_TOLERANCE) != 0) 4408 msr ^= TIOCM_CAR; 4409 } 4410 } else 4411 com->modem_car_chg_timer = 0; 4412 delta = ( msr ^ com->pc98_prev_modem_status ) & 4413 (TIOCM_CAR|TIOCM_RI|TIOCM_DSR|TIOCM_CTS); 4414 com->pc98_prev_modem_status = msr; 4415 delta = ( com->pc98_modem_delta |= delta ); 4416 splx(s); 4417 if ( com->modem_checking || (tp->t_state & (TS_ISOPEN)) ) { 4418 if ( delta ) { 4419 commint(dev); 4420 } 4421 timeout(pc98_check_msr, (caddr_t)dev, 4422 PC98_CHECK_MODEM_INTERVAL); 4423 } else { 4424 com->modem_checking = 0; 4425 } 4426} 4427 4428static void 4429pc98_msrint_start(struct cdev *dev) 4430{ 4431 struct com_s *com; 4432 int s = spltty(); 4433 4434 com = dev->si_drv1; 4435 /* modem control line check routine envoke interval is 1/10 sec */ 4436 if ( com->modem_checking == 0 ) { 4437 com->pc98_prev_modem_status = pc98_get_modem_status(com); 4438 com->pc98_modem_delta = 0; 4439 timeout(pc98_check_msr, (caddr_t)dev, 4440 PC98_CHECK_MODEM_INTERVAL); 4441 com->modem_checking = 1; 4442 } 4443 splx(s); 4444} 4445 4446static void 4447pc98_disable_i8251_interrupt(struct com_s *com, int mod) 4448{ 4449 /* disable interrupt */ 4450 register int tmp; 4451 4452 mod |= ~(IEN_Tx|IEN_TxEMP|IEN_Rx); 4453 COM_INT_DISABLE 4454 tmp = inb( com->intr_ctrl_port ) & ~(IEN_Tx|IEN_TxEMP|IEN_Rx); 4455 outb( com->intr_ctrl_port, (com->intr_enable&=~mod) | tmp ); 4456 COM_INT_ENABLE 4457} 4458 4459static void 4460pc98_enable_i8251_interrupt(struct com_s *com, int mod) 4461{ 4462 register int tmp; 4463 4464 COM_INT_DISABLE 4465 tmp = inb( com->intr_ctrl_port ) & ~(IEN_Tx|IEN_TxEMP|IEN_Rx); 4466 outb( com->intr_ctrl_port, (com->intr_enable|=mod) | tmp ); 4467 COM_INT_ENABLE 4468} 4469 4470static int 4471pc98_check_i8251_interrupt(struct com_s *com) 4472{ 4473 return ( com->intr_enable & 0x07 ); 4474} 4475 4476static void 4477pc98_i8251_clear_cmd(struct com_s *com, int x) 4478{ 4479 int tmp; 4480 4481 COM_INT_DISABLE 4482 tmp = com->pc98_prev_siocmd & ~(x); 4483 if (com->pc98_8251fifo_enable) 4484 outb(I8251F_fcr, 0); 4485 outb(com->cmd_port, tmp); 4486 com->pc98_prev_siocmd = tmp & ~(CMD8251_ER|CMD8251_RESET|CMD8251_EH); 4487 if (com->pc98_8251fifo_enable) 4488 outb(I8251F_fcr, CTRL8251F_ENABLE); 4489 COM_INT_ENABLE 4490} 4491 4492static void 4493pc98_i8251_or_cmd(struct com_s *com, int x) 4494{ 4495 int tmp; 4496 4497 COM_INT_DISABLE 4498 if (com->pc98_8251fifo_enable) 4499 outb(I8251F_fcr, 0); 4500 tmp = com->pc98_prev_siocmd | (x); 4501 outb(com->cmd_port, tmp); 4502 com->pc98_prev_siocmd = tmp & ~(CMD8251_ER|CMD8251_RESET|CMD8251_EH); 4503 if (com->pc98_8251fifo_enable) 4504 outb(I8251F_fcr, CTRL8251F_ENABLE); 4505 COM_INT_ENABLE 4506} 4507 4508static void 4509pc98_i8251_set_cmd(struct com_s *com, int x) 4510{ 4511 int tmp; 4512 4513 COM_INT_DISABLE 4514 if (com->pc98_8251fifo_enable) 4515 outb(I8251F_fcr, 0); 4516 tmp = (x); 4517 outb(com->cmd_port, tmp); 4518 com->pc98_prev_siocmd = tmp & ~(CMD8251_ER|CMD8251_RESET|CMD8251_EH); 4519 if (com->pc98_8251fifo_enable) 4520 outb(I8251F_fcr, CTRL8251F_ENABLE); 4521 COM_INT_ENABLE 4522} 4523 4524static void 4525pc98_i8251_clear_or_cmd(struct com_s *com, int clr, int x) 4526{ 4527 int tmp; 4528 COM_INT_DISABLE 4529 if (com->pc98_8251fifo_enable) 4530 outb(I8251F_fcr, 0); 4531 tmp = com->pc98_prev_siocmd & ~(clr); 4532 tmp |= (x); 4533 outb(com->cmd_port, tmp); 4534 com->pc98_prev_siocmd = tmp & ~(CMD8251_ER|CMD8251_RESET|CMD8251_EH); 4535 if (com->pc98_8251fifo_enable) 4536 outb(I8251F_fcr, CTRL8251F_ENABLE); 4537 COM_INT_ENABLE 4538} 4539 4540static int 4541pc98_i8251_get_cmd(struct com_s *com) 4542{ 4543 return com->pc98_prev_siocmd; 4544} 4545 4546static int 4547pc98_i8251_get_mod(struct com_s *com) 4548{ 4549 return com->pc98_prev_siomod; 4550} 4551 4552static void 4553pc98_i8251_reset(struct com_s *com, int mode, int command) 4554{ 4555 if (com->pc98_8251fifo_enable) 4556 outb(I8251F_fcr, 0); 4557 outb(com->cmd_port, 0); /* dummy */ 4558 DELAY(2); 4559 outb(com->cmd_port, 0); /* dummy */ 4560 DELAY(2); 4561 outb(com->cmd_port, 0); /* dummy */ 4562 DELAY(2); 4563 outb(com->cmd_port, CMD8251_RESET); /* internal reset */ 4564 DELAY(2); 4565 outb(com->cmd_port, mode ); /* mode register */ 4566 com->pc98_prev_siomod = mode; 4567 DELAY(2); 4568 pc98_i8251_set_cmd( com, (command|CMD8251_ER) ); 4569 DELAY(10); 4570 if (com->pc98_8251fifo_enable) 4571 outb(I8251F_fcr, CTRL8251F_ENABLE | 4572 CTRL8251F_XMT_RST | CTRL8251F_RCV_RST); 4573} 4574 4575static void 4576pc98_check_sysclock(void) 4577{ 4578 /* get system clock from port */ 4579 if ( pc98_machine_type & M_8M ) { 4580 /* 8 MHz system & H98 */ 4581 sysclock = 8; 4582 } else { 4583 /* 5 MHz system */ 4584 sysclock = 5; 4585 } 4586} 4587 4588static void 4589com_cflag_and_speed_set( struct com_s *com, int cflag, int speed) 4590{ 4591 int cfcr=0; 4592 int previnterrupt; 4593 u_int count; 4594 4595 if (pc98_ttspeedtab(com, speed, &count) != 0) 4596 return; 4597 4598 previnterrupt = pc98_check_i8251_interrupt(com); 4599 pc98_disable_i8251_interrupt( com, IEN_Tx|IEN_TxEMP|IEN_Rx ); 4600 4601 switch ( cflag&CSIZE ) { 4602 case CS5: 4603 cfcr = MOD8251_5BITS; break; 4604 case CS6: 4605 cfcr = MOD8251_6BITS; break; 4606 case CS7: 4607 cfcr = MOD8251_7BITS; break; 4608 case CS8: 4609 cfcr = MOD8251_8BITS; break; 4610 } 4611 if ( cflag&PARENB ) { 4612 if ( cflag&PARODD ) 4613 cfcr |= MOD8251_PODD; 4614 else 4615 cfcr |= MOD8251_PEVEN; 4616 } else 4617 cfcr |= MOD8251_PDISAB; 4618 4619 if ( cflag&CSTOPB ) 4620 cfcr |= MOD8251_STOP2; 4621 else 4622 cfcr |= MOD8251_STOP1; 4623 4624 if ( count & 0x10000 ) 4625 cfcr |= MOD8251_CLKX1; 4626 else 4627 cfcr |= MOD8251_CLKX16; 4628 4629 if (epson_machine_id != 0x20) { /* XXX */ 4630 int tmp; 4631 while (!((tmp = inb(com->sts_port)) & STS8251_TxEMP)) 4632 ; 4633 } 4634 /* set baud rate from ospeed */ 4635 pc98_set_baud_rate( com, count ); 4636 4637 if ( cfcr != pc98_i8251_get_mod(com) ) 4638 pc98_i8251_reset(com, cfcr, pc98_i8251_get_cmd(com) ); 4639 4640 pc98_enable_i8251_interrupt( com, previnterrupt ); 4641} 4642 4643static int 4644pc98_ttspeedtab(struct com_s *com, int speed, u_int *divisor) 4645{ 4646 int if_type, effect_sp, count = -1, mod; 4647 4648 if_type = com->pc98_if_type & 0x0f; 4649 4650 switch (com->pc98_if_type) { 4651 case COM_IF_INTERNAL: 4652 if (PC98SIO_baud_rate_port(if_type) != -1) { 4653 count = ttspeedtab(speed, if_8251_type[if_type].speedtab); 4654 if (count > 0) { 4655 count |= COM1_EXT_CLOCK; 4656 break; 4657 } 4658 } 4659 4660 /* for *1CLK asynchronous! mode, TEFUTEFU */ 4661 mod = (sysclock == 5) ? 2457600 : 1996800; 4662 effect_sp = ttspeedtab( speed, pc98speedtab ); 4663 if ( effect_sp < 0 ) /* XXX */ 4664 effect_sp = ttspeedtab( (speed - 1), pc98speedtab ); 4665 if ( effect_sp <= 0 ) 4666 return effect_sp; 4667 if ( effect_sp == speed ) 4668 mod /= 16; 4669 if ( mod % effect_sp ) 4670 return(-1); 4671 count = mod / effect_sp; 4672 if ( count > 65535 ) 4673 return(-1); 4674 if ( effect_sp != speed ) 4675 count |= 0x10000; 4676 break; 4677 case COM_IF_PC9861K_1: 4678 case COM_IF_PC9861K_2: 4679 count = 1; 4680 break; 4681 case COM_IF_IND_SS_1: 4682 case COM_IF_IND_SS_2: 4683 case COM_IF_PIO9032B_1: 4684 case COM_IF_PIO9032B_2: 4685 count = ttspeedtab( speed, if_8251_type[if_type].speedtab ); 4686 break; 4687 case COM_IF_B98_01_1: 4688 case COM_IF_B98_01_2: 4689 count = ttspeedtab( speed, if_8251_type[if_type].speedtab ); 4690#ifdef B98_01_OLD 4691 if (count == 0 || count == 1) { 4692 count += 4; 4693 count |= 0x20000; /* x1 mode for 76800 and 153600 */ 4694 } 4695#endif 4696 break; 4697 } 4698 4699 if (count < 0) 4700 return count; 4701 4702 *divisor = (u_int) count; 4703 return 0; 4704} 4705 4706static void 4707pc98_set_baud_rate( struct com_s *com, u_int count ) 4708{ 4709 int if_type, io, s; 4710 4711 if_type = com->pc98_if_type & 0x0f; 4712 io = rman_get_start(com->ioportres) & 0xff00; 4713 4714 switch (com->pc98_if_type) { 4715 case COM_IF_INTERNAL: 4716 if (PC98SIO_baud_rate_port(if_type) != -1) { 4717 if (count & COM1_EXT_CLOCK) { 4718 outb((Port_t)PC98SIO_baud_rate_port(if_type), count & 0xff); 4719 break; 4720 } else { 4721 outb((Port_t)PC98SIO_baud_rate_port(if_type), 0x09); 4722 } 4723 } 4724 4725 if (count == 0) 4726 return; 4727 4728 /* set i8253 */ 4729 s = splclock(); 4730 if (count != 3) 4731 outb( 0x77, 0xb6 ); 4732 else 4733 outb( 0x77, 0xb4 ); 4734 outb( 0x5f, 0); 4735 outb( 0x75, count & 0xff ); 4736 outb( 0x5f, 0); 4737 outb( 0x75, (count >> 8) & 0xff ); 4738 splx(s); 4739 break; 4740 case COM_IF_IND_SS_1: 4741 case COM_IF_IND_SS_2: 4742 outb(io | PC98SIO_intr_ctrl_port(if_type), 0); 4743 outb(io | PC98SIO_baud_rate_port(if_type), 0); 4744 outb(io | PC98SIO_baud_rate_port(if_type), 0xc0); 4745 outb(io | PC98SIO_baud_rate_port(if_type), (count >> 8) | 0x80); 4746 outb(io | PC98SIO_baud_rate_port(if_type), count & 0xff); 4747 break; 4748 case COM_IF_PIO9032B_1: 4749 case COM_IF_PIO9032B_2: 4750 outb(io | PC98SIO_baud_rate_port(if_type), count); 4751 break; 4752 case COM_IF_B98_01_1: 4753 case COM_IF_B98_01_2: 4754 outb(io | PC98SIO_baud_rate_port(if_type), count & 0x0f); 4755#ifdef B98_01_OLD 4756 /* 4757 * Some old B98_01 board should be controlled 4758 * in different way, but this hasn't been tested yet. 4759 */ 4760 outb(io | PC98SIO_func_port(if_type), 4761 (count & 0x20000) ? 0xf0 : 0xf2); 4762#endif 4763 break; 4764 } 4765} 4766static int 4767pc98_check_if_type(device_t dev, struct siodev *iod) 4768{ 4769 int irr, io, if_type, tmp; 4770 static short irq_tab[2][8] = { 4771 { 3, 5, 6, 9, 10, 12, 13, -1}, 4772 { 3, 10, 12, 13, 5, 6, 9, -1} 4773 }; 4774 4775 if_type = iod->if_type & 0x0f; 4776 iod->irq = 0; 4777 io = isa_get_port(dev) & 0xff00; 4778 4779 if (IS_8251(iod->if_type)) { 4780 if (PC98SIO_func_port(if_type) != -1) { 4781 outb(io | PC98SIO_func_port(if_type), 0xf2); 4782 tmp = ttspeedtab(9600, if_8251_type[if_type].speedtab); 4783 if (tmp != -1 && PC98SIO_baud_rate_port(if_type) != -1) 4784 outb(io | PC98SIO_baud_rate_port(if_type), tmp); 4785 } 4786 4787 iod->cmd = io | PC98SIO_cmd_port(if_type); 4788 iod->sts = io | PC98SIO_sts_port(if_type); 4789 iod->mod = io | PC98SIO_in_modem_port(if_type); 4790 iod->ctrl = io | PC98SIO_intr_ctrl_port(if_type); 4791 4792 if (iod->if_type == COM_IF_INTERNAL) { 4793 iod->irq = 4; 4794 4795 if (pc98_check_8251vfast()) { 4796 PC98SIO_baud_rate_port(if_type) = I8251F_div; 4797 if_8251_type[if_type].speedtab = pc98fast_speedtab; 4798 } 4799 } else { 4800 tmp = inb( iod->mod ) & if_8251_type[if_type].irr_mask; 4801 if ((isa_get_port(dev) & 0xff) == IO_COM2) 4802 iod->irq = irq_tab[0][tmp]; 4803 else 4804 iod->irq = irq_tab[1][tmp]; 4805 } 4806 } else { 4807 irr = if_16550a_type[if_type].irr_read; 4808#ifdef COM_MULTIPORT 4809 if (!COM_ISMULTIPORT(device_get_flags(dev)) || 4810 device_get_unit(dev) == COM_MPMASTER(device_get_flags(dev))) 4811#endif 4812 if (irr != -1) { 4813 tmp = inb(io | irr); 4814 if (isa_get_port(dev) & 0x01) /* XXX depend on RSB-384 */ 4815 iod->irq = irq_tab[1][tmp >> 3]; 4816 else 4817 iod->irq = irq_tab[0][tmp & 0x07]; 4818 } 4819 } 4820 if ( iod->irq == -1 ) return -1; 4821 4822 return 0; 4823} 4824static void 4825pc98_set_ioport(struct com_s *com) 4826{ 4827 int if_type = com->pc98_if_type & 0x0f; 4828 Port_t io = rman_get_start(com->ioportres) & 0xff00; 4829 4830 pc98_check_sysclock(); 4831 com->data_port = io | PC98SIO_data_port(if_type); 4832 com->cmd_port = io | PC98SIO_cmd_port(if_type); 4833 com->sts_port = io | PC98SIO_sts_port(if_type); 4834 com->in_modem_port = io | PC98SIO_in_modem_port(if_type); 4835 com->intr_ctrl_port = io | PC98SIO_intr_ctrl_port(if_type); 4836} 4837static int 4838pc98_check_8251vfast(void) 4839{ 4840 int i; 4841 4842 outb(I8251F_div, 0x8c); 4843 DELAY(10); 4844 for (i = 0; i < 100; i++) { 4845 if ((inb(I8251F_div) & 0x80) != 0) { 4846 i = 0; 4847 break; 4848 } 4849 DELAY(1); 4850 } 4851 outb(I8251F_div, 0); 4852 DELAY(10); 4853 for (; i < 100; i++) { 4854 if ((inb(I8251F_div) & 0x80) == 0) 4855 return 1; 4856 DELAY(1); 4857 } 4858 4859 return 0; 4860} 4861static int 4862pc98_check_8251fifo(void) 4863{ 4864 u_char tmp1, tmp2; 4865 4866 tmp1 = inb(I8251F_iir); 4867 DELAY(10); 4868 tmp2 = inb(I8251F_iir); 4869 if (((tmp1 ^ tmp2) & 0x40) != 0 && ((tmp1 | tmp2) & 0x20) == 0) 4870 return 1; 4871 4872 return 0; 4873} 4874#endif /* PC98 defined */ 4875