sio.c revision 132226
1/*-
2 * Copyright (c) 1991 The Regents of the University of California.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 *    notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 *    notice, this list of conditions and the following disclaimer in the
12 *    documentation and/or other materials provided with the distribution.
13 * 4. Neither the name of the University nor the names of its contributors
14 *    may be used to endorse or promote products derived from this software
15 *    without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 *
29 * $FreeBSD: head/sys/pc98/cbus/sio.c 132226 2004-07-15 20:47:41Z phk $
30 *	from: @(#)com.c	7.5 (Berkeley) 5/16/91
31 *	from: i386/isa sio.c,v 1.234
32 */
33
34#include "opt_comconsole.h"
35#include "opt_compat.h"
36#include "opt_gdb.h"
37#include "opt_kdb.h"
38#include "opt_sio.h"
39
40/*
41 * Serial driver, based on 386BSD-0.1 com driver.
42 * Mostly rewritten to use pseudo-DMA.
43 * Works for National Semiconductor NS8250-NS16550AF UARTs.
44 * COM driver, based on HP dca driver.
45 *
46 * Changes for PC-Card integration:
47 *	- Added PC-Card driver table and handlers
48 */
49/*===============================================================
50 * 386BSD(98),FreeBSD-1.1x(98) com driver.
51 * -----
52 * modified for PC9801 by M.Ishii
53 *			Kyoto University Microcomputer Club (KMC)
54 * Chou "TEFUTEFU" Hirotomi
55 *			Kyoto Univ.  the faculty of medicine
56 *===============================================================
57 * FreeBSD-2.0.1(98) sio driver.
58 * -----
59 * modified for pc98 Internal i8251 and MICRO CORE MC16550II
60 *			T.Koike(hfc01340@niftyserve.or.jp)
61 * implement kernel device configuration
62 *			aizu@orient.center.nitech.ac.jp
63 *
64 * Notes.
65 * -----
66 *  PC98 localization based on 386BSD(98) com driver. Using its PC98 local
67 *  functions.
68 *  This driver is under debugging,has bugs.
69 */
70/*
71 * modified for AIWA B98-01
72 * by T.Hatanou <hatanou@yasuda.comm.waseda.ac.jp>  last update: 15 Sep.1995
73 */
74/*
75 * Modified by Y.Takahashi of Kogakuin University.
76 */
77/*
78 * modified for 8251(FIFO) by Seigo TANIMURA <tanimura@FreeBSD.org>
79 */
80
81#include <sys/param.h>
82#include <sys/systm.h>
83#include <sys/bus.h>
84#include <sys/conf.h>
85#include <sys/fcntl.h>
86#include <sys/interrupt.h>
87#include <sys/kdb.h>
88#include <sys/kernel.h>
89#include <sys/limits.h>
90#include <sys/lock.h>
91#include <sys/malloc.h>
92#include <sys/module.h>
93#include <sys/mutex.h>
94#include <sys/proc.h>
95#include <sys/reboot.h>
96#include <sys/serial.h>
97#include <sys/sysctl.h>
98#include <sys/syslog.h>
99#include <sys/tty.h>
100#include <machine/bus.h>
101#include <sys/rman.h>
102#include <sys/timepps.h>
103#include <sys/uio.h>
104#include <sys/cons.h>
105
106#include <isa/isavar.h>
107
108#include <machine/resource.h>
109
110#include <dev/sio/sioreg.h>
111#include <dev/sio/siovar.h>
112
113#ifdef PC98
114#include <pc98/pc98/pc98.h>
115#include <pc98/pc98/pc98_machdep.h>
116#endif
117
118#ifdef COM_ESP
119#include <dev/ic/esp.h>
120#endif
121#include <dev/ic/ns16550.h>
122#ifdef PC98
123#include <dev/ic/i8251.h>
124#include <dev/ic/rsa.h>
125#endif
126
127#define	LOTS_OF_EVENTS	64	/* helps separate urgent events from input */
128
129#define	CALLOUT_MASK		0x80
130#define	CONTROL_MASK		0x60
131#define	CONTROL_INIT_STATE	0x20
132#define	CONTROL_LOCK_STATE	0x40
133#define	DEV_TO_UNIT(dev)	(MINOR_TO_UNIT(minor(dev)))
134#define	MINOR_TO_UNIT(mynor)	((((mynor) & ~0xffffU) >> (8 + 3)) \
135				 | ((mynor) & 0x1f))
136#define	UNIT_TO_MINOR(unit)	((((unit) & ~0x1fU) << (8 + 3)) \
137				 | ((unit) & 0x1f))
138
139/*
140 * Meaning of flags:
141 *
142 * 0x00000001	shared IRQs
143 * 0x00000002	disable FIFO
144 * 0x00000008	recover sooner from lost output interrupts
145 * 0x00000010	device is potential system console
146 * 0x00000020	device is forced to become system console
147 * 0x00000040	device is reserved for low-level IO
148 * 0x00000080	use this port for remote kernel debugging
149 * 0x0000??00	minor number of master port
150 * 0x00010000	PPS timestamping on CTS instead of DCD
151 * 0x00080000	IIR_TXRDY bug
152 * 0x00400000	If no comconsole found then mark as a comconsole
153 * 0x1?000000	interface type
154 */
155
156#ifdef COM_MULTIPORT
157/* checks in flags for multiport and which is multiport "master chip"
158 * for a given card
159 */
160#define	COM_ISMULTIPORT(flags)	((flags) & 0x01)
161#define	COM_MPMASTER(flags)	(((flags) >> 8) & 0x0ff)
162#ifndef PC98
163#define	COM_NOTAST4(flags)	((flags) & 0x04)
164#endif
165#else
166#define	COM_ISMULTIPORT(flags)	(0)
167#endif /* COM_MULTIPORT */
168
169#define	COM_C_IIR_TXRDYBUG	0x80000
170#define	COM_CONSOLE(flags)	((flags) & 0x10)
171#define	COM_DEBUGGER(flags)	((flags) & 0x80)
172#ifndef PC98
173#define	COM_FIFOSIZE(flags)	(((flags) & 0xff000000) >> 24)
174#endif
175#define	COM_FORCECONSOLE(flags)	((flags) & 0x20)
176#define	COM_IIR_TXRDYBUG(flags)	((flags) & COM_C_IIR_TXRDYBUG)
177#define	COM_LLCONSOLE(flags)	((flags) & 0x40)
178#define	COM_LOSESOUTINTS(flags)	((flags) & 0x08)
179#define	COM_NOFIFO(flags)	((flags) & 0x02)
180#ifndef PC98
181#define	COM_NOSCR(flags)	((flags) & 0x100000)
182#endif
183#define	COM_PPSCTS(flags)	((flags) & 0x10000)
184#ifndef PC98
185#define	COM_ST16650A(flags)	((flags) & 0x20000)
186#define	COM_TI16754(flags)	((flags) & 0x200000)
187#endif
188
189#define	sio_getreg(com, off) \
190	(bus_space_read_1((com)->bst, (com)->bsh, (off)))
191#define	sio_setreg(com, off, value) \
192	(bus_space_write_1((com)->bst, (com)->bsh, (off), (value)))
193
194/*
195 * com state bits.
196 * (CS_BUSY | CS_TTGO) and (CS_BUSY | CS_TTGO | CS_ODEVREADY) must be higher
197 * than the other bits so that they can be tested as a group without masking
198 * off the low bits.
199 *
200 * The following com and tty flags correspond closely:
201 *	CS_BUSY		= TS_BUSY (maintained by comstart(), siopoll() and
202 *				   comstop())
203 *	CS_TTGO		= ~TS_TTSTOP (maintained by comparam() and comstart())
204 *	CS_CTS_OFLOW	= CCTS_OFLOW (maintained by comparam())
205 *	CS_RTS_IFLOW	= CRTS_IFLOW (maintained by comparam())
206 * TS_FLUSH is not used.
207 * XXX I think TIOCSETA doesn't clear TS_TTSTOP when it clears IXON.
208 * XXX CS_*FLOW should be CF_*FLOW in com->flags (control flags not state).
209 */
210#define	CS_BUSY		0x80	/* output in progress */
211#define	CS_TTGO		0x40	/* output not stopped by XOFF */
212#define	CS_ODEVREADY	0x20	/* external device h/w ready (CTS) */
213#define	CS_CHECKMSR	1	/* check of MSR scheduled */
214#define	CS_CTS_OFLOW	2	/* use CTS output flow control */
215#define	CS_ODONE	4	/* output completed */
216#define	CS_RTS_IFLOW	8	/* use RTS input flow control */
217#define	CSE_BUSYCHECK	1	/* siobusycheck() scheduled */
218
219static	char const * const	error_desc[] = {
220#define	CE_OVERRUN			0
221	"silo overflow",
222#define	CE_INTERRUPT_BUF_OVERFLOW	1
223	"interrupt-level buffer overflow",
224#define	CE_TTY_BUF_OVERFLOW		2
225	"tty-level buffer overflow",
226};
227
228#define	CE_NTYPES			3
229#define	CE_RECORD(com, errnum)		(++(com)->delta_error_counts[errnum])
230
231/* types.  XXX - should be elsewhere */
232typedef u_int	Port_t;		/* hardware port */
233typedef u_char	bool_t;		/* boolean */
234
235/* queue of linear buffers */
236struct lbq {
237	u_char	*l_head;	/* next char to process */
238	u_char	*l_tail;	/* one past the last char to process */
239	struct lbq *l_next;	/* next in queue */
240	bool_t	l_queued;	/* nonzero if queued */
241};
242
243/* com device structure */
244struct com_s {
245	u_char	state;		/* miscellaneous flag bits */
246	bool_t  active_out;	/* nonzero if the callout device is open */
247	u_char	cfcr_image;	/* copy of value written to CFCR */
248#ifdef COM_ESP
249	bool_t	esp;		/* is this unit a hayes esp board? */
250#endif
251	u_char	extra_state;	/* more flag bits, separate for order trick */
252	u_char	fifo_image;	/* copy of value written to FIFO */
253	bool_t	hasfifo;	/* nonzero for 16550 UARTs */
254	bool_t	loses_outints;	/* nonzero if device loses output interrupts */
255	u_char	mcr_image;	/* copy of value written to MCR */
256#ifdef COM_MULTIPORT
257	bool_t	multiport;	/* is this unit part of a multiport device? */
258#endif /* COM_MULTIPORT */
259	bool_t	no_irq;		/* nonzero if irq is not attached */
260	bool_t  gone;		/* hardware disappeared */
261	bool_t	poll;		/* nonzero if polling is required */
262	bool_t	poll_output;	/* nonzero if polling for output is required */
263	bool_t	st16650a;	/* nonzero if Startech 16650A compatible */
264	int	unit;		/* unit	number */
265	u_int	flags;		/* copy of device flags */
266	u_int	tx_fifo_size;
267	u_int	wopeners;	/* # processes waiting for DCD in open() */
268
269	/*
270	 * The high level of the driver never reads status registers directly
271	 * because there would be too many side effects to handle conveniently.
272	 * Instead, it reads copies of the registers stored here by the
273	 * interrupt handler.
274	 */
275	u_char	last_modem_status;	/* last MSR read by intr handler */
276	u_char	prev_modem_status;	/* last MSR handled by high level */
277
278	u_char	*ibuf;		/* start of input buffer */
279	u_char	*ibufend;	/* end of input buffer */
280	u_char	*ibufold;	/* old input buffer, to be freed */
281	u_char	*ihighwater;	/* threshold in input buffer */
282	u_char	*iptr;		/* next free spot in input buffer */
283	int	ibufsize;	/* size of ibuf (not include error bytes) */
284	int	ierroff;	/* offset of error bytes in ibuf */
285
286	struct lbq	obufq;	/* head of queue of output buffers */
287	struct lbq	obufs[2];	/* output buffers */
288
289	bus_space_tag_t		bst;
290	bus_space_handle_t	bsh;
291
292#ifdef PC98
293	Port_t	cmd_port;
294	Port_t	sts_port;
295	Port_t	in_modem_port;
296	Port_t	intr_ctrl_port;
297	Port_t	rsabase;	/* Iobase address of an I/O-DATA RSA board. */
298	int	intr_enable;
299	int	pc98_prev_modem_status;
300	int	pc98_modem_delta;
301	int	modem_car_chg_timer;
302	int	pc98_prev_siocmd;
303	int	pc98_prev_siomod;
304	int	modem_checking;
305	int	pc98_if_type;
306
307	bool_t	pc98_8251fifo;
308	bool_t	pc98_8251fifo_enable;
309#endif /* PC98 */
310	Port_t	data_port;	/* i/o ports */
311#ifdef COM_ESP
312	Port_t	esp_port;
313#endif
314	Port_t	int_ctl_port;
315	Port_t	int_id_port;
316	Port_t	modem_ctl_port;
317	Port_t	line_status_port;
318	Port_t	modem_status_port;
319
320	struct tty	*tp;	/* cross reference */
321
322	/* Initial state. */
323	struct termios	it_in;	/* should be in struct tty */
324	struct termios	it_out;
325
326	/* Lock state. */
327	struct termios	lt_in;	/* should be in struct tty */
328	struct termios	lt_out;
329
330	bool_t	do_timestamp;
331	struct timeval	timestamp;
332	struct	pps_state pps;
333	int	pps_bit;
334#ifdef ALT_BREAK_TO_DEBUGGER
335	int	alt_brk_state;
336#endif
337
338	u_long	bytes_in;	/* statistics */
339	u_long	bytes_out;
340	u_int	delta_error_counts[CE_NTYPES];
341	u_long	error_counts[CE_NTYPES];
342
343	u_long	rclk;
344
345	struct resource *irqres;
346	struct resource *ioportres;
347	int	ioportrid;
348	void	*cookie;
349	struct cdev *devs[6];
350
351	/*
352	 * Data area for output buffers.  Someday we should build the output
353	 * buffer queue without copying data.
354	 */
355#ifdef PC98
356	int	obufsize;
357 	u_char	*obuf1;
358 	u_char	*obuf2;
359#else
360	u_char	obuf1[256];
361	u_char	obuf2[256];
362#endif
363};
364
365#ifdef COM_ESP
366static	int	espattach(struct com_s *com, Port_t esp_port);
367#endif
368
369static	void	combreak(struct tty *tp, int sig);
370static	timeout_t siobusycheck;
371static	u_int	siodivisor(u_long rclk, speed_t speed);
372static	void	comhardclose(struct com_s *com);
373static	void	sioinput(struct com_s *com);
374static	void	siointr1(struct com_s *com);
375static	void	siointr(void *arg);
376static	int	commodem(struct tty *tp, int sigon, int sigoff);
377static	int	comparam(struct tty *tp, struct termios *t);
378static	void	siopoll(void *);
379static	void	siosettimeout(void);
380static	int	siosetwater(struct com_s *com, speed_t speed);
381static	void	comstart(struct tty *tp);
382static	void	comstop(struct tty *tp, int rw);
383static	timeout_t comwakeup;
384
385char		sio_driver_name[] = "sio";
386static struct	mtx sio_lock;
387static int	sio_inited;
388
389/* table and macro for fast conversion from a unit number to its com struct */
390devclass_t	sio_devclass;
391#define	com_addr(unit)	((struct com_s *) \
392			 devclass_get_softc(sio_devclass, unit)) /* XXX */
393
394static	d_open_t	sioopen;
395static	d_close_t	sioclose;
396static	d_read_t	sioread;
397static	d_write_t	siowrite;
398static	d_ioctl_t	sioioctl;
399
400static struct cdevsw sio_cdevsw = {
401	.d_version =	D_VERSION,
402	.d_open =	sioopen,
403	.d_close =	sioclose,
404	.d_read =	sioread,
405	.d_write =	siowrite,
406	.d_ioctl =	sioioctl,
407	.d_name =	sio_driver_name,
408	.d_flags =	D_TTY | D_NEEDGIANT,
409};
410
411static	d_open_t	siocopen;
412static	d_close_t	siocclose;
413static	d_read_t	siocrdwr;
414static	d_ioctl_t	siocioctl;
415
416static struct cdevsw sioc_cdevsw = {
417	.d_version =	D_VERSION,
418	.d_open =	siocopen,
419	.d_close =	siocclose,
420	.d_read =	siocrdwr,
421	.d_write =	siocrdwr,
422	.d_ioctl =	siocioctl,
423	.d_name =	sio_driver_name,
424	.d_flags =	D_TTY | D_NEEDGIANT,
425};
426
427int	comconsole = -1;
428static	volatile speed_t	comdefaultrate = CONSPEED;
429static	u_long			comdefaultrclk = DEFAULT_RCLK;
430SYSCTL_ULONG(_machdep, OID_AUTO, conrclk, CTLFLAG_RW, &comdefaultrclk, 0, "");
431static	speed_t			gdbdefaultrate = GDBSPEED;
432SYSCTL_UINT(_machdep, OID_AUTO, gdbspeed, CTLFLAG_RW,
433	    &gdbdefaultrate, GDBSPEED, "");
434static	u_int	com_events;	/* input chars + weighted output completions */
435static	Port_t	siocniobase;
436static	int	siocnunit = -1;
437static	void	*sio_slow_ih;
438static	void	*sio_fast_ih;
439static	int	sio_timeout;
440static	int	sio_timeouts_until_log;
441static	struct	callout_handle sio_timeout_handle
442    = CALLOUT_HANDLE_INITIALIZER(&sio_timeout_handle);
443static	int	sio_numunits;
444
445#ifdef PC98
446struct	siodev	{
447	short	if_type;
448	short	irq;
449	Port_t	cmd, sts, ctrl, mod;
450};
451static	int	sysclock;
452
453#define	COM_INT_DISABLE		{int previpri; previpri=spltty();
454#define	COM_INT_ENABLE		splx(previpri);}
455#define IEN_TxFLAG		IEN_Tx
456
457#define COM_CARRIER_DETECT_EMULATE	0
458#define	PC98_CHECK_MODEM_INTERVAL	(hz/10)
459#define DCD_OFF_TOLERANCE		2
460#define DCD_ON_RECOGNITION		2
461#define IS_8251(if_type)		(!(if_type & 0x10))
462#define COM1_EXT_CLOCK			0x40000
463
464static	void	commint(struct cdev *dev);
465static	void	com_tiocm_bis(struct com_s *com, int msr);
466static	void	com_tiocm_bic(struct com_s *com, int msr);
467static	int	com_tiocm_get(struct com_s *com);
468static	int	com_tiocm_get_delta(struct com_s *com);
469static	void	pc98_msrint_start(struct cdev *dev);
470static	void	com_cflag_and_speed_set(struct com_s *com, int cflag, int speed);
471static	int	pc98_ttspeedtab(struct com_s *com, int speed, u_int *divisor);
472static	int	pc98_get_modem_status(struct com_s *com);
473static	timeout_t	pc98_check_msr;
474static	void	pc98_set_baud_rate(struct com_s *com, u_int count);
475static	void	pc98_i8251_reset(struct com_s *com, int mode, int command);
476static	void	pc98_disable_i8251_interrupt(struct com_s *com, int mod);
477static	void	pc98_enable_i8251_interrupt(struct com_s *com, int mod);
478static	int	pc98_check_i8251_interrupt(struct com_s *com);
479static	int	pc98_i8251_get_cmd(struct com_s *com);
480static	int	pc98_i8251_get_mod(struct com_s *com);
481static	void	pc98_i8251_set_cmd(struct com_s *com, int x);
482static	void	pc98_i8251_or_cmd(struct com_s *com, int x);
483static	void	pc98_i8251_clear_cmd(struct com_s *com, int x);
484static	void	pc98_i8251_clear_or_cmd(struct com_s *com, int clr, int x);
485static	int	pc98_check_if_type(device_t dev, struct siodev *iod);
486static	int	pc98_check_8251vfast(void);
487static	int	pc98_check_8251fifo(void);
488static	void	pc98_check_sysclock(void);
489static	void	pc98_set_ioport(struct com_s *com);
490
491#define com_int_Tx_disable(com) \
492		pc98_disable_i8251_interrupt(com,IEN_Tx|IEN_TxEMP)
493#define com_int_Tx_enable(com) \
494		pc98_enable_i8251_interrupt(com,IEN_TxFLAG)
495#define com_int_Rx_disable(com) \
496		pc98_disable_i8251_interrupt(com,IEN_Rx)
497#define com_int_Rx_enable(com) \
498		pc98_enable_i8251_interrupt(com,IEN_Rx)
499#define com_int_TxRx_disable(com) \
500		pc98_disable_i8251_interrupt(com,IEN_Tx|IEN_TxEMP|IEN_Rx)
501#define com_int_TxRx_enable(com) \
502		pc98_enable_i8251_interrupt(com,IEN_TxFLAG|IEN_Rx)
503#define com_send_break_on(com) \
504		(IS_8251((com)->pc98_if_type) ? \
505		 pc98_i8251_or_cmd((com), CMD8251_SBRK) : \
506		 sio_setreg((com), com_cfcr, (com)->cfcr_image |= CFCR_SBREAK))
507#define com_send_break_off(com) \
508		(IS_8251((com)->pc98_if_type) ? \
509		 pc98_i8251_clear_cmd((com), CMD8251_SBRK) : \
510		 sio_setreg((com), com_cfcr, (com)->cfcr_image &= ~CFCR_SBREAK))
511
512static struct speedtab pc98speedtab[] = {	/* internal RS232C interface */
513	{ 0,		0, },
514	{ 50,		50, },
515	{ 75,		75, },
516	{ 150,		150, },
517	{ 200,		200, },
518	{ 300,		300, },
519	{ 600,		600, },
520	{ 1200,		1200, },
521	{ 2400,		2400, },
522	{ 4800,		4800, },
523	{ 9600,		9600, },
524	{ 19200,	19200, },
525	{ 38400,	38400, },
526	{ 51200,	51200, },
527	{ 76800,	76800, },
528	{ 20800,	20800, },
529	{ 31200,	31200, },
530	{ 41600,	41600, },
531	{ 62400,	62400, },
532	{ -1,		-1 }
533};
534static struct speedtab pc98fast_speedtab[] = {
535	{ 9600,		0x80 | (DEFAULT_RCLK / (16 * (9600))), },
536	{ 19200,	0x80 | (DEFAULT_RCLK / (16 * (19200))), },
537	{ 38400,	0x80 | (DEFAULT_RCLK / (16 * (38400))), },
538	{ 57600,	0x80 | (DEFAULT_RCLK / (16 * (57600))), },
539	{ 115200,	0x80 | (DEFAULT_RCLK / (16 * (115200))), },
540	{ -1,		-1 }
541};
542static struct speedtab comspeedtab_pio9032b[] = {
543	{ 300,		6, },
544	{ 600,		5, },
545	{ 1200,		4, },
546	{ 2400,		3, },
547	{ 4800,		2, },
548	{ 9600,		1, },
549	{ 19200,	0, },
550	{ 38400,	7, },
551	{ -1,		-1 }
552};
553static struct speedtab comspeedtab_b98_01[] = {
554	{ 75,		11, },
555	{ 150,		10, },
556	{ 300,		9, },
557	{ 600,		8, },
558	{ 1200,		7, },
559	{ 2400,		6, },
560	{ 4800,		5, },
561	{ 9600,		4, },
562	{ 19200,	3, },
563	{ 38400,	2, },
564	{ 76800,	1, },
565	{ 153600,	0, },
566	{ -1,		-1 }
567};
568static struct speedtab comspeedtab_ind[] = {
569	{ 300,		1536, },
570	{ 600,		768, },
571	{ 1200,		384, },
572	{ 2400,		192, },
573	{ 4800,		96, },
574	{ 9600,		48, },
575	{ 19200,	24, },
576	{ 38400,	12, },
577	{ 57600,	8, },
578	{ 115200,	4, },
579	{ 153600,	3, },
580	{ 230400,	2, },
581	{ 460800,	1, },
582	{ -1,		-1 }
583};
584
585struct {
586	char	*name;
587	short	port_table[7];
588	short	irr_mask;
589	struct speedtab	*speedtab;
590	short	check_irq;
591} if_8251_type[] = {
592	/* COM_IF_INTERNAL */
593	{ " (internal)", {0x30, 0x32, 0x32, 0x33, 0x35, -1, -1},
594	     -1, pc98speedtab, 1 },
595	/* COM_IF_PC9861K_1 */
596	{ " (PC9861K)", {0xb1, 0xb3, 0xb3, 0xb0, 0xb0, -1, -1},
597	     3, NULL, 1 },
598	/* COM_IF_PC9861K_2 */
599	{ " (PC9861K)", {0xb9, 0xbb, 0xbb, 0xb2, 0xb2, -1, -1},
600	      3, NULL, 1 },
601	/* COM_IF_IND_SS_1 */
602	{ " (IND-SS)", {0xb1, 0xb3, 0xb3, 0xb0, 0xb0, 0xb3, -1},
603	     3, comspeedtab_ind, 1 },
604	/* COM_IF_IND_SS_2 */
605	{ " (IND-SS)", {0xb9, 0xbb, 0xbb, 0xb2, 0xb2, 0xbb, -1},
606	     3, comspeedtab_ind, 1 },
607	/* COM_IF_PIO9032B_1 */
608	{ " (PIO9032B)", {0xb1, 0xb3, 0xb3, 0xb0, 0xb0, 0xb8, -1},
609	      7, comspeedtab_pio9032b, 1 },
610	/* COM_IF_PIO9032B_2 */
611	{ " (PIO9032B)", {0xb9, 0xbb, 0xbb, 0xb2, 0xb2, 0xba, -1},
612	      7, comspeedtab_pio9032b, 1 },
613	/* COM_IF_B98_01_1 */
614	{ " (B98-01)", {0xb1, 0xb3, 0xb3, 0xb0, 0xb0, 0xd1, 0xd3},
615	      7, comspeedtab_b98_01, 0 },
616	/* COM_IF_B98_01_2 */
617	{ " (B98-01)", {0xb9, 0xbb, 0xbb, 0xb2, 0xb2, 0xd5, 0xd7},
618	     7, comspeedtab_b98_01, 0 },
619};
620#define	PC98SIO_data_port(type)		(if_8251_type[type].port_table[0])
621#define	PC98SIO_cmd_port(type)		(if_8251_type[type].port_table[1])
622#define	PC98SIO_sts_port(type)		(if_8251_type[type].port_table[2])
623#define	PC98SIO_in_modem_port(type)	(if_8251_type[type].port_table[3])
624#define	PC98SIO_intr_ctrl_port(type)	(if_8251_type[type].port_table[4])
625#define	PC98SIO_baud_rate_port(type)	(if_8251_type[type].port_table[5])
626#define	PC98SIO_func_port(type)		(if_8251_type[type].port_table[6])
627
628#define	I8251F_data		0x130
629#define	I8251F_lsr		0x132
630#define	I8251F_msr		0x134
631#define	I8251F_iir		0x136
632#define	I8251F_fcr		0x138
633#define	I8251F_div		0x13a
634
635
636static bus_addr_t port_table_0[] =
637	{0x000, 0x001, 0x002, 0x003, 0x004, 0x005, 0x006, 0x007};
638static bus_addr_t port_table_1[] =
639	{0x000, 0x002, 0x004, 0x006, 0x008, 0x00a, 0x00c, 0x00e};
640static bus_addr_t port_table_8[] =
641	{0x000, 0x100, 0x200, 0x300, 0x400, 0x500, 0x600, 0x700};
642static bus_addr_t port_table_rsa[] = {
643	0x008, 0x009, 0x00a, 0x00b, 0x00c, 0x00d, 0x00e, 0x00f,
644	0x000, 0x001, 0x002, 0x003, 0x004, 0x005, 0x006, 0x007
645};
646
647struct {
648	char		*name;
649	short		irr_read;
650	short		irr_write;
651	bus_addr_t	*iat;
652	bus_size_t	iatsz;
653	u_long		rclk;
654} if_16550a_type[] = {
655	/* COM_IF_RSA98 */
656	{" (RSA-98)", -1, -1, port_table_0, IO_COMSIZE, DEFAULT_RCLK},
657	/* COM_IF_NS16550 */
658	{"", -1, -1, port_table_0, IO_COMSIZE, DEFAULT_RCLK},
659	/* COM_IF_SECOND_CCU */
660	{"", -1, -1, port_table_0, IO_COMSIZE, DEFAULT_RCLK},
661	/* COM_IF_MC16550II */
662	{" (MC16550II)", -1, 0x1000, port_table_8, IO_COMSIZE,
663	 DEFAULT_RCLK * 4},
664	/* COM_IF_MCRS98 */
665	{" (MC-RS98)", -1, 0x1000, port_table_8, IO_COMSIZE, DEFAULT_RCLK * 4},
666	/* COM_IF_RSB3000 */
667	{" (RSB-3000)", 0xbf, -1, port_table_1, IO_COMSIZE, DEFAULT_RCLK * 10},
668	/* COM_IF_RSB384 */
669	{" (RSB-384)", 0xbf, -1, port_table_1, IO_COMSIZE, DEFAULT_RCLK * 10},
670	/* COM_IF_MODEM_CARD */
671	{"", -1, -1, port_table_0, IO_COMSIZE, DEFAULT_RCLK},
672	/* COM_IF_RSA98III */
673	{" (RSA-98III)", -1, -1, port_table_rsa, 16, DEFAULT_RCLK * 8},
674	/* COM_IF_ESP98 */
675	{" (ESP98)", -1, -1, port_table_1, IO_COMSIZE, DEFAULT_RCLK * 4},
676};
677#endif /* PC98 */
678
679#ifdef GDB
680static	Port_t	siogdbiobase = 0;
681#endif
682
683#ifdef COM_ESP
684#ifdef PC98
685
686/* XXX configure this properly. */
687/* XXX quite broken for new-bus. */
688static  Port_t  likely_com_ports[] = { 0, 0xb0, 0xb1, 0 };
689static  Port_t  likely_esp_ports[] = { 0xc0d0, 0 };
690
691#define	ESP98_CMD1	(ESP_CMD1 * 0x100)
692#define	ESP98_CMD2	(ESP_CMD2 * 0x100)
693#define	ESP98_STATUS1	(ESP_STATUS1 * 0x100)
694#define	ESP98_STATUS2	(ESP_STATUS2 * 0x100)
695
696#else /* PC98 */
697
698/* XXX configure this properly. */
699static	Port_t	likely_com_ports[] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8, };
700static	Port_t	likely_esp_ports[] = { 0x140, 0x180, 0x280, 0 };
701
702#endif /* PC98 */
703#endif
704
705/*
706 * handle sysctl read/write requests for console speed
707 *
708 * In addition to setting comdefaultrate for I/O through /dev/console,
709 * also set the initial and lock values for the /dev/ttyXX device
710 * if there is one associated with the console.  Finally, if the /dev/tty
711 * device has already been open, change the speed on the open running port
712 * itself.
713 */
714
715static int
716sysctl_machdep_comdefaultrate(SYSCTL_HANDLER_ARGS)
717{
718	int error, s;
719	speed_t newspeed;
720	struct com_s *com;
721	struct tty *tp;
722
723	newspeed = comdefaultrate;
724
725	error = sysctl_handle_opaque(oidp, &newspeed, sizeof newspeed, req);
726	if (error || !req->newptr)
727		return (error);
728
729	comdefaultrate = newspeed;
730
731	if (comconsole < 0)		/* serial console not selected? */
732		return (0);
733
734	com = com_addr(comconsole);
735	if (com == NULL)
736		return (ENXIO);
737
738	/*
739	 * set the initial and lock rates for /dev/ttydXX and /dev/cuaXX
740	 * (note, the lock rates really are boolean -- if non-zero, disallow
741	 *  speed changes)
742	 */
743	com->it_in.c_ispeed  = com->it_in.c_ospeed =
744	com->lt_in.c_ispeed  = com->lt_in.c_ospeed =
745	com->it_out.c_ispeed = com->it_out.c_ospeed =
746	com->lt_out.c_ispeed = com->lt_out.c_ospeed = comdefaultrate;
747
748	/*
749	 * if we're open, change the running rate too
750	 */
751	tp = com->tp;
752	if (tp && (tp->t_state & TS_ISOPEN)) {
753		tp->t_termios.c_ispeed =
754		tp->t_termios.c_ospeed = comdefaultrate;
755		s = spltty();
756		error = comparam(tp, &tp->t_termios);
757		splx(s);
758	}
759	return error;
760}
761
762SYSCTL_PROC(_machdep, OID_AUTO, conspeed, CTLTYPE_INT | CTLFLAG_RW,
763	    0, 0, sysctl_machdep_comdefaultrate, "I", "");
764
765/*
766 *	Unload the driver and clear the table.
767 *	XXX this is mostly wrong.
768 *	XXX TODO:
769 *	This is usually called when the card is ejected, but
770 *	can be caused by a kldunload of a controller driver.
771 *	The idea is to reset the driver's view of the device
772 *	and ensure that any driver entry points such as
773 *	read and write do not hang.
774 */
775int
776siodetach(dev)
777	device_t	dev;
778{
779	struct com_s	*com;
780	int i;
781
782	com = (struct com_s *) device_get_softc(dev);
783	if (com == NULL) {
784		device_printf(dev, "NULL com in siounload\n");
785		return (0);
786	}
787	com->gone = TRUE;
788	ttygone(com->tp);
789	for (i = 0 ; i < 6; i++)
790		destroy_dev(com->devs[i]);
791	if (com->irqres) {
792		bus_teardown_intr(dev, com->irqres, com->cookie);
793		bus_release_resource(dev, SYS_RES_IRQ, 0, com->irqres);
794	}
795	if (com->ioportres)
796		bus_release_resource(dev, SYS_RES_IOPORT, com->ioportrid,
797				     com->ioportres);
798	if (com->tp && (com->tp->t_state & TS_ISOPEN)) {
799		device_printf(dev, "still open, forcing close\n");
800		ttyld_close(com->tp, 0);
801		tty_close(com->tp);
802	} else {
803		if (com->ibuf != NULL)
804			free(com->ibuf, M_DEVBUF);
805#ifdef PC98
806		if (com->obuf1 != NULL)
807			free(com->obuf1, M_DEVBUF);
808#endif
809		device_set_softc(dev, NULL);
810		free(com, M_DEVBUF);
811	}
812	return (0);
813}
814
815int
816sioprobe(dev, xrid, rclk, noprobe)
817	device_t	dev;
818	int		xrid;
819	u_long		rclk;
820	int		noprobe;
821{
822#if 0
823	static bool_t	already_init;
824	device_t	xdev;
825#endif
826	struct com_s	*com;
827	u_int		divisor;
828	bool_t		failures[10];
829	int		fn;
830	device_t	idev;
831	Port_t		iobase;
832	intrmask_t	irqmap[4];
833	intrmask_t	irqs;
834	u_char		mcr_image;
835	int		result;
836	u_long		xirq;
837	u_int		flags = device_get_flags(dev);
838	int		rid;
839	struct resource *port;
840#ifdef PC98
841	int		tmp;
842	struct siodev	iod;
843#endif
844
845#ifdef PC98
846	iod.if_type = GET_IFTYPE(flags);
847	if ((iod.if_type < 0 || iod.if_type > COM_IF_END1) &&
848	    (iod.if_type < 0x10 || iod.if_type > COM_IF_END2))
849			return ENXIO;
850#endif
851
852	rid = xrid;
853#ifdef PC98
854	if (IS_8251(iod.if_type)) {
855		port = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid,
856					      RF_ACTIVE);
857	} else if (iod.if_type == COM_IF_MODEM_CARD ||
858		   iod.if_type == COM_IF_RSA98III ||
859		   isa_get_vendorid(dev)) {
860		port = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 0, ~0,
861		  if_16550a_type[iod.if_type & 0x0f].iatsz, RF_ACTIVE);
862	} else {
863		port = isa_alloc_resourcev(dev, SYS_RES_IOPORT, &rid,
864		   if_16550a_type[iod.if_type & 0x0f].iat,
865		   if_16550a_type[iod.if_type & 0x0f].iatsz, RF_ACTIVE);
866	}
867#else
868	port = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid,
869				  0, ~0, IO_COMSIZE, RF_ACTIVE);
870#endif
871	if (!port)
872		return (ENXIO);
873#ifdef PC98
874	if (!IS_8251(iod.if_type)) {
875		if (isa_load_resourcev(port,
876		       if_16550a_type[iod.if_type & 0x0f].iat,
877		       if_16550a_type[iod.if_type & 0x0f].iatsz) != 0) {
878			bus_release_resource(dev, SYS_RES_IOPORT, rid, port);
879			return ENXIO;
880		}
881	}
882#endif
883
884	com = malloc(sizeof(*com), M_DEVBUF, M_NOWAIT | M_ZERO);
885	if (com == NULL) {
886		bus_release_resource(dev, SYS_RES_IOPORT, rid, port);
887		return (ENOMEM);
888	}
889	device_set_softc(dev, com);
890	com->bst = rman_get_bustag(port);
891	com->bsh = rman_get_bushandle(port);
892#ifdef PC98
893	if (!IS_8251(iod.if_type) && rclk == 0)
894		rclk = if_16550a_type[iod.if_type & 0x0f].rclk;
895#else
896	if (rclk == 0)
897		rclk = DEFAULT_RCLK;
898#endif
899	com->rclk = rclk;
900
901	while (sio_inited != 2)
902		if (atomic_cmpset_int(&sio_inited, 0, 1)) {
903			mtx_init(&sio_lock, sio_driver_name, NULL,
904			    (comconsole != -1) ?
905			    MTX_SPIN | MTX_QUIET : MTX_SPIN);
906			atomic_store_rel_int(&sio_inited, 2);
907		}
908
909#if 0
910	/*
911	 * XXX this is broken - when we are first called, there are no
912	 * previously configured IO ports.  We could hard code
913	 * 0x3f8, 0x2f8, 0x3e8, 0x2e8 etc but that's probably worse.
914	 * This code has been doing nothing since the conversion since
915	 * "count" is zero the first time around.
916	 */
917	if (!already_init) {
918		/*
919		 * Turn off MCR_IENABLE for all likely serial ports.  An unused
920		 * port with its MCR_IENABLE gate open will inhibit interrupts
921		 * from any used port that shares the interrupt vector.
922		 * XXX the gate enable is elsewhere for some multiports.
923		 */
924		device_t *devs;
925		int count, i, xioport;
926#ifdef PC98
927		int xiftype;
928#endif
929
930		devclass_get_devices(sio_devclass, &devs, &count);
931#ifdef PC98
932		for (i = 0; i < count; i++) {
933			xdev = devs[i];
934			xioport = bus_get_resource_start(xdev, SYS_RES_IOPORT, 0);
935			xiftype = GET_IFTYPE(device_get_flags(xdev));
936			if (device_is_enabled(xdev) && xioport > 0) {
937			    if (IS_8251(xiftype))
938				outb((xioport & 0xff00) | PC98SIO_cmd_port(xiftype & 0x0f), 0xf2);
939			    else
940				outb(xioport + if_16550a_type[xiftype & 0x0f].iat[com_mcr], 0);
941			}
942		}
943#else
944		for (i = 0; i < count; i++) {
945			xdev = devs[i];
946			if (device_is_enabled(xdev) &&
947			    bus_get_resource(xdev, SYS_RES_IOPORT, 0, &xioport,
948					     NULL) == 0)
949				outb(xioport + com_mcr, 0);
950		}
951#endif
952		free(devs, M_TEMP);
953		already_init = TRUE;
954	}
955#endif
956
957	if (COM_LLCONSOLE(flags)) {
958		printf("sio%d: reserved for low-level i/o\n",
959		       device_get_unit(dev));
960		bus_release_resource(dev, SYS_RES_IOPORT, rid, port);
961		device_set_softc(dev, NULL);
962		free(com, M_DEVBUF);
963		return (ENXIO);
964	}
965
966#ifdef PC98
967	DELAY(10);
968
969	/*
970	 * If the port is i8251 UART (internal, B98_01)
971	 */
972	if (pc98_check_if_type(dev, &iod) == -1) {
973		bus_release_resource(dev, SYS_RES_IOPORT, rid, port);
974		device_set_softc(dev, NULL);
975		free(com, M_DEVBUF);
976		return (ENXIO);
977	}
978	if (iod.irq > 0)
979		bus_set_resource(dev, SYS_RES_IRQ, 0, iod.irq, 1);
980	if (IS_8251(iod.if_type)) {
981		outb(iod.cmd, 0);
982		DELAY(10);
983		outb(iod.cmd, 0);
984		DELAY(10);
985		outb(iod.cmd, 0);
986		DELAY(10);
987		outb(iod.cmd, CMD8251_RESET);
988		DELAY(1000);		/* for a while...*/
989		outb(iod.cmd, 0xf2);	/* MODE (dummy) */
990		DELAY(10);
991		outb(iod.cmd, 0x01);	/* CMD (dummy) */
992		DELAY(1000);		/* for a while...*/
993		if (( inb(iod.sts) & STS8251_TxEMP ) == 0 ) {
994		    result = (ENXIO);
995		}
996		if (if_8251_type[iod.if_type & 0x0f].check_irq) {
997		    COM_INT_DISABLE
998		    tmp = ( inb( iod.ctrl ) & ~(IEN_Rx|IEN_TxEMP|IEN_Tx));
999		    outb( iod.ctrl, tmp|IEN_TxEMP );
1000		    DELAY(10);
1001		    result = isa_irq_pending() ? 0 : ENXIO;
1002		    outb( iod.ctrl, tmp );
1003		    COM_INT_ENABLE
1004		} else {
1005		    /*
1006		     * B98_01 doesn't activate TxEMP interrupt line
1007		     * when being reset, so we can't check irq pending.
1008		     */
1009		    result = 0;
1010		}
1011		if (epson_machine_id==0x20) {	/* XXX */
1012		    result = 0;
1013		}
1014		bus_release_resource(dev, SYS_RES_IOPORT, rid, port);
1015		if (result) {
1016			device_set_softc(dev, NULL);
1017			free(com, M_DEVBUF);
1018		}
1019		return result;
1020	}
1021#endif /* PC98 */
1022	/*
1023	 * If the device is on a multiport card and has an AST/4
1024	 * compatible interrupt control register, initialize this
1025	 * register and prepare to leave MCR_IENABLE clear in the mcr.
1026	 * Otherwise, prepare to set MCR_IENABLE in the mcr.
1027	 * Point idev to the device struct giving the correct id_irq.
1028	 * This is the struct for the master device if there is one.
1029	 */
1030	idev = dev;
1031	mcr_image = MCR_IENABLE;
1032#ifdef COM_MULTIPORT
1033	if (COM_ISMULTIPORT(flags)) {
1034#ifndef PC98
1035		Port_t xiobase;
1036		u_long io;
1037#endif
1038
1039		idev = devclass_get_device(sio_devclass, COM_MPMASTER(flags));
1040		if (idev == NULL) {
1041			printf("sio%d: master device %d not configured\n",
1042			       device_get_unit(dev), COM_MPMASTER(flags));
1043			idev = dev;
1044		}
1045#ifndef PC98
1046		if (!COM_NOTAST4(flags)) {
1047			if (bus_get_resource(idev, SYS_RES_IOPORT, 0, &io,
1048					     NULL) == 0) {
1049				xiobase = io;
1050				if (bus_get_resource(idev, SYS_RES_IRQ, 0,
1051				    NULL, NULL) == 0)
1052					outb(xiobase + com_scr, 0x80);
1053				else
1054					outb(xiobase + com_scr, 0);
1055			}
1056			mcr_image = 0;
1057		}
1058#endif
1059	}
1060#endif /* COM_MULTIPORT */
1061	if (bus_get_resource(idev, SYS_RES_IRQ, 0, NULL, NULL) != 0)
1062		mcr_image = 0;
1063
1064	bzero(failures, sizeof failures);
1065	iobase = rman_get_start(port);
1066
1067#ifdef PC98
1068        if (iod.if_type == COM_IF_RSA98III) {
1069		mcr_image = 0;
1070
1071		outb(iobase + rsa_msr,   0x04);
1072		outb(iobase + rsa_frr,   0x00);
1073		if ((inb(iobase + rsa_srr) & 0x36) != 0x36) {
1074			bus_release_resource(dev, SYS_RES_IOPORT, rid, port);
1075			device_set_softc(dev, NULL);
1076			free(com, M_DEVBUF);
1077			return (ENXIO);
1078		}
1079		outb(iobase + rsa_ier,   0x00);
1080		outb(iobase + rsa_frr,   0x00);
1081		outb(iobase + rsa_tivsr, 0x00);
1082		outb(iobase + rsa_tcr,   0x00);
1083	}
1084
1085	tmp = if_16550a_type[iod.if_type & 0x0f].irr_write;
1086	if (tmp != -1) {
1087	    /* MC16550II */
1088	    int	irqout;
1089	    switch (isa_get_irq(idev)) {
1090	    case 3: irqout = 4; break;
1091	    case 5: irqout = 5; break;
1092	    case 6: irqout = 6; break;
1093	    case 12: irqout = 7; break;
1094	    default:
1095		printf("sio%d: irq configuration error\n",
1096		       device_get_unit(dev));
1097		bus_release_resource(dev, SYS_RES_IOPORT, rid, port);
1098		device_set_softc(dev, NULL);
1099		free(com, M_DEVBUF);
1100		return (ENXIO);
1101	    }
1102	    outb((iobase & 0x00ff) | tmp, irqout);
1103	}
1104#endif
1105
1106	/*
1107	 * We don't want to get actual interrupts, just masked ones.
1108	 * Interrupts from this line should already be masked in the ICU,
1109	 * but mask them in the processor as well in case there are some
1110	 * (misconfigured) shared interrupts.
1111	 */
1112	mtx_lock_spin(&sio_lock);
1113/* EXTRA DELAY? */
1114
1115	/*
1116	 * Initialize the speed and the word size and wait long enough to
1117	 * drain the maximum of 16 bytes of junk in device output queues.
1118	 * The speed is undefined after a master reset and must be set
1119	 * before relying on anything related to output.  There may be
1120	 * junk after a (very fast) soft reboot and (apparently) after
1121	 * master reset.
1122	 * XXX what about the UART bug avoided by waiting in comparam()?
1123	 * We don't want to to wait long enough to drain at 2 bps.
1124	 */
1125	if (iobase == siocniobase)
1126		DELAY((16 + 1) * 1000000 / (comdefaultrate / 10));
1127	else {
1128		sio_setreg(com, com_cfcr, CFCR_DLAB | CFCR_8BITS);
1129		divisor = siodivisor(rclk, SIO_TEST_SPEED);
1130		sio_setreg(com, com_dlbl, divisor & 0xff);
1131		sio_setreg(com, com_dlbh, divisor >> 8);
1132		sio_setreg(com, com_cfcr, CFCR_8BITS);
1133		DELAY((16 + 1) * 1000000 / (SIO_TEST_SPEED / 10));
1134	}
1135
1136	/*
1137	 * Enable the interrupt gate and disable device interupts.  This
1138	 * should leave the device driving the interrupt line low and
1139	 * guarantee an edge trigger if an interrupt can be generated.
1140	 */
1141/* EXTRA DELAY? */
1142	sio_setreg(com, com_mcr, mcr_image);
1143	sio_setreg(com, com_ier, 0);
1144	DELAY(1000);		/* XXX */
1145	irqmap[0] = isa_irq_pending();
1146
1147	/*
1148	 * Attempt to set loopback mode so that we can send a null byte
1149	 * without annoying any external device.
1150	 */
1151/* EXTRA DELAY? */
1152	sio_setreg(com, com_mcr, mcr_image | MCR_LOOPBACK);
1153
1154	/*
1155	 * Attempt to generate an output interrupt.  On 8250's, setting
1156	 * IER_ETXRDY generates an interrupt independent of the current
1157	 * setting and independent of whether the THR is empty.  On 16450's,
1158	 * setting IER_ETXRDY generates an interrupt independent of the
1159	 * current setting.  On 16550A's, setting IER_ETXRDY only
1160	 * generates an interrupt when IER_ETXRDY is not already set.
1161	 */
1162	sio_setreg(com, com_ier, IER_ETXRDY);
1163#ifdef PC98
1164        if (iod.if_type == COM_IF_RSA98III)
1165		outb(iobase + rsa_ier, 0x04);
1166#endif
1167
1168	/*
1169	 * On some 16x50 incompatibles, setting IER_ETXRDY doesn't generate
1170	 * an interrupt.  They'd better generate one for actually doing
1171	 * output.  Loopback may be broken on the same incompatibles but
1172	 * it's unlikely to do more than allow the null byte out.
1173	 */
1174	sio_setreg(com, com_data, 0);
1175	if (iobase == siocniobase)
1176		DELAY((1 + 2) * 1000000 / (comdefaultrate / 10));
1177	else
1178		DELAY((1 + 2) * 1000000 / (SIO_TEST_SPEED / 10));
1179
1180	/*
1181	 * Turn off loopback mode so that the interrupt gate works again
1182	 * (MCR_IENABLE was hidden).  This should leave the device driving
1183	 * an interrupt line high.  It doesn't matter if the interrupt
1184	 * line oscillates while we are not looking at it, since interrupts
1185	 * are disabled.
1186	 */
1187/* EXTRA DELAY? */
1188	sio_setreg(com, com_mcr, mcr_image);
1189
1190	/*
1191	 * It seems my Xircom CBEM56G Cardbus modem wants to be reset
1192	 * to 8 bits *again*, or else probe test 0 will fail.
1193	 * gwk@sgi.com, 4/19/2001
1194	 */
1195	sio_setreg(com, com_cfcr, CFCR_8BITS);
1196
1197	/*
1198	 * Some PCMCIA cards (Palido 321s, DC-1S, ...) have the "TXRDY bug",
1199	 * so we probe for a buggy IIR_TXRDY implementation even in the
1200	 * noprobe case.  We don't probe for it in the !noprobe case because
1201	 * noprobe is always set for PCMCIA cards and the problem is not
1202	 * known to affect any other cards.
1203	 */
1204	if (noprobe) {
1205		/* Read IIR a few times. */
1206		for (fn = 0; fn < 2; fn ++) {
1207			DELAY(10000);
1208			failures[6] = sio_getreg(com, com_iir);
1209		}
1210
1211		/* IIR_TXRDY should be clear.  Is it? */
1212		result = 0;
1213		if (failures[6] & IIR_TXRDY) {
1214			/*
1215			 * No.  We seem to have the bug.  Does our fix for
1216			 * it work?
1217			 */
1218			sio_setreg(com, com_ier, 0);
1219			if (sio_getreg(com, com_iir) & IIR_NOPEND) {
1220				/* Yes.  We discovered the TXRDY bug! */
1221				SET_FLAG(dev, COM_C_IIR_TXRDYBUG);
1222			} else {
1223				/* No.  Just fail.  XXX */
1224				result = ENXIO;
1225				sio_setreg(com, com_mcr, 0);
1226			}
1227		} else {
1228			/* Yes.  No bug. */
1229			CLR_FLAG(dev, COM_C_IIR_TXRDYBUG);
1230		}
1231		sio_setreg(com, com_ier, 0);
1232		sio_setreg(com, com_cfcr, CFCR_8BITS);
1233		mtx_unlock_spin(&sio_lock);
1234		bus_release_resource(dev, SYS_RES_IOPORT, rid, port);
1235		if (iobase == siocniobase)
1236			result = 0;
1237		if (result != 0) {
1238			device_set_softc(dev, NULL);
1239			free(com, M_DEVBUF);
1240		}
1241		return (result);
1242	}
1243
1244	/*
1245	 * Check that
1246	 *	o the CFCR, IER and MCR in UART hold the values written to them
1247	 *	  (the values happen to be all distinct - this is good for
1248	 *	  avoiding false positive tests from bus echoes).
1249	 *	o an output interrupt is generated and its vector is correct.
1250	 *	o the interrupt goes away when the IIR in the UART is read.
1251	 */
1252/* EXTRA DELAY? */
1253	failures[0] = sio_getreg(com, com_cfcr) - CFCR_8BITS;
1254	failures[1] = sio_getreg(com, com_ier) - IER_ETXRDY;
1255	failures[2] = sio_getreg(com, com_mcr) - mcr_image;
1256	DELAY(10000);		/* Some internal modems need this time */
1257	irqmap[1] = isa_irq_pending();
1258	failures[4] = (sio_getreg(com, com_iir) & IIR_IMASK) - IIR_TXRDY;
1259#ifdef PC98
1260        if (iod.if_type == COM_IF_RSA98III)
1261		inb(iobase + rsa_srr);
1262#endif
1263	DELAY(1000);		/* XXX */
1264	irqmap[2] = isa_irq_pending();
1265	failures[6] = (sio_getreg(com, com_iir) & IIR_IMASK) - IIR_NOPEND;
1266#ifdef PC98
1267        if (iod.if_type == COM_IF_RSA98III)
1268		inb(iobase + rsa_srr);
1269#endif
1270
1271	/*
1272	 * Turn off all device interrupts and check that they go off properly.
1273	 * Leave MCR_IENABLE alone.  For ports without a master port, it gates
1274	 * the OUT2 output of the UART to
1275	 * the ICU input.  Closing the gate would give a floating ICU input
1276	 * (unless there is another device driving it) and spurious interrupts.
1277	 * (On the system that this was first tested on, the input floats high
1278	 * and gives a (masked) interrupt as soon as the gate is closed.)
1279	 */
1280	sio_setreg(com, com_ier, 0);
1281	sio_setreg(com, com_cfcr, CFCR_8BITS);	/* dummy to avoid bus echo */
1282	failures[7] = sio_getreg(com, com_ier);
1283#ifdef PC98
1284        if (iod.if_type == COM_IF_RSA98III)
1285		outb(iobase + rsa_ier, 0x00);
1286#endif
1287	DELAY(1000);		/* XXX */
1288	irqmap[3] = isa_irq_pending();
1289	failures[9] = (sio_getreg(com, com_iir) & IIR_IMASK) - IIR_NOPEND;
1290#ifdef PC98
1291        if (iod.if_type == COM_IF_RSA98III) {
1292		inb(iobase + rsa_srr);
1293		outb(iobase + rsa_frr, 0x00);
1294	}
1295#endif
1296
1297	mtx_unlock_spin(&sio_lock);
1298
1299	irqs = irqmap[1] & ~irqmap[0];
1300	if (bus_get_resource(idev, SYS_RES_IRQ, 0, &xirq, NULL) == 0 &&
1301	    ((1 << xirq) & irqs) == 0) {
1302		printf(
1303		"sio%d: configured irq %ld not in bitmap of probed irqs %#x\n",
1304		    device_get_unit(dev), xirq, irqs);
1305		printf(
1306		"sio%d: port may not be enabled\n",
1307		    device_get_unit(dev));
1308	}
1309	if (bootverbose)
1310		printf("sio%d: irq maps: %#x %#x %#x %#x\n",
1311		    device_get_unit(dev),
1312		    irqmap[0], irqmap[1], irqmap[2], irqmap[3]);
1313
1314	result = 0;
1315	for (fn = 0; fn < sizeof failures; ++fn)
1316		if (failures[fn]) {
1317			sio_setreg(com, com_mcr, 0);
1318			result = ENXIO;
1319			if (bootverbose) {
1320				printf("sio%d: probe failed test(s):",
1321				    device_get_unit(dev));
1322				for (fn = 0; fn < sizeof failures; ++fn)
1323					if (failures[fn])
1324						printf(" %d", fn);
1325				printf("\n");
1326			}
1327			break;
1328		}
1329	bus_release_resource(dev, SYS_RES_IOPORT, rid, port);
1330	if (iobase == siocniobase)
1331		result = 0;
1332	if (result != 0) {
1333		device_set_softc(dev, NULL);
1334		free(com, M_DEVBUF);
1335	}
1336	return (result);
1337}
1338
1339#ifdef COM_ESP
1340static int
1341espattach(com, esp_port)
1342	struct com_s		*com;
1343	Port_t			esp_port;
1344{
1345	u_char	dips;
1346	u_char	val;
1347
1348	/*
1349	 * Check the ESP-specific I/O port to see if we're an ESP
1350	 * card.  If not, return failure immediately.
1351	 */
1352	if ((inb(esp_port) & 0xf3) == 0) {
1353		printf(" port 0x%x is not an ESP board?\n", esp_port);
1354		return (0);
1355	}
1356
1357	/*
1358	 * We've got something that claims to be a Hayes ESP card.
1359	 * Let's hope so.
1360	 */
1361
1362	/* Get the dip-switch configuration */
1363#ifdef PC98
1364	outb(esp_port + ESP98_CMD1, ESP_GETDIPS);
1365	dips = inb(esp_port + ESP98_STATUS1);
1366#else
1367	outb(esp_port + ESP_CMD1, ESP_GETDIPS);
1368	dips = inb(esp_port + ESP_STATUS1);
1369#endif
1370
1371	/*
1372	 * Bits 0,1 of dips say which COM port we are.
1373	 */
1374#ifdef PC98
1375	if ((rman_get_start(com->ioportres) & 0xff) ==
1376	    likely_com_ports[dips & 0x03])
1377#else
1378	if (rman_get_start(com->ioportres) == likely_com_ports[dips & 0x03])
1379#endif
1380		printf(" : ESP");
1381	else {
1382		printf(" esp_port has com %d\n", dips & 0x03);
1383		return (0);
1384	}
1385
1386	/*
1387	 * Check for ESP version 2.0 or later:  bits 4,5,6 = 010.
1388	 */
1389#ifdef PC98
1390	outb(esp_port + ESP98_CMD1, ESP_GETTEST);
1391	val = inb(esp_port + ESP98_STATUS1);	/* clear reg 1 */
1392	val = inb(esp_port + ESP98_STATUS2);
1393#else
1394	outb(esp_port + ESP_CMD1, ESP_GETTEST);
1395	val = inb(esp_port + ESP_STATUS1);	/* clear reg 1 */
1396	val = inb(esp_port + ESP_STATUS2);
1397#endif
1398	if ((val & 0x70) < 0x20) {
1399		printf("-old (%o)", val & 0x70);
1400		return (0);
1401	}
1402
1403	/*
1404	 * Check for ability to emulate 16550:  bit 7 == 1
1405	 */
1406	if ((dips & 0x80) == 0) {
1407		printf(" slave");
1408		return (0);
1409	}
1410
1411	/*
1412	 * Okay, we seem to be a Hayes ESP card.  Whee.
1413	 */
1414	com->esp = TRUE;
1415	com->esp_port = esp_port;
1416	return (1);
1417}
1418#endif /* COM_ESP */
1419
1420int
1421sioattach(dev, xrid, rclk)
1422	device_t	dev;
1423	int		xrid;
1424	u_long		rclk;
1425{
1426	struct com_s	*com;
1427#ifdef COM_ESP
1428	Port_t		*espp;
1429#endif
1430	Port_t		iobase;
1431	int		minorbase;
1432	int		unit;
1433	u_int		flags;
1434	int		rid;
1435	struct resource *port;
1436	int		ret;
1437#ifdef PC98
1438	u_char		*obuf;
1439	u_long		obufsize;
1440	int		if_type = GET_IFTYPE(device_get_flags(dev));
1441#endif
1442
1443	rid = xrid;
1444#ifdef PC98
1445	if (IS_8251(if_type)) {
1446		port = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid,
1447					      RF_ACTIVE);
1448	} else if (if_type == COM_IF_MODEM_CARD ||
1449		   if_type == COM_IF_RSA98III ||
1450		   isa_get_vendorid(dev)) {
1451		port = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 0, ~0,
1452			  if_16550a_type[if_type & 0x0f].iatsz, RF_ACTIVE);
1453	} else {
1454		port = isa_alloc_resourcev(dev, SYS_RES_IOPORT, &rid,
1455			   if_16550a_type[if_type & 0x0f].iat,
1456			   if_16550a_type[if_type & 0x0f].iatsz, RF_ACTIVE);
1457	}
1458#else
1459	port = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid,
1460				  0, ~0, IO_COMSIZE, RF_ACTIVE);
1461#endif
1462	if (!port)
1463		return (ENXIO);
1464#ifdef PC98
1465	if (!IS_8251(if_type)) {
1466		if (isa_load_resourcev(port,
1467			       if_16550a_type[if_type & 0x0f].iat,
1468			       if_16550a_type[if_type & 0x0f].iatsz) != 0) {
1469			bus_release_resource(dev, SYS_RES_IOPORT, rid, port);
1470			return ENXIO;
1471		}
1472	}
1473#endif
1474
1475	iobase = rman_get_start(port);
1476	unit = device_get_unit(dev);
1477	com = device_get_softc(dev);
1478	flags = device_get_flags(dev);
1479
1480	if (unit >= sio_numunits)
1481		sio_numunits = unit + 1;
1482
1483#ifdef PC98
1484	obufsize = 256;
1485	if (if_type == COM_IF_RSA98III)
1486		obufsize = 2048;
1487	if ((obuf = malloc(obufsize * 2, M_DEVBUF, M_NOWAIT)) == NULL) {
1488		bus_release_resource(dev, SYS_RES_IOPORT, rid, port);
1489		return ENXIO;
1490	}
1491	bzero(obuf, obufsize * 2);
1492#endif
1493
1494	/*
1495	 * sioprobe() has initialized the device registers as follows:
1496	 *	o cfcr = CFCR_8BITS.
1497	 *	  It is most important that CFCR_DLAB is off, so that the
1498	 *	  data port is not hidden when we enable interrupts.
1499	 *	o ier = 0.
1500	 *	  Interrupts are only enabled when the line is open.
1501	 *	o mcr = MCR_IENABLE, or 0 if the port has AST/4 compatible
1502	 *	  interrupt control register or the config specifies no irq.
1503	 *	  Keeping MCR_DTR and MCR_RTS off might stop the external
1504	 *	  device from sending before we are ready.
1505	 */
1506	bzero(com, sizeof *com);
1507	com->unit = unit;
1508	com->ioportres = port;
1509	com->ioportrid = rid;
1510	com->bst = rman_get_bustag(port);
1511	com->bsh = rman_get_bushandle(port);
1512	com->cfcr_image = CFCR_8BITS;
1513	com->loses_outints = COM_LOSESOUTINTS(flags) != 0;
1514	com->no_irq = bus_get_resource(dev, SYS_RES_IRQ, 0, NULL, NULL) != 0;
1515	com->tx_fifo_size = 1;
1516#ifdef PC98
1517	com->obufsize = obufsize;
1518	com->obuf1 = obuf;
1519	com->obuf2 = obuf + obufsize;
1520#endif
1521	com->obufs[0].l_head = com->obuf1;
1522	com->obufs[1].l_head = com->obuf2;
1523
1524#ifdef PC98
1525	com->pc98_if_type = if_type;
1526
1527	if (IS_8251(if_type)) {
1528	    pc98_set_ioport(com);
1529
1530	    if (if_type == COM_IF_INTERNAL && pc98_check_8251fifo()) {
1531		com->pc98_8251fifo = 1;
1532		com->pc98_8251fifo_enable = 0;
1533	    }
1534	} else {
1535	    bus_addr_t	*iat = if_16550a_type[if_type & 0x0f].iat;
1536
1537	    com->data_port = iobase + iat[com_data];
1538	    com->int_ctl_port = iobase + iat[com_ier];
1539	    com->int_id_port = iobase + iat[com_iir];
1540	    com->modem_ctl_port = iobase + iat[com_mcr];
1541	    com->mcr_image = inb(com->modem_ctl_port);
1542	    com->line_status_port = iobase + iat[com_lsr];
1543	    com->modem_status_port = iobase + iat[com_msr];
1544	}
1545#else /* not PC98 */
1546	com->data_port = iobase + com_data;
1547	com->int_ctl_port = iobase + com_ier;
1548	com->int_id_port = iobase + com_iir;
1549	com->modem_ctl_port = iobase + com_mcr;
1550	com->mcr_image = inb(com->modem_ctl_port);
1551	com->line_status_port = iobase + com_lsr;
1552	com->modem_status_port = iobase + com_msr;
1553#endif
1554
1555#ifdef PC98
1556	if (!IS_8251(if_type) && rclk == 0)
1557		rclk = if_16550a_type[if_type & 0x0f].rclk;
1558#else
1559	if (rclk == 0)
1560		rclk = DEFAULT_RCLK;
1561#endif
1562	com->rclk = rclk;
1563
1564	/*
1565	 * We don't use all the flags from <sys/ttydefaults.h> since they
1566	 * are only relevant for logins.  It's important to have echo off
1567	 * initially so that the line doesn't start blathering before the
1568	 * echo flag can be turned off.
1569	 */
1570	com->it_in.c_iflag = 0;
1571	com->it_in.c_oflag = 0;
1572	com->it_in.c_cflag = TTYDEF_CFLAG;
1573	com->it_in.c_lflag = 0;
1574	if (unit == comconsole) {
1575#ifdef PC98
1576		if (IS_8251(com->pc98_if_type))
1577			DELAY(100000);
1578#endif
1579		com->it_in.c_iflag = TTYDEF_IFLAG;
1580		com->it_in.c_oflag = TTYDEF_OFLAG;
1581		com->it_in.c_cflag = TTYDEF_CFLAG | CLOCAL;
1582		com->it_in.c_lflag = TTYDEF_LFLAG;
1583		com->lt_out.c_cflag = com->lt_in.c_cflag = CLOCAL;
1584		com->lt_out.c_ispeed = com->lt_out.c_ospeed =
1585		com->lt_in.c_ispeed = com->lt_in.c_ospeed =
1586		com->it_in.c_ispeed = com->it_in.c_ospeed = comdefaultrate;
1587	} else
1588		com->it_in.c_ispeed = com->it_in.c_ospeed = TTYDEF_SPEED;
1589	if (siosetwater(com, com->it_in.c_ispeed) != 0) {
1590		mtx_unlock_spin(&sio_lock);
1591		/*
1592		 * Leave i/o resources allocated if this is a `cn'-level
1593		 * console, so that other devices can't snarf them.
1594		 */
1595		if (iobase != siocniobase)
1596			bus_release_resource(dev, SYS_RES_IOPORT, rid, port);
1597		return (ENOMEM);
1598	}
1599	mtx_unlock_spin(&sio_lock);
1600	termioschars(&com->it_in);
1601	com->it_out = com->it_in;
1602
1603	/* attempt to determine UART type */
1604	printf("sio%d: type", unit);
1605
1606
1607#ifndef PC98
1608	if (!COM_ISMULTIPORT(flags) &&
1609	    !COM_IIR_TXRDYBUG(flags) && !COM_NOSCR(flags)) {
1610		u_char	scr;
1611		u_char	scr1;
1612		u_char	scr2;
1613
1614		scr = sio_getreg(com, com_scr);
1615		sio_setreg(com, com_scr, 0xa5);
1616		scr1 = sio_getreg(com, com_scr);
1617		sio_setreg(com, com_scr, 0x5a);
1618		scr2 = sio_getreg(com, com_scr);
1619		sio_setreg(com, com_scr, scr);
1620		if (scr1 != 0xa5 || scr2 != 0x5a) {
1621			printf(" 8250 or not responding");
1622			goto determined_type;
1623		}
1624	}
1625#endif /* !PC98 */
1626#ifdef PC98
1627	if (IS_8251(com->pc98_if_type)) {
1628	    if (com->pc98_8251fifo && !COM_NOFIFO(flags))
1629		com->tx_fifo_size = 16;
1630	    com_int_TxRx_disable( com );
1631	    com_cflag_and_speed_set( com, com->it_in.c_cflag, comdefaultrate );
1632	    com_tiocm_bic( com, TIOCM_DTR|TIOCM_RTS|TIOCM_LE );
1633	    com_send_break_off( com );
1634
1635	    if (com->pc98_if_type == COM_IF_INTERNAL) {
1636		printf(" (internal%s%s)",
1637		       com->pc98_8251fifo ? " fifo" : "",
1638		       PC98SIO_baud_rate_port(com->pc98_if_type) != -1 ?
1639		       " v-fast" : "");
1640	    } else {
1641		printf(" 8251%s", if_8251_type[com->pc98_if_type & 0x0f].name);
1642	    }
1643	} else {
1644#endif /* PC98 */
1645	sio_setreg(com, com_fifo, FIFO_ENABLE | FIFO_RX_HIGH);
1646	DELAY(100);
1647	switch (inb(com->int_id_port) & IIR_FIFO_MASK) {
1648	case FIFO_RX_LOW:
1649		printf(" 16450");
1650		break;
1651	case FIFO_RX_MEDL:
1652		printf(" 16450?");
1653		break;
1654	case FIFO_RX_MEDH:
1655		printf(" 16550?");
1656		break;
1657	case FIFO_RX_HIGH:
1658		if (COM_NOFIFO(flags)) {
1659			printf(" 16550A fifo disabled");
1660			break;
1661		}
1662		com->hasfifo = TRUE;
1663#ifdef PC98
1664		if (com->pc98_if_type == COM_IF_RSA98III) {
1665			com->tx_fifo_size = 2048;
1666			com->rsabase = iobase;
1667			outb(com->rsabase + rsa_ier, 0x00);
1668			outb(com->rsabase + rsa_frr, 0x00);
1669		}
1670#else
1671		if (COM_ST16650A(flags)) {
1672			printf(" ST16650A");
1673			com->st16650a = TRUE;
1674			com->tx_fifo_size = 32;
1675			break;
1676		}
1677		if (COM_TI16754(flags)) {
1678			printf(" TI16754");
1679			com->tx_fifo_size = 64;
1680			break;
1681		}
1682#endif
1683		printf(" 16550A");
1684#ifdef COM_ESP
1685#ifdef PC98
1686		if (com->pc98_if_type == COM_IF_ESP98)
1687#endif
1688		for (espp = likely_esp_ports; *espp != 0; espp++)
1689			if (espattach(com, *espp)) {
1690				com->tx_fifo_size = 1024;
1691				break;
1692			}
1693		if (com->esp)
1694			break;
1695#endif
1696#ifdef PC98
1697		com->tx_fifo_size = 16;
1698#else
1699		com->tx_fifo_size = COM_FIFOSIZE(flags);
1700		if (com->tx_fifo_size == 0)
1701			com->tx_fifo_size = 16;
1702		else
1703			printf(" lookalike with %u bytes FIFO",
1704			       com->tx_fifo_size);
1705#endif
1706		break;
1707	}
1708
1709#ifdef PC98
1710	if (com->pc98_if_type == COM_IF_RSB3000) {
1711	    /* Set RSB-2000/3000 Extended Buffer mode. */
1712	    u_char lcr;
1713	    lcr = sio_getreg(com, com_cfcr);
1714	    sio_setreg(com, com_cfcr, lcr | CFCR_DLAB);
1715	    sio_setreg(com, com_emr, EMR_EXBUFF | EMR_EFMODE);
1716	    sio_setreg(com, com_cfcr, lcr);
1717	}
1718#endif
1719
1720#ifdef COM_ESP
1721	if (com->esp) {
1722		/*
1723		 * Set 16550 compatibility mode.
1724		 * We don't use the ESP_MODE_SCALE bit to increase the
1725		 * fifo trigger levels because we can't handle large
1726		 * bursts of input.
1727		 * XXX flow control should be set in comparam(), not here.
1728		 */
1729#ifdef PC98
1730		outb(com->esp_port + ESP98_CMD1, ESP_SETMODE);
1731		outb(com->esp_port + ESP98_CMD2, ESP_MODE_RTS | ESP_MODE_FIFO);
1732#else
1733		outb(com->esp_port + ESP_CMD1, ESP_SETMODE);
1734		outb(com->esp_port + ESP_CMD2, ESP_MODE_RTS | ESP_MODE_FIFO);
1735#endif
1736
1737		/* Set RTS/CTS flow control. */
1738#ifdef PC98
1739		outb(com->esp_port + ESP98_CMD1, ESP_SETFLOWTYPE);
1740		outb(com->esp_port + ESP98_CMD2, ESP_FLOW_RTS);
1741		outb(com->esp_port + ESP98_CMD2, ESP_FLOW_CTS);
1742#else
1743		outb(com->esp_port + ESP_CMD1, ESP_SETFLOWTYPE);
1744		outb(com->esp_port + ESP_CMD2, ESP_FLOW_RTS);
1745		outb(com->esp_port + ESP_CMD2, ESP_FLOW_CTS);
1746#endif
1747
1748		/* Set flow-control levels. */
1749#ifdef PC98
1750		outb(com->esp_port + ESP98_CMD1, ESP_SETRXFLOW);
1751		outb(com->esp_port + ESP98_CMD2, HIBYTE(768));
1752		outb(com->esp_port + ESP98_CMD2, LOBYTE(768));
1753		outb(com->esp_port + ESP98_CMD2, HIBYTE(512));
1754		outb(com->esp_port + ESP98_CMD2, LOBYTE(512));
1755#else
1756		outb(com->esp_port + ESP_CMD1, ESP_SETRXFLOW);
1757		outb(com->esp_port + ESP_CMD2, HIBYTE(768));
1758		outb(com->esp_port + ESP_CMD2, LOBYTE(768));
1759		outb(com->esp_port + ESP_CMD2, HIBYTE(512));
1760		outb(com->esp_port + ESP_CMD2, LOBYTE(512));
1761#endif
1762
1763#ifdef PC98
1764                /* Set UART clock prescaler. */
1765                outb(com->esp_port + ESP98_CMD1, ESP_SETCLOCK);
1766                outb(com->esp_port + ESP98_CMD2, 2);	/* 4 times */
1767#endif
1768	}
1769#endif /* COM_ESP */
1770	sio_setreg(com, com_fifo, 0);
1771#ifdef PC98
1772	printf("%s", if_16550a_type[com->pc98_if_type & 0x0f].name);
1773#else
1774determined_type: ;
1775#endif
1776
1777#ifdef COM_MULTIPORT
1778	if (COM_ISMULTIPORT(flags)) {
1779		device_t masterdev;
1780
1781		com->multiport = TRUE;
1782		printf(" (multiport");
1783		if (unit == COM_MPMASTER(flags))
1784			printf(" master");
1785		printf(")");
1786		masterdev = devclass_get_device(sio_devclass,
1787		    COM_MPMASTER(flags));
1788		com->no_irq = (masterdev == NULL || bus_get_resource(masterdev,
1789		    SYS_RES_IRQ, 0, NULL, NULL) != 0);
1790	 }
1791#endif /* COM_MULTIPORT */
1792#ifdef PC98
1793	}
1794#endif
1795	if (unit == comconsole)
1796		printf(", console");
1797	if (COM_IIR_TXRDYBUG(flags))
1798		printf(" with a buggy IIR_TXRDY implementation");
1799	printf("\n");
1800
1801	if (sio_fast_ih == NULL) {
1802		swi_add(&tty_ithd, "sio", siopoll, NULL, SWI_TTY, 0,
1803		    &sio_fast_ih);
1804		swi_add(&clk_ithd, "sio", siopoll, NULL, SWI_CLOCK, 0,
1805		    &sio_slow_ih);
1806	}
1807	minorbase = UNIT_TO_MINOR(unit);
1808	com->devs[0] = make_dev(&sio_cdevsw, minorbase,
1809	    UID_ROOT, GID_WHEEL, 0600, "ttyd%r", unit);
1810	com->devs[1] = make_dev(&sioc_cdevsw, minorbase | CONTROL_INIT_STATE,
1811	    UID_ROOT, GID_WHEEL, 0600, "ttyid%r", unit);
1812	com->devs[2] = make_dev(&sioc_cdevsw, minorbase | CONTROL_LOCK_STATE,
1813	    UID_ROOT, GID_WHEEL, 0600, "ttyld%r", unit);
1814	com->devs[3] = make_dev(&sio_cdevsw, minorbase | CALLOUT_MASK,
1815	    UID_UUCP, GID_DIALER, 0660, "cuaa%r", unit);
1816	com->devs[4] = make_dev(&sioc_cdevsw,
1817	    minorbase | CALLOUT_MASK | CONTROL_INIT_STATE,
1818	    UID_UUCP, GID_DIALER, 0660, "cuaia%r", unit);
1819	com->devs[5] = make_dev(&sioc_cdevsw,
1820	    minorbase | CALLOUT_MASK | CONTROL_LOCK_STATE,
1821	    UID_UUCP, GID_DIALER, 0660, "cuala%r", unit);
1822	for (rid = 0; rid < 6; rid++)
1823		com->devs[rid]->si_drv1 = com;
1824	com->flags = flags;
1825	com->pps.ppscap = PPS_CAPTUREASSERT | PPS_CAPTURECLEAR;
1826
1827	if (COM_PPSCTS(flags))
1828		com->pps_bit = MSR_CTS;
1829	else
1830		com->pps_bit = MSR_DCD;
1831	pps_init(&com->pps);
1832
1833	rid = 0;
1834	com->irqres = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1835					     RF_ACTIVE);
1836	if (com->irqres) {
1837		ret = BUS_SETUP_INTR(device_get_parent(dev), dev, com->irqres,
1838				     INTR_TYPE_TTY | INTR_FAST,
1839				     siointr, com, &com->cookie);
1840		if (ret) {
1841			ret = BUS_SETUP_INTR(device_get_parent(dev), dev,
1842					     com->irqres, INTR_TYPE_TTY,
1843					     siointr, com, &com->cookie);
1844			if (ret == 0)
1845				device_printf(dev, "unable to activate interrupt in fast mode - using normal mode\n");
1846		}
1847		if (ret)
1848			device_printf(dev, "could not activate interrupt\n");
1849#if defined(KDB) && (defined(BREAK_TO_DEBUGGER) || \
1850    defined(ALT_BREAK_TO_DEBUGGER))
1851		/*
1852		 * Enable interrupts for early break-to-debugger support
1853		 * on the console.
1854		 */
1855		if (ret == 0 && unit == comconsole)
1856			outb(siocniobase + com_ier, IER_ERXRDY | IER_ERLS |
1857			    IER_EMSC);
1858#endif
1859	}
1860
1861	return (0);
1862}
1863
1864static int
1865siocopen(dev, flag, mode, td)
1866	struct cdev *dev;
1867	int		flag;
1868	int		mode;
1869	struct thread	*td;
1870{
1871	struct com_s	*com;
1872
1873	com = dev->si_drv1;
1874	if (com == NULL)
1875		return (ENXIO);
1876	if (com->gone)
1877		return (ENXIO);
1878	return (0);
1879}
1880
1881static int
1882sioopen(dev, flag, mode, td)
1883	struct cdev *dev;
1884	int		flag;
1885	int		mode;
1886	struct thread	*td;
1887{
1888	struct com_s	*com;
1889	int		error;
1890	int		mynor;
1891	int		s;
1892	struct tty	*tp;
1893	int		unit;
1894
1895	mynor = minor(dev);
1896	unit = MINOR_TO_UNIT(mynor);
1897	com = dev->si_drv1;
1898	if (com == NULL)
1899		return (ENXIO);
1900	if (com->gone)
1901		return (ENXIO);
1902	tp = dev->si_tty = com->tp = ttymalloc(com->tp);
1903	s = spltty();
1904	/*
1905	 * We jump to this label after all non-interrupted sleeps to pick
1906	 * up any changes of the device state.
1907	 */
1908open_top:
1909	error = ttydtrwaitsleep(tp);
1910	if (error)
1911		goto out;
1912	if (tp->t_state & TS_ISOPEN) {
1913		/*
1914		 * The device is open, so everything has been initialized.
1915		 * Handle conflicts.
1916		 */
1917		if (mynor & CALLOUT_MASK) {
1918			if (!com->active_out) {
1919				error = EBUSY;
1920				goto out;
1921			}
1922		} else {
1923			if (com->active_out) {
1924				if (flag & O_NONBLOCK) {
1925					error = EBUSY;
1926					goto out;
1927				}
1928				error =	tsleep(&com->active_out,
1929					       TTIPRI | PCATCH, "siobi", 0);
1930				if (com_addr(unit) == NULL)
1931					return (ENXIO);
1932				if (error != 0 || com->gone)
1933					goto out;
1934				goto open_top;
1935			}
1936		}
1937		if (tp->t_state & TS_XCLUDE &&
1938		    suser(td)) {
1939			error = EBUSY;
1940			goto out;
1941		}
1942	} else {
1943		/*
1944		 * The device isn't open, so there are no conflicts.
1945		 * Initialize it.  Initialization is done twice in many
1946		 * cases: to preempt sleeping callin opens if we are
1947		 * callout, and to complete a callin open after DCD rises.
1948		 */
1949		tp->t_oproc = comstart;
1950		tp->t_param = comparam;
1951		tp->t_stop = comstop;
1952		tp->t_modem = commodem;
1953		tp->t_break = combreak;
1954		tp->t_dev = dev;
1955		tp->t_termios = mynor & CALLOUT_MASK
1956				? com->it_out : com->it_in;
1957#ifdef PC98
1958		if (!IS_8251(com->pc98_if_type))
1959#endif
1960		(void)commodem(tp, SER_DTR | SER_RTS, 0);
1961		com->poll = com->no_irq;
1962		com->poll_output = com->loses_outints;
1963		++com->wopeners;
1964		error = comparam(tp, &tp->t_termios);
1965		--com->wopeners;
1966		if (error != 0)
1967			goto out;
1968#ifdef PC98
1969		if (IS_8251(com->pc98_if_type)) {
1970			com_tiocm_bis(com, TIOCM_DTR|TIOCM_RTS);
1971			pc98_msrint_start(dev);
1972			if (com->pc98_8251fifo) {
1973			    com->pc98_8251fifo_enable = 1;
1974			    outb(I8251F_fcr, CTRL8251F_ENABLE |
1975				 CTRL8251F_XMT_RST | CTRL8251F_RCV_RST);
1976			}
1977		}
1978#endif
1979		/*
1980		 * XXX we should goto open_top if comparam() slept.
1981		 */
1982		if (com->hasfifo) {
1983			int i;
1984			/*
1985			 * (Re)enable and drain fifos.
1986			 *
1987			 * Certain SMC chips cause problems if the fifos
1988			 * are enabled while input is ready.  Turn off the
1989			 * fifo if necessary to clear the input.  We test
1990			 * the input ready bit after enabling the fifos
1991			 * since we've already enabled them in comparam()
1992			 * and to handle races between enabling and fresh
1993			 * input.
1994			 */
1995			for (i = 0; i < 500; i++) {
1996				sio_setreg(com, com_fifo,
1997					   FIFO_RCV_RST | FIFO_XMT_RST
1998					   | com->fifo_image);
1999#ifdef PC98
2000				if (com->pc98_if_type == COM_IF_RSA98III)
2001					outb(com->rsabase + rsa_frr , 0x00);
2002#endif
2003				/*
2004				 * XXX the delays are for superstitious
2005				 * historical reasons.  It must be less than
2006				 * the character time at the maximum
2007				 * supported speed (87 usec at 115200 bps
2008				 * 8N1).  Otherwise we might loop endlessly
2009				 * if data is streaming in.  We used to use
2010				 * delays of 100.  That usually worked
2011				 * because DELAY(100) used to usually delay
2012				 * for about 85 usec instead of 100.
2013				 */
2014				DELAY(50);
2015#ifdef PC98
2016				if (com->pc98_if_type == COM_IF_RSA98III ?
2017				    !(inb(com->rsabase + rsa_srr) & 0x08) :
2018				    !(inb(com->line_status_port) & LSR_RXRDY))
2019					break;
2020#else
2021				if (!(inb(com->line_status_port) & LSR_RXRDY))
2022					break;
2023#endif
2024				sio_setreg(com, com_fifo, 0);
2025				DELAY(50);
2026				(void) inb(com->data_port);
2027			}
2028			if (i == 500) {
2029				error = EIO;
2030				goto out;
2031			}
2032		}
2033
2034		mtx_lock_spin(&sio_lock);
2035#ifdef PC98
2036		if (IS_8251(com->pc98_if_type)) {
2037		    com_tiocm_bis(com, TIOCM_LE);
2038		    com->pc98_prev_modem_status = pc98_get_modem_status(com);
2039		    com_int_Rx_enable(com);
2040		} else {
2041#endif
2042		(void) inb(com->line_status_port);
2043		(void) inb(com->data_port);
2044		com->prev_modem_status = com->last_modem_status
2045		    = inb(com->modem_status_port);
2046		outb(com->int_ctl_port,
2047		     IER_ERXRDY | IER_ERLS | IER_EMSC
2048		     | (COM_IIR_TXRDYBUG(com->flags) ? 0 : IER_ETXRDY));
2049#ifdef PC98
2050		if (com->pc98_if_type == COM_IF_RSA98III) {
2051			outb(com->rsabase + rsa_ier, 0x1d);
2052			outb(com->int_ctl_port, IER_ERLS | IER_EMSC);
2053		}
2054#endif
2055#ifdef PC98
2056		}
2057#endif
2058		mtx_unlock_spin(&sio_lock);
2059		/*
2060		 * Handle initial DCD.  Callout devices get a fake initial
2061		 * DCD (trapdoor DCD).  If we are callout, then any sleeping
2062		 * callin opens get woken up and resume sleeping on "siobi"
2063		 * instead of "siodcd".
2064		 */
2065		/*
2066		 * XXX `mynor & CALLOUT_MASK' should be
2067		 * `tp->t_cflag & (SOFT_CARRIER | TRAPDOOR_CARRIER) where
2068		 * TRAPDOOR_CARRIER is the default initial state for callout
2069		 * devices and SOFT_CARRIER is like CLOCAL except it hides
2070		 * the true carrier.
2071		 */
2072#ifdef PC98
2073		if ((IS_8251(com->pc98_if_type) &&
2074			(pc98_get_modem_status(com) & TIOCM_CAR)) ||
2075		    (!IS_8251(com->pc98_if_type) &&
2076			(com->prev_modem_status & MSR_DCD)) ||
2077		    mynor & CALLOUT_MASK)
2078			ttyld_modem(tp, 1);
2079#else
2080		if (com->prev_modem_status & MSR_DCD || mynor & CALLOUT_MASK)
2081			ttyld_modem(tp, 1);
2082#endif
2083	}
2084	/*
2085	 * Wait for DCD if necessary.
2086	 */
2087	if (!(tp->t_state & TS_CARR_ON) && !(mynor & CALLOUT_MASK)
2088	    && !(tp->t_cflag & CLOCAL) && !(flag & O_NONBLOCK)) {
2089		++com->wopeners;
2090		error = tsleep(TSA_CARR_ON(tp), TTIPRI | PCATCH, "siodcd", 0);
2091		if (com_addr(unit) == NULL)
2092			return (ENXIO);
2093		--com->wopeners;
2094		if (error != 0 || com->gone)
2095			goto out;
2096		goto open_top;
2097	}
2098	error =	ttyld_open(tp, dev);
2099	ttyldoptim(tp);
2100	if (tp->t_state & TS_ISOPEN && mynor & CALLOUT_MASK)
2101		com->active_out = TRUE;
2102	siosettimeout();
2103out:
2104	splx(s);
2105	if (!(tp->t_state & TS_ISOPEN) && com->wopeners == 0)
2106		comhardclose(com);
2107	return (error);
2108}
2109
2110static int
2111siocclose(dev, flag, mode, td)
2112	struct cdev *dev;
2113	int		flag;
2114	int		mode;
2115	struct thread	*td;
2116{
2117
2118	return (0);
2119}
2120
2121static int
2122sioclose(dev, flag, mode, td)
2123	struct cdev *dev;
2124	int		flag;
2125	int		mode;
2126	struct thread	*td;
2127{
2128	struct com_s	*com;
2129	int		mynor;
2130	int		s;
2131	struct tty	*tp;
2132
2133	mynor = minor(dev);
2134	com = dev->si_drv1;
2135	if (com == NULL)
2136		return (ENODEV);
2137	tp = com->tp;
2138	s = spltty();
2139	ttyld_close(tp, flag);
2140#ifdef PC98
2141	com->modem_checking = 0;
2142#endif
2143	ttyldoptim(tp);
2144	comhardclose(com);
2145	tty_close(tp);
2146	siosettimeout();
2147	splx(s);
2148	if (com->gone) {
2149		printf("sio%d: gone\n", com->unit);
2150		s = spltty();
2151		if (com->ibuf != NULL)
2152			free(com->ibuf, M_DEVBUF);
2153		bzero(tp, sizeof *tp);
2154		splx(s);
2155	}
2156	return (0);
2157}
2158
2159static void
2160comhardclose(com)
2161	struct com_s	*com;
2162{
2163	int		s;
2164	struct tty	*tp;
2165
2166	s = spltty();
2167	com->poll = FALSE;
2168	com->poll_output = FALSE;
2169	com->do_timestamp = FALSE;
2170	com->pps.ppsparam.mode = 0;
2171#ifdef PC98
2172	com_send_break_off(com);
2173#else
2174	sio_setreg(com, com_cfcr, com->cfcr_image &= ~CFCR_SBREAK);
2175#endif
2176	tp = com->tp;
2177
2178#if defined(KDB) && (defined(BREAK_TO_DEBUGGER) || \
2179    defined(ALT_BREAK_TO_DEBUGGER))
2180	/*
2181	 * Leave interrupts enabled and don't clear DTR if this is the
2182	 * console. This allows us to detect break-to-debugger events
2183	 * while the console device is closed.
2184	 */
2185	if (com->unit != comconsole)
2186#endif
2187	{
2188#ifdef PC98
2189		int	tmp;
2190		if (IS_8251(com->pc98_if_type))
2191			com_int_TxRx_disable(com);
2192		else
2193			sio_setreg(com, com_ier, 0);
2194		if (com->pc98_if_type == COM_IF_RSA98III)
2195			outb(com->rsabase + rsa_ier, 0x00);
2196		if (IS_8251(com->pc98_if_type))
2197			tmp = pc98_get_modem_status(com) & TIOCM_CAR;
2198		else
2199			tmp = com->prev_modem_status & MSR_DCD;
2200#else
2201		sio_setreg(com, com_ier, 0);
2202#endif
2203		if (tp->t_cflag & HUPCL
2204		    /*
2205		     * XXX we will miss any carrier drop between here and the
2206		     * next open.  Perhaps we should watch DCD even when the
2207		     * port is closed; it is not sufficient to check it at
2208		     * the next open because it might go up and down while
2209		     * we're not watching.
2210		     */
2211		    || (!com->active_out
2212#ifdef PC98
2213			&& !(tmp)
2214#else
2215		        && !(com->prev_modem_status & MSR_DCD)
2216#endif
2217		        && !(com->it_in.c_cflag & CLOCAL))
2218		    || !(tp->t_state & TS_ISOPEN)) {
2219#ifdef PC98
2220			if (IS_8251(com->pc98_if_type))
2221			    com_tiocm_bic(com, TIOCM_DTR|TIOCM_RTS|TIOCM_LE);
2222			else
2223#endif
2224			(void)commodem(tp, 0, SER_DTR);
2225			ttydtrwaitstart(tp);
2226		}
2227#ifdef PC98
2228		else {
2229			if (IS_8251(com->pc98_if_type))
2230				com_tiocm_bic(com, TIOCM_LE);
2231		}
2232#endif
2233	}
2234#ifdef PC98
2235	if (com->pc98_8251fifo)	{
2236	    if (com->pc98_8251fifo_enable)
2237		outb(I8251F_fcr, CTRL8251F_XMT_RST | CTRL8251F_RCV_RST);
2238	    com->pc98_8251fifo_enable = 0;
2239	}
2240#endif
2241	if (com->hasfifo) {
2242		/*
2243		 * Disable fifos so that they are off after controlled
2244		 * reboots.  Some BIOSes fail to detect 16550s when the
2245		 * fifos are enabled.
2246		 */
2247		sio_setreg(com, com_fifo, 0);
2248	}
2249	com->active_out = FALSE;
2250	wakeup(&com->active_out);
2251	wakeup(TSA_CARR_ON(tp));	/* restart any wopeners */
2252	splx(s);
2253}
2254
2255static int
2256siocrdwr(dev, uio, flag)
2257	struct cdev *dev;
2258	struct uio	*uio;
2259	int		flag;
2260{
2261
2262	return (ENODEV);
2263}
2264
2265static int
2266sioread(dev, uio, flag)
2267	struct cdev *dev;
2268	struct uio	*uio;
2269	int		flag;
2270{
2271	struct com_s	*com;
2272
2273	com = dev->si_drv1;
2274	if (com == NULL || com->gone)
2275		return (ENODEV);
2276	return (ttyld_read(com->tp, uio, flag));
2277}
2278
2279static int
2280siowrite(dev, uio, flag)
2281	struct cdev *dev;
2282	struct uio	*uio;
2283	int		flag;
2284{
2285	int		mynor;
2286	struct com_s	*com;
2287	int		unit;
2288
2289	mynor = minor(dev);
2290
2291	unit = MINOR_TO_UNIT(mynor);
2292	com = com_addr(unit);
2293	if (com == NULL || com->gone)
2294		return (ENODEV);
2295	/*
2296	 * (XXX) We disallow virtual consoles if the physical console is
2297	 * a serial port.  This is in case there is a display attached that
2298	 * is not the console.  In that situation we don't need/want the X
2299	 * server taking over the console.
2300	 */
2301	if (constty != NULL && unit == comconsole)
2302		constty = NULL;
2303	return (ttyld_write(com->tp, uio, flag));
2304}
2305
2306static void
2307siobusycheck(chan)
2308	void	*chan;
2309{
2310	struct com_s	*com;
2311	int		s;
2312
2313	com = (struct com_s *)chan;
2314
2315	/*
2316	 * Clear TS_BUSY if low-level output is complete.
2317	 * spl locking is sufficient because siointr1() does not set CS_BUSY.
2318	 * If siointr1() clears CS_BUSY after we look at it, then we'll get
2319	 * called again.  Reading the line status port outside of siointr1()
2320	 * is safe because CS_BUSY is clear so there are no output interrupts
2321	 * to lose.
2322	 */
2323	s = spltty();
2324	if (com->state & CS_BUSY)
2325		com->extra_state &= ~CSE_BUSYCHECK;	/* False alarm. */
2326#ifdef	PC98
2327	else if ((IS_8251(com->pc98_if_type) &&
2328		  ((com->pc98_8251fifo_enable &&
2329		    (inb(I8251F_lsr) & (STS8251F_TxRDY | STS8251F_TxEMP))
2330		    == (STS8251F_TxRDY | STS8251F_TxEMP)) ||
2331		   (!com->pc98_8251fifo_enable &&
2332		    (inb(com->sts_port) & (STS8251_TxRDY | STS8251_TxEMP))
2333		    == (STS8251_TxRDY | STS8251_TxEMP)))) ||
2334		 ((inb(com->line_status_port) & (LSR_TSRE | LSR_TXRDY))
2335		  == (LSR_TSRE | LSR_TXRDY))) {
2336#else
2337	else if ((inb(com->line_status_port) & (LSR_TSRE | LSR_TXRDY))
2338	    == (LSR_TSRE | LSR_TXRDY)) {
2339#endif
2340		com->tp->t_state &= ~TS_BUSY;
2341		ttwwakeup(com->tp);
2342		com->extra_state &= ~CSE_BUSYCHECK;
2343	} else
2344		timeout(siobusycheck, com, hz / 100);
2345	splx(s);
2346}
2347
2348static u_int
2349siodivisor(rclk, speed)
2350	u_long	rclk;
2351	speed_t	speed;
2352{
2353	long	actual_speed;
2354	u_int	divisor;
2355	int	error;
2356
2357	if (speed == 0)
2358		return (0);
2359#if UINT_MAX > (ULONG_MAX - 1) / 8
2360	if (speed > (ULONG_MAX - 1) / 8)
2361		return (0);
2362#endif
2363	divisor = (rclk / (8UL * speed) + 1) / 2;
2364	if (divisor == 0 || divisor >= 65536)
2365		return (0);
2366	actual_speed = rclk / (16UL * divisor);
2367
2368	/* 10 times error in percent: */
2369	error = ((actual_speed - (long)speed) * 2000 / (long)speed + 1) / 2;
2370
2371	/* 3.0% maximum error tolerance: */
2372	if (error < -30 || error > 30)
2373		return (0);
2374
2375	return (divisor);
2376}
2377
2378/*
2379 * Call this function with the sio_lock mutex held.  It will return with the
2380 * lock still held.
2381 */
2382static void
2383sioinput(com)
2384	struct com_s	*com;
2385{
2386	u_char		*buf;
2387	int		incc;
2388	u_char		line_status;
2389	int		recv_data;
2390	struct tty	*tp;
2391
2392	buf = com->ibuf;
2393	tp = com->tp;
2394	if (!(tp->t_state & TS_ISOPEN) || !(tp->t_cflag & CREAD)) {
2395		com_events -= (com->iptr - com->ibuf);
2396		com->iptr = com->ibuf;
2397		return;
2398	}
2399	if (tp->t_state & TS_CAN_BYPASS_L_RINT) {
2400		/*
2401		 * Avoid the grotesquely inefficient lineswitch routine
2402		 * (ttyinput) in "raw" mode.  It usually takes about 450
2403		 * instructions (that's without canonical processing or echo!).
2404		 * slinput is reasonably fast (usually 40 instructions plus
2405		 * call overhead).
2406		 */
2407		do {
2408			/*
2409			 * This may look odd, but it is using save-and-enable
2410			 * semantics instead of the save-and-disable semantics
2411			 * that are used everywhere else.
2412			 */
2413			mtx_unlock_spin(&sio_lock);
2414			incc = com->iptr - buf;
2415			if (tp->t_rawq.c_cc + incc > tp->t_ihiwat
2416			    && (com->state & CS_RTS_IFLOW
2417				|| tp->t_iflag & IXOFF)
2418			    && !(tp->t_state & TS_TBLOCK))
2419				ttyblock(tp);
2420			com->delta_error_counts[CE_TTY_BUF_OVERFLOW]
2421				+= b_to_q((char *)buf, incc, &tp->t_rawq);
2422			buf += incc;
2423			tk_nin += incc;
2424			tk_rawcc += incc;
2425			tp->t_rawcc += incc;
2426			ttwakeup(tp);
2427			if (tp->t_state & TS_TTSTOP
2428			    && (tp->t_iflag & IXANY
2429				|| tp->t_cc[VSTART] == tp->t_cc[VSTOP])) {
2430				tp->t_state &= ~TS_TTSTOP;
2431				tp->t_lflag &= ~FLUSHO;
2432				comstart(tp);
2433			}
2434			mtx_lock_spin(&sio_lock);
2435		} while (buf < com->iptr);
2436	} else {
2437		do {
2438			/*
2439			 * This may look odd, but it is using save-and-enable
2440			 * semantics instead of the save-and-disable semantics
2441			 * that are used everywhere else.
2442			 */
2443			mtx_unlock_spin(&sio_lock);
2444			line_status = buf[com->ierroff];
2445			recv_data = *buf++;
2446			if (line_status
2447			    & (LSR_BI | LSR_FE | LSR_OE | LSR_PE)) {
2448				if (line_status & LSR_BI)
2449					recv_data |= TTY_BI;
2450				if (line_status & LSR_FE)
2451					recv_data |= TTY_FE;
2452				if (line_status & LSR_OE)
2453					recv_data |= TTY_OE;
2454				if (line_status & LSR_PE)
2455					recv_data |= TTY_PE;
2456			}
2457			ttyld_rint(tp, recv_data);
2458			mtx_lock_spin(&sio_lock);
2459		} while (buf < com->iptr);
2460	}
2461	com_events -= (com->iptr - com->ibuf);
2462	com->iptr = com->ibuf;
2463
2464	/*
2465	 * There is now room for another low-level buffer full of input,
2466	 * so enable RTS if it is now disabled and there is room in the
2467	 * high-level buffer.
2468	 */
2469#ifdef PC98
2470	if (IS_8251(com->pc98_if_type)) {
2471		if ((com->state & CS_RTS_IFLOW) &&
2472		    !(com_tiocm_get(com) & TIOCM_RTS) &&
2473		    !(tp->t_state & TS_TBLOCK))
2474			com_tiocm_bis(com, TIOCM_RTS);
2475	} else {
2476		if ((com->state & CS_RTS_IFLOW) &&
2477		    !(com->mcr_image & MCR_RTS) &&
2478		    !(tp->t_state & TS_TBLOCK))
2479			outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS);
2480	}
2481#else
2482	if ((com->state & CS_RTS_IFLOW) && !(com->mcr_image & MCR_RTS) &&
2483	    !(tp->t_state & TS_TBLOCK))
2484		outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS);
2485#endif
2486}
2487
2488static void
2489siointr(arg)
2490	void		*arg;
2491{
2492	struct com_s	*com;
2493#if defined(PC98) && defined(COM_MULTIPORT)
2494	u_char		rsa_buf_status;
2495#endif
2496
2497#ifndef COM_MULTIPORT
2498	com = (struct com_s *)arg;
2499
2500	mtx_lock_spin(&sio_lock);
2501	siointr1(com);
2502	mtx_unlock_spin(&sio_lock);
2503#else /* COM_MULTIPORT */
2504	bool_t		possibly_more_intrs;
2505	int		unit;
2506
2507	/*
2508	 * Loop until there is no activity on any port.  This is necessary
2509	 * to get an interrupt edge more than to avoid another interrupt.
2510	 * If the IRQ signal is just an OR of the IRQ signals from several
2511	 * devices, then the edge from one may be lost because another is
2512	 * on.
2513	 */
2514	mtx_lock_spin(&sio_lock);
2515	do {
2516		possibly_more_intrs = FALSE;
2517		for (unit = 0; unit < sio_numunits; ++unit) {
2518			com = com_addr(unit);
2519			/*
2520			 * XXX COM_LOCK();
2521			 * would it work here, or be counter-productive?
2522			 */
2523#ifdef PC98
2524			if (com != NULL
2525			    && !com->gone
2526			    && IS_8251(com->pc98_if_type)) {
2527				siointr1(com);
2528			} else if (com != NULL
2529			    && !com->gone
2530			    && com->pc98_if_type == COM_IF_RSA98III) {
2531				rsa_buf_status =
2532				    inb(com->rsabase + rsa_srr) & 0xc9;
2533				if ((rsa_buf_status & 0xc8)
2534				    || !(rsa_buf_status & 0x01)) {
2535				    siointr1(com);
2536				    if (rsa_buf_status !=
2537					(inb(com->rsabase + rsa_srr) & 0xc9))
2538					possibly_more_intrs = TRUE;
2539				}
2540			} else
2541#endif
2542			if (com != NULL
2543			    && !com->gone
2544			    && (inb(com->int_id_port) & IIR_IMASK)
2545			       != IIR_NOPEND) {
2546				siointr1(com);
2547				possibly_more_intrs = TRUE;
2548			}
2549			/* XXX COM_UNLOCK(); */
2550		}
2551	} while (possibly_more_intrs);
2552	mtx_unlock_spin(&sio_lock);
2553#endif /* COM_MULTIPORT */
2554}
2555
2556static struct timespec siots[8];
2557static int siotso;
2558static int volatile siotsunit = -1;
2559
2560static int
2561sysctl_siots(SYSCTL_HANDLER_ARGS)
2562{
2563	char buf[128];
2564	long long delta;
2565	size_t len;
2566	int error, i, tso;
2567
2568	for (i = 1, tso = siotso; i < tso; i++) {
2569		delta = (long long)(siots[i].tv_sec - siots[i - 1].tv_sec) *
2570		    1000000000 +
2571		    (siots[i].tv_nsec - siots[i - 1].tv_nsec);
2572		len = sprintf(buf, "%lld\n", delta);
2573		if (delta >= 110000)
2574			len += sprintf(buf + len - 1, ": *** %ld.%09ld\n",
2575			    (long)siots[i].tv_sec, siots[i].tv_nsec) - 1;
2576		if (i == tso - 1)
2577			buf[len - 1] = '\0';
2578		error = SYSCTL_OUT(req, buf, len);
2579		if (error != 0)
2580			return (error);
2581		uio_yield();
2582	}
2583	return (0);
2584}
2585
2586SYSCTL_PROC(_machdep, OID_AUTO, siots, CTLTYPE_STRING | CTLFLAG_RD,
2587    0, 0, sysctl_siots, "A", "sio timestamps");
2588
2589static void
2590siointr1(com)
2591	struct com_s	*com;
2592{
2593	u_char	int_ctl;
2594	u_char	int_ctl_new;
2595	u_char	line_status;
2596	u_char	modem_status;
2597	u_char	*ioptr;
2598	u_char	recv_data;
2599
2600#ifdef PC98
2601	u_char	tmp = 0;
2602	u_char	rsa_buf_status = 0;
2603	int	rsa_tx_fifo_size = 0;
2604#endif /* PC98 */
2605
2606	if (COM_IIR_TXRDYBUG(com->flags)) {
2607		int_ctl = inb(com->int_ctl_port);
2608		int_ctl_new = int_ctl;
2609	} else {
2610		int_ctl = 0;
2611		int_ctl_new = 0;
2612	}
2613
2614	while (!com->gone) {
2615#ifdef PC98
2616status_read:;
2617		if (IS_8251(com->pc98_if_type)) {
2618			if (com->pc98_8251fifo_enable)
2619				tmp = inb(I8251F_lsr);
2620			else
2621				tmp = inb(com->sts_port);
2622more_intr:
2623			line_status = 0;
2624			if (com->pc98_8251fifo_enable) {
2625			    if (tmp & STS8251F_TxRDY) line_status |= LSR_TXRDY;
2626			    if (tmp & STS8251F_RxRDY) line_status |= LSR_RXRDY;
2627			    if (tmp & STS8251F_TxEMP) line_status |= LSR_TSRE;
2628			    if (tmp & STS8251F_PE)    line_status |= LSR_PE;
2629			    if (tmp & STS8251F_OE)    line_status |= LSR_OE;
2630			    if (tmp & STS8251F_BD_SD) line_status |= LSR_BI;
2631			} else {
2632			    if (tmp & STS8251_TxRDY)  line_status |= LSR_TXRDY;
2633			    if (tmp & STS8251_RxRDY)  line_status |= LSR_RXRDY;
2634			    if (tmp & STS8251_TxEMP)  line_status |= LSR_TSRE;
2635			    if (tmp & STS8251_PE)     line_status |= LSR_PE;
2636			    if (tmp & STS8251_OE)     line_status |= LSR_OE;
2637			    if (tmp & STS8251_FE)     line_status |= LSR_FE;
2638			    if (tmp & STS8251_BD_SD)  line_status |= LSR_BI;
2639			}
2640		} else {
2641#endif /* PC98 */
2642		if (com->pps.ppsparam.mode & PPS_CAPTUREBOTH) {
2643			modem_status = inb(com->modem_status_port);
2644		        if ((modem_status ^ com->last_modem_status) &
2645			    com->pps_bit) {
2646				pps_capture(&com->pps);
2647				pps_event(&com->pps,
2648				    (modem_status & com->pps_bit) ?
2649				    PPS_CAPTUREASSERT : PPS_CAPTURECLEAR);
2650			}
2651		}
2652		line_status = inb(com->line_status_port);
2653#ifdef PC98
2654		}
2655		if (com->pc98_if_type == COM_IF_RSA98III)
2656			rsa_buf_status = inb(com->rsabase + rsa_srr);
2657#endif /* PC98 */
2658
2659		/* input event? (check first to help avoid overruns) */
2660#ifndef PC98
2661		while (line_status & LSR_RCV_MASK) {
2662#else
2663		while ((line_status & LSR_RCV_MASK)
2664		       || (com->pc98_if_type == COM_IF_RSA98III
2665			   && (rsa_buf_status & 0x08))) {
2666#endif /* PC98 */
2667			/* break/unnattached error bits or real input? */
2668#ifdef PC98
2669			if (IS_8251(com->pc98_if_type)) {
2670				if (com->pc98_8251fifo_enable) {
2671				    recv_data = inb(I8251F_data);
2672				    if (tmp & (STS8251F_PE | STS8251F_OE |
2673					       STS8251F_BD_SD)) {
2674					pc98_i8251_or_cmd(com, CMD8251_ER);
2675					recv_data = 0;
2676				    }
2677				} else {
2678				    recv_data = inb(com->data_port);
2679				    if (tmp & (STS8251_PE | STS8251_OE |
2680					       STS8251_FE | STS8251_BD_SD)) {
2681					pc98_i8251_or_cmd(com, CMD8251_ER);
2682					recv_data = 0;
2683				    }
2684				}
2685			} else if (com->pc98_if_type == COM_IF_RSA98III) {
2686				if (!(rsa_buf_status & 0x08))
2687					recv_data = 0;
2688				else
2689					recv_data = inb(com->data_port);
2690			} else
2691#endif
2692			if (!(line_status & LSR_RXRDY))
2693				recv_data = 0;
2694			else
2695				recv_data = inb(com->data_port);
2696#ifdef KDB
2697#ifdef ALT_BREAK_TO_DEBUGGER
2698			if (com->unit == comconsole &&
2699			    kdb_alt_break(recv_data, &com->alt_brk_state) != 0)
2700				kdb_enter("Break sequence on console");
2701#endif /* ALT_BREAK_TO_DEBUGGER */
2702#endif /* KDB */
2703			if (line_status & (LSR_BI | LSR_FE | LSR_PE)) {
2704				/*
2705				 * Don't store BI if IGNBRK or FE/PE if IGNPAR.
2706				 * Otherwise, push the work to a higher level
2707				 * (to handle PARMRK) if we're bypassing.
2708				 * Otherwise, convert BI/FE and PE+INPCK to 0.
2709				 *
2710				 * This makes bypassing work right in the
2711				 * usual "raw" case (IGNBRK set, and IGNPAR
2712				 * and INPCK clear).
2713				 *
2714				 * Note: BI together with FE/PE means just BI.
2715				 */
2716				if (line_status & LSR_BI) {
2717#if defined(KDB) && defined(BREAK_TO_DEBUGGER)
2718					if (com->unit == comconsole) {
2719						kdb_enter("Line break on console");
2720						goto cont;
2721					}
2722#endif
2723					if (com->tp == NULL
2724					    || com->tp->t_iflag & IGNBRK)
2725						goto cont;
2726				} else {
2727					if (com->tp == NULL
2728					    || com->tp->t_iflag & IGNPAR)
2729						goto cont;
2730				}
2731				if (com->tp->t_state & TS_CAN_BYPASS_L_RINT
2732				    && (line_status & (LSR_BI | LSR_FE)
2733					|| com->tp->t_iflag & INPCK))
2734					recv_data = 0;
2735			}
2736			++com->bytes_in;
2737			if (com->tp != NULL &&
2738			    com->tp->t_hotchar != 0 && recv_data == com->tp->t_hotchar)
2739				swi_sched(sio_fast_ih, 0);
2740			ioptr = com->iptr;
2741			if (ioptr >= com->ibufend)
2742				CE_RECORD(com, CE_INTERRUPT_BUF_OVERFLOW);
2743			else {
2744				if (com->do_timestamp)
2745					microtime(&com->timestamp);
2746				++com_events;
2747				swi_sched(sio_slow_ih, SWI_DELAY);
2748#if 0 /* for testing input latency vs efficiency */
2749if (com->iptr - com->ibuf == 8)
2750	swi_sched(sio_fast_ih, 0);
2751#endif
2752				ioptr[0] = recv_data;
2753				ioptr[com->ierroff] = line_status;
2754				com->iptr = ++ioptr;
2755				if (ioptr == com->ihighwater
2756				    && com->state & CS_RTS_IFLOW)
2757#ifdef PC98
2758					IS_8251(com->pc98_if_type) ?
2759						com_tiocm_bic(com, TIOCM_RTS) :
2760#endif
2761					outb(com->modem_ctl_port,
2762					     com->mcr_image &= ~MCR_RTS);
2763				if (line_status & LSR_OE)
2764					CE_RECORD(com, CE_OVERRUN);
2765			}
2766cont:
2767			if (line_status & LSR_TXRDY
2768			    && com->state >= (CS_BUSY | CS_TTGO | CS_ODEVREADY))
2769				goto txrdy;
2770
2771			/*
2772			 * "& 0x7F" is to avoid the gcc-1.40 generating a slow
2773			 * jump from the top of the loop to here
2774			 */
2775#ifdef PC98
2776			if (IS_8251(com->pc98_if_type))
2777				goto status_read;
2778			else
2779#endif
2780			line_status = inb(com->line_status_port) & 0x7F;
2781#ifdef PC98
2782			if (com->pc98_if_type == COM_IF_RSA98III)
2783				rsa_buf_status = inb(com->rsabase + rsa_srr);
2784#endif /* PC98 */
2785		}
2786
2787		/* modem status change? (always check before doing output) */
2788#ifdef PC98
2789		if (!IS_8251(com->pc98_if_type)) {
2790#endif
2791		modem_status = inb(com->modem_status_port);
2792		if (modem_status != com->last_modem_status) {
2793			/*
2794			 * Schedule high level to handle DCD changes.  Note
2795			 * that we don't use the delta bits anywhere.  Some
2796			 * UARTs mess them up, and it's easy to remember the
2797			 * previous bits and calculate the delta.
2798			 */
2799			com->last_modem_status = modem_status;
2800			if (!(com->state & CS_CHECKMSR)) {
2801				com_events += LOTS_OF_EVENTS;
2802				com->state |= CS_CHECKMSR;
2803				swi_sched(sio_fast_ih, 0);
2804			}
2805
2806			/* handle CTS change immediately for crisp flow ctl */
2807			if (com->state & CS_CTS_OFLOW) {
2808				if (modem_status & MSR_CTS)
2809					com->state |= CS_ODEVREADY;
2810				else
2811					com->state &= ~CS_ODEVREADY;
2812			}
2813		}
2814#ifdef PC98
2815		}
2816#endif
2817
2818txrdy:
2819		/* output queued and everything ready? */
2820#ifndef PC98
2821		if (line_status & LSR_TXRDY
2822		    && com->state >= (CS_BUSY | CS_TTGO | CS_ODEVREADY)) {
2823#else
2824		if (((com->pc98_if_type == COM_IF_RSA98III)
2825		     ? (rsa_buf_status & 0x02)
2826		     : (line_status & LSR_TXRDY))
2827		    && com->state >= (CS_BUSY | CS_TTGO | CS_ODEVREADY)) {
2828#endif
2829#ifdef PC98
2830			Port_t	tmp_data_port;
2831
2832			if (IS_8251(com->pc98_if_type) &&
2833			    com->pc98_8251fifo_enable)
2834				tmp_data_port = I8251F_data;
2835			else
2836				tmp_data_port = com->data_port;
2837#endif
2838
2839			ioptr = com->obufq.l_head;
2840			if (com->tx_fifo_size > 1 && com->unit != siotsunit) {
2841				u_int	ocount;
2842
2843				ocount = com->obufq.l_tail - ioptr;
2844#ifdef PC98
2845				if (com->pc98_if_type == COM_IF_RSA98III) {
2846				  rsa_buf_status = inb(com->rsabase + rsa_srr);
2847				  rsa_tx_fifo_size = 1024;
2848				  if (!(rsa_buf_status & 0x01))
2849				      rsa_tx_fifo_size = 2048;
2850				  if (ocount > rsa_tx_fifo_size)
2851				      ocount = rsa_tx_fifo_size;
2852				} else
2853#endif
2854				if (ocount > com->tx_fifo_size)
2855					ocount = com->tx_fifo_size;
2856				com->bytes_out += ocount;
2857				do
2858#ifdef PC98
2859					outb(tmp_data_port, *ioptr++);
2860#else
2861					outb(com->data_port, *ioptr++);
2862#endif
2863				while (--ocount != 0);
2864			} else {
2865#ifdef PC98
2866				outb(tmp_data_port, *ioptr++);
2867#else
2868				outb(com->data_port, *ioptr++);
2869#endif
2870				++com->bytes_out;
2871				if (com->unit == siotsunit
2872				    && siotso < sizeof siots / sizeof siots[0])
2873					nanouptime(&siots[siotso++]);
2874			}
2875#ifdef PC98
2876			if (IS_8251(com->pc98_if_type))
2877			    if (!(pc98_check_i8251_interrupt(com) & IEN_TxFLAG))
2878				com_int_Tx_enable(com);
2879#endif
2880			com->obufq.l_head = ioptr;
2881			if (COM_IIR_TXRDYBUG(com->flags))
2882				int_ctl_new = int_ctl | IER_ETXRDY;
2883			if (ioptr >= com->obufq.l_tail) {
2884				struct lbq	*qp;
2885
2886				qp = com->obufq.l_next;
2887				qp->l_queued = FALSE;
2888				qp = qp->l_next;
2889				if (qp != NULL) {
2890					com->obufq.l_head = qp->l_head;
2891					com->obufq.l_tail = qp->l_tail;
2892					com->obufq.l_next = qp;
2893				} else {
2894					/* output just completed */
2895					if (COM_IIR_TXRDYBUG(com->flags))
2896						int_ctl_new = int_ctl
2897							      & ~IER_ETXRDY;
2898					com->state &= ~CS_BUSY;
2899#if defined(PC98)
2900					if (IS_8251(com->pc98_if_type) &&
2901					    pc98_check_i8251_interrupt(com) & IEN_TxFLAG)
2902						com_int_Tx_disable(com);
2903#endif
2904				}
2905				if (!(com->state & CS_ODONE)) {
2906					com_events += LOTS_OF_EVENTS;
2907					com->state |= CS_ODONE;
2908					/* handle at high level ASAP */
2909					swi_sched(sio_fast_ih, 0);
2910				}
2911			}
2912#ifdef PC98
2913			if (COM_IIR_TXRDYBUG(com->flags)
2914			    && int_ctl != int_ctl_new) {
2915				if (com->pc98_if_type == COM_IF_RSA98III) {
2916				    int_ctl_new &= ~(IER_ETXRDY | IER_ERXRDY);
2917				    outb(com->int_ctl_port, int_ctl_new);
2918				    outb(com->rsabase + rsa_ier, 0x1d);
2919				} else
2920				    outb(com->int_ctl_port, int_ctl_new);
2921			}
2922#else
2923			if (COM_IIR_TXRDYBUG(com->flags)
2924			    && int_ctl != int_ctl_new)
2925				outb(com->int_ctl_port, int_ctl_new);
2926#endif
2927		}
2928#ifdef PC98
2929		else if (line_status & LSR_TXRDY) {
2930		    if (IS_8251(com->pc98_if_type))
2931			if (pc98_check_i8251_interrupt(com) & IEN_TxFLAG)
2932			    com_int_Tx_disable(com);
2933		}
2934		if (IS_8251(com->pc98_if_type)) {
2935		    if (com->pc98_8251fifo_enable) {
2936			if ((tmp = inb(I8251F_lsr)) & STS8251F_RxRDY)
2937			    goto more_intr;
2938		    } else {
2939			if ((tmp = inb(com->sts_port)) & STS8251_RxRDY)
2940			    goto more_intr;
2941		    }
2942		}
2943#endif
2944
2945		/* finished? */
2946#ifndef COM_MULTIPORT
2947#ifdef PC98
2948		if (IS_8251(com->pc98_if_type))
2949			return;
2950#endif
2951		if ((inb(com->int_id_port) & IIR_IMASK) == IIR_NOPEND)
2952#endif /* COM_MULTIPORT */
2953			return;
2954	}
2955}
2956
2957static int
2958siocioctl(dev, cmd, data, flag, td)
2959	struct cdev *dev;
2960	u_long		cmd;
2961	caddr_t		data;
2962	int		flag;
2963	struct thread	*td;
2964{
2965	struct com_s	*com;
2966	int		error;
2967	int		mynor;
2968	struct termios	*ct;
2969
2970	mynor = minor(dev);
2971	com = com_addr(MINOR_TO_UNIT(mynor));
2972	if (com == NULL || com->gone)
2973		return (ENODEV);
2974
2975	switch (mynor & CONTROL_MASK) {
2976	case CONTROL_INIT_STATE:
2977		ct = mynor & CALLOUT_MASK ? &com->it_out : &com->it_in;
2978		break;
2979	case CONTROL_LOCK_STATE:
2980		ct = mynor & CALLOUT_MASK ? &com->lt_out : &com->lt_in;
2981		break;
2982	default:
2983		return (ENODEV);	/* /dev/nodev */
2984	}
2985	switch (cmd) {
2986	case TIOCSETA:
2987		error = suser(td);
2988		if (error != 0)
2989			return (error);
2990		*ct = *(struct termios *)data;
2991		return (0);
2992	case TIOCGETA:
2993		*(struct termios *)data = *ct;
2994		return (0);
2995	case TIOCGETD:
2996		*(int *)data = TTYDISC;
2997		return (0);
2998	case TIOCGWINSZ:
2999		bzero(data, sizeof(struct winsize));
3000		return (0);
3001	default:
3002		return (ENOTTY);
3003	}
3004}
3005
3006static int
3007sioioctl(dev, cmd, data, flag, td)
3008	struct cdev *dev;
3009	u_long		cmd;
3010	caddr_t		data;
3011	int		flag;
3012	struct thread	*td;
3013{
3014	struct com_s	*com;
3015	int		error;
3016	int		mynor;
3017	int		s;
3018	struct tty	*tp;
3019#ifndef BURN_BRIDGES
3020#if defined(COMPAT_43)
3021	u_long		oldcmd;
3022	struct termios	term;
3023#endif
3024#endif
3025
3026	mynor = minor(dev);
3027	com = dev->si_drv1;
3028	if (com == NULL || com->gone)
3029		return (ENODEV);
3030	tp = com->tp;
3031#ifndef BURN_BRIDGES
3032#if defined(COMPAT_43)
3033	term = tp->t_termios;
3034	oldcmd = cmd;
3035	error = ttsetcompat(tp, &cmd, data, &term);
3036	if (error != 0)
3037		return (error);
3038	if (cmd != oldcmd)
3039		data = (caddr_t)&term;
3040#endif
3041#endif
3042	if (cmd == TIOCSETA || cmd == TIOCSETAW || cmd == TIOCSETAF) {
3043		int	cc;
3044		struct termios *dt = (struct termios *)data;
3045		struct termios *lt = mynor & CALLOUT_MASK
3046				     ? &com->lt_out : &com->lt_in;
3047
3048		dt->c_iflag = (tp->t_iflag & lt->c_iflag)
3049			      | (dt->c_iflag & ~lt->c_iflag);
3050		dt->c_oflag = (tp->t_oflag & lt->c_oflag)
3051			      | (dt->c_oflag & ~lt->c_oflag);
3052		dt->c_cflag = (tp->t_cflag & lt->c_cflag)
3053			      | (dt->c_cflag & ~lt->c_cflag);
3054		dt->c_lflag = (tp->t_lflag & lt->c_lflag)
3055			      | (dt->c_lflag & ~lt->c_lflag);
3056		for (cc = 0; cc < NCCS; ++cc)
3057			if (lt->c_cc[cc] != 0)
3058				dt->c_cc[cc] = tp->t_cc[cc];
3059		if (lt->c_ispeed != 0)
3060			dt->c_ispeed = tp->t_ispeed;
3061		if (lt->c_ospeed != 0)
3062			dt->c_ospeed = tp->t_ospeed;
3063	}
3064	error = ttyioctl(dev, cmd, data, flag, td);
3065	ttyldoptim(tp);
3066	if (error != ENOTTY)
3067		return (error);
3068	s = spltty();
3069	switch (cmd) {
3070	case TIOCTIMESTAMP:
3071		com->do_timestamp = TRUE;
3072		*(struct timeval *)data = com->timestamp;
3073		break;
3074	default:
3075		splx(s);
3076		error = pps_ioctl(cmd, data, &com->pps);
3077		if (error == ENODEV)
3078			error = ENOTTY;
3079		return (error);
3080	}
3081	splx(s);
3082	return (0);
3083}
3084
3085/* software interrupt handler for SWI_TTY */
3086static void
3087siopoll(void *dummy)
3088{
3089	int		unit;
3090
3091	if (com_events == 0)
3092		return;
3093repeat:
3094	for (unit = 0; unit < sio_numunits; ++unit) {
3095		struct com_s	*com;
3096		int		incc;
3097		struct tty	*tp;
3098
3099		com = com_addr(unit);
3100		if (com == NULL)
3101			continue;
3102		tp = com->tp;
3103		if (tp == NULL || com->gone) {
3104			/*
3105			 * Discard any events related to never-opened or
3106			 * going-away devices.
3107			 */
3108			mtx_lock_spin(&sio_lock);
3109			incc = com->iptr - com->ibuf;
3110			com->iptr = com->ibuf;
3111			if (com->state & CS_CHECKMSR) {
3112				incc += LOTS_OF_EVENTS;
3113				com->state &= ~CS_CHECKMSR;
3114			}
3115			com_events -= incc;
3116			mtx_unlock_spin(&sio_lock);
3117			continue;
3118		}
3119		if (com->iptr != com->ibuf) {
3120			mtx_lock_spin(&sio_lock);
3121			sioinput(com);
3122			mtx_unlock_spin(&sio_lock);
3123		}
3124		if (com->state & CS_CHECKMSR) {
3125			u_char	delta_modem_status;
3126
3127#ifdef PC98
3128			if (!IS_8251(com->pc98_if_type)) {
3129#endif
3130			mtx_lock_spin(&sio_lock);
3131			delta_modem_status = com->last_modem_status
3132					     ^ com->prev_modem_status;
3133			com->prev_modem_status = com->last_modem_status;
3134			com_events -= LOTS_OF_EVENTS;
3135			com->state &= ~CS_CHECKMSR;
3136			mtx_unlock_spin(&sio_lock);
3137			if (delta_modem_status & MSR_DCD)
3138				ttyld_modem(tp,
3139				    com->prev_modem_status & MSR_DCD);
3140#ifdef PC98
3141			}
3142#endif
3143		}
3144		if (com->state & CS_ODONE) {
3145			mtx_lock_spin(&sio_lock);
3146			com_events -= LOTS_OF_EVENTS;
3147			com->state &= ~CS_ODONE;
3148			mtx_unlock_spin(&sio_lock);
3149			if (!(com->state & CS_BUSY)
3150			    && !(com->extra_state & CSE_BUSYCHECK)) {
3151				timeout(siobusycheck, com, hz / 100);
3152				com->extra_state |= CSE_BUSYCHECK;
3153			}
3154			ttyld_start(tp);
3155		}
3156		if (com_events == 0)
3157			break;
3158	}
3159	if (com_events >= LOTS_OF_EVENTS)
3160		goto repeat;
3161}
3162
3163static void
3164combreak(tp, sig)
3165	struct tty 	*tp;
3166	int		sig;
3167{
3168	struct com_s	*com;
3169
3170	com = tp->t_dev->si_drv1;
3171
3172#ifdef PC98
3173	if (sig)
3174		com_send_break_on(com);
3175	else
3176		com_send_break_off(com);
3177#else
3178	if (sig)
3179		sio_setreg(com, com_cfcr, com->cfcr_image |= CFCR_SBREAK);
3180	else
3181		sio_setreg(com, com_cfcr, com->cfcr_image &= ~CFCR_SBREAK);
3182#endif
3183}
3184
3185static int
3186comparam(tp, t)
3187	struct tty	*tp;
3188	struct termios	*t;
3189{
3190	u_int		cfcr;
3191	int		cflag;
3192	struct com_s	*com;
3193	u_int		divisor;
3194	u_char		dlbh;
3195	u_char		dlbl;
3196	u_char		efr_flowbits;
3197	int		s;
3198	int		unit;
3199#ifdef PC98
3200	u_char		param = 0;
3201#endif
3202
3203	unit = DEV_TO_UNIT(tp->t_dev);
3204	com = com_addr(unit);
3205	if (com == NULL)
3206		return (ENODEV);
3207
3208#ifdef PC98
3209	cfcr = 0;
3210
3211	if (IS_8251(com->pc98_if_type)) {
3212		if (pc98_ttspeedtab(com, t->c_ospeed, &divisor) != 0)
3213			return (EINVAL);
3214	} else {
3215#endif
3216	/* check requested parameters */
3217	if (t->c_ispeed != (t->c_ospeed != 0 ? t->c_ospeed : tp->t_ospeed))
3218		return (EINVAL);
3219	divisor = siodivisor(com->rclk, t->c_ispeed);
3220	if (divisor == 0)
3221		return (EINVAL);
3222#ifdef PC98
3223	}
3224#endif
3225
3226	/* parameters are OK, convert them to the com struct and the device */
3227	s = spltty();
3228#ifdef PC98
3229	if (IS_8251(com->pc98_if_type)) {
3230		if (t->c_ospeed == 0)
3231			com_tiocm_bic(com, TIOCM_DTR|TIOCM_RTS|TIOCM_LE);
3232		else
3233			com_tiocm_bis(com, TIOCM_DTR|TIOCM_RTS|TIOCM_LE);
3234	} else
3235#endif
3236	if (t->c_ospeed == 0)
3237		(void)commodem(tp, 0, SER_DTR);	/* hang up line */
3238	else
3239		(void)commodem(tp, SER_DTR, 0);
3240	cflag = t->c_cflag;
3241#ifdef PC98
3242	if (!IS_8251(com->pc98_if_type)) {
3243#endif
3244	switch (cflag & CSIZE) {
3245	case CS5:
3246		cfcr = CFCR_5BITS;
3247		break;
3248	case CS6:
3249		cfcr = CFCR_6BITS;
3250		break;
3251	case CS7:
3252		cfcr = CFCR_7BITS;
3253		break;
3254	default:
3255		cfcr = CFCR_8BITS;
3256		break;
3257	}
3258	if (cflag & PARENB) {
3259		cfcr |= CFCR_PENAB;
3260		if (!(cflag & PARODD))
3261			cfcr |= CFCR_PEVEN;
3262	}
3263	if (cflag & CSTOPB)
3264		cfcr |= CFCR_STOPB;
3265
3266	if (com->hasfifo) {
3267		/*
3268		 * Use a fifo trigger level low enough so that the input
3269		 * latency from the fifo is less than about 16 msec and
3270		 * the total latency is less than about 30 msec.  These
3271		 * latencies are reasonable for humans.  Serial comms
3272		 * protocols shouldn't expect anything better since modem
3273		 * latencies are larger.
3274		 *
3275		 * The fifo trigger level cannot be set at RX_HIGH for high
3276		 * speed connections without further work on reducing
3277		 * interrupt disablement times in other parts of the system,
3278		 * without producing silo overflow errors.
3279		 */
3280		com->fifo_image = com->unit == siotsunit ? 0
3281				  : t->c_ispeed <= 4800
3282				  ? FIFO_ENABLE : FIFO_ENABLE | FIFO_RX_MEDH;
3283#ifdef COM_ESP
3284		/*
3285		 * The Hayes ESP card needs the fifo DMA mode bit set
3286		 * in compatibility mode.  If not, it will interrupt
3287		 * for each character received.
3288		 */
3289		if (com->esp)
3290			com->fifo_image |= FIFO_DMA_MODE;
3291#endif
3292		sio_setreg(com, com_fifo, com->fifo_image);
3293	}
3294#ifdef PC98
3295	}
3296#endif
3297
3298	/*
3299	 * This returns with interrupts disabled so that we can complete
3300	 * the speed change atomically.  Keeping interrupts disabled is
3301	 * especially important while com_data is hidden.
3302	 */
3303	(void) siosetwater(com, t->c_ispeed);
3304
3305#ifdef PC98
3306	if (IS_8251(com->pc98_if_type))
3307		com_cflag_and_speed_set(com, cflag, t->c_ospeed);
3308	else {
3309#endif
3310	sio_setreg(com, com_cfcr, cfcr | CFCR_DLAB);
3311	/*
3312	 * Only set the divisor registers if they would change, since on
3313	 * some 16550 incompatibles (UMC8669F), setting them while input
3314	 * is arriving loses sync until data stops arriving.
3315	 */
3316	dlbl = divisor & 0xFF;
3317	if (sio_getreg(com, com_dlbl) != dlbl)
3318		sio_setreg(com, com_dlbl, dlbl);
3319	dlbh = divisor >> 8;
3320	if (sio_getreg(com, com_dlbh) != dlbh)
3321		sio_setreg(com, com_dlbh, dlbh);
3322#ifdef PC98
3323	}
3324#endif
3325
3326	efr_flowbits = 0;
3327
3328	if (cflag & CRTS_IFLOW) {
3329		com->state |= CS_RTS_IFLOW;
3330		efr_flowbits |= EFR_AUTORTS;
3331		/*
3332		 * If CS_RTS_IFLOW just changed from off to on, the change
3333		 * needs to be propagated to MCR_RTS.  This isn't urgent,
3334		 * so do it later by calling comstart() instead of repeating
3335		 * a lot of code from comstart() here.
3336		 */
3337	} else if (com->state & CS_RTS_IFLOW) {
3338		com->state &= ~CS_RTS_IFLOW;
3339		/*
3340		 * CS_RTS_IFLOW just changed from on to off.  Force MCR_RTS
3341		 * on here, since comstart() won't do it later.
3342		 */
3343#ifdef PC98
3344		if (IS_8251(com->pc98_if_type))
3345			com_tiocm_bis(com, TIOCM_RTS);
3346		else
3347			outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS);
3348#else
3349		outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS);
3350#endif
3351	}
3352
3353	/*
3354	 * Set up state to handle output flow control.
3355	 * XXX - worth handling MDMBUF (DCD) flow control at the lowest level?
3356	 * Now has 10+ msec latency, while CTS flow has 50- usec latency.
3357	 */
3358	com->state |= CS_ODEVREADY;
3359	com->state &= ~CS_CTS_OFLOW;
3360#ifdef PC98
3361	if (com->pc98_if_type == COM_IF_RSA98III) {
3362		param = inb(com->rsabase + rsa_msr);
3363		outb(com->rsabase + rsa_msr, param & 0x14);
3364	}
3365#endif
3366	if (cflag & CCTS_OFLOW) {
3367		com->state |= CS_CTS_OFLOW;
3368		efr_flowbits |= EFR_AUTOCTS;
3369#ifdef PC98
3370		if (IS_8251(com->pc98_if_type)) {
3371			if (!(pc98_get_modem_status(com) & TIOCM_CTS))
3372				com->state &= ~CS_ODEVREADY;
3373		} else if (com->pc98_if_type == COM_IF_RSA98III) {
3374			/* Set automatic flow control mode */
3375			outb(com->rsabase + rsa_msr, param | 0x08);
3376		} else
3377#endif
3378		if (!(com->last_modem_status & MSR_CTS))
3379			com->state &= ~CS_ODEVREADY;
3380	}
3381
3382#ifdef PC98
3383	if (!IS_8251(com->pc98_if_type))
3384		sio_setreg(com, com_cfcr, com->cfcr_image = cfcr);
3385#else
3386	if (com->st16650a) {
3387		sio_setreg(com, com_lcr, LCR_EFR_ENABLE);
3388		sio_setreg(com, com_efr,
3389			   (sio_getreg(com, com_efr)
3390			    & ~(EFR_AUTOCTS | EFR_AUTORTS)) | efr_flowbits);
3391	}
3392	sio_setreg(com, com_cfcr, com->cfcr_image = cfcr);
3393#endif
3394
3395	/* XXX shouldn't call functions while intrs are disabled. */
3396	ttyldoptim(tp);
3397
3398	mtx_unlock_spin(&sio_lock);
3399	splx(s);
3400	comstart(tp);
3401	if (com->ibufold != NULL) {
3402		free(com->ibufold, M_DEVBUF);
3403		com->ibufold = NULL;
3404	}
3405	return (0);
3406}
3407
3408/*
3409 * This function must be called with the sio_lock mutex released and will
3410 * return with it obtained.
3411 */
3412static int
3413siosetwater(com, speed)
3414	struct com_s	*com;
3415	speed_t		speed;
3416{
3417	int		cp4ticks;
3418	u_char		*ibuf;
3419	int		ibufsize;
3420	struct tty	*tp;
3421
3422	/*
3423	 * Make the buffer size large enough to handle a softtty interrupt
3424	 * latency of about 2 ticks without loss of throughput or data
3425	 * (about 3 ticks if input flow control is not used or not honoured,
3426	 * but a bit less for CS5-CS7 modes).
3427	 */
3428	cp4ticks = speed / 10 / hz * 4;
3429	for (ibufsize = 128; ibufsize < cp4ticks;)
3430		ibufsize <<= 1;
3431#ifdef PC98
3432	if (com->pc98_if_type == COM_IF_RSA98III)
3433		ibufsize = 2048;
3434#endif
3435	if (ibufsize == com->ibufsize) {
3436		mtx_lock_spin(&sio_lock);
3437		return (0);
3438	}
3439
3440	/*
3441	 * Allocate input buffer.  The extra factor of 2 in the size is
3442	 * to allow for an error byte for each input byte.
3443	 */
3444	ibuf = malloc(2 * ibufsize, M_DEVBUF, M_NOWAIT);
3445	if (ibuf == NULL) {
3446		mtx_lock_spin(&sio_lock);
3447		return (ENOMEM);
3448	}
3449
3450	/* Initialize non-critical variables. */
3451	com->ibufold = com->ibuf;
3452	com->ibufsize = ibufsize;
3453	tp = com->tp;
3454	if (tp != NULL) {
3455		tp->t_ififosize = 2 * ibufsize;
3456		tp->t_ispeedwat = (speed_t)-1;
3457		tp->t_ospeedwat = (speed_t)-1;
3458	}
3459
3460	/*
3461	 * Read current input buffer, if any.  Continue with interrupts
3462	 * disabled.
3463	 */
3464	mtx_lock_spin(&sio_lock);
3465	if (com->iptr != com->ibuf)
3466		sioinput(com);
3467
3468	/*-
3469	 * Initialize critical variables, including input buffer watermarks.
3470	 * The external device is asked to stop sending when the buffer
3471	 * exactly reaches high water, or when the high level requests it.
3472	 * The high level is notified immediately (rather than at a later
3473	 * clock tick) when this watermark is reached.
3474	 * The buffer size is chosen so the watermark should almost never
3475	 * be reached.
3476	 * The low watermark is invisibly 0 since the buffer is always
3477	 * emptied all at once.
3478	 */
3479	com->iptr = com->ibuf = ibuf;
3480	com->ibufend = ibuf + ibufsize;
3481	com->ierroff = ibufsize;
3482	com->ihighwater = ibuf + 3 * ibufsize / 4;
3483	return (0);
3484}
3485
3486static void
3487comstart(tp)
3488	struct tty	*tp;
3489{
3490	struct com_s	*com;
3491	int		s;
3492	int		unit;
3493
3494	unit = DEV_TO_UNIT(tp->t_dev);
3495	com = com_addr(unit);
3496	if (com == NULL)
3497		return;
3498	s = spltty();
3499	mtx_lock_spin(&sio_lock);
3500	if (tp->t_state & TS_TTSTOP)
3501		com->state &= ~CS_TTGO;
3502	else
3503		com->state |= CS_TTGO;
3504	if (tp->t_state & TS_TBLOCK) {
3505#ifdef PC98
3506		if (IS_8251(com->pc98_if_type)) {
3507		    if ((com_tiocm_get(com) & TIOCM_RTS) &&
3508			(com->state & CS_RTS_IFLOW))
3509			com_tiocm_bic(com, TIOCM_RTS);
3510		} else {
3511		    if ((com->mcr_image & MCR_RTS) &&
3512			(com->state & CS_RTS_IFLOW))
3513			outb(com->modem_ctl_port, com->mcr_image &= ~MCR_RTS);
3514		}
3515#else
3516		if (com->mcr_image & MCR_RTS && com->state & CS_RTS_IFLOW)
3517			outb(com->modem_ctl_port, com->mcr_image &= ~MCR_RTS);
3518#endif
3519	} else {
3520#ifdef PC98
3521		if (IS_8251(com->pc98_if_type)) {
3522		    if (!(com_tiocm_get(com) & TIOCM_RTS) &&
3523			com->iptr < com->ihighwater &&
3524			com->state & CS_RTS_IFLOW)
3525			com_tiocm_bis(com, TIOCM_RTS);
3526		} else {
3527		    if (!(com->mcr_image & MCR_RTS) &&
3528			com->iptr < com->ihighwater &&
3529			com->state & CS_RTS_IFLOW)
3530			outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS);
3531		}
3532#else
3533		if (!(com->mcr_image & MCR_RTS) && com->iptr < com->ihighwater
3534		    && com->state & CS_RTS_IFLOW)
3535			outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS);
3536#endif
3537	}
3538	mtx_unlock_spin(&sio_lock);
3539	if (tp->t_state & (TS_TIMEOUT | TS_TTSTOP)) {
3540		ttwwakeup(tp);
3541		splx(s);
3542		return;
3543	}
3544	if (tp->t_outq.c_cc != 0) {
3545		struct lbq	*qp;
3546		struct lbq	*next;
3547
3548		if (!com->obufs[0].l_queued) {
3549			com->obufs[0].l_tail
3550			    = com->obuf1 + q_to_b(&tp->t_outq, com->obuf1,
3551#ifdef PC98
3552						  com->obufsize);
3553#else
3554						  sizeof com->obuf1);
3555#endif
3556			com->obufs[0].l_next = NULL;
3557			com->obufs[0].l_queued = TRUE;
3558			mtx_lock_spin(&sio_lock);
3559			if (com->state & CS_BUSY) {
3560				qp = com->obufq.l_next;
3561				while ((next = qp->l_next) != NULL)
3562					qp = next;
3563				qp->l_next = &com->obufs[0];
3564			} else {
3565				com->obufq.l_head = com->obufs[0].l_head;
3566				com->obufq.l_tail = com->obufs[0].l_tail;
3567				com->obufq.l_next = &com->obufs[0];
3568				com->state |= CS_BUSY;
3569			}
3570			mtx_unlock_spin(&sio_lock);
3571		}
3572		if (tp->t_outq.c_cc != 0 && !com->obufs[1].l_queued) {
3573			com->obufs[1].l_tail
3574			    = com->obuf2 + q_to_b(&tp->t_outq, com->obuf2,
3575#ifdef PC98
3576						  com->obufsize);
3577#else
3578						  sizeof com->obuf2);
3579#endif
3580			com->obufs[1].l_next = NULL;
3581			com->obufs[1].l_queued = TRUE;
3582			mtx_lock_spin(&sio_lock);
3583			if (com->state & CS_BUSY) {
3584				qp = com->obufq.l_next;
3585				while ((next = qp->l_next) != NULL)
3586					qp = next;
3587				qp->l_next = &com->obufs[1];
3588			} else {
3589				com->obufq.l_head = com->obufs[1].l_head;
3590				com->obufq.l_tail = com->obufs[1].l_tail;
3591				com->obufq.l_next = &com->obufs[1];
3592				com->state |= CS_BUSY;
3593			}
3594			mtx_unlock_spin(&sio_lock);
3595		}
3596		tp->t_state |= TS_BUSY;
3597	}
3598	mtx_lock_spin(&sio_lock);
3599	if (com->state >= (CS_BUSY | CS_TTGO))
3600		siointr1(com);	/* fake interrupt to start output */
3601	mtx_unlock_spin(&sio_lock);
3602	ttwwakeup(tp);
3603	splx(s);
3604}
3605
3606static void
3607comstop(tp, rw)
3608	struct tty	*tp;
3609	int		rw;
3610{
3611	struct com_s	*com;
3612#ifdef PC98
3613	int		rsa98_tmp  = 0;
3614#endif
3615
3616	com = com_addr(DEV_TO_UNIT(tp->t_dev));
3617	if (com == NULL || com->gone)
3618		return;
3619	mtx_lock_spin(&sio_lock);
3620	if (rw & FWRITE) {
3621#ifdef PC98
3622		if (!IS_8251(com->pc98_if_type)) {
3623#endif
3624		if (com->hasfifo)
3625#ifdef COM_ESP
3626		    /* XXX avoid h/w bug. */
3627		    if (!com->esp)
3628#endif
3629			sio_setreg(com, com_fifo,
3630				   FIFO_XMT_RST | com->fifo_image);
3631#ifdef PC98
3632		if (com->pc98_if_type == COM_IF_RSA98III)
3633		    for (rsa98_tmp = 0; rsa98_tmp < 2048; rsa98_tmp++)
3634			sio_setreg(com, com_fifo,
3635				   FIFO_XMT_RST | com->fifo_image);
3636		}
3637#endif
3638		com->obufs[0].l_queued = FALSE;
3639		com->obufs[1].l_queued = FALSE;
3640		if (com->state & CS_ODONE)
3641			com_events -= LOTS_OF_EVENTS;
3642		com->state &= ~(CS_ODONE | CS_BUSY);
3643		com->tp->t_state &= ~TS_BUSY;
3644	}
3645	if (rw & FREAD) {
3646#ifdef PC98
3647		if (!IS_8251(com->pc98_if_type)) {
3648		    if (com->pc98_if_type == COM_IF_RSA98III)
3649			for (rsa98_tmp = 0; rsa98_tmp < 2048; rsa98_tmp++)
3650			    sio_getreg(com, com_data);
3651#endif
3652		if (com->hasfifo)
3653#ifdef COM_ESP
3654		    /* XXX avoid h/w bug. */
3655		    if (!com->esp)
3656#endif
3657			sio_setreg(com, com_fifo,
3658				   FIFO_RCV_RST | com->fifo_image);
3659#ifdef PC98
3660		}
3661#endif
3662		com_events -= (com->iptr - com->ibuf);
3663		com->iptr = com->ibuf;
3664	}
3665	mtx_unlock_spin(&sio_lock);
3666	comstart(tp);
3667}
3668
3669static int
3670commodem(tp, sigon, sigoff)
3671	struct tty 	*tp;
3672	int		sigon, sigoff;
3673{
3674	struct com_s	*com;
3675	int	bitand, bitor, msr;
3676#ifdef PC98
3677	int	clr, set;
3678#endif
3679
3680	com = tp->t_dev->si_drv1;
3681	if (com->gone)
3682		return(0);
3683	if (sigon != 0 || sigoff != 0) {
3684#ifdef PC98
3685		if (IS_8251(com->pc98_if_type)) {
3686			bitand = bitor = 0;
3687			clr = set = 0;
3688			if (sigoff & SER_DTR) {
3689				bitand |= TIOCM_DTR;
3690				clr |= CMD8251_DTR;
3691			}
3692			if (sigoff & SER_RTS) {
3693				bitand |= TIOCM_RTS;
3694				clr |= CMD8251_RxEN | CMD8251_RTS;
3695			}
3696			if (sigon & SER_DTR) {
3697				bitor |= TIOCM_DTR;
3698				set |= CMD8251_TxEN | CMD8251_RxEN |
3699					CMD8251_DTR;
3700			}
3701			if (sigon & SER_RTS) {
3702				bitor |= TIOCM_RTS;
3703				set |= CMD8251_TxEN | CMD8251_RxEN |
3704					CMD8251_RTS;
3705			}
3706			bitand = ~bitand;
3707			mtx_lock_spin(&sio_lock);
3708			com->pc98_prev_modem_status &= bitand;
3709			com->pc98_prev_modem_status |= bitor;
3710			pc98_i8251_clear_or_cmd(com, clr, set);
3711			mtx_unlock_spin(&sio_lock);
3712			return (0);
3713		} else {
3714#endif
3715		bitand = bitor = 0;
3716		if (sigoff & SER_DTR)
3717			bitand |= MCR_DTR;
3718		if (sigoff & SER_RTS)
3719			bitand |= MCR_RTS;
3720		if (sigon & SER_DTR)
3721			bitor |= MCR_DTR;
3722		if (sigon & SER_RTS)
3723			bitor |= MCR_RTS;
3724		bitand = ~bitand;
3725		mtx_lock_spin(&sio_lock);
3726		com->mcr_image &= bitand;
3727		com->mcr_image |= bitor;
3728		outb(com->modem_ctl_port, com->mcr_image);
3729		mtx_unlock_spin(&sio_lock);
3730		return (0);
3731#ifdef PC98
3732		}
3733#endif
3734	} else {
3735#ifdef PC98
3736		if (IS_8251(com->pc98_if_type))
3737			return (com_tiocm_get(com));
3738		else {
3739#endif
3740		bitor = 0;
3741		if (com->mcr_image & MCR_DTR)
3742			bitor |= SER_DTR;
3743		if (com->mcr_image & MCR_RTS)
3744			bitor |= SER_RTS;
3745		msr = com->prev_modem_status;
3746		if (msr & MSR_CTS)
3747			bitor |= SER_CTS;
3748		if (msr & MSR_DCD)
3749			bitor |= SER_DCD;
3750		if (msr & MSR_DSR)
3751			bitor |= SER_DSR;
3752		if (msr & MSR_DSR)
3753			bitor |= SER_DSR;
3754		if (msr & (MSR_RI | MSR_TERI))
3755			bitor |= SER_RI;
3756		return (bitor);
3757#ifdef PC98
3758		}
3759#endif
3760	}
3761}
3762
3763static void
3764siosettimeout()
3765{
3766	struct com_s	*com;
3767	bool_t		someopen;
3768	int		unit;
3769
3770	/*
3771	 * Set our timeout period to 1 second if no polled devices are open.
3772	 * Otherwise set it to max(1/200, 1/hz).
3773	 * Enable timeouts iff some device is open.
3774	 */
3775	untimeout(comwakeup, (void *)NULL, sio_timeout_handle);
3776	sio_timeout = hz;
3777	someopen = FALSE;
3778	for (unit = 0; unit < sio_numunits; ++unit) {
3779		com = com_addr(unit);
3780		if (com != NULL && com->tp != NULL
3781		    && com->tp->t_state & TS_ISOPEN && !com->gone) {
3782			someopen = TRUE;
3783			if (com->poll || com->poll_output) {
3784				sio_timeout = hz > 200 ? hz / 200 : 1;
3785				break;
3786			}
3787		}
3788	}
3789	if (someopen) {
3790		sio_timeouts_until_log = hz / sio_timeout;
3791		sio_timeout_handle = timeout(comwakeup, (void *)NULL,
3792					     sio_timeout);
3793	} else {
3794		/* Flush error messages, if any. */
3795		sio_timeouts_until_log = 1;
3796		comwakeup((void *)NULL);
3797		untimeout(comwakeup, (void *)NULL, sio_timeout_handle);
3798	}
3799}
3800
3801static void
3802comwakeup(chan)
3803	void	*chan;
3804{
3805	struct com_s	*com;
3806	int		unit;
3807
3808	sio_timeout_handle = timeout(comwakeup, (void *)NULL, sio_timeout);
3809
3810	/*
3811	 * Recover from lost output interrupts.
3812	 * Poll any lines that don't use interrupts.
3813	 */
3814	for (unit = 0; unit < sio_numunits; ++unit) {
3815		com = com_addr(unit);
3816		if (com != NULL && !com->gone
3817		    && (com->state >= (CS_BUSY | CS_TTGO) || com->poll)) {
3818			mtx_lock_spin(&sio_lock);
3819			siointr1(com);
3820			mtx_unlock_spin(&sio_lock);
3821		}
3822	}
3823
3824	/*
3825	 * Check for and log errors, but not too often.
3826	 */
3827	if (--sio_timeouts_until_log > 0)
3828		return;
3829	sio_timeouts_until_log = hz / sio_timeout;
3830	for (unit = 0; unit < sio_numunits; ++unit) {
3831		int	errnum;
3832
3833		com = com_addr(unit);
3834		if (com == NULL)
3835			continue;
3836		if (com->gone)
3837			continue;
3838		for (errnum = 0; errnum < CE_NTYPES; ++errnum) {
3839			u_int	delta;
3840			u_long	total;
3841
3842			mtx_lock_spin(&sio_lock);
3843			delta = com->delta_error_counts[errnum];
3844			com->delta_error_counts[errnum] = 0;
3845			mtx_unlock_spin(&sio_lock);
3846			if (delta == 0)
3847				continue;
3848			total = com->error_counts[errnum] += delta;
3849			log(LOG_ERR, "sio%d: %u more %s%s (total %lu)\n",
3850			    unit, delta, error_desc[errnum],
3851			    delta == 1 ? "" : "s", total);
3852		}
3853	}
3854}
3855
3856#ifdef PC98
3857/* commint is called when modem control line changes */
3858static void
3859commint(struct cdev *dev)
3860{
3861	register struct tty *tp;
3862	int	stat,delta;
3863	struct com_s *com;
3864	int	mynor,unit;
3865
3866	mynor = minor(dev);
3867	unit = MINOR_TO_UNIT(mynor);
3868	com = com_addr(unit);
3869	tp = com->tp;
3870
3871	stat = com_tiocm_get(com);
3872	delta = com_tiocm_get_delta(com);
3873
3874	if (com->state & CS_CTS_OFLOW) {
3875		if (stat & TIOCM_CTS)
3876			com->state |= CS_ODEVREADY;
3877		else
3878			com->state &= ~CS_ODEVREADY;
3879	}
3880	if ((delta & TIOCM_CAR) && (mynor & CALLOUT_MASK) == 0) {
3881	    if (stat & TIOCM_CAR )
3882		(void)ttyld_modem(tp, 1);
3883	    else if (ttyld_modem(tp, 0) == 0) {
3884		/* negate DTR, RTS */
3885		com_tiocm_bic(com, (tp->t_cflag & HUPCL) ?
3886				TIOCM_DTR|TIOCM_RTS|TIOCM_LE : TIOCM_LE );
3887		/* disable IENABLE */
3888		com_int_TxRx_disable( com );
3889	    }
3890	}
3891}
3892#endif
3893
3894/*
3895 * Following are all routines needed for SIO to act as console
3896 */
3897struct siocnstate {
3898	u_char	dlbl;
3899	u_char	dlbh;
3900	u_char	ier;
3901	u_char	cfcr;
3902	u_char	mcr;
3903};
3904
3905/*
3906 * This is a function in order to not replicate "ttyd%d" more
3907 * places than absolutely necessary.
3908 */
3909static void
3910siocnset(struct consdev *cd, int unit)
3911{
3912
3913	cd->cn_unit = unit;
3914	sprintf(cd->cn_name, "ttyd%d", unit);
3915}
3916
3917static speed_t siocngetspeed(Port_t, u_long rclk);
3918static void siocnclose(struct siocnstate *sp, Port_t iobase);
3919static void siocnopen(struct siocnstate *sp, Port_t iobase, int speed);
3920static void siocntxwait(Port_t iobase);
3921
3922static cn_probe_t siocnprobe;
3923static cn_init_t siocninit;
3924static cn_term_t siocnterm;
3925static cn_checkc_t siocncheckc;
3926static cn_getc_t siocngetc;
3927static cn_putc_t siocnputc;
3928
3929CONS_DRIVER(sio, siocnprobe, siocninit, siocnterm, siocngetc, siocncheckc,
3930	    siocnputc, NULL);
3931
3932static void
3933siocntxwait(iobase)
3934	Port_t	iobase;
3935{
3936	int	timo;
3937
3938	/*
3939	 * Wait for any pending transmission to finish.  Required to avoid
3940	 * the UART lockup bug when the speed is changed, and for normal
3941	 * transmits.
3942	 */
3943	timo = 100000;
3944	while ((inb(iobase + com_lsr) & (LSR_TSRE | LSR_TXRDY))
3945	       != (LSR_TSRE | LSR_TXRDY) && --timo != 0)
3946		;
3947}
3948
3949/*
3950 * Read the serial port specified and try to figure out what speed
3951 * it's currently running at.  We're assuming the serial port has
3952 * been initialized and is basicly idle.  This routine is only intended
3953 * to be run at system startup.
3954 *
3955 * If the value read from the serial port doesn't make sense, return 0.
3956 */
3957
3958static speed_t
3959siocngetspeed(iobase, rclk)
3960	Port_t	iobase;
3961	u_long	rclk;
3962{
3963	u_int	divisor;
3964	u_char	dlbh;
3965	u_char	dlbl;
3966	u_char  cfcr;
3967
3968	cfcr = inb(iobase + com_cfcr);
3969	outb(iobase + com_cfcr, CFCR_DLAB | cfcr);
3970
3971	dlbl = inb(iobase + com_dlbl);
3972	dlbh = inb(iobase + com_dlbh);
3973
3974	outb(iobase + com_cfcr, cfcr);
3975
3976	divisor = dlbh << 8 | dlbl;
3977
3978	/* XXX there should be more sanity checking. */
3979	if (divisor == 0)
3980		return (CONSPEED);
3981	return (rclk / (16UL * divisor));
3982}
3983
3984static void
3985siocnopen(sp, iobase, speed)
3986	struct siocnstate	*sp;
3987	Port_t			iobase;
3988	int			speed;
3989{
3990	u_int	divisor;
3991	u_char	dlbh;
3992	u_char	dlbl;
3993
3994	/*
3995	 * Save all the device control registers except the fifo register
3996	 * and set our default ones (cs8 -parenb speed=comdefaultrate).
3997	 * We can't save the fifo register since it is read-only.
3998	 */
3999	sp->ier = inb(iobase + com_ier);
4000	outb(iobase + com_ier, 0);	/* spltty() doesn't stop siointr() */
4001	siocntxwait(iobase);
4002	sp->cfcr = inb(iobase + com_cfcr);
4003	outb(iobase + com_cfcr, CFCR_DLAB | CFCR_8BITS);
4004	sp->dlbl = inb(iobase + com_dlbl);
4005	sp->dlbh = inb(iobase + com_dlbh);
4006	/*
4007	 * Only set the divisor registers if they would change, since on
4008	 * some 16550 incompatibles (Startech), setting them clears the
4009	 * data input register.  This also reduces the effects of the
4010	 * UMC8669F bug.
4011	 */
4012	divisor = siodivisor(comdefaultrclk, speed);
4013	dlbl = divisor & 0xFF;
4014	if (sp->dlbl != dlbl)
4015		outb(iobase + com_dlbl, dlbl);
4016	dlbh = divisor >> 8;
4017	if (sp->dlbh != dlbh)
4018		outb(iobase + com_dlbh, dlbh);
4019	outb(iobase + com_cfcr, CFCR_8BITS);
4020	sp->mcr = inb(iobase + com_mcr);
4021	/*
4022	 * We don't want interrupts, but must be careful not to "disable"
4023	 * them by clearing the MCR_IENABLE bit, since that might cause
4024	 * an interrupt by floating the IRQ line.
4025	 */
4026	outb(iobase + com_mcr, (sp->mcr & MCR_IENABLE) | MCR_DTR | MCR_RTS);
4027}
4028
4029static void
4030siocnclose(sp, iobase)
4031	struct siocnstate	*sp;
4032	Port_t			iobase;
4033{
4034	/*
4035	 * Restore the device control registers.
4036	 */
4037	siocntxwait(iobase);
4038	outb(iobase + com_cfcr, CFCR_DLAB | CFCR_8BITS);
4039	if (sp->dlbl != inb(iobase + com_dlbl))
4040		outb(iobase + com_dlbl, sp->dlbl);
4041	if (sp->dlbh != inb(iobase + com_dlbh))
4042		outb(iobase + com_dlbh, sp->dlbh);
4043	outb(iobase + com_cfcr, sp->cfcr);
4044	/*
4045	 * XXX damp oscillations of MCR_DTR and MCR_RTS by not restoring them.
4046	 */
4047	outb(iobase + com_mcr, sp->mcr | MCR_DTR | MCR_RTS);
4048	outb(iobase + com_ier, sp->ier);
4049}
4050
4051static void
4052siocnprobe(cp)
4053	struct consdev	*cp;
4054{
4055	speed_t			boot_speed;
4056	u_char			cfcr;
4057	u_int			divisor;
4058	int			s, unit;
4059	struct siocnstate	sp;
4060
4061	/*
4062	 * Find our first enabled console, if any.  If it is a high-level
4063	 * console device, then initialize it and return successfully.
4064	 * If it is a low-level console device, then initialize it and
4065	 * return unsuccessfully.  It must be initialized in both cases
4066	 * for early use by console drivers and debuggers.  Initializing
4067	 * the hardware is not necessary in all cases, since the i/o
4068	 * routines initialize it on the fly, but it is necessary if
4069	 * input might arrive while the hardware is switched back to an
4070	 * uninitialized state.  We can't handle multiple console devices
4071	 * yet because our low-level routines don't take a device arg.
4072	 * We trust the user to set the console flags properly so that we
4073	 * don't need to probe.
4074	 */
4075	cp->cn_pri = CN_DEAD;
4076
4077	for (unit = 0; unit < 16; unit++) { /* XXX need to know how many */
4078		int flags;
4079
4080		if (resource_disabled("sio", unit))
4081			continue;
4082		if (resource_int_value("sio", unit, "flags", &flags))
4083			continue;
4084		if (COM_CONSOLE(flags) || COM_DEBUGGER(flags)) {
4085			int port;
4086			Port_t iobase;
4087
4088			if (resource_int_value("sio", unit, "port", &port))
4089				continue;
4090			iobase = port;
4091			s = spltty();
4092			if (boothowto & RB_SERIAL) {
4093				boot_speed =
4094				    siocngetspeed(iobase, comdefaultrclk);
4095				if (boot_speed)
4096					comdefaultrate = boot_speed;
4097			}
4098
4099			/*
4100			 * Initialize the divisor latch.  We can't rely on
4101			 * siocnopen() to do this the first time, since it
4102			 * avoids writing to the latch if the latch appears
4103			 * to have the correct value.  Also, if we didn't
4104			 * just read the speed from the hardware, then we
4105			 * need to set the speed in hardware so that
4106			 * switching it later is null.
4107			 */
4108			cfcr = inb(iobase + com_cfcr);
4109			outb(iobase + com_cfcr, CFCR_DLAB | cfcr);
4110			divisor = siodivisor(comdefaultrclk, comdefaultrate);
4111			outb(iobase + com_dlbl, divisor & 0xff);
4112			outb(iobase + com_dlbh, divisor >> 8);
4113			outb(iobase + com_cfcr, cfcr);
4114
4115			siocnopen(&sp, iobase, comdefaultrate);
4116
4117			splx(s);
4118			if (COM_CONSOLE(flags) && !COM_LLCONSOLE(flags)) {
4119				siocnset(cp, unit);
4120				cp->cn_pri = COM_FORCECONSOLE(flags)
4121					     || boothowto & RB_SERIAL
4122					     ? CN_REMOTE : CN_NORMAL;
4123				siocniobase = iobase;
4124				siocnunit = unit;
4125			}
4126#ifdef GDB
4127			if (COM_DEBUGGER(flags))
4128				siogdbiobase = iobase;
4129#endif
4130		}
4131	}
4132}
4133
4134static void
4135siocninit(cp)
4136	struct consdev	*cp;
4137{
4138	comconsole = cp->cn_unit;
4139}
4140
4141static void
4142siocnterm(cp)
4143	struct consdev	*cp;
4144{
4145	comconsole = -1;
4146}
4147
4148static int
4149siocncheckc(struct consdev *cd)
4150{
4151	int	c;
4152	Port_t	iobase;
4153	int	s;
4154	struct siocnstate	sp;
4155	speed_t	speed;
4156
4157	if (cd != NULL && cd->cn_unit == siocnunit) {
4158		iobase = siocniobase;
4159		speed = comdefaultrate;
4160	} else {
4161#ifdef GDB
4162		iobase = siogdbiobase;
4163		speed = gdbdefaultrate;
4164#else
4165		return (-1);
4166#endif
4167	}
4168	s = spltty();
4169	siocnopen(&sp, iobase, speed);
4170	if (inb(iobase + com_lsr) & LSR_RXRDY)
4171		c = inb(iobase + com_data);
4172	else
4173		c = -1;
4174	siocnclose(&sp, iobase);
4175	splx(s);
4176	return (c);
4177}
4178
4179static int
4180siocngetc(struct consdev *cd)
4181{
4182	int	c;
4183	Port_t	iobase;
4184	int	s;
4185	struct siocnstate	sp;
4186	speed_t	speed;
4187
4188	if (cd != NULL && cd->cn_unit == siocnunit) {
4189		iobase = siocniobase;
4190		speed = comdefaultrate;
4191	} else {
4192#ifdef GDB
4193		iobase = siogdbiobase;
4194		speed = gdbdefaultrate;
4195#else
4196		return (-1);
4197#endif
4198	}
4199	s = spltty();
4200	siocnopen(&sp, iobase, speed);
4201	while (!(inb(iobase + com_lsr) & LSR_RXRDY))
4202		;
4203	c = inb(iobase + com_data);
4204	siocnclose(&sp, iobase);
4205	splx(s);
4206	return (c);
4207}
4208
4209static void
4210siocnputc(struct consdev *cd, int c)
4211{
4212	int	need_unlock;
4213	int	s;
4214	struct siocnstate	sp;
4215	Port_t	iobase;
4216	speed_t	speed;
4217
4218	if (cd != NULL && cd->cn_unit == siocnunit) {
4219		iobase = siocniobase;
4220		speed = comdefaultrate;
4221	} else {
4222#ifdef GDB
4223		iobase = siogdbiobase;
4224		speed = gdbdefaultrate;
4225#else
4226		return;
4227#endif
4228	}
4229	s = spltty();
4230	need_unlock = 0;
4231	if (sio_inited == 2 && !mtx_owned(&sio_lock)) {
4232		mtx_lock_spin(&sio_lock);
4233		need_unlock = 1;
4234	}
4235	siocnopen(&sp, iobase, speed);
4236	siocntxwait(iobase);
4237	outb(iobase + com_data, c);
4238	siocnclose(&sp, iobase);
4239	if (need_unlock)
4240		mtx_unlock_spin(&sio_lock);
4241	splx(s);
4242}
4243
4244/*
4245 * Remote gdb(1) support.
4246 */
4247
4248#if defined(GDB)
4249
4250#include <gdb/gdb.h>
4251
4252static gdb_probe_f siogdbprobe;
4253static gdb_init_f siogdbinit;
4254static gdb_term_f siogdbterm;
4255static gdb_getc_f siogdbgetc;
4256static gdb_checkc_f siogdbcheckc;
4257static gdb_putc_f siogdbputc;
4258
4259GDB_DBGPORT(sio, siogdbprobe, siogdbinit, siogdbterm, siogdbcheckc,
4260    siogdbgetc, siogdbputc);
4261
4262static int
4263siogdbprobe(void)
4264{
4265	return ((siogdbiobase != 0) ? 0 : -1);
4266}
4267
4268static void
4269siogdbinit(void)
4270{
4271}
4272
4273static void
4274siogdbterm(void)
4275{
4276}
4277
4278static void
4279siogdbputc(int c)
4280{
4281	siocnputc(NULL, c);
4282}
4283
4284static int
4285siogdbcheckc(void)
4286{
4287	return (siocncheckc(NULL));
4288}
4289
4290static int
4291siogdbgetc(void)
4292{
4293	return (siocngetc(NULL));
4294}
4295
4296#endif
4297
4298#ifdef PC98
4299/*
4300 *  pc98 local function
4301 */
4302static void
4303com_tiocm_bis(struct com_s *com, int msr)
4304{
4305	int	s;
4306	int	tmp = 0;
4307
4308	s=spltty();
4309	com->pc98_prev_modem_status |= ( msr & (TIOCM_LE|TIOCM_DTR|TIOCM_RTS) );
4310	tmp |= CMD8251_TxEN|CMD8251_RxEN;
4311	if ( msr & TIOCM_DTR ) tmp |= CMD8251_DTR;
4312	if ( msr & TIOCM_RTS ) tmp |= CMD8251_RTS;
4313
4314	pc98_i8251_or_cmd( com, tmp );
4315	splx(s);
4316}
4317
4318static void
4319com_tiocm_bic(struct com_s *com, int msr)
4320{
4321	int	s;
4322	int	tmp = msr;
4323
4324	s=spltty();
4325	com->pc98_prev_modem_status &= ~( msr & (TIOCM_LE|TIOCM_DTR|TIOCM_RTS) );
4326	if ( msr & TIOCM_DTR ) tmp |= CMD8251_DTR;
4327	if ( msr & TIOCM_RTS ) tmp |= CMD8251_RTS;
4328
4329	pc98_i8251_clear_cmd( com, tmp );
4330	splx(s);
4331}
4332
4333static int
4334com_tiocm_get(struct com_s *com)
4335{
4336	return( com->pc98_prev_modem_status );
4337}
4338
4339static int
4340com_tiocm_get_delta(struct com_s *com)
4341{
4342	int	tmp;
4343
4344	tmp = com->pc98_modem_delta;
4345	com->pc98_modem_delta = 0;
4346	return( tmp );
4347}
4348
4349/* convert to TIOCM_?? ( ioctl.h ) */
4350static int
4351pc98_get_modem_status(struct com_s *com)
4352{
4353	register int	msr;
4354
4355	msr = com->pc98_prev_modem_status
4356			& ~(TIOCM_CAR|TIOCM_RI|TIOCM_DSR|TIOCM_CTS);
4357	if (com->pc98_8251fifo_enable) {
4358		int	stat2;
4359
4360		stat2 = inb(I8251F_msr);
4361		if ( stat2 & CICSCDF_CD ) msr |= TIOCM_CAR;
4362		if ( stat2 & CICSCDF_CI ) msr |= TIOCM_RI;
4363		if ( stat2 & CICSCDF_DR ) msr |= TIOCM_DSR;
4364		if ( stat2 & CICSCDF_CS ) msr |= TIOCM_CTS;
4365#if COM_CARRIER_DETECT_EMULATE
4366		if ( msr & (TIOCM_DSR|TIOCM_CTS) ) {
4367			msr |= TIOCM_CAR;
4368		}
4369#endif
4370	} else {
4371		int	stat, stat2;
4372
4373		stat  = inb(com->sts_port);
4374		stat2 = inb(com->in_modem_port);
4375		if ( !(stat2 & CICSCD_CD) ) msr |= TIOCM_CAR;
4376		if ( !(stat2 & CICSCD_CI) ) msr |= TIOCM_RI;
4377		if (   stat & STS8251_DSR ) msr |= TIOCM_DSR;
4378		if ( !(stat2 & CICSCD_CS) ) msr |= TIOCM_CTS;
4379#if COM_CARRIER_DETECT_EMULATE
4380		if ( msr & (TIOCM_DSR|TIOCM_CTS) ) {
4381			msr |= TIOCM_CAR;
4382		}
4383#endif
4384	}
4385	return(msr);
4386}
4387
4388static void
4389pc98_check_msr(void* chan)
4390{
4391	int	msr, delta;
4392	int	s;
4393	register struct tty *tp;
4394	struct	com_s *com;
4395	int	mynor;
4396	int	unit;
4397	struct cdev *dev;
4398
4399	dev=(struct cdev *)chan;
4400	mynor = minor(dev);
4401	unit = MINOR_TO_UNIT(mynor);
4402	com = com_addr(unit);
4403	tp = com->tp;
4404
4405	s = spltty();
4406	msr = pc98_get_modem_status(com);
4407	/* make change flag */
4408	delta = msr ^ com->pc98_prev_modem_status;
4409	if ( delta & TIOCM_CAR ) {
4410	    if ( com->modem_car_chg_timer ) {
4411		if ( -- com->modem_car_chg_timer )
4412		    msr ^= TIOCM_CAR;
4413	    } else {
4414		if ((com->modem_car_chg_timer = (msr & TIOCM_CAR) ?
4415		     DCD_ON_RECOGNITION : DCD_OFF_TOLERANCE) != 0)
4416		    msr ^= TIOCM_CAR;
4417	    }
4418	} else
4419	    com->modem_car_chg_timer = 0;
4420	delta = ( msr ^ com->pc98_prev_modem_status ) &
4421			(TIOCM_CAR|TIOCM_RI|TIOCM_DSR|TIOCM_CTS);
4422	com->pc98_prev_modem_status = msr;
4423	delta = ( com->pc98_modem_delta |= delta );
4424	splx(s);
4425	if ( com->modem_checking || (tp->t_state & (TS_ISOPEN)) ) {
4426		if ( delta ) {
4427			commint(dev);
4428		}
4429		timeout(pc98_check_msr, (caddr_t)dev,
4430					PC98_CHECK_MODEM_INTERVAL);
4431	} else {
4432		com->modem_checking = 0;
4433	}
4434}
4435
4436static void
4437pc98_msrint_start(struct cdev *dev)
4438{
4439	struct	com_s *com;
4440	int	mynor;
4441	int	unit;
4442	int	s = spltty();
4443
4444	mynor = minor(dev);
4445	unit = MINOR_TO_UNIT(mynor);
4446	com = com_addr(unit);
4447	/* modem control line check routine envoke interval is 1/10 sec */
4448	if ( com->modem_checking == 0 ) {
4449		com->pc98_prev_modem_status = pc98_get_modem_status(com);
4450		com->pc98_modem_delta = 0;
4451		timeout(pc98_check_msr, (caddr_t)dev,
4452					PC98_CHECK_MODEM_INTERVAL);
4453		com->modem_checking = 1;
4454	}
4455	splx(s);
4456}
4457
4458static void
4459pc98_disable_i8251_interrupt(struct com_s *com, int mod)
4460{
4461	/* disable interrupt */
4462	register int	tmp;
4463
4464	mod |= ~(IEN_Tx|IEN_TxEMP|IEN_Rx);
4465	COM_INT_DISABLE
4466	tmp = inb( com->intr_ctrl_port ) & ~(IEN_Tx|IEN_TxEMP|IEN_Rx);
4467	outb( com->intr_ctrl_port, (com->intr_enable&=~mod) | tmp );
4468	COM_INT_ENABLE
4469}
4470
4471static void
4472pc98_enable_i8251_interrupt(struct com_s *com, int mod)
4473{
4474	register int	tmp;
4475
4476	COM_INT_DISABLE
4477	tmp = inb( com->intr_ctrl_port ) & ~(IEN_Tx|IEN_TxEMP|IEN_Rx);
4478	outb( com->intr_ctrl_port, (com->intr_enable|=mod) | tmp );
4479	COM_INT_ENABLE
4480}
4481
4482static int
4483pc98_check_i8251_interrupt(struct com_s *com)
4484{
4485	return ( com->intr_enable & 0x07 );
4486}
4487
4488static void
4489pc98_i8251_clear_cmd(struct com_s *com, int x)
4490{
4491	int	tmp;
4492
4493	COM_INT_DISABLE
4494	tmp = com->pc98_prev_siocmd & ~(x);
4495	if (com->pc98_8251fifo_enable)
4496	    outb(I8251F_fcr, 0);
4497	outb(com->cmd_port, tmp);
4498	com->pc98_prev_siocmd = tmp & ~(CMD8251_ER|CMD8251_RESET|CMD8251_EH);
4499	if (com->pc98_8251fifo_enable)
4500	    outb(I8251F_fcr, CTRL8251F_ENABLE);
4501	COM_INT_ENABLE
4502}
4503
4504static void
4505pc98_i8251_or_cmd(struct com_s *com, int x)
4506{
4507	int	tmp;
4508
4509	COM_INT_DISABLE
4510	if (com->pc98_8251fifo_enable)
4511	    outb(I8251F_fcr, 0);
4512	tmp = com->pc98_prev_siocmd | (x);
4513	outb(com->cmd_port, tmp);
4514	com->pc98_prev_siocmd = tmp & ~(CMD8251_ER|CMD8251_RESET|CMD8251_EH);
4515	if (com->pc98_8251fifo_enable)
4516	    outb(I8251F_fcr, CTRL8251F_ENABLE);
4517	COM_INT_ENABLE
4518}
4519
4520static void
4521pc98_i8251_set_cmd(struct com_s *com, int x)
4522{
4523	int	tmp;
4524
4525	COM_INT_DISABLE
4526	if (com->pc98_8251fifo_enable)
4527	    outb(I8251F_fcr, 0);
4528	tmp = (x);
4529	outb(com->cmd_port, tmp);
4530	com->pc98_prev_siocmd = tmp & ~(CMD8251_ER|CMD8251_RESET|CMD8251_EH);
4531	if (com->pc98_8251fifo_enable)
4532	    outb(I8251F_fcr, CTRL8251F_ENABLE);
4533	COM_INT_ENABLE
4534}
4535
4536static void
4537pc98_i8251_clear_or_cmd(struct com_s *com, int clr, int x)
4538{
4539	int	tmp;
4540	COM_INT_DISABLE
4541	if (com->pc98_8251fifo_enable)
4542	    outb(I8251F_fcr, 0);
4543	tmp = com->pc98_prev_siocmd & ~(clr);
4544	tmp |= (x);
4545	outb(com->cmd_port, tmp);
4546	com->pc98_prev_siocmd = tmp & ~(CMD8251_ER|CMD8251_RESET|CMD8251_EH);
4547	if (com->pc98_8251fifo_enable)
4548	    outb(I8251F_fcr, CTRL8251F_ENABLE);
4549	COM_INT_ENABLE
4550}
4551
4552static int
4553pc98_i8251_get_cmd(struct com_s *com)
4554{
4555	return com->pc98_prev_siocmd;
4556}
4557
4558static int
4559pc98_i8251_get_mod(struct com_s *com)
4560{
4561	return com->pc98_prev_siomod;
4562}
4563
4564static void
4565pc98_i8251_reset(struct com_s *com, int mode, int command)
4566{
4567	if (com->pc98_8251fifo_enable)
4568	    outb(I8251F_fcr, 0);
4569	outb(com->cmd_port, 0);	/* dummy */
4570	DELAY(2);
4571	outb(com->cmd_port, 0);	/* dummy */
4572	DELAY(2);
4573	outb(com->cmd_port, 0);	/* dummy */
4574	DELAY(2);
4575	outb(com->cmd_port, CMD8251_RESET);	/* internal reset */
4576	DELAY(2);
4577	outb(com->cmd_port, mode );	/* mode register */
4578	com->pc98_prev_siomod = mode;
4579	DELAY(2);
4580	pc98_i8251_set_cmd( com, (command|CMD8251_ER) );
4581	DELAY(10);
4582	if (com->pc98_8251fifo_enable)
4583	    outb(I8251F_fcr, CTRL8251F_ENABLE |
4584		 CTRL8251F_XMT_RST | CTRL8251F_RCV_RST);
4585}
4586
4587static void
4588pc98_check_sysclock(void)
4589{
4590	/* get system clock from port */
4591	if ( pc98_machine_type & M_8M ) {
4592	/* 8 MHz system & H98 */
4593		sysclock = 8;
4594	} else {
4595	/* 5 MHz system */
4596		sysclock = 5;
4597	}
4598}
4599
4600static void
4601com_cflag_and_speed_set( struct com_s *com, int cflag, int speed)
4602{
4603	int	cfcr=0;
4604	int	previnterrupt;
4605	u_int	count;
4606
4607	if (pc98_ttspeedtab(com, speed, &count) != 0)
4608		return;
4609
4610	previnterrupt = pc98_check_i8251_interrupt(com);
4611	pc98_disable_i8251_interrupt( com, IEN_Tx|IEN_TxEMP|IEN_Rx );
4612
4613	switch ( cflag&CSIZE ) {
4614	  case CS5:
4615		cfcr = MOD8251_5BITS; break;
4616	  case CS6:
4617		cfcr = MOD8251_6BITS; break;
4618	  case CS7:
4619		cfcr = MOD8251_7BITS; break;
4620	  case CS8:
4621		cfcr = MOD8251_8BITS; break;
4622	}
4623	if ( cflag&PARENB ) {
4624	    if ( cflag&PARODD )
4625		cfcr |= MOD8251_PODD;
4626	    else
4627		cfcr |= MOD8251_PEVEN;
4628	} else
4629		cfcr |= MOD8251_PDISAB;
4630
4631	if ( cflag&CSTOPB )
4632		cfcr |= MOD8251_STOP2;
4633	else
4634		cfcr |= MOD8251_STOP1;
4635
4636	if ( count & 0x10000 )
4637		cfcr |= MOD8251_CLKX1;
4638	else
4639		cfcr |= MOD8251_CLKX16;
4640
4641	if (epson_machine_id != 0x20) {	/* XXX */
4642		int	tmp;
4643		while (!((tmp = inb(com->sts_port)) & STS8251_TxEMP))
4644			;
4645	}
4646	/* set baud rate from ospeed */
4647	pc98_set_baud_rate( com, count );
4648
4649	if ( cfcr != pc98_i8251_get_mod(com) )
4650		pc98_i8251_reset(com, cfcr, pc98_i8251_get_cmd(com) );
4651
4652	pc98_enable_i8251_interrupt( com, previnterrupt );
4653}
4654
4655static int
4656pc98_ttspeedtab(struct com_s *com, int speed, u_int *divisor)
4657{
4658	int	if_type, effect_sp, count = -1, mod;
4659
4660	if_type = com->pc98_if_type & 0x0f;
4661
4662	switch (com->pc98_if_type) {
4663	case COM_IF_INTERNAL:
4664	    if (PC98SIO_baud_rate_port(if_type) != -1) {
4665		count = ttspeedtab(speed, if_8251_type[if_type].speedtab);
4666		if (count > 0) {
4667		    count |= COM1_EXT_CLOCK;
4668		    break;
4669		}
4670	    }
4671
4672	    /* for *1CLK asynchronous! mode, TEFUTEFU */
4673	    mod = (sysclock == 5) ? 2457600 : 1996800;
4674	    effect_sp = ttspeedtab( speed, pc98speedtab );
4675	    if ( effect_sp < 0 )	/* XXX */
4676		effect_sp = ttspeedtab( (speed - 1), pc98speedtab );
4677	    if ( effect_sp <= 0 )
4678		return effect_sp;
4679	    if ( effect_sp == speed )
4680		mod /= 16;
4681	    if ( mod % effect_sp )
4682		return(-1);
4683	    count = mod / effect_sp;
4684	    if ( count > 65535 )
4685		return(-1);
4686	    if ( effect_sp != speed )
4687		count |= 0x10000;
4688	    break;
4689	case COM_IF_PC9861K_1:
4690	case COM_IF_PC9861K_2:
4691	    count = 1;
4692	    break;
4693	case COM_IF_IND_SS_1:
4694	case COM_IF_IND_SS_2:
4695	case COM_IF_PIO9032B_1:
4696	case COM_IF_PIO9032B_2:
4697	    count = ttspeedtab( speed, if_8251_type[if_type].speedtab );
4698	    break;
4699	case COM_IF_B98_01_1:
4700	case COM_IF_B98_01_2:
4701	    count = ttspeedtab( speed, if_8251_type[if_type].speedtab );
4702#ifdef B98_01_OLD
4703	    if (count == 0 || count == 1) {
4704		count += 4;
4705		count |= 0x20000;  /* x1 mode for 76800 and 153600 */
4706	    }
4707#endif
4708	    break;
4709	}
4710
4711	if (count < 0)
4712		return count;
4713
4714	*divisor = (u_int) count;
4715	return 0;
4716}
4717
4718static void
4719pc98_set_baud_rate( struct com_s *com, u_int count )
4720{
4721	int	if_type, io, s;
4722
4723	if_type = com->pc98_if_type & 0x0f;
4724	io = rman_get_start(com->ioportres) & 0xff00;
4725
4726	switch (com->pc98_if_type) {
4727	case COM_IF_INTERNAL:
4728	    if (PC98SIO_baud_rate_port(if_type) != -1) {
4729		if (count & COM1_EXT_CLOCK) {
4730		    outb((Port_t)PC98SIO_baud_rate_port(if_type), count & 0xff);
4731		    break;
4732		} else {
4733		    outb((Port_t)PC98SIO_baud_rate_port(if_type), 0x09);
4734		}
4735	    }
4736
4737	    if (count == 0)
4738		return;
4739
4740	    /* set i8253 */
4741	    s = splclock();
4742	    if (count != 3)
4743		outb( 0x77, 0xb6 );
4744	    else
4745		outb( 0x77, 0xb4 );
4746	    outb( 0x5f, 0);
4747	    outb( 0x75, count & 0xff );
4748	    outb( 0x5f, 0);
4749	    outb( 0x75, (count >> 8) & 0xff );
4750	    splx(s);
4751	    break;
4752	case COM_IF_IND_SS_1:
4753	case COM_IF_IND_SS_2:
4754	    outb(io | PC98SIO_intr_ctrl_port(if_type), 0);
4755	    outb(io | PC98SIO_baud_rate_port(if_type), 0);
4756	    outb(io | PC98SIO_baud_rate_port(if_type), 0xc0);
4757	    outb(io | PC98SIO_baud_rate_port(if_type), (count >> 8) | 0x80);
4758	    outb(io | PC98SIO_baud_rate_port(if_type), count & 0xff);
4759	    break;
4760	case COM_IF_PIO9032B_1:
4761	case COM_IF_PIO9032B_2:
4762	    outb(io | PC98SIO_baud_rate_port(if_type), count);
4763	    break;
4764	case COM_IF_B98_01_1:
4765	case COM_IF_B98_01_2:
4766	    outb(io | PC98SIO_baud_rate_port(if_type), count & 0x0f);
4767#ifdef B98_01_OLD
4768	    /*
4769	     * Some old B98_01 board should be controlled
4770	     * in different way, but this hasn't been tested yet.
4771	     */
4772	    outb(io | PC98SIO_func_port(if_type),
4773		 (count & 0x20000) ? 0xf0 : 0xf2);
4774#endif
4775	    break;
4776	}
4777}
4778static int
4779pc98_check_if_type(device_t dev, struct siodev *iod)
4780{
4781	int	irr, io, if_type, tmp;
4782	static  short	irq_tab[2][8] = {
4783		{  3,  5,  6,  9, 10, 12, 13, -1},
4784		{  3, 10, 12, 13,  5,  6,  9, -1}
4785	};
4786
4787	if_type = iod->if_type & 0x0f;
4788	iod->irq = 0;
4789	io = isa_get_port(dev) & 0xff00;
4790
4791	if (IS_8251(iod->if_type)) {
4792	    if (PC98SIO_func_port(if_type) != -1) {
4793		outb(io | PC98SIO_func_port(if_type), 0xf2);
4794		tmp = ttspeedtab(9600, if_8251_type[if_type].speedtab);
4795		if (tmp != -1 && PC98SIO_baud_rate_port(if_type) != -1)
4796		    outb(io | PC98SIO_baud_rate_port(if_type), tmp);
4797	    }
4798
4799	    iod->cmd  = io | PC98SIO_cmd_port(if_type);
4800	    iod->sts  = io | PC98SIO_sts_port(if_type);
4801	    iod->mod  = io | PC98SIO_in_modem_port(if_type);
4802	    iod->ctrl = io | PC98SIO_intr_ctrl_port(if_type);
4803
4804	    if (iod->if_type == COM_IF_INTERNAL) {
4805		iod->irq = 4;
4806
4807		if (pc98_check_8251vfast()) {
4808			PC98SIO_baud_rate_port(if_type) = I8251F_div;
4809			if_8251_type[if_type].speedtab = pc98fast_speedtab;
4810		}
4811	    } else {
4812		tmp = inb( iod->mod ) & if_8251_type[if_type].irr_mask;
4813		if ((isa_get_port(dev) & 0xff) == IO_COM2)
4814		    iod->irq = irq_tab[0][tmp];
4815		else
4816		    iod->irq = irq_tab[1][tmp];
4817	    }
4818	} else {
4819	    irr = if_16550a_type[if_type].irr_read;
4820#ifdef COM_MULTIPORT
4821	    if (!COM_ISMULTIPORT(device_get_flags(dev)) ||
4822		    device_get_unit(dev) == COM_MPMASTER(device_get_flags(dev)))
4823#endif
4824	    if (irr != -1) {
4825		tmp = inb(io | irr);
4826		if (isa_get_port(dev) & 0x01)	/* XXX depend on RSB-384 */
4827		    iod->irq = irq_tab[1][tmp >> 3];
4828		else
4829		    iod->irq = irq_tab[0][tmp & 0x07];
4830	    }
4831	}
4832	if ( iod->irq == -1 ) return -1;
4833
4834	return 0;
4835}
4836static void
4837pc98_set_ioport(struct com_s *com)
4838{
4839	int	if_type = com->pc98_if_type & 0x0f;
4840	Port_t	io = rman_get_start(com->ioportres) & 0xff00;
4841
4842	pc98_check_sysclock();
4843	com->data_port		= io | PC98SIO_data_port(if_type);
4844	com->cmd_port		= io | PC98SIO_cmd_port(if_type);
4845	com->sts_port		= io | PC98SIO_sts_port(if_type);
4846	com->in_modem_port	= io | PC98SIO_in_modem_port(if_type);
4847	com->intr_ctrl_port	= io | PC98SIO_intr_ctrl_port(if_type);
4848}
4849static int
4850pc98_check_8251vfast(void)
4851{
4852    int	i;
4853
4854    outb(I8251F_div, 0x8c);
4855    DELAY(10);
4856    for (i = 0; i < 100; i++) {
4857	if ((inb(I8251F_div) & 0x80) != 0) {
4858	    i = 0;
4859	    break;
4860	}
4861	DELAY(1);
4862    }
4863    outb(I8251F_div, 0);
4864    DELAY(10);
4865    for (; i < 100; i++) {
4866	if ((inb(I8251F_div) & 0x80) == 0)
4867	    return 1;
4868	DELAY(1);
4869    }
4870
4871    return 0;
4872}
4873static int
4874pc98_check_8251fifo(void)
4875{
4876    u_char	tmp1, tmp2;
4877
4878    tmp1 = inb(I8251F_iir);
4879    DELAY(10);
4880    tmp2 = inb(I8251F_iir);
4881    if (((tmp1 ^ tmp2) & 0x40) != 0 && ((tmp1 | tmp2) & 0x20) == 0)
4882	return 1;
4883
4884    return 0;
4885}
4886#endif /* PC98 defined */
4887