sio.c revision 130096
1/*- 2 * Copyright (c) 1991 The Regents of the University of California. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 4. Neither the name of the University nor the names of its contributors 14 * may be used to endorse or promote products derived from this software 15 * without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * $FreeBSD: head/sys/pc98/cbus/sio.c 130096 2004-06-04 21:55:55Z phk $ 30 * from: @(#)com.c 7.5 (Berkeley) 5/16/91 31 * from: i386/isa sio.c,v 1.234 32 */ 33 34#include "opt_comconsole.h" 35#include "opt_compat.h" 36#include "opt_ddb.h" 37#include "opt_sio.h" 38 39/* 40 * Serial driver, based on 386BSD-0.1 com driver. 41 * Mostly rewritten to use pseudo-DMA. 42 * Works for National Semiconductor NS8250-NS16550AF UARTs. 43 * COM driver, based on HP dca driver. 44 * 45 * Changes for PC-Card integration: 46 * - Added PC-Card driver table and handlers 47 */ 48/*=============================================================== 49 * 386BSD(98),FreeBSD-1.1x(98) com driver. 50 * ----- 51 * modified for PC9801 by M.Ishii 52 * Kyoto University Microcomputer Club (KMC) 53 * Chou "TEFUTEFU" Hirotomi 54 * Kyoto Univ. the faculty of medicine 55 *=============================================================== 56 * FreeBSD-2.0.1(98) sio driver. 57 * ----- 58 * modified for pc98 Internal i8251 and MICRO CORE MC16550II 59 * T.Koike(hfc01340@niftyserve.or.jp) 60 * implement kernel device configuration 61 * aizu@orient.center.nitech.ac.jp 62 * 63 * Notes. 64 * ----- 65 * PC98 localization based on 386BSD(98) com driver. Using its PC98 local 66 * functions. 67 * This driver is under debugging,has bugs. 68 */ 69/* 70 * modified for AIWA B98-01 71 * by T.Hatanou <hatanou@yasuda.comm.waseda.ac.jp> last update: 15 Sep.1995 72 */ 73/* 74 * Modified by Y.Takahashi of Kogakuin University. 75 */ 76/* 77 * modified for 8251(FIFO) by Seigo TANIMURA <tanimura@FreeBSD.org> 78 */ 79 80#include <sys/param.h> 81#include <sys/systm.h> 82#include <sys/bus.h> 83#include <sys/conf.h> 84#include <sys/fcntl.h> 85#include <sys/interrupt.h> 86#include <sys/kernel.h> 87#include <sys/limits.h> 88#include <sys/lock.h> 89#include <sys/malloc.h> 90#include <sys/module.h> 91#include <sys/mutex.h> 92#include <sys/proc.h> 93#include <sys/reboot.h> 94#include <sys/sysctl.h> 95#include <sys/syslog.h> 96#include <sys/tty.h> 97#include <machine/bus.h> 98#include <sys/rman.h> 99#include <sys/timepps.h> 100#include <sys/uio.h> 101#include <sys/cons.h> 102#if DDB > 0 103#include <ddb/ddb.h> 104#endif 105 106#include <isa/isavar.h> 107 108#include <machine/resource.h> 109 110#include <dev/sio/sioreg.h> 111#include <dev/sio/siovar.h> 112 113#ifdef PC98 114#include <pc98/pc98/pc98.h> 115#include <pc98/pc98/pc98_machdep.h> 116#endif 117 118#ifdef COM_ESP 119#include <dev/ic/esp.h> 120#endif 121#include <dev/ic/ns16550.h> 122#ifdef PC98 123#include <dev/ic/i8251.h> 124#include <dev/ic/rsa.h> 125#endif 126 127#define LOTS_OF_EVENTS 64 /* helps separate urgent events from input */ 128 129#define CALLOUT_MASK 0x80 130#define CONTROL_MASK 0x60 131#define CONTROL_INIT_STATE 0x20 132#define CONTROL_LOCK_STATE 0x40 133#define DEV_TO_UNIT(dev) (MINOR_TO_UNIT(minor(dev))) 134#define MINOR_TO_UNIT(mynor) ((((mynor) & ~0xffffU) >> (8 + 3)) \ 135 | ((mynor) & 0x1f)) 136#define UNIT_TO_MINOR(unit) ((((unit) & ~0x1fU) << (8 + 3)) \ 137 | ((unit) & 0x1f)) 138 139/* 140 * Meaning of flags: 141 * 142 * 0x00000001 shared IRQs 143 * 0x00000002 disable FIFO 144 * 0x00000008 recover sooner from lost output interrupts 145 * 0x00000010 device is potential system console 146 * 0x00000020 device is forced to become system console 147 * 0x00000040 device is reserved for low-level IO 148 * 0x00000080 use this port for remote kernel debugging 149 * 0x0000??00 minor number of master port 150 * 0x00010000 PPS timestamping on CTS instead of DCD 151 * 0x00080000 IIR_TXRDY bug 152 * 0x00400000 If no comconsole found then mark as a comconsole 153 * 0x1?000000 interface type 154 */ 155 156#ifdef COM_MULTIPORT 157/* checks in flags for multiport and which is multiport "master chip" 158 * for a given card 159 */ 160#define COM_ISMULTIPORT(flags) ((flags) & 0x01) 161#define COM_MPMASTER(flags) (((flags) >> 8) & 0x0ff) 162#ifndef PC98 163#define COM_NOTAST4(flags) ((flags) & 0x04) 164#endif 165#else 166#define COM_ISMULTIPORT(flags) (0) 167#endif /* COM_MULTIPORT */ 168 169#define COM_C_IIR_TXRDYBUG 0x80000 170#define COM_CONSOLE(flags) ((flags) & 0x10) 171#define COM_DEBUGGER(flags) ((flags) & 0x80) 172#ifndef PC98 173#define COM_FIFOSIZE(flags) (((flags) & 0xff000000) >> 24) 174#endif 175#define COM_FORCECONSOLE(flags) ((flags) & 0x20) 176#define COM_IIR_TXRDYBUG(flags) ((flags) & COM_C_IIR_TXRDYBUG) 177#define COM_LLCONSOLE(flags) ((flags) & 0x40) 178#define COM_LOSESOUTINTS(flags) ((flags) & 0x08) 179#define COM_NOFIFO(flags) ((flags) & 0x02) 180#ifndef PC98 181#define COM_NOSCR(flags) ((flags) & 0x100000) 182#endif 183#define COM_PPSCTS(flags) ((flags) & 0x10000) 184#ifndef PC98 185#define COM_ST16650A(flags) ((flags) & 0x20000) 186#define COM_TI16754(flags) ((flags) & 0x200000) 187#endif 188 189#define sio_getreg(com, off) \ 190 (bus_space_read_1((com)->bst, (com)->bsh, (off))) 191#define sio_setreg(com, off, value) \ 192 (bus_space_write_1((com)->bst, (com)->bsh, (off), (value))) 193 194/* 195 * com state bits. 196 * (CS_BUSY | CS_TTGO) and (CS_BUSY | CS_TTGO | CS_ODEVREADY) must be higher 197 * than the other bits so that they can be tested as a group without masking 198 * off the low bits. 199 * 200 * The following com and tty flags correspond closely: 201 * CS_BUSY = TS_BUSY (maintained by comstart(), siopoll() and 202 * comstop()) 203 * CS_TTGO = ~TS_TTSTOP (maintained by comparam() and comstart()) 204 * CS_CTS_OFLOW = CCTS_OFLOW (maintained by comparam()) 205 * CS_RTS_IFLOW = CRTS_IFLOW (maintained by comparam()) 206 * TS_FLUSH is not used. 207 * XXX I think TIOCSETA doesn't clear TS_TTSTOP when it clears IXON. 208 * XXX CS_*FLOW should be CF_*FLOW in com->flags (control flags not state). 209 */ 210#define CS_BUSY 0x80 /* output in progress */ 211#define CS_TTGO 0x40 /* output not stopped by XOFF */ 212#define CS_ODEVREADY 0x20 /* external device h/w ready (CTS) */ 213#define CS_CHECKMSR 1 /* check of MSR scheduled */ 214#define CS_CTS_OFLOW 2 /* use CTS output flow control */ 215#define CS_DTR_OFF 0x10 /* DTR held off */ 216#define CS_ODONE 4 /* output completed */ 217#define CS_RTS_IFLOW 8 /* use RTS input flow control */ 218#define CSE_BUSYCHECK 1 /* siobusycheck() scheduled */ 219 220static char const * const error_desc[] = { 221#define CE_OVERRUN 0 222 "silo overflow", 223#define CE_INTERRUPT_BUF_OVERFLOW 1 224 "interrupt-level buffer overflow", 225#define CE_TTY_BUF_OVERFLOW 2 226 "tty-level buffer overflow", 227}; 228 229#define CE_NTYPES 3 230#define CE_RECORD(com, errnum) (++(com)->delta_error_counts[errnum]) 231 232/* types. XXX - should be elsewhere */ 233typedef u_int Port_t; /* hardware port */ 234typedef u_char bool_t; /* boolean */ 235 236/* queue of linear buffers */ 237struct lbq { 238 u_char *l_head; /* next char to process */ 239 u_char *l_tail; /* one past the last char to process */ 240 struct lbq *l_next; /* next in queue */ 241 bool_t l_queued; /* nonzero if queued */ 242}; 243 244/* com device structure */ 245struct com_s { 246 u_char state; /* miscellaneous flag bits */ 247 bool_t active_out; /* nonzero if the callout device is open */ 248 u_char cfcr_image; /* copy of value written to CFCR */ 249#ifdef COM_ESP 250 bool_t esp; /* is this unit a hayes esp board? */ 251#endif 252 u_char extra_state; /* more flag bits, separate for order trick */ 253 u_char fifo_image; /* copy of value written to FIFO */ 254 bool_t hasfifo; /* nonzero for 16550 UARTs */ 255 bool_t loses_outints; /* nonzero if device loses output interrupts */ 256 u_char mcr_image; /* copy of value written to MCR */ 257#ifdef COM_MULTIPORT 258 bool_t multiport; /* is this unit part of a multiport device? */ 259#endif /* COM_MULTIPORT */ 260 bool_t no_irq; /* nonzero if irq is not attached */ 261 bool_t gone; /* hardware disappeared */ 262 bool_t poll; /* nonzero if polling is required */ 263 bool_t poll_output; /* nonzero if polling for output is required */ 264 bool_t st16650a; /* nonzero if Startech 16650A compatible */ 265 int unit; /* unit number */ 266 int dtr_wait; /* time to hold DTR down on close (* 1/hz) */ 267 u_int flags; /* copy of device flags */ 268 u_int tx_fifo_size; 269 u_int wopeners; /* # processes waiting for DCD in open() */ 270 271 /* 272 * The high level of the driver never reads status registers directly 273 * because there would be too many side effects to handle conveniently. 274 * Instead, it reads copies of the registers stored here by the 275 * interrupt handler. 276 */ 277 u_char last_modem_status; /* last MSR read by intr handler */ 278 u_char prev_modem_status; /* last MSR handled by high level */ 279 280 u_char hotchar; /* ldisc-specific char to be handled ASAP */ 281 u_char *ibuf; /* start of input buffer */ 282 u_char *ibufend; /* end of input buffer */ 283 u_char *ibufold; /* old input buffer, to be freed */ 284 u_char *ihighwater; /* threshold in input buffer */ 285 u_char *iptr; /* next free spot in input buffer */ 286 int ibufsize; /* size of ibuf (not include error bytes) */ 287 int ierroff; /* offset of error bytes in ibuf */ 288 289 struct lbq obufq; /* head of queue of output buffers */ 290 struct lbq obufs[2]; /* output buffers */ 291 292 bus_space_tag_t bst; 293 bus_space_handle_t bsh; 294 295#ifdef PC98 296 Port_t cmd_port; 297 Port_t sts_port; 298 Port_t in_modem_port; 299 Port_t intr_ctrl_port; 300 Port_t rsabase; /* Iobase address of an I/O-DATA RSA board. */ 301 int intr_enable; 302 int pc98_prev_modem_status; 303 int pc98_modem_delta; 304 int modem_car_chg_timer; 305 int pc98_prev_siocmd; 306 int pc98_prev_siomod; 307 int modem_checking; 308 int pc98_if_type; 309 310 bool_t pc98_8251fifo; 311 bool_t pc98_8251fifo_enable; 312#endif /* PC98 */ 313 Port_t data_port; /* i/o ports */ 314#ifdef COM_ESP 315 Port_t esp_port; 316#endif 317 Port_t int_ctl_port; 318 Port_t int_id_port; 319 Port_t modem_ctl_port; 320 Port_t line_status_port; 321 Port_t modem_status_port; 322 323 struct tty *tp; /* cross reference */ 324 325 /* Initial state. */ 326 struct termios it_in; /* should be in struct tty */ 327 struct termios it_out; 328 329 /* Lock state. */ 330 struct termios lt_in; /* should be in struct tty */ 331 struct termios lt_out; 332 333 bool_t do_timestamp; 334 bool_t do_dcd_timestamp; 335 struct timeval timestamp; 336 struct timeval dcd_timestamp; 337 struct pps_state pps; 338 int pps_bit; 339#ifdef ALT_BREAK_TO_DEBUGGER 340 int alt_brk_state; 341#endif 342 343 u_long bytes_in; /* statistics */ 344 u_long bytes_out; 345 u_int delta_error_counts[CE_NTYPES]; 346 u_long error_counts[CE_NTYPES]; 347 348 u_long rclk; 349 350 struct resource *irqres; 351 struct resource *ioportres; 352 int ioportrid; 353 void *cookie; 354 dev_t devs[6]; 355 356 /* 357 * Data area for output buffers. Someday we should build the output 358 * buffer queue without copying data. 359 */ 360#ifdef PC98 361 int obufsize; 362 u_char *obuf1; 363 u_char *obuf2; 364#else 365 u_char obuf1[256]; 366 u_char obuf2[256]; 367#endif 368}; 369 370#ifdef COM_ESP 371static int espattach(struct com_s *com, Port_t esp_port); 372#endif 373 374static timeout_t siobusycheck; 375static u_int siodivisor(u_long rclk, speed_t speed); 376static timeout_t siodtrwakeup; 377static void comhardclose(struct com_s *com); 378static void sioinput(struct com_s *com); 379static void siointr1(struct com_s *com); 380static void siointr(void *arg); 381static int commctl(struct com_s *com, int bits, int how); 382static int comparam(struct tty *tp, struct termios *t); 383static void siopoll(void *); 384static void siosettimeout(void); 385static int siosetwater(struct com_s *com, speed_t speed); 386static void comstart(struct tty *tp); 387static void comstop(struct tty *tp, int rw); 388static timeout_t comwakeup; 389 390char sio_driver_name[] = "sio"; 391static struct mtx sio_lock; 392static int sio_inited; 393 394/* table and macro for fast conversion from a unit number to its com struct */ 395devclass_t sio_devclass; 396#define com_addr(unit) ((struct com_s *) \ 397 devclass_get_softc(sio_devclass, unit)) /* XXX */ 398 399static d_open_t sioopen; 400static d_close_t sioclose; 401static d_read_t sioread; 402static d_write_t siowrite; 403static d_ioctl_t sioioctl; 404 405static struct cdevsw sio_cdevsw = { 406 .d_version = D_VERSION, 407 .d_open = sioopen, 408 .d_close = sioclose, 409 .d_read = sioread, 410 .d_write = siowrite, 411 .d_ioctl = sioioctl, 412 .d_name = sio_driver_name, 413 .d_flags = D_TTY | D_NEEDGIANT, 414}; 415 416int comconsole = -1; 417static volatile speed_t comdefaultrate = CONSPEED; 418static u_long comdefaultrclk = DEFAULT_RCLK; 419SYSCTL_ULONG(_machdep, OID_AUTO, conrclk, CTLFLAG_RW, &comdefaultrclk, 0, ""); 420static speed_t gdbdefaultrate = GDBSPEED; 421SYSCTL_UINT(_machdep, OID_AUTO, gdbspeed, CTLFLAG_RW, 422 &gdbdefaultrate, GDBSPEED, ""); 423static u_int com_events; /* input chars + weighted output completions */ 424static Port_t siocniobase; 425static int siocnunit = -1; 426static Port_t siogdbiobase; 427static int siogdbunit = -1; 428static void *sio_slow_ih; 429static void *sio_fast_ih; 430static int sio_timeout; 431static int sio_timeouts_until_log; 432static struct callout_handle sio_timeout_handle 433 = CALLOUT_HANDLE_INITIALIZER(&sio_timeout_handle); 434static int sio_numunits; 435 436#ifdef PC98 437struct siodev { 438 short if_type; 439 short irq; 440 Port_t cmd, sts, ctrl, mod; 441}; 442static int sysclock; 443 444#define COM_INT_DISABLE {int previpri; previpri=spltty(); 445#define COM_INT_ENABLE splx(previpri);} 446#define IEN_TxFLAG IEN_Tx 447 448#define COM_CARRIER_DETECT_EMULATE 0 449#define PC98_CHECK_MODEM_INTERVAL (hz/10) 450#define DCD_OFF_TOLERANCE 2 451#define DCD_ON_RECOGNITION 2 452#define IS_8251(if_type) (!(if_type & 0x10)) 453#define COM1_EXT_CLOCK 0x40000 454 455static void commint(dev_t dev); 456static void com_tiocm_set(struct com_s *com, int msr); 457static void com_tiocm_bis(struct com_s *com, int msr); 458static void com_tiocm_bic(struct com_s *com, int msr); 459static int com_tiocm_get(struct com_s *com); 460static int com_tiocm_get_delta(struct com_s *com); 461static void pc98_msrint_start(dev_t dev); 462static void com_cflag_and_speed_set(struct com_s *com, int cflag, int speed); 463static int pc98_ttspeedtab(struct com_s *com, int speed, u_int *divisor); 464static int pc98_get_modem_status(struct com_s *com); 465static timeout_t pc98_check_msr; 466static void pc98_set_baud_rate(struct com_s *com, u_int count); 467static void pc98_i8251_reset(struct com_s *com, int mode, int command); 468static void pc98_disable_i8251_interrupt(struct com_s *com, int mod); 469static void pc98_enable_i8251_interrupt(struct com_s *com, int mod); 470static int pc98_check_i8251_interrupt(struct com_s *com); 471static int pc98_i8251_get_cmd(struct com_s *com); 472static int pc98_i8251_get_mod(struct com_s *com); 473static void pc98_i8251_set_cmd(struct com_s *com, int x); 474static void pc98_i8251_or_cmd(struct com_s *com, int x); 475static void pc98_i8251_clear_cmd(struct com_s *com, int x); 476static void pc98_i8251_clear_or_cmd(struct com_s *com, int clr, int x); 477static int pc98_check_if_type(device_t dev, struct siodev *iod); 478static int pc98_check_8251vfast(void); 479static int pc98_check_8251fifo(void); 480static void pc98_check_sysclock(void); 481static void pc98_set_ioport(struct com_s *com); 482 483#define com_int_Tx_disable(com) \ 484 pc98_disable_i8251_interrupt(com,IEN_Tx|IEN_TxEMP) 485#define com_int_Tx_enable(com) \ 486 pc98_enable_i8251_interrupt(com,IEN_TxFLAG) 487#define com_int_Rx_disable(com) \ 488 pc98_disable_i8251_interrupt(com,IEN_Rx) 489#define com_int_Rx_enable(com) \ 490 pc98_enable_i8251_interrupt(com,IEN_Rx) 491#define com_int_TxRx_disable(com) \ 492 pc98_disable_i8251_interrupt(com,IEN_Tx|IEN_TxEMP|IEN_Rx) 493#define com_int_TxRx_enable(com) \ 494 pc98_enable_i8251_interrupt(com,IEN_TxFLAG|IEN_Rx) 495#define com_send_break_on(com) \ 496 pc98_i8251_or_cmd(com,CMD8251_SBRK) 497#define com_send_break_off(com) \ 498 pc98_i8251_clear_cmd(com,CMD8251_SBRK) 499 500static struct speedtab pc98speedtab[] = { /* internal RS232C interface */ 501 { 0, 0, }, 502 { 50, 50, }, 503 { 75, 75, }, 504 { 150, 150, }, 505 { 200, 200, }, 506 { 300, 300, }, 507 { 600, 600, }, 508 { 1200, 1200, }, 509 { 2400, 2400, }, 510 { 4800, 4800, }, 511 { 9600, 9600, }, 512 { 19200, 19200, }, 513 { 38400, 38400, }, 514 { 51200, 51200, }, 515 { 76800, 76800, }, 516 { 20800, 20800, }, 517 { 31200, 31200, }, 518 { 41600, 41600, }, 519 { 62400, 62400, }, 520 { -1, -1 } 521}; 522static struct speedtab pc98fast_speedtab[] = { 523 { 9600, 0x80 | (DEFAULT_RCLK / (16 * (9600))), }, 524 { 19200, 0x80 | (DEFAULT_RCLK / (16 * (19200))), }, 525 { 38400, 0x80 | (DEFAULT_RCLK / (16 * (38400))), }, 526 { 57600, 0x80 | (DEFAULT_RCLK / (16 * (57600))), }, 527 { 115200, 0x80 | (DEFAULT_RCLK / (16 * (115200))), }, 528 { -1, -1 } 529}; 530static struct speedtab comspeedtab_pio9032b[] = { 531 { 300, 6, }, 532 { 600, 5, }, 533 { 1200, 4, }, 534 { 2400, 3, }, 535 { 4800, 2, }, 536 { 9600, 1, }, 537 { 19200, 0, }, 538 { 38400, 7, }, 539 { -1, -1 } 540}; 541static struct speedtab comspeedtab_b98_01[] = { 542 { 75, 11, }, 543 { 150, 10, }, 544 { 300, 9, }, 545 { 600, 8, }, 546 { 1200, 7, }, 547 { 2400, 6, }, 548 { 4800, 5, }, 549 { 9600, 4, }, 550 { 19200, 3, }, 551 { 38400, 2, }, 552 { 76800, 1, }, 553 { 153600, 0, }, 554 { -1, -1 } 555}; 556static struct speedtab comspeedtab_ind[] = { 557 { 300, 1536, }, 558 { 600, 768, }, 559 { 1200, 384, }, 560 { 2400, 192, }, 561 { 4800, 96, }, 562 { 9600, 48, }, 563 { 19200, 24, }, 564 { 38400, 12, }, 565 { 57600, 8, }, 566 { 115200, 4, }, 567 { 153600, 3, }, 568 { 230400, 2, }, 569 { 460800, 1, }, 570 { -1, -1 } 571}; 572 573struct { 574 char *name; 575 short port_table[7]; 576 short irr_mask; 577 struct speedtab *speedtab; 578 short check_irq; 579} if_8251_type[] = { 580 /* COM_IF_INTERNAL */ 581 { " (internal)", {0x30, 0x32, 0x32, 0x33, 0x35, -1, -1}, 582 -1, pc98speedtab, 1 }, 583 /* COM_IF_PC9861K_1 */ 584 { " (PC9861K)", {0xb1, 0xb3, 0xb3, 0xb0, 0xb0, -1, -1}, 585 3, NULL, 1 }, 586 /* COM_IF_PC9861K_2 */ 587 { " (PC9861K)", {0xb9, 0xbb, 0xbb, 0xb2, 0xb2, -1, -1}, 588 3, NULL, 1 }, 589 /* COM_IF_IND_SS_1 */ 590 { " (IND-SS)", {0xb1, 0xb3, 0xb3, 0xb0, 0xb0, 0xb3, -1}, 591 3, comspeedtab_ind, 1 }, 592 /* COM_IF_IND_SS_2 */ 593 { " (IND-SS)", {0xb9, 0xbb, 0xbb, 0xb2, 0xb2, 0xbb, -1}, 594 3, comspeedtab_ind, 1 }, 595 /* COM_IF_PIO9032B_1 */ 596 { " (PIO9032B)", {0xb1, 0xb3, 0xb3, 0xb0, 0xb0, 0xb8, -1}, 597 7, comspeedtab_pio9032b, 1 }, 598 /* COM_IF_PIO9032B_2 */ 599 { " (PIO9032B)", {0xb9, 0xbb, 0xbb, 0xb2, 0xb2, 0xba, -1}, 600 7, comspeedtab_pio9032b, 1 }, 601 /* COM_IF_B98_01_1 */ 602 { " (B98-01)", {0xb1, 0xb3, 0xb3, 0xb0, 0xb0, 0xd1, 0xd3}, 603 7, comspeedtab_b98_01, 0 }, 604 /* COM_IF_B98_01_2 */ 605 { " (B98-01)", {0xb9, 0xbb, 0xbb, 0xb2, 0xb2, 0xd5, 0xd7}, 606 7, comspeedtab_b98_01, 0 }, 607}; 608#define PC98SIO_data_port(type) (if_8251_type[type].port_table[0]) 609#define PC98SIO_cmd_port(type) (if_8251_type[type].port_table[1]) 610#define PC98SIO_sts_port(type) (if_8251_type[type].port_table[2]) 611#define PC98SIO_in_modem_port(type) (if_8251_type[type].port_table[3]) 612#define PC98SIO_intr_ctrl_port(type) (if_8251_type[type].port_table[4]) 613#define PC98SIO_baud_rate_port(type) (if_8251_type[type].port_table[5]) 614#define PC98SIO_func_port(type) (if_8251_type[type].port_table[6]) 615 616#define I8251F_data 0x130 617#define I8251F_lsr 0x132 618#define I8251F_msr 0x134 619#define I8251F_iir 0x136 620#define I8251F_fcr 0x138 621#define I8251F_div 0x13a 622 623 624static bus_addr_t port_table_0[] = 625 {0x000, 0x001, 0x002, 0x003, 0x004, 0x005, 0x006, 0x007}; 626static bus_addr_t port_table_1[] = 627 {0x000, 0x002, 0x004, 0x006, 0x008, 0x00a, 0x00c, 0x00e}; 628static bus_addr_t port_table_8[] = 629 {0x000, 0x100, 0x200, 0x300, 0x400, 0x500, 0x600, 0x700}; 630static bus_addr_t port_table_rsa[] = { 631 0x008, 0x009, 0x00a, 0x00b, 0x00c, 0x00d, 0x00e, 0x00f, 632 0x000, 0x001, 0x002, 0x003, 0x004, 0x005, 0x006, 0x007 633}; 634 635struct { 636 char *name; 637 short irr_read; 638 short irr_write; 639 bus_addr_t *iat; 640 bus_size_t iatsz; 641 u_long rclk; 642} if_16550a_type[] = { 643 /* COM_IF_RSA98 */ 644 {" (RSA-98)", -1, -1, port_table_0, IO_COMSIZE, DEFAULT_RCLK}, 645 /* COM_IF_NS16550 */ 646 {"", -1, -1, port_table_0, IO_COMSIZE, DEFAULT_RCLK}, 647 /* COM_IF_SECOND_CCU */ 648 {"", -1, -1, port_table_0, IO_COMSIZE, DEFAULT_RCLK}, 649 /* COM_IF_MC16550II */ 650 {" (MC16550II)", -1, 0x1000, port_table_8, IO_COMSIZE, 651 DEFAULT_RCLK * 4}, 652 /* COM_IF_MCRS98 */ 653 {" (MC-RS98)", -1, 0x1000, port_table_8, IO_COMSIZE, DEFAULT_RCLK * 4}, 654 /* COM_IF_RSB3000 */ 655 {" (RSB-3000)", 0xbf, -1, port_table_1, IO_COMSIZE, DEFAULT_RCLK * 10}, 656 /* COM_IF_RSB384 */ 657 {" (RSB-384)", 0xbf, -1, port_table_1, IO_COMSIZE, DEFAULT_RCLK * 10}, 658 /* COM_IF_MODEM_CARD */ 659 {"", -1, -1, port_table_0, IO_COMSIZE, DEFAULT_RCLK}, 660 /* COM_IF_RSA98III */ 661 {" (RSA-98III)", -1, -1, port_table_rsa, 16, DEFAULT_RCLK * 8}, 662 /* COM_IF_ESP98 */ 663 {" (ESP98)", -1, -1, port_table_1, IO_COMSIZE, DEFAULT_RCLK * 4}, 664}; 665#endif /* PC98 */ 666 667#ifdef COM_ESP 668#ifdef PC98 669 670/* XXX configure this properly. */ 671/* XXX quite broken for new-bus. */ 672static Port_t likely_com_ports[] = { 0, 0xb0, 0xb1, 0 }; 673static Port_t likely_esp_ports[] = { 0xc0d0, 0 }; 674 675#define ESP98_CMD1 (ESP_CMD1 * 0x100) 676#define ESP98_CMD2 (ESP_CMD2 * 0x100) 677#define ESP98_STATUS1 (ESP_STATUS1 * 0x100) 678#define ESP98_STATUS2 (ESP_STATUS2 * 0x100) 679 680#else /* PC98 */ 681 682/* XXX configure this properly. */ 683static Port_t likely_com_ports[] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8, }; 684static Port_t likely_esp_ports[] = { 0x140, 0x180, 0x280, 0 }; 685 686#endif /* PC98 */ 687#endif 688 689/* 690 * handle sysctl read/write requests for console speed 691 * 692 * In addition to setting comdefaultrate for I/O through /dev/console, 693 * also set the initial and lock values for the /dev/ttyXX device 694 * if there is one associated with the console. Finally, if the /dev/tty 695 * device has already been open, change the speed on the open running port 696 * itself. 697 */ 698 699static int 700sysctl_machdep_comdefaultrate(SYSCTL_HANDLER_ARGS) 701{ 702 int error, s; 703 speed_t newspeed; 704 struct com_s *com; 705 struct tty *tp; 706 707 newspeed = comdefaultrate; 708 709 error = sysctl_handle_opaque(oidp, &newspeed, sizeof newspeed, req); 710 if (error || !req->newptr) 711 return (error); 712 713 comdefaultrate = newspeed; 714 715 if (comconsole < 0) /* serial console not selected? */ 716 return (0); 717 718 com = com_addr(comconsole); 719 if (com == NULL) 720 return (ENXIO); 721 722 /* 723 * set the initial and lock rates for /dev/ttydXX and /dev/cuaXX 724 * (note, the lock rates really are boolean -- if non-zero, disallow 725 * speed changes) 726 */ 727 com->it_in.c_ispeed = com->it_in.c_ospeed = 728 com->lt_in.c_ispeed = com->lt_in.c_ospeed = 729 com->it_out.c_ispeed = com->it_out.c_ospeed = 730 com->lt_out.c_ispeed = com->lt_out.c_ospeed = comdefaultrate; 731 732 /* 733 * if we're open, change the running rate too 734 */ 735 tp = com->tp; 736 if (tp && (tp->t_state & TS_ISOPEN)) { 737 tp->t_termios.c_ispeed = 738 tp->t_termios.c_ospeed = comdefaultrate; 739 s = spltty(); 740 error = comparam(tp, &tp->t_termios); 741 splx(s); 742 } 743 return error; 744} 745 746SYSCTL_PROC(_machdep, OID_AUTO, conspeed, CTLTYPE_INT | CTLFLAG_RW, 747 0, 0, sysctl_machdep_comdefaultrate, "I", ""); 748 749/* 750 * Unload the driver and clear the table. 751 * XXX this is mostly wrong. 752 * XXX TODO: 753 * This is usually called when the card is ejected, but 754 * can be caused by a kldunload of a controller driver. 755 * The idea is to reset the driver's view of the device 756 * and ensure that any driver entry points such as 757 * read and write do not hang. 758 */ 759int 760siodetach(dev) 761 device_t dev; 762{ 763 struct com_s *com; 764 int i; 765 766 com = (struct com_s *) device_get_softc(dev); 767 if (com == NULL) { 768 device_printf(dev, "NULL com in siounload\n"); 769 return (0); 770 } 771 com->gone = TRUE; 772 for (i = 0 ; i < 6; i++) 773 destroy_dev(com->devs[i]); 774 if (com->irqres) { 775 bus_teardown_intr(dev, com->irqres, com->cookie); 776 bus_release_resource(dev, SYS_RES_IRQ, 0, com->irqres); 777 } 778 if (com->ioportres) 779 bus_release_resource(dev, SYS_RES_IOPORT, com->ioportrid, 780 com->ioportres); 781 if (com->tp && (com->tp->t_state & TS_ISOPEN)) { 782 device_printf(dev, "still open, forcing close\n"); 783 ttyld_close(com->tp, 0); 784 ttyclose(com->tp); 785 } else { 786 if (com->ibuf != NULL) 787 free(com->ibuf, M_DEVBUF); 788#ifdef PC98 789 if (com->obuf1 != NULL) 790 free(com->obuf1, M_DEVBUF); 791#endif 792 device_set_softc(dev, NULL); 793 free(com, M_DEVBUF); 794 } 795 return (0); 796} 797 798int 799sioprobe(dev, xrid, rclk, noprobe) 800 device_t dev; 801 int xrid; 802 u_long rclk; 803 int noprobe; 804{ 805#if 0 806 static bool_t already_init; 807 device_t xdev; 808#endif 809 struct com_s *com; 810 u_int divisor; 811 bool_t failures[10]; 812 int fn; 813 device_t idev; 814 Port_t iobase; 815 intrmask_t irqmap[4]; 816 intrmask_t irqs; 817 u_char mcr_image; 818 int result; 819 u_long xirq; 820 u_int flags = device_get_flags(dev); 821 int rid; 822 struct resource *port; 823#ifdef PC98 824 int tmp; 825 struct siodev iod; 826#endif 827 828#ifdef PC98 829 iod.if_type = GET_IFTYPE(flags); 830 if ((iod.if_type < 0 || iod.if_type > COM_IF_END1) && 831 (iod.if_type < 0x10 || iod.if_type > COM_IF_END2)) 832 return ENXIO; 833#endif 834 835 rid = xrid; 836#ifdef PC98 837 if (IS_8251(iod.if_type)) { 838 port = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid, 839 RF_ACTIVE); 840 } else if (iod.if_type == COM_IF_MODEM_CARD || 841 iod.if_type == COM_IF_RSA98III || 842 isa_get_vendorid(dev)) { 843 port = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 0, ~0, 844 if_16550a_type[iod.if_type & 0x0f].iatsz, RF_ACTIVE); 845 } else { 846 port = isa_alloc_resourcev(dev, SYS_RES_IOPORT, &rid, 847 if_16550a_type[iod.if_type & 0x0f].iat, 848 if_16550a_type[iod.if_type & 0x0f].iatsz, RF_ACTIVE); 849 } 850#else 851 port = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 852 0, ~0, IO_COMSIZE, RF_ACTIVE); 853#endif 854 if (!port) 855 return (ENXIO); 856#ifdef PC98 857 if (!IS_8251(iod.if_type)) { 858 if (isa_load_resourcev(port, 859 if_16550a_type[iod.if_type & 0x0f].iat, 860 if_16550a_type[iod.if_type & 0x0f].iatsz) != 0) { 861 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 862 return ENXIO; 863 } 864 } 865#endif 866 867 com = malloc(sizeof(*com), M_DEVBUF, M_NOWAIT | M_ZERO); 868 if (com == NULL) { 869 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 870 return (ENOMEM); 871 } 872 device_set_softc(dev, com); 873 com->bst = rman_get_bustag(port); 874 com->bsh = rman_get_bushandle(port); 875#ifdef PC98 876 if (!IS_8251(iod.if_type) && rclk == 0) 877 rclk = if_16550a_type[iod.if_type & 0x0f].rclk; 878#else 879 if (rclk == 0) 880 rclk = DEFAULT_RCLK; 881#endif 882 com->rclk = rclk; 883 884 while (sio_inited != 2) 885 if (atomic_cmpset_int(&sio_inited, 0, 1)) { 886 mtx_init(&sio_lock, sio_driver_name, NULL, 887 (comconsole != -1) ? 888 MTX_SPIN | MTX_QUIET : MTX_SPIN); 889 atomic_store_rel_int(&sio_inited, 2); 890 } 891 892#if 0 893 /* 894 * XXX this is broken - when we are first called, there are no 895 * previously configured IO ports. We could hard code 896 * 0x3f8, 0x2f8, 0x3e8, 0x2e8 etc but that's probably worse. 897 * This code has been doing nothing since the conversion since 898 * "count" is zero the first time around. 899 */ 900 if (!already_init) { 901 /* 902 * Turn off MCR_IENABLE for all likely serial ports. An unused 903 * port with its MCR_IENABLE gate open will inhibit interrupts 904 * from any used port that shares the interrupt vector. 905 * XXX the gate enable is elsewhere for some multiports. 906 */ 907 device_t *devs; 908 int count, i, xioport; 909#ifdef PC98 910 int xiftype; 911#endif 912 913 devclass_get_devices(sio_devclass, &devs, &count); 914#ifdef PC98 915 for (i = 0; i < count; i++) { 916 xdev = devs[i]; 917 xioport = bus_get_resource_start(xdev, SYS_RES_IOPORT, 0); 918 xiftype = GET_IFTYPE(device_get_flags(xdev)); 919 if (device_is_enabled(xdev) && xioport > 0) { 920 if (IS_8251(xiftype)) 921 outb((xioport & 0xff00) | PC98SIO_cmd_port(xiftype & 0x0f), 0xf2); 922 else 923 outb(xioport + if_16550a_type[xiftype & 0x0f].iat[com_mcr], 0); 924 } 925 } 926#else 927 for (i = 0; i < count; i++) { 928 xdev = devs[i]; 929 if (device_is_enabled(xdev) && 930 bus_get_resource(xdev, SYS_RES_IOPORT, 0, &xioport, 931 NULL) == 0) 932 outb(xioport + com_mcr, 0); 933 } 934#endif 935 free(devs, M_TEMP); 936 already_init = TRUE; 937 } 938#endif 939 940 if (COM_LLCONSOLE(flags)) { 941 printf("sio%d: reserved for low-level i/o\n", 942 device_get_unit(dev)); 943 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 944 device_set_softc(dev, NULL); 945 free(com, M_DEVBUF); 946 return (ENXIO); 947 } 948 949#ifdef PC98 950 DELAY(10); 951 952 /* 953 * If the port is i8251 UART (internal, B98_01) 954 */ 955 if (pc98_check_if_type(dev, &iod) == -1) { 956 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 957 device_set_softc(dev, NULL); 958 free(com, M_DEVBUF); 959 return (ENXIO); 960 } 961 if (iod.irq > 0) 962 bus_set_resource(dev, SYS_RES_IRQ, 0, iod.irq, 1); 963 if (IS_8251(iod.if_type)) { 964 outb(iod.cmd, 0); 965 DELAY(10); 966 outb(iod.cmd, 0); 967 DELAY(10); 968 outb(iod.cmd, 0); 969 DELAY(10); 970 outb(iod.cmd, CMD8251_RESET); 971 DELAY(1000); /* for a while...*/ 972 outb(iod.cmd, 0xf2); /* MODE (dummy) */ 973 DELAY(10); 974 outb(iod.cmd, 0x01); /* CMD (dummy) */ 975 DELAY(1000); /* for a while...*/ 976 if (( inb(iod.sts) & STS8251_TxEMP ) == 0 ) { 977 result = (ENXIO); 978 } 979 if (if_8251_type[iod.if_type & 0x0f].check_irq) { 980 COM_INT_DISABLE 981 tmp = ( inb( iod.ctrl ) & ~(IEN_Rx|IEN_TxEMP|IEN_Tx)); 982 outb( iod.ctrl, tmp|IEN_TxEMP ); 983 DELAY(10); 984 result = isa_irq_pending() ? 0 : ENXIO; 985 outb( iod.ctrl, tmp ); 986 COM_INT_ENABLE 987 } else { 988 /* 989 * B98_01 doesn't activate TxEMP interrupt line 990 * when being reset, so we can't check irq pending. 991 */ 992 result = 0; 993 } 994 if (epson_machine_id==0x20) { /* XXX */ 995 result = 0; 996 } 997 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 998 if (result) { 999 device_set_softc(dev, NULL); 1000 free(com, M_DEVBUF); 1001 } 1002 return result; 1003 } 1004#endif /* PC98 */ 1005 /* 1006 * If the device is on a multiport card and has an AST/4 1007 * compatible interrupt control register, initialize this 1008 * register and prepare to leave MCR_IENABLE clear in the mcr. 1009 * Otherwise, prepare to set MCR_IENABLE in the mcr. 1010 * Point idev to the device struct giving the correct id_irq. 1011 * This is the struct for the master device if there is one. 1012 */ 1013 idev = dev; 1014 mcr_image = MCR_IENABLE; 1015#ifdef COM_MULTIPORT 1016 if (COM_ISMULTIPORT(flags)) { 1017#ifndef PC98 1018 Port_t xiobase; 1019 u_long io; 1020#endif 1021 1022 idev = devclass_get_device(sio_devclass, COM_MPMASTER(flags)); 1023 if (idev == NULL) { 1024 printf("sio%d: master device %d not configured\n", 1025 device_get_unit(dev), COM_MPMASTER(flags)); 1026 idev = dev; 1027 } 1028#ifndef PC98 1029 if (!COM_NOTAST4(flags)) { 1030 if (bus_get_resource(idev, SYS_RES_IOPORT, 0, &io, 1031 NULL) == 0) { 1032 xiobase = io; 1033 if (bus_get_resource(idev, SYS_RES_IRQ, 0, 1034 NULL, NULL) == 0) 1035 outb(xiobase + com_scr, 0x80); 1036 else 1037 outb(xiobase + com_scr, 0); 1038 } 1039 mcr_image = 0; 1040 } 1041#endif 1042 } 1043#endif /* COM_MULTIPORT */ 1044 if (bus_get_resource(idev, SYS_RES_IRQ, 0, NULL, NULL) != 0) 1045 mcr_image = 0; 1046 1047 bzero(failures, sizeof failures); 1048 iobase = rman_get_start(port); 1049 1050#ifdef PC98 1051 if (iod.if_type == COM_IF_RSA98III) { 1052 mcr_image = 0; 1053 1054 outb(iobase + rsa_msr, 0x04); 1055 outb(iobase + rsa_frr, 0x00); 1056 if ((inb(iobase + rsa_srr) & 0x36) != 0x36) { 1057 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 1058 device_set_softc(dev, NULL); 1059 free(com, M_DEVBUF); 1060 return (ENXIO); 1061 } 1062 outb(iobase + rsa_ier, 0x00); 1063 outb(iobase + rsa_frr, 0x00); 1064 outb(iobase + rsa_tivsr, 0x00); 1065 outb(iobase + rsa_tcr, 0x00); 1066 } 1067 1068 tmp = if_16550a_type[iod.if_type & 0x0f].irr_write; 1069 if (tmp != -1) { 1070 /* MC16550II */ 1071 int irqout; 1072 switch (isa_get_irq(idev)) { 1073 case 3: irqout = 4; break; 1074 case 5: irqout = 5; break; 1075 case 6: irqout = 6; break; 1076 case 12: irqout = 7; break; 1077 default: 1078 printf("sio%d: irq configuration error\n", 1079 device_get_unit(dev)); 1080 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 1081 device_set_softc(dev, NULL); 1082 free(com, M_DEVBUF); 1083 return (ENXIO); 1084 } 1085 outb((iobase & 0x00ff) | tmp, irqout); 1086 } 1087#endif 1088 1089 /* 1090 * We don't want to get actual interrupts, just masked ones. 1091 * Interrupts from this line should already be masked in the ICU, 1092 * but mask them in the processor as well in case there are some 1093 * (misconfigured) shared interrupts. 1094 */ 1095 mtx_lock_spin(&sio_lock); 1096/* EXTRA DELAY? */ 1097 1098 /* 1099 * Initialize the speed and the word size and wait long enough to 1100 * drain the maximum of 16 bytes of junk in device output queues. 1101 * The speed is undefined after a master reset and must be set 1102 * before relying on anything related to output. There may be 1103 * junk after a (very fast) soft reboot and (apparently) after 1104 * master reset. 1105 * XXX what about the UART bug avoided by waiting in comparam()? 1106 * We don't want to to wait long enough to drain at 2 bps. 1107 */ 1108 if (iobase == siocniobase) 1109 DELAY((16 + 1) * 1000000 / (comdefaultrate / 10)); 1110 else { 1111 sio_setreg(com, com_cfcr, CFCR_DLAB | CFCR_8BITS); 1112 divisor = siodivisor(rclk, SIO_TEST_SPEED); 1113 sio_setreg(com, com_dlbl, divisor & 0xff); 1114 sio_setreg(com, com_dlbh, divisor >> 8); 1115 sio_setreg(com, com_cfcr, CFCR_8BITS); 1116 DELAY((16 + 1) * 1000000 / (SIO_TEST_SPEED / 10)); 1117 } 1118 1119 /* 1120 * Enable the interrupt gate and disable device interupts. This 1121 * should leave the device driving the interrupt line low and 1122 * guarantee an edge trigger if an interrupt can be generated. 1123 */ 1124/* EXTRA DELAY? */ 1125 sio_setreg(com, com_mcr, mcr_image); 1126 sio_setreg(com, com_ier, 0); 1127 DELAY(1000); /* XXX */ 1128 irqmap[0] = isa_irq_pending(); 1129 1130 /* 1131 * Attempt to set loopback mode so that we can send a null byte 1132 * without annoying any external device. 1133 */ 1134/* EXTRA DELAY? */ 1135 sio_setreg(com, com_mcr, mcr_image | MCR_LOOPBACK); 1136 1137 /* 1138 * Attempt to generate an output interrupt. On 8250's, setting 1139 * IER_ETXRDY generates an interrupt independent of the current 1140 * setting and independent of whether the THR is empty. On 16450's, 1141 * setting IER_ETXRDY generates an interrupt independent of the 1142 * current setting. On 16550A's, setting IER_ETXRDY only 1143 * generates an interrupt when IER_ETXRDY is not already set. 1144 */ 1145 sio_setreg(com, com_ier, IER_ETXRDY); 1146#ifdef PC98 1147 if (iod.if_type == COM_IF_RSA98III) 1148 outb(iobase + rsa_ier, 0x04); 1149#endif 1150 1151 /* 1152 * On some 16x50 incompatibles, setting IER_ETXRDY doesn't generate 1153 * an interrupt. They'd better generate one for actually doing 1154 * output. Loopback may be broken on the same incompatibles but 1155 * it's unlikely to do more than allow the null byte out. 1156 */ 1157 sio_setreg(com, com_data, 0); 1158 if (iobase == siocniobase) 1159 DELAY((1 + 2) * 1000000 / (comdefaultrate / 10)); 1160 else 1161 DELAY((1 + 2) * 1000000 / (SIO_TEST_SPEED / 10)); 1162 1163 /* 1164 * Turn off loopback mode so that the interrupt gate works again 1165 * (MCR_IENABLE was hidden). This should leave the device driving 1166 * an interrupt line high. It doesn't matter if the interrupt 1167 * line oscillates while we are not looking at it, since interrupts 1168 * are disabled. 1169 */ 1170/* EXTRA DELAY? */ 1171 sio_setreg(com, com_mcr, mcr_image); 1172 1173 /* 1174 * It seems my Xircom CBEM56G Cardbus modem wants to be reset 1175 * to 8 bits *again*, or else probe test 0 will fail. 1176 * gwk@sgi.com, 4/19/2001 1177 */ 1178 sio_setreg(com, com_cfcr, CFCR_8BITS); 1179 1180 /* 1181 * Some PCMCIA cards (Palido 321s, DC-1S, ...) have the "TXRDY bug", 1182 * so we probe for a buggy IIR_TXRDY implementation even in the 1183 * noprobe case. We don't probe for it in the !noprobe case because 1184 * noprobe is always set for PCMCIA cards and the problem is not 1185 * known to affect any other cards. 1186 */ 1187 if (noprobe) { 1188 /* Read IIR a few times. */ 1189 for (fn = 0; fn < 2; fn ++) { 1190 DELAY(10000); 1191 failures[6] = sio_getreg(com, com_iir); 1192 } 1193 1194 /* IIR_TXRDY should be clear. Is it? */ 1195 result = 0; 1196 if (failures[6] & IIR_TXRDY) { 1197 /* 1198 * No. We seem to have the bug. Does our fix for 1199 * it work? 1200 */ 1201 sio_setreg(com, com_ier, 0); 1202 if (sio_getreg(com, com_iir) & IIR_NOPEND) { 1203 /* Yes. We discovered the TXRDY bug! */ 1204 SET_FLAG(dev, COM_C_IIR_TXRDYBUG); 1205 } else { 1206 /* No. Just fail. XXX */ 1207 result = ENXIO; 1208 sio_setreg(com, com_mcr, 0); 1209 } 1210 } else { 1211 /* Yes. No bug. */ 1212 CLR_FLAG(dev, COM_C_IIR_TXRDYBUG); 1213 } 1214 sio_setreg(com, com_ier, 0); 1215 sio_setreg(com, com_cfcr, CFCR_8BITS); 1216 mtx_unlock_spin(&sio_lock); 1217 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 1218 if (iobase == siocniobase) 1219 result = 0; 1220 if (result != 0) { 1221 device_set_softc(dev, NULL); 1222 free(com, M_DEVBUF); 1223 } 1224 return (result); 1225 } 1226 1227 /* 1228 * Check that 1229 * o the CFCR, IER and MCR in UART hold the values written to them 1230 * (the values happen to be all distinct - this is good for 1231 * avoiding false positive tests from bus echoes). 1232 * o an output interrupt is generated and its vector is correct. 1233 * o the interrupt goes away when the IIR in the UART is read. 1234 */ 1235/* EXTRA DELAY? */ 1236 failures[0] = sio_getreg(com, com_cfcr) - CFCR_8BITS; 1237 failures[1] = sio_getreg(com, com_ier) - IER_ETXRDY; 1238 failures[2] = sio_getreg(com, com_mcr) - mcr_image; 1239 DELAY(10000); /* Some internal modems need this time */ 1240 irqmap[1] = isa_irq_pending(); 1241 failures[4] = (sio_getreg(com, com_iir) & IIR_IMASK) - IIR_TXRDY; 1242#ifdef PC98 1243 if (iod.if_type == COM_IF_RSA98III) 1244 inb(iobase + rsa_srr); 1245#endif 1246 DELAY(1000); /* XXX */ 1247 irqmap[2] = isa_irq_pending(); 1248 failures[6] = (sio_getreg(com, com_iir) & IIR_IMASK) - IIR_NOPEND; 1249#ifdef PC98 1250 if (iod.if_type == COM_IF_RSA98III) 1251 inb(iobase + rsa_srr); 1252#endif 1253 1254 /* 1255 * Turn off all device interrupts and check that they go off properly. 1256 * Leave MCR_IENABLE alone. For ports without a master port, it gates 1257 * the OUT2 output of the UART to 1258 * the ICU input. Closing the gate would give a floating ICU input 1259 * (unless there is another device driving it) and spurious interrupts. 1260 * (On the system that this was first tested on, the input floats high 1261 * and gives a (masked) interrupt as soon as the gate is closed.) 1262 */ 1263 sio_setreg(com, com_ier, 0); 1264 sio_setreg(com, com_cfcr, CFCR_8BITS); /* dummy to avoid bus echo */ 1265 failures[7] = sio_getreg(com, com_ier); 1266#ifdef PC98 1267 if (iod.if_type == COM_IF_RSA98III) 1268 outb(iobase + rsa_ier, 0x00); 1269#endif 1270 DELAY(1000); /* XXX */ 1271 irqmap[3] = isa_irq_pending(); 1272 failures[9] = (sio_getreg(com, com_iir) & IIR_IMASK) - IIR_NOPEND; 1273#ifdef PC98 1274 if (iod.if_type == COM_IF_RSA98III) { 1275 inb(iobase + rsa_srr); 1276 outb(iobase + rsa_frr, 0x00); 1277 } 1278#endif 1279 1280 mtx_unlock_spin(&sio_lock); 1281 1282 irqs = irqmap[1] & ~irqmap[0]; 1283 if (bus_get_resource(idev, SYS_RES_IRQ, 0, &xirq, NULL) == 0 && 1284 ((1 << xirq) & irqs) == 0) { 1285 printf( 1286 "sio%d: configured irq %ld not in bitmap of probed irqs %#x\n", 1287 device_get_unit(dev), xirq, irqs); 1288 printf( 1289 "sio%d: port may not be enabled\n", 1290 device_get_unit(dev)); 1291 } 1292 if (bootverbose) 1293 printf("sio%d: irq maps: %#x %#x %#x %#x\n", 1294 device_get_unit(dev), 1295 irqmap[0], irqmap[1], irqmap[2], irqmap[3]); 1296 1297 result = 0; 1298 for (fn = 0; fn < sizeof failures; ++fn) 1299 if (failures[fn]) { 1300 sio_setreg(com, com_mcr, 0); 1301 result = ENXIO; 1302 if (bootverbose) { 1303 printf("sio%d: probe failed test(s):", 1304 device_get_unit(dev)); 1305 for (fn = 0; fn < sizeof failures; ++fn) 1306 if (failures[fn]) 1307 printf(" %d", fn); 1308 printf("\n"); 1309 } 1310 break; 1311 } 1312 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 1313 if (iobase == siocniobase) 1314 result = 0; 1315 if (result != 0) { 1316 device_set_softc(dev, NULL); 1317 free(com, M_DEVBUF); 1318 } 1319 return (result); 1320} 1321 1322#ifdef COM_ESP 1323static int 1324espattach(com, esp_port) 1325 struct com_s *com; 1326 Port_t esp_port; 1327{ 1328 u_char dips; 1329 u_char val; 1330 1331 /* 1332 * Check the ESP-specific I/O port to see if we're an ESP 1333 * card. If not, return failure immediately. 1334 */ 1335 if ((inb(esp_port) & 0xf3) == 0) { 1336 printf(" port 0x%x is not an ESP board?\n", esp_port); 1337 return (0); 1338 } 1339 1340 /* 1341 * We've got something that claims to be a Hayes ESP card. 1342 * Let's hope so. 1343 */ 1344 1345 /* Get the dip-switch configuration */ 1346#ifdef PC98 1347 outb(esp_port + ESP98_CMD1, ESP_GETDIPS); 1348 dips = inb(esp_port + ESP98_STATUS1); 1349#else 1350 outb(esp_port + ESP_CMD1, ESP_GETDIPS); 1351 dips = inb(esp_port + ESP_STATUS1); 1352#endif 1353 1354 /* 1355 * Bits 0,1 of dips say which COM port we are. 1356 */ 1357#ifdef PC98 1358 if ((rman_get_start(com->ioportres) & 0xff) == 1359 likely_com_ports[dips & 0x03]) 1360#else 1361 if (rman_get_start(com->ioportres) == likely_com_ports[dips & 0x03]) 1362#endif 1363 printf(" : ESP"); 1364 else { 1365 printf(" esp_port has com %d\n", dips & 0x03); 1366 return (0); 1367 } 1368 1369 /* 1370 * Check for ESP version 2.0 or later: bits 4,5,6 = 010. 1371 */ 1372#ifdef PC98 1373 outb(esp_port + ESP98_CMD1, ESP_GETTEST); 1374 val = inb(esp_port + ESP98_STATUS1); /* clear reg 1 */ 1375 val = inb(esp_port + ESP98_STATUS2); 1376#else 1377 outb(esp_port + ESP_CMD1, ESP_GETTEST); 1378 val = inb(esp_port + ESP_STATUS1); /* clear reg 1 */ 1379 val = inb(esp_port + ESP_STATUS2); 1380#endif 1381 if ((val & 0x70) < 0x20) { 1382 printf("-old (%o)", val & 0x70); 1383 return (0); 1384 } 1385 1386 /* 1387 * Check for ability to emulate 16550: bit 7 == 1 1388 */ 1389 if ((dips & 0x80) == 0) { 1390 printf(" slave"); 1391 return (0); 1392 } 1393 1394 /* 1395 * Okay, we seem to be a Hayes ESP card. Whee. 1396 */ 1397 com->esp = TRUE; 1398 com->esp_port = esp_port; 1399 return (1); 1400} 1401#endif /* COM_ESP */ 1402 1403int 1404sioattach(dev, xrid, rclk) 1405 device_t dev; 1406 int xrid; 1407 u_long rclk; 1408{ 1409 struct com_s *com; 1410#ifdef COM_ESP 1411 Port_t *espp; 1412#endif 1413 Port_t iobase; 1414 int minorbase; 1415 int unit; 1416 u_int flags; 1417 int rid; 1418 struct resource *port; 1419 int ret; 1420#ifdef PC98 1421 u_char *obuf; 1422 u_long obufsize; 1423 int if_type = GET_IFTYPE(device_get_flags(dev)); 1424#endif 1425 1426 rid = xrid; 1427#ifdef PC98 1428 if (IS_8251(if_type)) { 1429 port = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid, 1430 RF_ACTIVE); 1431 } else if (if_type == COM_IF_MODEM_CARD || 1432 if_type == COM_IF_RSA98III || 1433 isa_get_vendorid(dev)) { 1434 port = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 0, ~0, 1435 if_16550a_type[if_type & 0x0f].iatsz, RF_ACTIVE); 1436 } else { 1437 port = isa_alloc_resourcev(dev, SYS_RES_IOPORT, &rid, 1438 if_16550a_type[if_type & 0x0f].iat, 1439 if_16550a_type[if_type & 0x0f].iatsz, RF_ACTIVE); 1440 } 1441#else 1442 port = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 1443 0, ~0, IO_COMSIZE, RF_ACTIVE); 1444#endif 1445 if (!port) 1446 return (ENXIO); 1447#ifdef PC98 1448 if (!IS_8251(if_type)) { 1449 if (isa_load_resourcev(port, 1450 if_16550a_type[if_type & 0x0f].iat, 1451 if_16550a_type[if_type & 0x0f].iatsz) != 0) { 1452 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 1453 return ENXIO; 1454 } 1455 } 1456#endif 1457 1458 iobase = rman_get_start(port); 1459 unit = device_get_unit(dev); 1460 com = device_get_softc(dev); 1461 flags = device_get_flags(dev); 1462 1463 if (unit >= sio_numunits) 1464 sio_numunits = unit + 1; 1465 1466#ifdef PC98 1467 obufsize = 256; 1468 if (if_type == COM_IF_RSA98III) 1469 obufsize = 2048; 1470 if ((obuf = malloc(obufsize * 2, M_DEVBUF, M_NOWAIT)) == NULL) { 1471 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 1472 return ENXIO; 1473 } 1474 bzero(obuf, obufsize * 2); 1475#endif 1476 1477 /* 1478 * sioprobe() has initialized the device registers as follows: 1479 * o cfcr = CFCR_8BITS. 1480 * It is most important that CFCR_DLAB is off, so that the 1481 * data port is not hidden when we enable interrupts. 1482 * o ier = 0. 1483 * Interrupts are only enabled when the line is open. 1484 * o mcr = MCR_IENABLE, or 0 if the port has AST/4 compatible 1485 * interrupt control register or the config specifies no irq. 1486 * Keeping MCR_DTR and MCR_RTS off might stop the external 1487 * device from sending before we are ready. 1488 */ 1489 bzero(com, sizeof *com); 1490 com->unit = unit; 1491 com->ioportres = port; 1492 com->ioportrid = rid; 1493 com->bst = rman_get_bustag(port); 1494 com->bsh = rman_get_bushandle(port); 1495 com->cfcr_image = CFCR_8BITS; 1496 com->dtr_wait = 3 * hz; 1497 com->loses_outints = COM_LOSESOUTINTS(flags) != 0; 1498 com->no_irq = bus_get_resource(dev, SYS_RES_IRQ, 0, NULL, NULL) != 0; 1499 com->tx_fifo_size = 1; 1500#ifdef PC98 1501 com->obufsize = obufsize; 1502 com->obuf1 = obuf; 1503 com->obuf2 = obuf + obufsize; 1504#endif 1505 com->obufs[0].l_head = com->obuf1; 1506 com->obufs[1].l_head = com->obuf2; 1507 1508#ifdef PC98 1509 com->pc98_if_type = if_type; 1510 1511 if (IS_8251(if_type)) { 1512 pc98_set_ioport(com); 1513 1514 if (if_type == COM_IF_INTERNAL && pc98_check_8251fifo()) { 1515 com->pc98_8251fifo = 1; 1516 com->pc98_8251fifo_enable = 0; 1517 } 1518 } else { 1519 bus_addr_t *iat = if_16550a_type[if_type & 0x0f].iat; 1520 1521 com->data_port = iobase + iat[com_data]; 1522 com->int_ctl_port = iobase + iat[com_ier]; 1523 com->int_id_port = iobase + iat[com_iir]; 1524 com->modem_ctl_port = iobase + iat[com_mcr]; 1525 com->mcr_image = inb(com->modem_ctl_port); 1526 com->line_status_port = iobase + iat[com_lsr]; 1527 com->modem_status_port = iobase + iat[com_msr]; 1528 } 1529#else /* not PC98 */ 1530 com->data_port = iobase + com_data; 1531 com->int_ctl_port = iobase + com_ier; 1532 com->int_id_port = iobase + com_iir; 1533 com->modem_ctl_port = iobase + com_mcr; 1534 com->mcr_image = inb(com->modem_ctl_port); 1535 com->line_status_port = iobase + com_lsr; 1536 com->modem_status_port = iobase + com_msr; 1537#endif 1538 1539#ifdef PC98 1540 if (!IS_8251(if_type) && rclk == 0) 1541 rclk = if_16550a_type[if_type & 0x0f].rclk; 1542#else 1543 if (rclk == 0) 1544 rclk = DEFAULT_RCLK; 1545#endif 1546 com->rclk = rclk; 1547 1548 /* 1549 * We don't use all the flags from <sys/ttydefaults.h> since they 1550 * are only relevant for logins. It's important to have echo off 1551 * initially so that the line doesn't start blathering before the 1552 * echo flag can be turned off. 1553 */ 1554 com->it_in.c_iflag = 0; 1555 com->it_in.c_oflag = 0; 1556 com->it_in.c_cflag = TTYDEF_CFLAG; 1557 com->it_in.c_lflag = 0; 1558 if (unit == comconsole) { 1559#ifdef PC98 1560 if (IS_8251(com->pc98_if_type)) 1561 DELAY(100000); 1562#endif 1563 com->it_in.c_iflag = TTYDEF_IFLAG; 1564 com->it_in.c_oflag = TTYDEF_OFLAG; 1565 com->it_in.c_cflag = TTYDEF_CFLAG | CLOCAL; 1566 com->it_in.c_lflag = TTYDEF_LFLAG; 1567 com->lt_out.c_cflag = com->lt_in.c_cflag = CLOCAL; 1568 com->lt_out.c_ispeed = com->lt_out.c_ospeed = 1569 com->lt_in.c_ispeed = com->lt_in.c_ospeed = 1570 com->it_in.c_ispeed = com->it_in.c_ospeed = comdefaultrate; 1571 } else 1572 com->it_in.c_ispeed = com->it_in.c_ospeed = TTYDEF_SPEED; 1573 if (siosetwater(com, com->it_in.c_ispeed) != 0) { 1574 mtx_unlock_spin(&sio_lock); 1575 /* 1576 * Leave i/o resources allocated if this is a `cn'-level 1577 * console, so that other devices can't snarf them. 1578 */ 1579 if (iobase != siocniobase) 1580 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 1581 return (ENOMEM); 1582 } 1583 mtx_unlock_spin(&sio_lock); 1584 termioschars(&com->it_in); 1585 com->it_out = com->it_in; 1586 1587 /* attempt to determine UART type */ 1588 printf("sio%d: type", unit); 1589 1590 1591#ifndef PC98 1592 if (!COM_ISMULTIPORT(flags) && 1593 !COM_IIR_TXRDYBUG(flags) && !COM_NOSCR(flags)) { 1594 u_char scr; 1595 u_char scr1; 1596 u_char scr2; 1597 1598 scr = sio_getreg(com, com_scr); 1599 sio_setreg(com, com_scr, 0xa5); 1600 scr1 = sio_getreg(com, com_scr); 1601 sio_setreg(com, com_scr, 0x5a); 1602 scr2 = sio_getreg(com, com_scr); 1603 sio_setreg(com, com_scr, scr); 1604 if (scr1 != 0xa5 || scr2 != 0x5a) { 1605 printf(" 8250 or not responding"); 1606 goto determined_type; 1607 } 1608 } 1609#endif /* !PC98 */ 1610#ifdef PC98 1611 if (IS_8251(com->pc98_if_type)) { 1612 if (com->pc98_8251fifo && !COM_NOFIFO(flags)) 1613 com->tx_fifo_size = 16; 1614 com_int_TxRx_disable( com ); 1615 com_cflag_and_speed_set( com, com->it_in.c_cflag, comdefaultrate ); 1616 com_tiocm_bic( com, TIOCM_DTR|TIOCM_RTS|TIOCM_LE ); 1617 com_send_break_off( com ); 1618 1619 if (com->pc98_if_type == COM_IF_INTERNAL) { 1620 printf(" (internal%s%s)", 1621 com->pc98_8251fifo ? " fifo" : "", 1622 PC98SIO_baud_rate_port(com->pc98_if_type) != -1 ? 1623 " v-fast" : ""); 1624 } else { 1625 printf(" 8251%s", if_8251_type[com->pc98_if_type & 0x0f].name); 1626 } 1627 } else { 1628#endif /* PC98 */ 1629 sio_setreg(com, com_fifo, FIFO_ENABLE | FIFO_RX_HIGH); 1630 DELAY(100); 1631 switch (inb(com->int_id_port) & IIR_FIFO_MASK) { 1632 case FIFO_RX_LOW: 1633 printf(" 16450"); 1634 break; 1635 case FIFO_RX_MEDL: 1636 printf(" 16450?"); 1637 break; 1638 case FIFO_RX_MEDH: 1639 printf(" 16550?"); 1640 break; 1641 case FIFO_RX_HIGH: 1642 if (COM_NOFIFO(flags)) { 1643 printf(" 16550A fifo disabled"); 1644 break; 1645 } 1646 com->hasfifo = TRUE; 1647#ifdef PC98 1648 if (com->pc98_if_type == COM_IF_RSA98III) { 1649 com->tx_fifo_size = 2048; 1650 com->rsabase = iobase; 1651 outb(com->rsabase + rsa_ier, 0x00); 1652 outb(com->rsabase + rsa_frr, 0x00); 1653 } 1654#else 1655 if (COM_ST16650A(flags)) { 1656 printf(" ST16650A"); 1657 com->st16650a = TRUE; 1658 com->tx_fifo_size = 32; 1659 break; 1660 } 1661 if (COM_TI16754(flags)) { 1662 printf(" TI16754"); 1663 com->tx_fifo_size = 64; 1664 break; 1665 } 1666#endif 1667 printf(" 16550A"); 1668#ifdef COM_ESP 1669#ifdef PC98 1670 if (com->pc98_if_type == COM_IF_ESP98) 1671#endif 1672 for (espp = likely_esp_ports; *espp != 0; espp++) 1673 if (espattach(com, *espp)) { 1674 com->tx_fifo_size = 1024; 1675 break; 1676 } 1677 if (com->esp) 1678 break; 1679#endif 1680#ifdef PC98 1681 com->tx_fifo_size = 16; 1682#else 1683 com->tx_fifo_size = COM_FIFOSIZE(flags); 1684 if (com->tx_fifo_size == 0) 1685 com->tx_fifo_size = 16; 1686 else 1687 printf(" lookalike with %u bytes FIFO", 1688 com->tx_fifo_size); 1689#endif 1690 break; 1691 } 1692 1693#ifdef PC98 1694 if (com->pc98_if_type == COM_IF_RSB3000) { 1695 /* Set RSB-2000/3000 Extended Buffer mode. */ 1696 u_char lcr; 1697 lcr = sio_getreg(com, com_cfcr); 1698 sio_setreg(com, com_cfcr, lcr | CFCR_DLAB); 1699 sio_setreg(com, com_emr, EMR_EXBUFF | EMR_EFMODE); 1700 sio_setreg(com, com_cfcr, lcr); 1701 } 1702#endif 1703 1704#ifdef COM_ESP 1705 if (com->esp) { 1706 /* 1707 * Set 16550 compatibility mode. 1708 * We don't use the ESP_MODE_SCALE bit to increase the 1709 * fifo trigger levels because we can't handle large 1710 * bursts of input. 1711 * XXX flow control should be set in comparam(), not here. 1712 */ 1713#ifdef PC98 1714 outb(com->esp_port + ESP98_CMD1, ESP_SETMODE); 1715 outb(com->esp_port + ESP98_CMD2, ESP_MODE_RTS | ESP_MODE_FIFO); 1716#else 1717 outb(com->esp_port + ESP_CMD1, ESP_SETMODE); 1718 outb(com->esp_port + ESP_CMD2, ESP_MODE_RTS | ESP_MODE_FIFO); 1719#endif 1720 1721 /* Set RTS/CTS flow control. */ 1722#ifdef PC98 1723 outb(com->esp_port + ESP98_CMD1, ESP_SETFLOWTYPE); 1724 outb(com->esp_port + ESP98_CMD2, ESP_FLOW_RTS); 1725 outb(com->esp_port + ESP98_CMD2, ESP_FLOW_CTS); 1726#else 1727 outb(com->esp_port + ESP_CMD1, ESP_SETFLOWTYPE); 1728 outb(com->esp_port + ESP_CMD2, ESP_FLOW_RTS); 1729 outb(com->esp_port + ESP_CMD2, ESP_FLOW_CTS); 1730#endif 1731 1732 /* Set flow-control levels. */ 1733#ifdef PC98 1734 outb(com->esp_port + ESP98_CMD1, ESP_SETRXFLOW); 1735 outb(com->esp_port + ESP98_CMD2, HIBYTE(768)); 1736 outb(com->esp_port + ESP98_CMD2, LOBYTE(768)); 1737 outb(com->esp_port + ESP98_CMD2, HIBYTE(512)); 1738 outb(com->esp_port + ESP98_CMD2, LOBYTE(512)); 1739#else 1740 outb(com->esp_port + ESP_CMD1, ESP_SETRXFLOW); 1741 outb(com->esp_port + ESP_CMD2, HIBYTE(768)); 1742 outb(com->esp_port + ESP_CMD2, LOBYTE(768)); 1743 outb(com->esp_port + ESP_CMD2, HIBYTE(512)); 1744 outb(com->esp_port + ESP_CMD2, LOBYTE(512)); 1745#endif 1746 1747#ifdef PC98 1748 /* Set UART clock prescaler. */ 1749 outb(com->esp_port + ESP98_CMD1, ESP_SETCLOCK); 1750 outb(com->esp_port + ESP98_CMD2, 2); /* 4 times */ 1751#endif 1752 } 1753#endif /* COM_ESP */ 1754 sio_setreg(com, com_fifo, 0); 1755#ifdef PC98 1756 printf("%s", if_16550a_type[com->pc98_if_type & 0x0f].name); 1757#else 1758determined_type: ; 1759#endif 1760 1761#ifdef COM_MULTIPORT 1762 if (COM_ISMULTIPORT(flags)) { 1763 device_t masterdev; 1764 1765 com->multiport = TRUE; 1766 printf(" (multiport"); 1767 if (unit == COM_MPMASTER(flags)) 1768 printf(" master"); 1769 printf(")"); 1770 masterdev = devclass_get_device(sio_devclass, 1771 COM_MPMASTER(flags)); 1772 com->no_irq = (masterdev == NULL || bus_get_resource(masterdev, 1773 SYS_RES_IRQ, 0, NULL, NULL) != 0); 1774 } 1775#endif /* COM_MULTIPORT */ 1776#ifdef PC98 1777 } 1778#endif 1779 if (unit == comconsole) 1780 printf(", console"); 1781 if (COM_IIR_TXRDYBUG(flags)) 1782 printf(" with a buggy IIR_TXRDY implementation"); 1783 printf("\n"); 1784 1785 if (sio_fast_ih == NULL) { 1786 swi_add(&tty_ithd, "tty:sio", siopoll, NULL, SWI_TTY, 0, 1787 &sio_fast_ih); 1788 swi_add(&clk_ithd, "tty:sio", siopoll, NULL, SWI_TTY, 0, 1789 &sio_slow_ih); 1790 } 1791 minorbase = UNIT_TO_MINOR(unit); 1792 com->devs[0] = make_dev(&sio_cdevsw, minorbase, 1793 UID_ROOT, GID_WHEEL, 0600, "ttyd%r", unit); 1794 com->devs[1] = make_dev(&sio_cdevsw, minorbase | CONTROL_INIT_STATE, 1795 UID_ROOT, GID_WHEEL, 0600, "ttyid%r", unit); 1796 com->devs[2] = make_dev(&sio_cdevsw, minorbase | CONTROL_LOCK_STATE, 1797 UID_ROOT, GID_WHEEL, 0600, "ttyld%r", unit); 1798 com->devs[3] = make_dev(&sio_cdevsw, minorbase | CALLOUT_MASK, 1799 UID_UUCP, GID_DIALER, 0660, "cuaa%r", unit); 1800 com->devs[4] = make_dev(&sio_cdevsw, 1801 minorbase | CALLOUT_MASK | CONTROL_INIT_STATE, 1802 UID_UUCP, GID_DIALER, 0660, "cuaia%r", unit); 1803 com->devs[5] = make_dev(&sio_cdevsw, 1804 minorbase | CALLOUT_MASK | CONTROL_LOCK_STATE, 1805 UID_UUCP, GID_DIALER, 0660, "cuala%r", unit); 1806 for (rid = 0; rid < 6; rid++) 1807 com->devs[rid]->si_drv1 = com; 1808 com->flags = flags; 1809 com->pps.ppscap = PPS_CAPTUREASSERT | PPS_CAPTURECLEAR; 1810 1811 if (COM_PPSCTS(flags)) 1812 com->pps_bit = MSR_CTS; 1813 else 1814 com->pps_bit = MSR_DCD; 1815 pps_init(&com->pps); 1816 1817 rid = 0; 1818 com->irqres = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1819 RF_ACTIVE); 1820 if (com->irqres) { 1821 ret = BUS_SETUP_INTR(device_get_parent(dev), dev, com->irqres, 1822 INTR_TYPE_TTY | INTR_FAST, 1823 siointr, com, &com->cookie); 1824 if (ret) { 1825 ret = BUS_SETUP_INTR(device_get_parent(dev), dev, 1826 com->irqres, INTR_TYPE_TTY, 1827 siointr, com, &com->cookie); 1828 if (ret == 0) 1829 device_printf(dev, "unable to activate interrupt in fast mode - using normal mode\n"); 1830 } 1831 if (ret) 1832 device_printf(dev, "could not activate interrupt\n"); 1833#if defined(DDB) && (defined(BREAK_TO_DEBUGGER) || \ 1834 defined(ALT_BREAK_TO_DEBUGGER)) 1835 /* 1836 * Enable interrupts for early break-to-debugger support 1837 * on the console. 1838 */ 1839 if (ret == 0 && unit == comconsole) 1840 outb(siocniobase + com_ier, IER_ERXRDY | IER_ERLS | 1841 IER_EMSC); 1842#endif 1843 } 1844 1845 return (0); 1846} 1847 1848static int 1849sioopen(dev, flag, mode, td) 1850 dev_t dev; 1851 int flag; 1852 int mode; 1853 struct thread *td; 1854{ 1855 struct com_s *com; 1856 int error; 1857 int mynor; 1858 int s; 1859 struct tty *tp; 1860 int unit; 1861 1862 mynor = minor(dev); 1863 unit = MINOR_TO_UNIT(mynor); 1864 com = com_addr(unit); 1865 if (com == NULL) 1866 return (ENXIO); 1867 if (com->gone) 1868 return (ENXIO); 1869 if (mynor & CONTROL_MASK) 1870 return (0); 1871 tp = dev->si_tty = com->tp = ttymalloc(com->tp); 1872 s = spltty(); 1873 /* 1874 * We jump to this label after all non-interrupted sleeps to pick 1875 * up any changes of the device state. 1876 */ 1877open_top: 1878 while (com->state & CS_DTR_OFF) { 1879 error = tsleep(&com->dtr_wait, TTIPRI | PCATCH, "siodtr", 0); 1880 if (com_addr(unit) == NULL) 1881 return (ENXIO); 1882 if (error != 0 || com->gone) 1883 goto out; 1884 } 1885 if (tp->t_state & TS_ISOPEN) { 1886 /* 1887 * The device is open, so everything has been initialized. 1888 * Handle conflicts. 1889 */ 1890 if (mynor & CALLOUT_MASK) { 1891 if (!com->active_out) { 1892 error = EBUSY; 1893 goto out; 1894 } 1895 } else { 1896 if (com->active_out) { 1897 if (flag & O_NONBLOCK) { 1898 error = EBUSY; 1899 goto out; 1900 } 1901 error = tsleep(&com->active_out, 1902 TTIPRI | PCATCH, "siobi", 0); 1903 if (com_addr(unit) == NULL) 1904 return (ENXIO); 1905 if (error != 0 || com->gone) 1906 goto out; 1907 goto open_top; 1908 } 1909 } 1910 if (tp->t_state & TS_XCLUDE && 1911 suser(td)) { 1912 error = EBUSY; 1913 goto out; 1914 } 1915 } else { 1916 /* 1917 * The device isn't open, so there are no conflicts. 1918 * Initialize it. Initialization is done twice in many 1919 * cases: to preempt sleeping callin opens if we are 1920 * callout, and to complete a callin open after DCD rises. 1921 */ 1922 tp->t_oproc = comstart; 1923 tp->t_param = comparam; 1924 tp->t_stop = comstop; 1925 tp->t_dev = dev; 1926 tp->t_termios = mynor & CALLOUT_MASK 1927 ? com->it_out : com->it_in; 1928#ifdef PC98 1929 if (!IS_8251(com->pc98_if_type)) 1930#endif 1931 (void)commctl(com, TIOCM_DTR | TIOCM_RTS, DMSET); 1932 com->poll = com->no_irq; 1933 com->poll_output = com->loses_outints; 1934 ++com->wopeners; 1935 error = comparam(tp, &tp->t_termios); 1936 --com->wopeners; 1937 if (error != 0) 1938 goto out; 1939#ifdef PC98 1940 if (IS_8251(com->pc98_if_type)) { 1941 com_tiocm_bis(com, TIOCM_DTR|TIOCM_RTS); 1942 pc98_msrint_start(dev); 1943 if (com->pc98_8251fifo) { 1944 com->pc98_8251fifo_enable = 1; 1945 outb(I8251F_fcr, CTRL8251F_ENABLE | 1946 CTRL8251F_XMT_RST | CTRL8251F_RCV_RST); 1947 } 1948 } 1949#endif 1950 /* 1951 * XXX we should goto open_top if comparam() slept. 1952 */ 1953 if (com->hasfifo) { 1954 int i; 1955 /* 1956 * (Re)enable and drain fifos. 1957 * 1958 * Certain SMC chips cause problems if the fifos 1959 * are enabled while input is ready. Turn off the 1960 * fifo if necessary to clear the input. We test 1961 * the input ready bit after enabling the fifos 1962 * since we've already enabled them in comparam() 1963 * and to handle races between enabling and fresh 1964 * input. 1965 */ 1966 for (i = 0; i < 500; i++) { 1967 sio_setreg(com, com_fifo, 1968 FIFO_RCV_RST | FIFO_XMT_RST 1969 | com->fifo_image); 1970#ifdef PC98 1971 if (com->pc98_if_type == COM_IF_RSA98III) 1972 outb(com->rsabase + rsa_frr , 0x00); 1973#endif 1974 /* 1975 * XXX the delays are for superstitious 1976 * historical reasons. It must be less than 1977 * the character time at the maximum 1978 * supported speed (87 usec at 115200 bps 1979 * 8N1). Otherwise we might loop endlessly 1980 * if data is streaming in. We used to use 1981 * delays of 100. That usually worked 1982 * because DELAY(100) used to usually delay 1983 * for about 85 usec instead of 100. 1984 */ 1985 DELAY(50); 1986#ifdef PC98 1987 if (com->pc98_if_type == COM_IF_RSA98III ? 1988 !(inb(com->rsabase + rsa_srr) & 0x08) : 1989 !(inb(com->line_status_port) & LSR_RXRDY)) 1990 break; 1991#else 1992 if (!(inb(com->line_status_port) & LSR_RXRDY)) 1993 break; 1994#endif 1995 sio_setreg(com, com_fifo, 0); 1996 DELAY(50); 1997 (void) inb(com->data_port); 1998 } 1999 if (i == 500) { 2000 error = EIO; 2001 goto out; 2002 } 2003 } 2004 2005 mtx_lock_spin(&sio_lock); 2006#ifdef PC98 2007 if (IS_8251(com->pc98_if_type)) { 2008 com_tiocm_bis(com, TIOCM_LE); 2009 com->pc98_prev_modem_status = pc98_get_modem_status(com); 2010 com_int_Rx_enable(com); 2011 } else { 2012#endif 2013 (void) inb(com->line_status_port); 2014 (void) inb(com->data_port); 2015 com->prev_modem_status = com->last_modem_status 2016 = inb(com->modem_status_port); 2017 outb(com->int_ctl_port, 2018 IER_ERXRDY | IER_ERLS | IER_EMSC 2019 | (COM_IIR_TXRDYBUG(com->flags) ? 0 : IER_ETXRDY)); 2020#ifdef PC98 2021 if (com->pc98_if_type == COM_IF_RSA98III) { 2022 outb(com->rsabase + rsa_ier, 0x1d); 2023 outb(com->int_ctl_port, IER_ERLS | IER_EMSC); 2024 } 2025#endif 2026#ifdef PC98 2027 } 2028#endif 2029 mtx_unlock_spin(&sio_lock); 2030 /* 2031 * Handle initial DCD. Callout devices get a fake initial 2032 * DCD (trapdoor DCD). If we are callout, then any sleeping 2033 * callin opens get woken up and resume sleeping on "siobi" 2034 * instead of "siodcd". 2035 */ 2036 /* 2037 * XXX `mynor & CALLOUT_MASK' should be 2038 * `tp->t_cflag & (SOFT_CARRIER | TRAPDOOR_CARRIER) where 2039 * TRAPDOOR_CARRIER is the default initial state for callout 2040 * devices and SOFT_CARRIER is like CLOCAL except it hides 2041 * the true carrier. 2042 */ 2043#ifdef PC98 2044 if ((IS_8251(com->pc98_if_type) && 2045 (pc98_get_modem_status(com) & TIOCM_CAR)) || 2046 (!IS_8251(com->pc98_if_type) && 2047 (com->prev_modem_status & MSR_DCD)) || 2048 mynor & CALLOUT_MASK) 2049 ttyld_modem(tp, 1); 2050#else 2051 if (com->prev_modem_status & MSR_DCD || mynor & CALLOUT_MASK) 2052 ttyld_modem(tp, 1); 2053#endif 2054 } 2055 /* 2056 * Wait for DCD if necessary. 2057 */ 2058 if (!(tp->t_state & TS_CARR_ON) && !(mynor & CALLOUT_MASK) 2059 && !(tp->t_cflag & CLOCAL) && !(flag & O_NONBLOCK)) { 2060 ++com->wopeners; 2061 error = tsleep(TSA_CARR_ON(tp), TTIPRI | PCATCH, "siodcd", 0); 2062 if (com_addr(unit) == NULL) 2063 return (ENXIO); 2064 --com->wopeners; 2065 if (error != 0 || com->gone) 2066 goto out; 2067 goto open_top; 2068 } 2069 error = ttyld_open(tp, dev); 2070 com->hotchar = ttyldoptim(tp); 2071 if (tp->t_state & TS_ISOPEN && mynor & CALLOUT_MASK) 2072 com->active_out = TRUE; 2073 siosettimeout(); 2074out: 2075 splx(s); 2076 if (!(tp->t_state & TS_ISOPEN) && com->wopeners == 0) 2077 comhardclose(com); 2078 return (error); 2079} 2080 2081static int 2082sioclose(dev, flag, mode, td) 2083 dev_t dev; 2084 int flag; 2085 int mode; 2086 struct thread *td; 2087{ 2088 struct com_s *com; 2089 int mynor; 2090 int s; 2091 struct tty *tp; 2092 2093 mynor = minor(dev); 2094 if (mynor & CONTROL_MASK) 2095 return (0); 2096 com = com_addr(MINOR_TO_UNIT(mynor)); 2097 if (com == NULL) 2098 return (ENODEV); 2099 tp = com->tp; 2100 s = spltty(); 2101 ttyld_close(tp, flag); 2102#ifdef PC98 2103 com->modem_checking = 0; 2104#endif 2105 com->hotchar = ttyldoptim(tp); 2106 comhardclose(com); 2107 ttyclose(tp); 2108 siosettimeout(); 2109 splx(s); 2110 if (com->gone) { 2111 printf("sio%d: gone\n", com->unit); 2112 s = spltty(); 2113 if (com->ibuf != NULL) 2114 free(com->ibuf, M_DEVBUF); 2115 bzero(tp, sizeof *tp); 2116 splx(s); 2117 } 2118 return (0); 2119} 2120 2121static void 2122comhardclose(com) 2123 struct com_s *com; 2124{ 2125 int s; 2126 struct tty *tp; 2127 2128 s = spltty(); 2129 com->poll = FALSE; 2130 com->poll_output = FALSE; 2131 com->do_timestamp = FALSE; 2132 com->do_dcd_timestamp = FALSE; 2133 com->pps.ppsparam.mode = 0; 2134#ifdef PC98 2135 if (IS_8251(com->pc98_if_type)) 2136 com_send_break_off(com); 2137 else 2138#endif 2139 sio_setreg(com, com_cfcr, com->cfcr_image &= ~CFCR_SBREAK); 2140 tp = com->tp; 2141 2142#if defined(DDB) && (defined(BREAK_TO_DEBUGGER) || \ 2143 defined(ALT_BREAK_TO_DEBUGGER)) 2144 /* 2145 * Leave interrupts enabled and don't clear DTR if this is the 2146 * console. This allows us to detect break-to-debugger events 2147 * while the console device is closed. 2148 */ 2149 if (com->unit != comconsole) 2150#endif 2151 { 2152#ifdef PC98 2153 int tmp; 2154 if (IS_8251(com->pc98_if_type)) 2155 com_int_TxRx_disable(com); 2156 else 2157 sio_setreg(com, com_ier, 0); 2158 if (com->pc98_if_type == COM_IF_RSA98III) 2159 outb(com->rsabase + rsa_ier, 0x00); 2160 if (IS_8251(com->pc98_if_type)) 2161 tmp = pc98_get_modem_status(com) & TIOCM_CAR; 2162 else 2163 tmp = com->prev_modem_status & MSR_DCD; 2164#else 2165 sio_setreg(com, com_ier, 0); 2166#endif 2167 if (tp->t_cflag & HUPCL 2168 /* 2169 * XXX we will miss any carrier drop between here and the 2170 * next open. Perhaps we should watch DCD even when the 2171 * port is closed; it is not sufficient to check it at 2172 * the next open because it might go up and down while 2173 * we're not watching. 2174 */ 2175 || (!com->active_out 2176#ifdef PC98 2177 && !(tmp) 2178#else 2179 && !(com->prev_modem_status & MSR_DCD) 2180#endif 2181 && !(com->it_in.c_cflag & CLOCAL)) 2182 || !(tp->t_state & TS_ISOPEN)) { 2183#ifdef PC98 2184 if (IS_8251(com->pc98_if_type)) 2185 com_tiocm_bic(com, TIOCM_DTR|TIOCM_RTS|TIOCM_LE); 2186 else 2187#endif 2188 (void)commctl(com, TIOCM_DTR, DMBIC); 2189 if (com->dtr_wait != 0 && !(com->state & CS_DTR_OFF)) { 2190 timeout(siodtrwakeup, com, com->dtr_wait); 2191 com->state |= CS_DTR_OFF; 2192 } 2193 } 2194#ifdef PC98 2195 else { 2196 if (IS_8251(com->pc98_if_type)) 2197 com_tiocm_bic(com, TIOCM_LE); 2198 } 2199#endif 2200 } 2201#ifdef PC98 2202 if (com->pc98_8251fifo) { 2203 if (com->pc98_8251fifo_enable) 2204 outb(I8251F_fcr, CTRL8251F_XMT_RST | CTRL8251F_RCV_RST); 2205 com->pc98_8251fifo_enable = 0; 2206 } 2207#endif 2208 if (com->hasfifo) { 2209 /* 2210 * Disable fifos so that they are off after controlled 2211 * reboots. Some BIOSes fail to detect 16550s when the 2212 * fifos are enabled. 2213 */ 2214 sio_setreg(com, com_fifo, 0); 2215 } 2216 com->active_out = FALSE; 2217 wakeup(&com->active_out); 2218 wakeup(TSA_CARR_ON(tp)); /* restart any wopeners */ 2219 splx(s); 2220} 2221 2222static int 2223sioread(dev, uio, flag) 2224 dev_t dev; 2225 struct uio *uio; 2226 int flag; 2227{ 2228 int mynor; 2229 struct com_s *com; 2230 2231 mynor = minor(dev); 2232 if (mynor & CONTROL_MASK) 2233 return (ENODEV); 2234 com = com_addr(MINOR_TO_UNIT(mynor)); 2235 if (com == NULL || com->gone) 2236 return (ENODEV); 2237 return (ttyld_read(com->tp, uio, flag)); 2238} 2239 2240static int 2241siowrite(dev, uio, flag) 2242 dev_t dev; 2243 struct uio *uio; 2244 int flag; 2245{ 2246 int mynor; 2247 struct com_s *com; 2248 int unit; 2249 2250 mynor = minor(dev); 2251 if (mynor & CONTROL_MASK) 2252 return (ENODEV); 2253 2254 unit = MINOR_TO_UNIT(mynor); 2255 com = com_addr(unit); 2256 if (com == NULL || com->gone) 2257 return (ENODEV); 2258 /* 2259 * (XXX) We disallow virtual consoles if the physical console is 2260 * a serial port. This is in case there is a display attached that 2261 * is not the console. In that situation we don't need/want the X 2262 * server taking over the console. 2263 */ 2264 if (constty != NULL && unit == comconsole) 2265 constty = NULL; 2266 return (ttyld_write(com->tp, uio, flag)); 2267} 2268 2269static void 2270siobusycheck(chan) 2271 void *chan; 2272{ 2273 struct com_s *com; 2274 int s; 2275 2276 com = (struct com_s *)chan; 2277 2278 /* 2279 * Clear TS_BUSY if low-level output is complete. 2280 * spl locking is sufficient because siointr1() does not set CS_BUSY. 2281 * If siointr1() clears CS_BUSY after we look at it, then we'll get 2282 * called again. Reading the line status port outside of siointr1() 2283 * is safe because CS_BUSY is clear so there are no output interrupts 2284 * to lose. 2285 */ 2286 s = spltty(); 2287 if (com->state & CS_BUSY) 2288 com->extra_state &= ~CSE_BUSYCHECK; /* False alarm. */ 2289#ifdef PC98 2290 else if ((IS_8251(com->pc98_if_type) && 2291 ((com->pc98_8251fifo_enable && 2292 (inb(I8251F_lsr) & (STS8251F_TxRDY | STS8251F_TxEMP)) 2293 == (STS8251F_TxRDY | STS8251F_TxEMP)) || 2294 (!com->pc98_8251fifo_enable && 2295 (inb(com->sts_port) & (STS8251_TxRDY | STS8251_TxEMP)) 2296 == (STS8251_TxRDY | STS8251_TxEMP)))) || 2297 ((inb(com->line_status_port) & (LSR_TSRE | LSR_TXRDY)) 2298 == (LSR_TSRE | LSR_TXRDY))) { 2299#else 2300 else if ((inb(com->line_status_port) & (LSR_TSRE | LSR_TXRDY)) 2301 == (LSR_TSRE | LSR_TXRDY)) { 2302#endif 2303 com->tp->t_state &= ~TS_BUSY; 2304 ttwwakeup(com->tp); 2305 com->extra_state &= ~CSE_BUSYCHECK; 2306 } else 2307 timeout(siobusycheck, com, hz / 100); 2308 splx(s); 2309} 2310 2311static u_int 2312siodivisor(rclk, speed) 2313 u_long rclk; 2314 speed_t speed; 2315{ 2316 long actual_speed; 2317 u_int divisor; 2318 int error; 2319 2320 if (speed == 0) 2321 return (0); 2322#if UINT_MAX > (ULONG_MAX - 1) / 8 2323 if (speed > (ULONG_MAX - 1) / 8) 2324 return (0); 2325#endif 2326 divisor = (rclk / (8UL * speed) + 1) / 2; 2327 if (divisor == 0 || divisor >= 65536) 2328 return (0); 2329 actual_speed = rclk / (16UL * divisor); 2330 2331 /* 10 times error in percent: */ 2332 error = ((actual_speed - (long)speed) * 2000 / (long)speed + 1) / 2; 2333 2334 /* 3.0% maximum error tolerance: */ 2335 if (error < -30 || error > 30) 2336 return (0); 2337 2338 return (divisor); 2339} 2340 2341static void 2342siodtrwakeup(chan) 2343 void *chan; 2344{ 2345 struct com_s *com; 2346 2347 com = (struct com_s *)chan; 2348 com->state &= ~CS_DTR_OFF; 2349 wakeup(&com->dtr_wait); 2350} 2351 2352/* 2353 * Call this function with the sio_lock mutex held. It will return with the 2354 * lock still held. 2355 */ 2356static void 2357sioinput(com) 2358 struct com_s *com; 2359{ 2360 u_char *buf; 2361 int incc; 2362 u_char line_status; 2363 int recv_data; 2364 struct tty *tp; 2365 2366 buf = com->ibuf; 2367 tp = com->tp; 2368 if (!(tp->t_state & TS_ISOPEN) || !(tp->t_cflag & CREAD)) { 2369 com_events -= (com->iptr - com->ibuf); 2370 com->iptr = com->ibuf; 2371 return; 2372 } 2373 if (tp->t_state & TS_CAN_BYPASS_L_RINT) { 2374 /* 2375 * Avoid the grotesquely inefficient lineswitch routine 2376 * (ttyinput) in "raw" mode. It usually takes about 450 2377 * instructions (that's without canonical processing or echo!). 2378 * slinput is reasonably fast (usually 40 instructions plus 2379 * call overhead). 2380 */ 2381 do { 2382 /* 2383 * This may look odd, but it is using save-and-enable 2384 * semantics instead of the save-and-disable semantics 2385 * that are used everywhere else. 2386 */ 2387 mtx_unlock_spin(&sio_lock); 2388 incc = com->iptr - buf; 2389 if (tp->t_rawq.c_cc + incc > tp->t_ihiwat 2390 && (com->state & CS_RTS_IFLOW 2391 || tp->t_iflag & IXOFF) 2392 && !(tp->t_state & TS_TBLOCK)) 2393 ttyblock(tp); 2394 com->delta_error_counts[CE_TTY_BUF_OVERFLOW] 2395 += b_to_q((char *)buf, incc, &tp->t_rawq); 2396 buf += incc; 2397 tk_nin += incc; 2398 tk_rawcc += incc; 2399 tp->t_rawcc += incc; 2400 ttwakeup(tp); 2401 if (tp->t_state & TS_TTSTOP 2402 && (tp->t_iflag & IXANY 2403 || tp->t_cc[VSTART] == tp->t_cc[VSTOP])) { 2404 tp->t_state &= ~TS_TTSTOP; 2405 tp->t_lflag &= ~FLUSHO; 2406 comstart(tp); 2407 } 2408 mtx_lock_spin(&sio_lock); 2409 } while (buf < com->iptr); 2410 } else { 2411 do { 2412 /* 2413 * This may look odd, but it is using save-and-enable 2414 * semantics instead of the save-and-disable semantics 2415 * that are used everywhere else. 2416 */ 2417 mtx_unlock_spin(&sio_lock); 2418 line_status = buf[com->ierroff]; 2419 recv_data = *buf++; 2420 if (line_status 2421 & (LSR_BI | LSR_FE | LSR_OE | LSR_PE)) { 2422 if (line_status & LSR_BI) 2423 recv_data |= TTY_BI; 2424 if (line_status & LSR_FE) 2425 recv_data |= TTY_FE; 2426 if (line_status & LSR_OE) 2427 recv_data |= TTY_OE; 2428 if (line_status & LSR_PE) 2429 recv_data |= TTY_PE; 2430 } 2431 ttyld_rint(tp, recv_data); 2432 mtx_lock_spin(&sio_lock); 2433 } while (buf < com->iptr); 2434 } 2435 com_events -= (com->iptr - com->ibuf); 2436 com->iptr = com->ibuf; 2437 2438 /* 2439 * There is now room for another low-level buffer full of input, 2440 * so enable RTS if it is now disabled and there is room in the 2441 * high-level buffer. 2442 */ 2443#ifdef PC98 2444 if (IS_8251(com->pc98_if_type)) { 2445 if ((com->state & CS_RTS_IFLOW) && 2446 !(com_tiocm_get(com) & TIOCM_RTS) && 2447 !(tp->t_state & TS_TBLOCK)) 2448 com_tiocm_bis(com, TIOCM_RTS); 2449 } else { 2450 if ((com->state & CS_RTS_IFLOW) && 2451 !(com->mcr_image & MCR_RTS) && 2452 !(tp->t_state & TS_TBLOCK)) 2453 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS); 2454 } 2455#else 2456 if ((com->state & CS_RTS_IFLOW) && !(com->mcr_image & MCR_RTS) && 2457 !(tp->t_state & TS_TBLOCK)) 2458 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS); 2459#endif 2460} 2461 2462static void 2463siointr(arg) 2464 void *arg; 2465{ 2466 struct com_s *com; 2467#if defined(PC98) && defined(COM_MULTIPORT) 2468 u_char rsa_buf_status; 2469#endif 2470 2471#ifndef COM_MULTIPORT 2472 com = (struct com_s *)arg; 2473 2474 mtx_lock_spin(&sio_lock); 2475 siointr1(com); 2476 mtx_unlock_spin(&sio_lock); 2477#else /* COM_MULTIPORT */ 2478 bool_t possibly_more_intrs; 2479 int unit; 2480 2481 /* 2482 * Loop until there is no activity on any port. This is necessary 2483 * to get an interrupt edge more than to avoid another interrupt. 2484 * If the IRQ signal is just an OR of the IRQ signals from several 2485 * devices, then the edge from one may be lost because another is 2486 * on. 2487 */ 2488 mtx_lock_spin(&sio_lock); 2489 do { 2490 possibly_more_intrs = FALSE; 2491 for (unit = 0; unit < sio_numunits; ++unit) { 2492 com = com_addr(unit); 2493 /* 2494 * XXX COM_LOCK(); 2495 * would it work here, or be counter-productive? 2496 */ 2497#ifdef PC98 2498 if (com != NULL 2499 && !com->gone 2500 && IS_8251(com->pc98_if_type)) { 2501 siointr1(com); 2502 } else if (com != NULL 2503 && !com->gone 2504 && com->pc98_if_type == COM_IF_RSA98III) { 2505 rsa_buf_status = 2506 inb(com->rsabase + rsa_srr) & 0xc9; 2507 if ((rsa_buf_status & 0xc8) 2508 || !(rsa_buf_status & 0x01)) { 2509 siointr1(com); 2510 if (rsa_buf_status != 2511 (inb(com->rsabase + rsa_srr) & 0xc9)) 2512 possibly_more_intrs = TRUE; 2513 } 2514 } else 2515#endif 2516 if (com != NULL 2517 && !com->gone 2518 && (inb(com->int_id_port) & IIR_IMASK) 2519 != IIR_NOPEND) { 2520 siointr1(com); 2521 possibly_more_intrs = TRUE; 2522 } 2523 /* XXX COM_UNLOCK(); */ 2524 } 2525 } while (possibly_more_intrs); 2526 mtx_unlock_spin(&sio_lock); 2527#endif /* COM_MULTIPORT */ 2528} 2529 2530static struct timespec siots[8]; 2531static int siotso; 2532static int volatile siotsunit = -1; 2533 2534static int 2535sysctl_siots(SYSCTL_HANDLER_ARGS) 2536{ 2537 char buf[128]; 2538 long long delta; 2539 size_t len; 2540 int error, i, tso; 2541 2542 for (i = 1, tso = siotso; i < tso; i++) { 2543 delta = (long long)(siots[i].tv_sec - siots[i - 1].tv_sec) * 2544 1000000000 + 2545 (siots[i].tv_nsec - siots[i - 1].tv_nsec); 2546 len = sprintf(buf, "%lld\n", delta); 2547 if (delta >= 110000) 2548 len += sprintf(buf + len - 1, ": *** %ld.%09ld\n", 2549 (long)siots[i].tv_sec, siots[i].tv_nsec) - 1; 2550 if (i == tso - 1) 2551 buf[len - 1] = '\0'; 2552 error = SYSCTL_OUT(req, buf, len); 2553 if (error != 0) 2554 return (error); 2555 uio_yield(); 2556 } 2557 return (0); 2558} 2559 2560SYSCTL_PROC(_machdep, OID_AUTO, siots, CTLTYPE_STRING | CTLFLAG_RD, 2561 0, 0, sysctl_siots, "A", "sio timestamps"); 2562 2563static void 2564siointr1(com) 2565 struct com_s *com; 2566{ 2567 u_char int_ctl; 2568 u_char int_ctl_new; 2569 u_char line_status; 2570 u_char modem_status; 2571 u_char *ioptr; 2572 u_char recv_data; 2573 2574#ifdef PC98 2575 u_char tmp = 0; 2576 u_char rsa_buf_status = 0; 2577 int rsa_tx_fifo_size = 0; 2578#endif /* PC98 */ 2579 2580 if (COM_IIR_TXRDYBUG(com->flags)) { 2581 int_ctl = inb(com->int_ctl_port); 2582 int_ctl_new = int_ctl; 2583 } else { 2584 int_ctl = 0; 2585 int_ctl_new = 0; 2586 } 2587 2588 while (!com->gone) { 2589#ifdef PC98 2590status_read:; 2591 if (IS_8251(com->pc98_if_type)) { 2592 if (com->pc98_8251fifo_enable) 2593 tmp = inb(I8251F_lsr); 2594 else 2595 tmp = inb(com->sts_port); 2596more_intr: 2597 line_status = 0; 2598 if (com->pc98_8251fifo_enable) { 2599 if (tmp & STS8251F_TxRDY) line_status |= LSR_TXRDY; 2600 if (tmp & STS8251F_RxRDY) line_status |= LSR_RXRDY; 2601 if (tmp & STS8251F_TxEMP) line_status |= LSR_TSRE; 2602 if (tmp & STS8251F_PE) line_status |= LSR_PE; 2603 if (tmp & STS8251F_OE) line_status |= LSR_OE; 2604 if (tmp & STS8251F_BD_SD) line_status |= LSR_BI; 2605 } else { 2606 if (tmp & STS8251_TxRDY) line_status |= LSR_TXRDY; 2607 if (tmp & STS8251_RxRDY) line_status |= LSR_RXRDY; 2608 if (tmp & STS8251_TxEMP) line_status |= LSR_TSRE; 2609 if (tmp & STS8251_PE) line_status |= LSR_PE; 2610 if (tmp & STS8251_OE) line_status |= LSR_OE; 2611 if (tmp & STS8251_FE) line_status |= LSR_FE; 2612 if (tmp & STS8251_BD_SD) line_status |= LSR_BI; 2613 } 2614 } else { 2615#endif /* PC98 */ 2616 if (com->pps.ppsparam.mode & PPS_CAPTUREBOTH) { 2617 modem_status = inb(com->modem_status_port); 2618 if ((modem_status ^ com->last_modem_status) & 2619 com->pps_bit) { 2620 pps_capture(&com->pps); 2621 pps_event(&com->pps, 2622 (modem_status & com->pps_bit) ? 2623 PPS_CAPTUREASSERT : PPS_CAPTURECLEAR); 2624 } 2625 } 2626 line_status = inb(com->line_status_port); 2627#ifdef PC98 2628 } 2629 if (com->pc98_if_type == COM_IF_RSA98III) 2630 rsa_buf_status = inb(com->rsabase + rsa_srr); 2631#endif /* PC98 */ 2632 2633 /* input event? (check first to help avoid overruns) */ 2634#ifndef PC98 2635 while (line_status & LSR_RCV_MASK) { 2636#else 2637 while ((line_status & LSR_RCV_MASK) 2638 || (com->pc98_if_type == COM_IF_RSA98III 2639 && (rsa_buf_status & 0x08))) { 2640#endif /* PC98 */ 2641 /* break/unnattached error bits or real input? */ 2642#ifdef PC98 2643 if (IS_8251(com->pc98_if_type)) { 2644 if (com->pc98_8251fifo_enable) { 2645 recv_data = inb(I8251F_data); 2646 if (tmp & (STS8251F_PE | STS8251F_OE | 2647 STS8251F_BD_SD)) { 2648 pc98_i8251_or_cmd(com, CMD8251_ER); 2649 recv_data = 0; 2650 } 2651 } else { 2652 recv_data = inb(com->data_port); 2653 if (tmp & (STS8251_PE | STS8251_OE | 2654 STS8251_FE | STS8251_BD_SD)) { 2655 pc98_i8251_or_cmd(com, CMD8251_ER); 2656 recv_data = 0; 2657 } 2658 } 2659 } else if (com->pc98_if_type == COM_IF_RSA98III) { 2660 if (!(rsa_buf_status & 0x08)) 2661 recv_data = 0; 2662 else 2663 recv_data = inb(com->data_port); 2664 } else 2665#endif 2666 if (!(line_status & LSR_RXRDY)) 2667 recv_data = 0; 2668 else 2669 recv_data = inb(com->data_port); 2670#ifdef DDB 2671#ifdef ALT_BREAK_TO_DEBUGGER 2672 if (com->unit == comconsole && 2673 db_alt_break(recv_data, &com->alt_brk_state) != 0) 2674 breakpoint(); 2675#endif /* ALT_BREAK_TO_DEBUGGER */ 2676#endif /* DDB */ 2677 if (line_status & (LSR_BI | LSR_FE | LSR_PE)) { 2678 /* 2679 * Don't store BI if IGNBRK or FE/PE if IGNPAR. 2680 * Otherwise, push the work to a higher level 2681 * (to handle PARMRK) if we're bypassing. 2682 * Otherwise, convert BI/FE and PE+INPCK to 0. 2683 * 2684 * This makes bypassing work right in the 2685 * usual "raw" case (IGNBRK set, and IGNPAR 2686 * and INPCK clear). 2687 * 2688 * Note: BI together with FE/PE means just BI. 2689 */ 2690 if (line_status & LSR_BI) { 2691#if defined(DDB) && defined(BREAK_TO_DEBUGGER) 2692 if (com->unit == comconsole) { 2693 breakpoint(); 2694 goto cont; 2695 } 2696#endif 2697 if (com->tp == NULL 2698 || com->tp->t_iflag & IGNBRK) 2699 goto cont; 2700 } else { 2701 if (com->tp == NULL 2702 || com->tp->t_iflag & IGNPAR) 2703 goto cont; 2704 } 2705 if (com->tp->t_state & TS_CAN_BYPASS_L_RINT 2706 && (line_status & (LSR_BI | LSR_FE) 2707 || com->tp->t_iflag & INPCK)) 2708 recv_data = 0; 2709 } 2710 ++com->bytes_in; 2711 if (com->hotchar != 0 && recv_data == com->hotchar) 2712 swi_sched(sio_fast_ih, 0); 2713 ioptr = com->iptr; 2714 if (ioptr >= com->ibufend) 2715 CE_RECORD(com, CE_INTERRUPT_BUF_OVERFLOW); 2716 else { 2717 if (com->do_timestamp) 2718 microtime(&com->timestamp); 2719 ++com_events; 2720 swi_sched(sio_slow_ih, SWI_DELAY); 2721#if 0 /* for testing input latency vs efficiency */ 2722if (com->iptr - com->ibuf == 8) 2723 swi_sched(sio_fast_ih, 0); 2724#endif 2725 ioptr[0] = recv_data; 2726 ioptr[com->ierroff] = line_status; 2727 com->iptr = ++ioptr; 2728 if (ioptr == com->ihighwater 2729 && com->state & CS_RTS_IFLOW) 2730#ifdef PC98 2731 IS_8251(com->pc98_if_type) ? 2732 com_tiocm_bic(com, TIOCM_RTS) : 2733#endif 2734 outb(com->modem_ctl_port, 2735 com->mcr_image &= ~MCR_RTS); 2736 if (line_status & LSR_OE) 2737 CE_RECORD(com, CE_OVERRUN); 2738 } 2739cont: 2740 if (line_status & LSR_TXRDY 2741 && com->state >= (CS_BUSY | CS_TTGO | CS_ODEVREADY)) 2742 goto txrdy; 2743 2744 /* 2745 * "& 0x7F" is to avoid the gcc-1.40 generating a slow 2746 * jump from the top of the loop to here 2747 */ 2748#ifdef PC98 2749 if (IS_8251(com->pc98_if_type)) 2750 goto status_read; 2751 else 2752#endif 2753 line_status = inb(com->line_status_port) & 0x7F; 2754#ifdef PC98 2755 if (com->pc98_if_type == COM_IF_RSA98III) 2756 rsa_buf_status = inb(com->rsabase + rsa_srr); 2757#endif /* PC98 */ 2758 } 2759 2760 /* modem status change? (always check before doing output) */ 2761#ifdef PC98 2762 if (!IS_8251(com->pc98_if_type)) { 2763#endif 2764 modem_status = inb(com->modem_status_port); 2765 if (modem_status != com->last_modem_status) { 2766 if (com->do_dcd_timestamp 2767 && !(com->last_modem_status & MSR_DCD) 2768 && modem_status & MSR_DCD) 2769 microtime(&com->dcd_timestamp); 2770 2771 /* 2772 * Schedule high level to handle DCD changes. Note 2773 * that we don't use the delta bits anywhere. Some 2774 * UARTs mess them up, and it's easy to remember the 2775 * previous bits and calculate the delta. 2776 */ 2777 com->last_modem_status = modem_status; 2778 if (!(com->state & CS_CHECKMSR)) { 2779 com_events += LOTS_OF_EVENTS; 2780 com->state |= CS_CHECKMSR; 2781 swi_sched(sio_fast_ih, 0); 2782 } 2783 2784 /* handle CTS change immediately for crisp flow ctl */ 2785 if (com->state & CS_CTS_OFLOW) { 2786 if (modem_status & MSR_CTS) 2787 com->state |= CS_ODEVREADY; 2788 else 2789 com->state &= ~CS_ODEVREADY; 2790 } 2791 } 2792#ifdef PC98 2793 } 2794#endif 2795 2796txrdy: 2797 /* output queued and everything ready? */ 2798#ifndef PC98 2799 if (line_status & LSR_TXRDY 2800 && com->state >= (CS_BUSY | CS_TTGO | CS_ODEVREADY)) { 2801#else 2802 if (((com->pc98_if_type == COM_IF_RSA98III) 2803 ? (rsa_buf_status & 0x02) 2804 : (line_status & LSR_TXRDY)) 2805 && com->state >= (CS_BUSY | CS_TTGO | CS_ODEVREADY)) { 2806#endif 2807#ifdef PC98 2808 Port_t tmp_data_port; 2809 2810 if (IS_8251(com->pc98_if_type) && 2811 com->pc98_8251fifo_enable) 2812 tmp_data_port = I8251F_data; 2813 else 2814 tmp_data_port = com->data_port; 2815#endif 2816 2817 ioptr = com->obufq.l_head; 2818 if (com->tx_fifo_size > 1 && com->unit != siotsunit) { 2819 u_int ocount; 2820 2821 ocount = com->obufq.l_tail - ioptr; 2822#ifdef PC98 2823 if (com->pc98_if_type == COM_IF_RSA98III) { 2824 rsa_buf_status = inb(com->rsabase + rsa_srr); 2825 rsa_tx_fifo_size = 1024; 2826 if (!(rsa_buf_status & 0x01)) 2827 rsa_tx_fifo_size = 2048; 2828 if (ocount > rsa_tx_fifo_size) 2829 ocount = rsa_tx_fifo_size; 2830 } else 2831#endif 2832 if (ocount > com->tx_fifo_size) 2833 ocount = com->tx_fifo_size; 2834 com->bytes_out += ocount; 2835 do 2836#ifdef PC98 2837 outb(tmp_data_port, *ioptr++); 2838#else 2839 outb(com->data_port, *ioptr++); 2840#endif 2841 while (--ocount != 0); 2842 } else { 2843#ifdef PC98 2844 outb(tmp_data_port, *ioptr++); 2845#else 2846 outb(com->data_port, *ioptr++); 2847#endif 2848 ++com->bytes_out; 2849 if (com->unit == siotsunit 2850 && siotso < sizeof siots / sizeof siots[0]) 2851 nanouptime(&siots[siotso++]); 2852 } 2853#ifdef PC98 2854 if (IS_8251(com->pc98_if_type)) 2855 if (!(pc98_check_i8251_interrupt(com) & IEN_TxFLAG)) 2856 com_int_Tx_enable(com); 2857#endif 2858 com->obufq.l_head = ioptr; 2859 if (COM_IIR_TXRDYBUG(com->flags)) 2860 int_ctl_new = int_ctl | IER_ETXRDY; 2861 if (ioptr >= com->obufq.l_tail) { 2862 struct lbq *qp; 2863 2864 qp = com->obufq.l_next; 2865 qp->l_queued = FALSE; 2866 qp = qp->l_next; 2867 if (qp != NULL) { 2868 com->obufq.l_head = qp->l_head; 2869 com->obufq.l_tail = qp->l_tail; 2870 com->obufq.l_next = qp; 2871 } else { 2872 /* output just completed */ 2873 if (COM_IIR_TXRDYBUG(com->flags)) 2874 int_ctl_new = int_ctl 2875 & ~IER_ETXRDY; 2876 com->state &= ~CS_BUSY; 2877#if defined(PC98) 2878 if (IS_8251(com->pc98_if_type) && 2879 pc98_check_i8251_interrupt(com) & IEN_TxFLAG) 2880 com_int_Tx_disable(com); 2881#endif 2882 } 2883 if (!(com->state & CS_ODONE)) { 2884 com_events += LOTS_OF_EVENTS; 2885 com->state |= CS_ODONE; 2886 /* handle at high level ASAP */ 2887 swi_sched(sio_fast_ih, 0); 2888 } 2889 } 2890#ifdef PC98 2891 if (COM_IIR_TXRDYBUG(com->flags) 2892 && int_ctl != int_ctl_new) { 2893 if (com->pc98_if_type == COM_IF_RSA98III) { 2894 int_ctl_new &= ~(IER_ETXRDY | IER_ERXRDY); 2895 outb(com->int_ctl_port, int_ctl_new); 2896 outb(com->rsabase + rsa_ier, 0x1d); 2897 } else 2898 outb(com->int_ctl_port, int_ctl_new); 2899 } 2900#else 2901 if (COM_IIR_TXRDYBUG(com->flags) 2902 && int_ctl != int_ctl_new) 2903 outb(com->int_ctl_port, int_ctl_new); 2904#endif 2905 } 2906#ifdef PC98 2907 else if (line_status & LSR_TXRDY) { 2908 if (IS_8251(com->pc98_if_type)) 2909 if (pc98_check_i8251_interrupt(com) & IEN_TxFLAG) 2910 com_int_Tx_disable(com); 2911 } 2912 if (IS_8251(com->pc98_if_type)) { 2913 if (com->pc98_8251fifo_enable) { 2914 if ((tmp = inb(I8251F_lsr)) & STS8251F_RxRDY) 2915 goto more_intr; 2916 } else { 2917 if ((tmp = inb(com->sts_port)) & STS8251_RxRDY) 2918 goto more_intr; 2919 } 2920 } 2921#endif 2922 2923 /* finished? */ 2924#ifndef COM_MULTIPORT 2925#ifdef PC98 2926 if (IS_8251(com->pc98_if_type)) 2927 return; 2928#endif 2929 if ((inb(com->int_id_port) & IIR_IMASK) == IIR_NOPEND) 2930#endif /* COM_MULTIPORT */ 2931 return; 2932 } 2933} 2934 2935static int 2936sioioctl(dev, cmd, data, flag, td) 2937 dev_t dev; 2938 u_long cmd; 2939 caddr_t data; 2940 int flag; 2941 struct thread *td; 2942{ 2943 struct com_s *com; 2944 int error; 2945 int mynor; 2946 int s; 2947 struct tty *tp; 2948#if defined(COMPAT_43) || defined(COMPAT_SUNOS) 2949 u_long oldcmd; 2950 struct termios term; 2951#endif 2952 2953 mynor = minor(dev); 2954 com = com_addr(MINOR_TO_UNIT(mynor)); 2955 if (com == NULL || com->gone) 2956 return (ENODEV); 2957 if (mynor & CONTROL_MASK) { 2958 struct termios *ct; 2959 2960 switch (mynor & CONTROL_MASK) { 2961 case CONTROL_INIT_STATE: 2962 ct = mynor & CALLOUT_MASK ? &com->it_out : &com->it_in; 2963 break; 2964 case CONTROL_LOCK_STATE: 2965 ct = mynor & CALLOUT_MASK ? &com->lt_out : &com->lt_in; 2966 break; 2967 default: 2968 return (ENODEV); /* /dev/nodev */ 2969 } 2970 switch (cmd) { 2971 case TIOCSETA: 2972 error = suser(td); 2973 if (error != 0) 2974 return (error); 2975 *ct = *(struct termios *)data; 2976 return (0); 2977 case TIOCGETA: 2978 *(struct termios *)data = *ct; 2979 return (0); 2980 case TIOCGETD: 2981 *(int *)data = TTYDISC; 2982 return (0); 2983 case TIOCGWINSZ: 2984 bzero(data, sizeof(struct winsize)); 2985 return (0); 2986 default: 2987 return (ENOTTY); 2988 } 2989 } 2990 tp = com->tp; 2991#if defined(COMPAT_43) || defined(COMPAT_SUNOS) 2992 term = tp->t_termios; 2993 oldcmd = cmd; 2994 error = ttsetcompat(tp, &cmd, data, &term); 2995 if (error != 0) 2996 return (error); 2997 if (cmd != oldcmd) 2998 data = (caddr_t)&term; 2999#endif 3000 if (cmd == TIOCSETA || cmd == TIOCSETAW || cmd == TIOCSETAF) { 3001 int cc; 3002 struct termios *dt = (struct termios *)data; 3003 struct termios *lt = mynor & CALLOUT_MASK 3004 ? &com->lt_out : &com->lt_in; 3005 3006 dt->c_iflag = (tp->t_iflag & lt->c_iflag) 3007 | (dt->c_iflag & ~lt->c_iflag); 3008 dt->c_oflag = (tp->t_oflag & lt->c_oflag) 3009 | (dt->c_oflag & ~lt->c_oflag); 3010 dt->c_cflag = (tp->t_cflag & lt->c_cflag) 3011 | (dt->c_cflag & ~lt->c_cflag); 3012 dt->c_lflag = (tp->t_lflag & lt->c_lflag) 3013 | (dt->c_lflag & ~lt->c_lflag); 3014 for (cc = 0; cc < NCCS; ++cc) 3015 if (lt->c_cc[cc] != 0) 3016 dt->c_cc[cc] = tp->t_cc[cc]; 3017 if (lt->c_ispeed != 0) 3018 dt->c_ispeed = tp->t_ispeed; 3019 if (lt->c_ospeed != 0) 3020 dt->c_ospeed = tp->t_ospeed; 3021 } 3022 error = ttyioctl(dev, cmd, data, flag, td); 3023 com->hotchar = ttyldoptim(tp); 3024 if (error != ENOTTY) 3025 return (error); 3026 s = spltty(); 3027#ifdef PC98 3028 if (IS_8251(com->pc98_if_type)) { 3029 switch (cmd) { 3030 case TIOCSBRK: 3031 com_send_break_on(com); 3032 break; 3033 case TIOCCBRK: 3034 com_send_break_off(com); 3035 break; 3036 case TIOCSDTR: 3037 com_tiocm_bis(com, TIOCM_DTR | TIOCM_RTS); 3038 break; 3039 case TIOCCDTR: 3040 com_tiocm_bic(com, TIOCM_DTR); 3041 break; 3042 /* 3043 * XXX should disallow changing MCR_RTS if CS_RTS_IFLOW is set. The 3044 * changes get undone on the next call to comparam(). 3045 */ 3046 case TIOCMSET: 3047 com_tiocm_set(com, *(int *)data); 3048 break; 3049 case TIOCMBIS: 3050 com_tiocm_bis(com, *(int *)data); 3051 break; 3052 case TIOCMBIC: 3053 com_tiocm_bic(com, *(int *)data); 3054 break; 3055 case TIOCMGET: 3056 *(int *)data = com_tiocm_get(com); 3057 break; 3058 case TIOCMSDTRWAIT: 3059 /* must be root since the wait applies to following logins */ 3060 error = suser(td); 3061 if (error != 0) { 3062 splx(s); 3063 return (error); 3064 } 3065 com->dtr_wait = *(int *)data * hz / 100; 3066 break; 3067 case TIOCMGDTRWAIT: 3068 *(int *)data = com->dtr_wait * 100 / hz; 3069 break; 3070 case TIOCTIMESTAMP: 3071 com->do_timestamp = TRUE; 3072 *(struct timeval *)data = com->timestamp; 3073 break; 3074 case TIOCDCDTIMESTAMP: 3075 com->do_dcd_timestamp = TRUE; 3076 *(struct timeval *)data = com->dcd_timestamp; 3077 break; 3078 default: 3079 splx(s); 3080 error = pps_ioctl(cmd, data, &com->pps); 3081 if (error == ENODEV) 3082 error = ENOTTY; 3083 return (error); 3084 } 3085 } else { 3086#endif 3087 switch (cmd) { 3088 case TIOCSBRK: 3089 sio_setreg(com, com_cfcr, com->cfcr_image |= CFCR_SBREAK); 3090 break; 3091 case TIOCCBRK: 3092 sio_setreg(com, com_cfcr, com->cfcr_image &= ~CFCR_SBREAK); 3093 break; 3094 case TIOCSDTR: 3095 (void)commctl(com, TIOCM_DTR, DMBIS); 3096 break; 3097 case TIOCCDTR: 3098 (void)commctl(com, TIOCM_DTR, DMBIC); 3099 break; 3100 /* 3101 * XXX should disallow changing MCR_RTS if CS_RTS_IFLOW is set. The 3102 * changes get undone on the next call to comparam(). 3103 */ 3104 case TIOCMSET: 3105 (void)commctl(com, *(int *)data, DMSET); 3106 break; 3107 case TIOCMBIS: 3108 (void)commctl(com, *(int *)data, DMBIS); 3109 break; 3110 case TIOCMBIC: 3111 (void)commctl(com, *(int *)data, DMBIC); 3112 break; 3113 case TIOCMGET: 3114 *(int *)data = commctl(com, 0, DMGET); 3115 break; 3116 case TIOCMSDTRWAIT: 3117 /* must be root since the wait applies to following logins */ 3118 error = suser(td); 3119 if (error != 0) { 3120 splx(s); 3121 return (error); 3122 } 3123 com->dtr_wait = *(int *)data * hz / 100; 3124 break; 3125 case TIOCMGDTRWAIT: 3126 *(int *)data = com->dtr_wait * 100 / hz; 3127 break; 3128 case TIOCTIMESTAMP: 3129 com->do_timestamp = TRUE; 3130 *(struct timeval *)data = com->timestamp; 3131 break; 3132 case TIOCDCDTIMESTAMP: 3133 com->do_dcd_timestamp = TRUE; 3134 *(struct timeval *)data = com->dcd_timestamp; 3135 break; 3136 default: 3137 splx(s); 3138 error = pps_ioctl(cmd, data, &com->pps); 3139 if (error == ENODEV) 3140 error = ENOTTY; 3141 return (error); 3142 } 3143#ifdef PC98 3144 } 3145#endif 3146 splx(s); 3147 return (0); 3148} 3149 3150/* software interrupt handler for SWI_TTY */ 3151static void 3152siopoll(void *dummy) 3153{ 3154 int unit; 3155 3156 if (com_events == 0) 3157 return; 3158repeat: 3159 for (unit = 0; unit < sio_numunits; ++unit) { 3160 struct com_s *com; 3161 int incc; 3162 struct tty *tp; 3163 3164 com = com_addr(unit); 3165 if (com == NULL) 3166 continue; 3167 tp = com->tp; 3168 if (tp == NULL || com->gone) { 3169 /* 3170 * Discard any events related to never-opened or 3171 * going-away devices. 3172 */ 3173 mtx_lock_spin(&sio_lock); 3174 incc = com->iptr - com->ibuf; 3175 com->iptr = com->ibuf; 3176 if (com->state & CS_CHECKMSR) { 3177 incc += LOTS_OF_EVENTS; 3178 com->state &= ~CS_CHECKMSR; 3179 } 3180 com_events -= incc; 3181 mtx_unlock_spin(&sio_lock); 3182 continue; 3183 } 3184 if (com->iptr != com->ibuf) { 3185 mtx_lock_spin(&sio_lock); 3186 sioinput(com); 3187 mtx_unlock_spin(&sio_lock); 3188 } 3189 if (com->state & CS_CHECKMSR) { 3190 u_char delta_modem_status; 3191 3192#ifdef PC98 3193 if (!IS_8251(com->pc98_if_type)) { 3194#endif 3195 mtx_lock_spin(&sio_lock); 3196 delta_modem_status = com->last_modem_status 3197 ^ com->prev_modem_status; 3198 com->prev_modem_status = com->last_modem_status; 3199 com_events -= LOTS_OF_EVENTS; 3200 com->state &= ~CS_CHECKMSR; 3201 mtx_unlock_spin(&sio_lock); 3202 if (delta_modem_status & MSR_DCD) 3203 ttyld_modem(tp, 3204 com->prev_modem_status & MSR_DCD); 3205#ifdef PC98 3206 } 3207#endif 3208 } 3209 if (com->state & CS_ODONE) { 3210 mtx_lock_spin(&sio_lock); 3211 com_events -= LOTS_OF_EVENTS; 3212 com->state &= ~CS_ODONE; 3213 mtx_unlock_spin(&sio_lock); 3214 if (!(com->state & CS_BUSY) 3215 && !(com->extra_state & CSE_BUSYCHECK)) { 3216 timeout(siobusycheck, com, hz / 100); 3217 com->extra_state |= CSE_BUSYCHECK; 3218 } 3219 ttyld_start(tp); 3220 } 3221 if (com_events == 0) 3222 break; 3223 } 3224 if (com_events >= LOTS_OF_EVENTS) 3225 goto repeat; 3226} 3227 3228static int 3229comparam(tp, t) 3230 struct tty *tp; 3231 struct termios *t; 3232{ 3233 u_int cfcr; 3234 int cflag; 3235 struct com_s *com; 3236 u_int divisor; 3237 u_char dlbh; 3238 u_char dlbl; 3239 u_char efr_flowbits; 3240 int s; 3241 int unit; 3242#ifdef PC98 3243 u_char param = 0; 3244#endif 3245 3246 unit = DEV_TO_UNIT(tp->t_dev); 3247 com = com_addr(unit); 3248 if (com == NULL) 3249 return (ENODEV); 3250 3251#ifdef PC98 3252 cfcr = 0; 3253 3254 if (IS_8251(com->pc98_if_type)) { 3255 if (pc98_ttspeedtab(com, t->c_ospeed, &divisor) != 0) 3256 return (EINVAL); 3257 } else { 3258#endif 3259 /* check requested parameters */ 3260 if (t->c_ispeed != (t->c_ospeed != 0 ? t->c_ospeed : tp->t_ospeed)) 3261 return (EINVAL); 3262 divisor = siodivisor(com->rclk, t->c_ispeed); 3263 if (divisor == 0) 3264 return (EINVAL); 3265#ifdef PC98 3266 } 3267#endif 3268 3269 /* parameters are OK, convert them to the com struct and the device */ 3270 s = spltty(); 3271#ifdef PC98 3272 if (IS_8251(com->pc98_if_type)) { 3273 if (t->c_ospeed == 0) 3274 com_tiocm_bic(com, TIOCM_DTR|TIOCM_RTS|TIOCM_LE); 3275 else 3276 com_tiocm_bis(com, TIOCM_DTR|TIOCM_RTS|TIOCM_LE); 3277 } else 3278#endif 3279 if (t->c_ospeed == 0) 3280 (void)commctl(com, TIOCM_DTR, DMBIC); /* hang up line */ 3281 else 3282 (void)commctl(com, TIOCM_DTR, DMBIS); 3283 cflag = t->c_cflag; 3284#ifdef PC98 3285 if (!IS_8251(com->pc98_if_type)) { 3286#endif 3287 switch (cflag & CSIZE) { 3288 case CS5: 3289 cfcr = CFCR_5BITS; 3290 break; 3291 case CS6: 3292 cfcr = CFCR_6BITS; 3293 break; 3294 case CS7: 3295 cfcr = CFCR_7BITS; 3296 break; 3297 default: 3298 cfcr = CFCR_8BITS; 3299 break; 3300 } 3301 if (cflag & PARENB) { 3302 cfcr |= CFCR_PENAB; 3303 if (!(cflag & PARODD)) 3304 cfcr |= CFCR_PEVEN; 3305 } 3306 if (cflag & CSTOPB) 3307 cfcr |= CFCR_STOPB; 3308 3309 if (com->hasfifo) { 3310 /* 3311 * Use a fifo trigger level low enough so that the input 3312 * latency from the fifo is less than about 16 msec and 3313 * the total latency is less than about 30 msec. These 3314 * latencies are reasonable for humans. Serial comms 3315 * protocols shouldn't expect anything better since modem 3316 * latencies are larger. 3317 * 3318 * The fifo trigger level cannot be set at RX_HIGH for high 3319 * speed connections without further work on reducing 3320 * interrupt disablement times in other parts of the system, 3321 * without producing silo overflow errors. 3322 */ 3323 com->fifo_image = com->unit == siotsunit ? 0 3324 : t->c_ispeed <= 4800 3325 ? FIFO_ENABLE : FIFO_ENABLE | FIFO_RX_MEDH; 3326#ifdef COM_ESP 3327 /* 3328 * The Hayes ESP card needs the fifo DMA mode bit set 3329 * in compatibility mode. If not, it will interrupt 3330 * for each character received. 3331 */ 3332 if (com->esp) 3333 com->fifo_image |= FIFO_DMA_MODE; 3334#endif 3335 sio_setreg(com, com_fifo, com->fifo_image); 3336 } 3337#ifdef PC98 3338 } 3339#endif 3340 3341 /* 3342 * This returns with interrupts disabled so that we can complete 3343 * the speed change atomically. Keeping interrupts disabled is 3344 * especially important while com_data is hidden. 3345 */ 3346 (void) siosetwater(com, t->c_ispeed); 3347 3348#ifdef PC98 3349 if (IS_8251(com->pc98_if_type)) 3350 com_cflag_and_speed_set(com, cflag, t->c_ospeed); 3351 else { 3352#endif 3353 sio_setreg(com, com_cfcr, cfcr | CFCR_DLAB); 3354 /* 3355 * Only set the divisor registers if they would change, since on 3356 * some 16550 incompatibles (UMC8669F), setting them while input 3357 * is arriving loses sync until data stops arriving. 3358 */ 3359 dlbl = divisor & 0xFF; 3360 if (sio_getreg(com, com_dlbl) != dlbl) 3361 sio_setreg(com, com_dlbl, dlbl); 3362 dlbh = divisor >> 8; 3363 if (sio_getreg(com, com_dlbh) != dlbh) 3364 sio_setreg(com, com_dlbh, dlbh); 3365#ifdef PC98 3366 } 3367#endif 3368 3369 efr_flowbits = 0; 3370 3371 if (cflag & CRTS_IFLOW) { 3372 com->state |= CS_RTS_IFLOW; 3373 efr_flowbits |= EFR_AUTORTS; 3374 /* 3375 * If CS_RTS_IFLOW just changed from off to on, the change 3376 * needs to be propagated to MCR_RTS. This isn't urgent, 3377 * so do it later by calling comstart() instead of repeating 3378 * a lot of code from comstart() here. 3379 */ 3380 } else if (com->state & CS_RTS_IFLOW) { 3381 com->state &= ~CS_RTS_IFLOW; 3382 /* 3383 * CS_RTS_IFLOW just changed from on to off. Force MCR_RTS 3384 * on here, since comstart() won't do it later. 3385 */ 3386#ifdef PC98 3387 if (IS_8251(com->pc98_if_type)) 3388 com_tiocm_bis(com, TIOCM_RTS); 3389 else 3390 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS); 3391#else 3392 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS); 3393#endif 3394 } 3395 3396 /* 3397 * Set up state to handle output flow control. 3398 * XXX - worth handling MDMBUF (DCD) flow control at the lowest level? 3399 * Now has 10+ msec latency, while CTS flow has 50- usec latency. 3400 */ 3401 com->state |= CS_ODEVREADY; 3402 com->state &= ~CS_CTS_OFLOW; 3403#ifdef PC98 3404 if (com->pc98_if_type == COM_IF_RSA98III) { 3405 param = inb(com->rsabase + rsa_msr); 3406 outb(com->rsabase + rsa_msr, param & 0x14); 3407 } 3408#endif 3409 if (cflag & CCTS_OFLOW) { 3410 com->state |= CS_CTS_OFLOW; 3411 efr_flowbits |= EFR_AUTOCTS; 3412#ifdef PC98 3413 if (IS_8251(com->pc98_if_type)) { 3414 if (!(pc98_get_modem_status(com) & TIOCM_CTS)) 3415 com->state &= ~CS_ODEVREADY; 3416 } else if (com->pc98_if_type == COM_IF_RSA98III) { 3417 /* Set automatic flow control mode */ 3418 outb(com->rsabase + rsa_msr, param | 0x08); 3419 } else 3420#endif 3421 if (!(com->last_modem_status & MSR_CTS)) 3422 com->state &= ~CS_ODEVREADY; 3423 } 3424 3425#ifdef PC98 3426 if (!IS_8251(com->pc98_if_type)) 3427 sio_setreg(com, com_cfcr, com->cfcr_image = cfcr); 3428#else 3429 if (com->st16650a) { 3430 sio_setreg(com, com_lcr, LCR_EFR_ENABLE); 3431 sio_setreg(com, com_efr, 3432 (sio_getreg(com, com_efr) 3433 & ~(EFR_AUTOCTS | EFR_AUTORTS)) | efr_flowbits); 3434 } 3435 sio_setreg(com, com_cfcr, com->cfcr_image = cfcr); 3436#endif 3437 3438 /* XXX shouldn't call functions while intrs are disabled. */ 3439 com->hotchar = ttyldoptim(tp); 3440 3441 mtx_unlock_spin(&sio_lock); 3442 splx(s); 3443 comstart(tp); 3444 if (com->ibufold != NULL) { 3445 free(com->ibufold, M_DEVBUF); 3446 com->ibufold = NULL; 3447 } 3448 return (0); 3449} 3450 3451/* 3452 * This function must be called with the sio_lock mutex released and will 3453 * return with it obtained. 3454 */ 3455static int 3456siosetwater(com, speed) 3457 struct com_s *com; 3458 speed_t speed; 3459{ 3460 int cp4ticks; 3461 u_char *ibuf; 3462 int ibufsize; 3463 struct tty *tp; 3464 3465 /* 3466 * Make the buffer size large enough to handle a softtty interrupt 3467 * latency of about 2 ticks without loss of throughput or data 3468 * (about 3 ticks if input flow control is not used or not honoured, 3469 * but a bit less for CS5-CS7 modes). 3470 */ 3471 cp4ticks = speed / 10 / hz * 4; 3472 for (ibufsize = 128; ibufsize < cp4ticks;) 3473 ibufsize <<= 1; 3474#ifdef PC98 3475 if (com->pc98_if_type == COM_IF_RSA98III) 3476 ibufsize = 2048; 3477#endif 3478 if (ibufsize == com->ibufsize) { 3479 mtx_lock_spin(&sio_lock); 3480 return (0); 3481 } 3482 3483 /* 3484 * Allocate input buffer. The extra factor of 2 in the size is 3485 * to allow for an error byte for each input byte. 3486 */ 3487 ibuf = malloc(2 * ibufsize, M_DEVBUF, M_NOWAIT); 3488 if (ibuf == NULL) { 3489 mtx_lock_spin(&sio_lock); 3490 return (ENOMEM); 3491 } 3492 3493 /* Initialize non-critical variables. */ 3494 com->ibufold = com->ibuf; 3495 com->ibufsize = ibufsize; 3496 tp = com->tp; 3497 if (tp != NULL) { 3498 tp->t_ififosize = 2 * ibufsize; 3499 tp->t_ispeedwat = (speed_t)-1; 3500 tp->t_ospeedwat = (speed_t)-1; 3501 } 3502 3503 /* 3504 * Read current input buffer, if any. Continue with interrupts 3505 * disabled. 3506 */ 3507 mtx_lock_spin(&sio_lock); 3508 if (com->iptr != com->ibuf) 3509 sioinput(com); 3510 3511 /*- 3512 * Initialize critical variables, including input buffer watermarks. 3513 * The external device is asked to stop sending when the buffer 3514 * exactly reaches high water, or when the high level requests it. 3515 * The high level is notified immediately (rather than at a later 3516 * clock tick) when this watermark is reached. 3517 * The buffer size is chosen so the watermark should almost never 3518 * be reached. 3519 * The low watermark is invisibly 0 since the buffer is always 3520 * emptied all at once. 3521 */ 3522 com->iptr = com->ibuf = ibuf; 3523 com->ibufend = ibuf + ibufsize; 3524 com->ierroff = ibufsize; 3525 com->ihighwater = ibuf + 3 * ibufsize / 4; 3526 return (0); 3527} 3528 3529static void 3530comstart(tp) 3531 struct tty *tp; 3532{ 3533 struct com_s *com; 3534 int s; 3535 int unit; 3536 3537 unit = DEV_TO_UNIT(tp->t_dev); 3538 com = com_addr(unit); 3539 if (com == NULL) 3540 return; 3541 s = spltty(); 3542 mtx_lock_spin(&sio_lock); 3543 if (tp->t_state & TS_TTSTOP) 3544 com->state &= ~CS_TTGO; 3545 else 3546 com->state |= CS_TTGO; 3547 if (tp->t_state & TS_TBLOCK) { 3548#ifdef PC98 3549 if (IS_8251(com->pc98_if_type)) { 3550 if ((com_tiocm_get(com) & TIOCM_RTS) && 3551 (com->state & CS_RTS_IFLOW)) 3552 com_tiocm_bic(com, TIOCM_RTS); 3553 } else { 3554 if ((com->mcr_image & MCR_RTS) && 3555 (com->state & CS_RTS_IFLOW)) 3556 outb(com->modem_ctl_port, com->mcr_image &= ~MCR_RTS); 3557 } 3558#else 3559 if (com->mcr_image & MCR_RTS && com->state & CS_RTS_IFLOW) 3560 outb(com->modem_ctl_port, com->mcr_image &= ~MCR_RTS); 3561#endif 3562 } else { 3563#ifdef PC98 3564 if (IS_8251(com->pc98_if_type)) { 3565 if (!(com_tiocm_get(com) & TIOCM_RTS) && 3566 com->iptr < com->ihighwater && 3567 com->state & CS_RTS_IFLOW) 3568 com_tiocm_bis(com, TIOCM_RTS); 3569 } else { 3570 if (!(com->mcr_image & MCR_RTS) && 3571 com->iptr < com->ihighwater && 3572 com->state & CS_RTS_IFLOW) 3573 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS); 3574 } 3575#else 3576 if (!(com->mcr_image & MCR_RTS) && com->iptr < com->ihighwater 3577 && com->state & CS_RTS_IFLOW) 3578 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS); 3579#endif 3580 } 3581 mtx_unlock_spin(&sio_lock); 3582 if (tp->t_state & (TS_TIMEOUT | TS_TTSTOP)) { 3583 ttwwakeup(tp); 3584 splx(s); 3585 return; 3586 } 3587 if (tp->t_outq.c_cc != 0) { 3588 struct lbq *qp; 3589 struct lbq *next; 3590 3591 if (!com->obufs[0].l_queued) { 3592 com->obufs[0].l_tail 3593 = com->obuf1 + q_to_b(&tp->t_outq, com->obuf1, 3594#ifdef PC98 3595 com->obufsize); 3596#else 3597 sizeof com->obuf1); 3598#endif 3599 com->obufs[0].l_next = NULL; 3600 com->obufs[0].l_queued = TRUE; 3601 mtx_lock_spin(&sio_lock); 3602 if (com->state & CS_BUSY) { 3603 qp = com->obufq.l_next; 3604 while ((next = qp->l_next) != NULL) 3605 qp = next; 3606 qp->l_next = &com->obufs[0]; 3607 } else { 3608 com->obufq.l_head = com->obufs[0].l_head; 3609 com->obufq.l_tail = com->obufs[0].l_tail; 3610 com->obufq.l_next = &com->obufs[0]; 3611 com->state |= CS_BUSY; 3612 } 3613 mtx_unlock_spin(&sio_lock); 3614 } 3615 if (tp->t_outq.c_cc != 0 && !com->obufs[1].l_queued) { 3616 com->obufs[1].l_tail 3617 = com->obuf2 + q_to_b(&tp->t_outq, com->obuf2, 3618#ifdef PC98 3619 com->obufsize); 3620#else 3621 sizeof com->obuf2); 3622#endif 3623 com->obufs[1].l_next = NULL; 3624 com->obufs[1].l_queued = TRUE; 3625 mtx_lock_spin(&sio_lock); 3626 if (com->state & CS_BUSY) { 3627 qp = com->obufq.l_next; 3628 while ((next = qp->l_next) != NULL) 3629 qp = next; 3630 qp->l_next = &com->obufs[1]; 3631 } else { 3632 com->obufq.l_head = com->obufs[1].l_head; 3633 com->obufq.l_tail = com->obufs[1].l_tail; 3634 com->obufq.l_next = &com->obufs[1]; 3635 com->state |= CS_BUSY; 3636 } 3637 mtx_unlock_spin(&sio_lock); 3638 } 3639 tp->t_state |= TS_BUSY; 3640 } 3641 mtx_lock_spin(&sio_lock); 3642 if (com->state >= (CS_BUSY | CS_TTGO)) 3643 siointr1(com); /* fake interrupt to start output */ 3644 mtx_unlock_spin(&sio_lock); 3645 ttwwakeup(tp); 3646 splx(s); 3647} 3648 3649static void 3650comstop(tp, rw) 3651 struct tty *tp; 3652 int rw; 3653{ 3654 struct com_s *com; 3655#ifdef PC98 3656 int rsa98_tmp = 0; 3657#endif 3658 3659 com = com_addr(DEV_TO_UNIT(tp->t_dev)); 3660 if (com == NULL || com->gone) 3661 return; 3662 mtx_lock_spin(&sio_lock); 3663 if (rw & FWRITE) { 3664#ifdef PC98 3665 if (!IS_8251(com->pc98_if_type)) { 3666#endif 3667 if (com->hasfifo) 3668#ifdef COM_ESP 3669 /* XXX avoid h/w bug. */ 3670 if (!com->esp) 3671#endif 3672 sio_setreg(com, com_fifo, 3673 FIFO_XMT_RST | com->fifo_image); 3674#ifdef PC98 3675 if (com->pc98_if_type == COM_IF_RSA98III) 3676 for (rsa98_tmp = 0; rsa98_tmp < 2048; rsa98_tmp++) 3677 sio_setreg(com, com_fifo, 3678 FIFO_XMT_RST | com->fifo_image); 3679 } 3680#endif 3681 com->obufs[0].l_queued = FALSE; 3682 com->obufs[1].l_queued = FALSE; 3683 if (com->state & CS_ODONE) 3684 com_events -= LOTS_OF_EVENTS; 3685 com->state &= ~(CS_ODONE | CS_BUSY); 3686 com->tp->t_state &= ~TS_BUSY; 3687 } 3688 if (rw & FREAD) { 3689#ifdef PC98 3690 if (!IS_8251(com->pc98_if_type)) { 3691 if (com->pc98_if_type == COM_IF_RSA98III) 3692 for (rsa98_tmp = 0; rsa98_tmp < 2048; rsa98_tmp++) 3693 sio_getreg(com, com_data); 3694#endif 3695 if (com->hasfifo) 3696#ifdef COM_ESP 3697 /* XXX avoid h/w bug. */ 3698 if (!com->esp) 3699#endif 3700 sio_setreg(com, com_fifo, 3701 FIFO_RCV_RST | com->fifo_image); 3702#ifdef PC98 3703 } 3704#endif 3705 com_events -= (com->iptr - com->ibuf); 3706 com->iptr = com->ibuf; 3707 } 3708 mtx_unlock_spin(&sio_lock); 3709 comstart(tp); 3710} 3711 3712static int 3713commctl(com, bits, how) 3714 struct com_s *com; 3715 int bits; 3716 int how; 3717{ 3718 int mcr; 3719 int msr; 3720 3721 if (how == DMGET) { 3722 bits = TIOCM_LE; /* XXX - always enabled while open */ 3723 mcr = com->mcr_image; 3724 if (mcr & MCR_DTR) 3725 bits |= TIOCM_DTR; 3726 if (mcr & MCR_RTS) 3727 bits |= TIOCM_RTS; 3728 msr = com->prev_modem_status; 3729 if (msr & MSR_CTS) 3730 bits |= TIOCM_CTS; 3731 if (msr & MSR_DCD) 3732 bits |= TIOCM_CD; 3733 if (msr & MSR_DSR) 3734 bits |= TIOCM_DSR; 3735 /* 3736 * XXX - MSR_RI is naturally volatile, and we make MSR_TERI 3737 * more volatile by reading the modem status a lot. Perhaps 3738 * we should latch both bits until the status is read here. 3739 */ 3740 if (msr & (MSR_RI | MSR_TERI)) 3741 bits |= TIOCM_RI; 3742 return (bits); 3743 } 3744 mcr = 0; 3745 if (bits & TIOCM_DTR) 3746 mcr |= MCR_DTR; 3747 if (bits & TIOCM_RTS) 3748 mcr |= MCR_RTS; 3749 if (com->gone) 3750 return(0); 3751 mtx_lock_spin(&sio_lock); 3752 switch (how) { 3753 case DMSET: 3754 outb(com->modem_ctl_port, 3755 com->mcr_image = mcr | (com->mcr_image & MCR_IENABLE)); 3756 break; 3757 case DMBIS: 3758 outb(com->modem_ctl_port, com->mcr_image |= mcr); 3759 break; 3760 case DMBIC: 3761 outb(com->modem_ctl_port, com->mcr_image &= ~mcr); 3762 break; 3763 } 3764 mtx_unlock_spin(&sio_lock); 3765 return (0); 3766} 3767 3768static void 3769siosettimeout() 3770{ 3771 struct com_s *com; 3772 bool_t someopen; 3773 int unit; 3774 3775 /* 3776 * Set our timeout period to 1 second if no polled devices are open. 3777 * Otherwise set it to max(1/200, 1/hz). 3778 * Enable timeouts iff some device is open. 3779 */ 3780 untimeout(comwakeup, (void *)NULL, sio_timeout_handle); 3781 sio_timeout = hz; 3782 someopen = FALSE; 3783 for (unit = 0; unit < sio_numunits; ++unit) { 3784 com = com_addr(unit); 3785 if (com != NULL && com->tp != NULL 3786 && com->tp->t_state & TS_ISOPEN && !com->gone) { 3787 someopen = TRUE; 3788 if (com->poll || com->poll_output) { 3789 sio_timeout = hz > 200 ? hz / 200 : 1; 3790 break; 3791 } 3792 } 3793 } 3794 if (someopen) { 3795 sio_timeouts_until_log = hz / sio_timeout; 3796 sio_timeout_handle = timeout(comwakeup, (void *)NULL, 3797 sio_timeout); 3798 } else { 3799 /* Flush error messages, if any. */ 3800 sio_timeouts_until_log = 1; 3801 comwakeup((void *)NULL); 3802 untimeout(comwakeup, (void *)NULL, sio_timeout_handle); 3803 } 3804} 3805 3806static void 3807comwakeup(chan) 3808 void *chan; 3809{ 3810 struct com_s *com; 3811 int unit; 3812 3813 sio_timeout_handle = timeout(comwakeup, (void *)NULL, sio_timeout); 3814 3815 /* 3816 * Recover from lost output interrupts. 3817 * Poll any lines that don't use interrupts. 3818 */ 3819 for (unit = 0; unit < sio_numunits; ++unit) { 3820 com = com_addr(unit); 3821 if (com != NULL && !com->gone 3822 && (com->state >= (CS_BUSY | CS_TTGO) || com->poll)) { 3823 mtx_lock_spin(&sio_lock); 3824 siointr1(com); 3825 mtx_unlock_spin(&sio_lock); 3826 } 3827 } 3828 3829 /* 3830 * Check for and log errors, but not too often. 3831 */ 3832 if (--sio_timeouts_until_log > 0) 3833 return; 3834 sio_timeouts_until_log = hz / sio_timeout; 3835 for (unit = 0; unit < sio_numunits; ++unit) { 3836 int errnum; 3837 3838 com = com_addr(unit); 3839 if (com == NULL) 3840 continue; 3841 if (com->gone) 3842 continue; 3843 for (errnum = 0; errnum < CE_NTYPES; ++errnum) { 3844 u_int delta; 3845 u_long total; 3846 3847 mtx_lock_spin(&sio_lock); 3848 delta = com->delta_error_counts[errnum]; 3849 com->delta_error_counts[errnum] = 0; 3850 mtx_unlock_spin(&sio_lock); 3851 if (delta == 0) 3852 continue; 3853 total = com->error_counts[errnum] += delta; 3854 log(LOG_ERR, "sio%d: %u more %s%s (total %lu)\n", 3855 unit, delta, error_desc[errnum], 3856 delta == 1 ? "" : "s", total); 3857 } 3858 } 3859} 3860 3861#ifdef PC98 3862/* commint is called when modem control line changes */ 3863static void 3864commint(dev_t dev) 3865{ 3866 register struct tty *tp; 3867 int stat,delta; 3868 struct com_s *com; 3869 int mynor,unit; 3870 3871 mynor = minor(dev); 3872 unit = MINOR_TO_UNIT(mynor); 3873 com = com_addr(unit); 3874 tp = com->tp; 3875 3876 stat = com_tiocm_get(com); 3877 delta = com_tiocm_get_delta(com); 3878 3879 if (com->state & CS_CTS_OFLOW) { 3880 if (stat & TIOCM_CTS) 3881 com->state |= CS_ODEVREADY; 3882 else 3883 com->state &= ~CS_ODEVREADY; 3884 } 3885 if ((delta & TIOCM_CAR) && (mynor & CALLOUT_MASK) == 0) { 3886 if (stat & TIOCM_CAR ) 3887 (void)ttyld_modem(tp, 1); 3888 else if (ttyld_modem(tp, 0) == 0) { 3889 /* negate DTR, RTS */ 3890 com_tiocm_bic(com, (tp->t_cflag & HUPCL) ? 3891 TIOCM_DTR|TIOCM_RTS|TIOCM_LE : TIOCM_LE ); 3892 /* disable IENABLE */ 3893 com_int_TxRx_disable( com ); 3894 } 3895 } 3896} 3897#endif 3898 3899/* 3900 * Following are all routines needed for SIO to act as console 3901 */ 3902struct siocnstate { 3903 u_char dlbl; 3904 u_char dlbh; 3905 u_char ier; 3906 u_char cfcr; 3907 u_char mcr; 3908}; 3909 3910/* 3911 * This is a function in order to not replicate "ttyd%d" more 3912 * places than absolutely necessary. 3913 */ 3914static void 3915siocnset(struct consdev *cd, int unit) 3916{ 3917 3918 cd->cn_unit = unit; 3919 sprintf(cd->cn_name, "ttyd%d", unit); 3920} 3921 3922#ifndef __alpha__ 3923static speed_t siocngetspeed(Port_t, u_long rclk); 3924#endif 3925static void siocnclose(struct siocnstate *sp, Port_t iobase); 3926static void siocnopen(struct siocnstate *sp, Port_t iobase, int speed); 3927static void siocntxwait(Port_t iobase); 3928 3929#ifdef __alpha__ 3930int siocnattach(int port, int speed); 3931int siogdbattach(int port, int speed); 3932int siogdbgetc(void); 3933void siogdbputc(int c); 3934#else 3935static cn_probe_t siocnprobe; 3936static cn_init_t siocninit; 3937static cn_term_t siocnterm; 3938#endif 3939static cn_checkc_t siocncheckc; 3940static cn_getc_t siocngetc; 3941static cn_putc_t siocnputc; 3942 3943#ifndef __alpha__ 3944CONS_DRIVER(sio, siocnprobe, siocninit, siocnterm, siocngetc, siocncheckc, 3945 siocnputc, NULL); 3946#endif 3947 3948#if DDB > 0 3949static struct consdev gdbconsdev; 3950#endif 3951 3952static void 3953siocntxwait(iobase) 3954 Port_t iobase; 3955{ 3956 int timo; 3957 3958 /* 3959 * Wait for any pending transmission to finish. Required to avoid 3960 * the UART lockup bug when the speed is changed, and for normal 3961 * transmits. 3962 */ 3963 timo = 100000; 3964 while ((inb(iobase + com_lsr) & (LSR_TSRE | LSR_TXRDY)) 3965 != (LSR_TSRE | LSR_TXRDY) && --timo != 0) 3966 ; 3967} 3968 3969#ifndef __alpha__ 3970 3971/* 3972 * Read the serial port specified and try to figure out what speed 3973 * it's currently running at. We're assuming the serial port has 3974 * been initialized and is basicly idle. This routine is only intended 3975 * to be run at system startup. 3976 * 3977 * If the value read from the serial port doesn't make sense, return 0. 3978 */ 3979 3980static speed_t 3981siocngetspeed(iobase, rclk) 3982 Port_t iobase; 3983 u_long rclk; 3984{ 3985 u_int divisor; 3986 u_char dlbh; 3987 u_char dlbl; 3988 u_char cfcr; 3989 3990 cfcr = inb(iobase + com_cfcr); 3991 outb(iobase + com_cfcr, CFCR_DLAB | cfcr); 3992 3993 dlbl = inb(iobase + com_dlbl); 3994 dlbh = inb(iobase + com_dlbh); 3995 3996 outb(iobase + com_cfcr, cfcr); 3997 3998 divisor = dlbh << 8 | dlbl; 3999 4000 /* XXX there should be more sanity checking. */ 4001 if (divisor == 0) 4002 return (CONSPEED); 4003 return (rclk / (16UL * divisor)); 4004} 4005 4006#endif 4007 4008static void 4009siocnopen(sp, iobase, speed) 4010 struct siocnstate *sp; 4011 Port_t iobase; 4012 int speed; 4013{ 4014 u_int divisor; 4015 u_char dlbh; 4016 u_char dlbl; 4017 4018 /* 4019 * Save all the device control registers except the fifo register 4020 * and set our default ones (cs8 -parenb speed=comdefaultrate). 4021 * We can't save the fifo register since it is read-only. 4022 */ 4023 sp->ier = inb(iobase + com_ier); 4024 outb(iobase + com_ier, 0); /* spltty() doesn't stop siointr() */ 4025 siocntxwait(iobase); 4026 sp->cfcr = inb(iobase + com_cfcr); 4027 outb(iobase + com_cfcr, CFCR_DLAB | CFCR_8BITS); 4028 sp->dlbl = inb(iobase + com_dlbl); 4029 sp->dlbh = inb(iobase + com_dlbh); 4030 /* 4031 * Only set the divisor registers if they would change, since on 4032 * some 16550 incompatibles (Startech), setting them clears the 4033 * data input register. This also reduces the effects of the 4034 * UMC8669F bug. 4035 */ 4036 divisor = siodivisor(comdefaultrclk, speed); 4037 dlbl = divisor & 0xFF; 4038 if (sp->dlbl != dlbl) 4039 outb(iobase + com_dlbl, dlbl); 4040 dlbh = divisor >> 8; 4041 if (sp->dlbh != dlbh) 4042 outb(iobase + com_dlbh, dlbh); 4043 outb(iobase + com_cfcr, CFCR_8BITS); 4044 sp->mcr = inb(iobase + com_mcr); 4045 /* 4046 * We don't want interrupts, but must be careful not to "disable" 4047 * them by clearing the MCR_IENABLE bit, since that might cause 4048 * an interrupt by floating the IRQ line. 4049 */ 4050 outb(iobase + com_mcr, (sp->mcr & MCR_IENABLE) | MCR_DTR | MCR_RTS); 4051} 4052 4053static void 4054siocnclose(sp, iobase) 4055 struct siocnstate *sp; 4056 Port_t iobase; 4057{ 4058 /* 4059 * Restore the device control registers. 4060 */ 4061 siocntxwait(iobase); 4062 outb(iobase + com_cfcr, CFCR_DLAB | CFCR_8BITS); 4063 if (sp->dlbl != inb(iobase + com_dlbl)) 4064 outb(iobase + com_dlbl, sp->dlbl); 4065 if (sp->dlbh != inb(iobase + com_dlbh)) 4066 outb(iobase + com_dlbh, sp->dlbh); 4067 outb(iobase + com_cfcr, sp->cfcr); 4068 /* 4069 * XXX damp oscillations of MCR_DTR and MCR_RTS by not restoring them. 4070 */ 4071 outb(iobase + com_mcr, sp->mcr | MCR_DTR | MCR_RTS); 4072 outb(iobase + com_ier, sp->ier); 4073} 4074 4075#ifndef __alpha__ 4076 4077static void 4078siocnprobe(cp) 4079 struct consdev *cp; 4080{ 4081 speed_t boot_speed; 4082 u_char cfcr; 4083 u_int divisor; 4084 int s, unit; 4085 struct siocnstate sp; 4086 4087 /* 4088 * Find our first enabled console, if any. If it is a high-level 4089 * console device, then initialize it and return successfully. 4090 * If it is a low-level console device, then initialize it and 4091 * return unsuccessfully. It must be initialized in both cases 4092 * for early use by console drivers and debuggers. Initializing 4093 * the hardware is not necessary in all cases, since the i/o 4094 * routines initialize it on the fly, but it is necessary if 4095 * input might arrive while the hardware is switched back to an 4096 * uninitialized state. We can't handle multiple console devices 4097 * yet because our low-level routines don't take a device arg. 4098 * We trust the user to set the console flags properly so that we 4099 * don't need to probe. 4100 */ 4101 cp->cn_pri = CN_DEAD; 4102 4103 for (unit = 0; unit < 16; unit++) { /* XXX need to know how many */ 4104 int flags; 4105 4106 if (resource_disabled("sio", unit)) 4107 continue; 4108 if (resource_int_value("sio", unit, "flags", &flags)) 4109 continue; 4110 if (COM_CONSOLE(flags) || COM_DEBUGGER(flags)) { 4111 int port; 4112 Port_t iobase; 4113 4114 if (resource_int_value("sio", unit, "port", &port)) 4115 continue; 4116 iobase = port; 4117 s = spltty(); 4118 if (boothowto & RB_SERIAL) { 4119 boot_speed = 4120 siocngetspeed(iobase, comdefaultrclk); 4121 if (boot_speed) 4122 comdefaultrate = boot_speed; 4123 } 4124 4125 /* 4126 * Initialize the divisor latch. We can't rely on 4127 * siocnopen() to do this the first time, since it 4128 * avoids writing to the latch if the latch appears 4129 * to have the correct value. Also, if we didn't 4130 * just read the speed from the hardware, then we 4131 * need to set the speed in hardware so that 4132 * switching it later is null. 4133 */ 4134 cfcr = inb(iobase + com_cfcr); 4135 outb(iobase + com_cfcr, CFCR_DLAB | cfcr); 4136 divisor = siodivisor(comdefaultrclk, comdefaultrate); 4137 outb(iobase + com_dlbl, divisor & 0xff); 4138 outb(iobase + com_dlbh, divisor >> 8); 4139 outb(iobase + com_cfcr, cfcr); 4140 4141 siocnopen(&sp, iobase, comdefaultrate); 4142 4143 splx(s); 4144 if (COM_CONSOLE(flags) && !COM_LLCONSOLE(flags)) { 4145 siocnset(cp, unit); 4146 cp->cn_pri = COM_FORCECONSOLE(flags) 4147 || boothowto & RB_SERIAL 4148 ? CN_REMOTE : CN_NORMAL; 4149 siocniobase = iobase; 4150 siocnunit = unit; 4151 } 4152 if (COM_DEBUGGER(flags)) { 4153 printf("sio%d: gdb debugging port\n", unit); 4154 siogdbiobase = iobase; 4155 siogdbunit = unit; 4156#if DDB > 0 4157 siocnset(&gdbconsdev, unit); 4158 gdb_arg = &gdbconsdev; 4159 gdb_getc = siocngetc; 4160 gdb_putc = siocnputc; 4161#endif 4162 } 4163 } 4164 } 4165#ifdef __i386__ 4166#if DDB > 0 4167 /* 4168 * XXX Ugly Compatability. 4169 * If no gdb port has been specified, set it to be the console 4170 * as some configuration files don't specify the gdb port. 4171 */ 4172 if (gdb_arg == NULL && (boothowto & RB_GDB)) { 4173 printf("Warning: no GDB port specified. Defaulting to sio%d.\n", 4174 siocnunit); 4175 printf("Set flag 0x80 on desired GDB port in your\n"); 4176 printf("configuration file (currently sio only).\n"); 4177 siogdbiobase = siocniobase; 4178 siogdbunit = siocnunit; 4179 siocnset(&gdbconsdev, siocnunit); 4180 gdb_arg = &gdbconsdev; 4181 gdb_getc = siocngetc; 4182 gdb_putc = siocnputc; 4183 } 4184#endif 4185#endif 4186} 4187 4188static void 4189siocninit(cp) 4190 struct consdev *cp; 4191{ 4192 comconsole = cp->cn_unit; 4193} 4194 4195static void 4196siocnterm(cp) 4197 struct consdev *cp; 4198{ 4199 comconsole = -1; 4200} 4201 4202#endif 4203 4204#ifdef __alpha__ 4205 4206CONS_DRIVER(sio, NULL, NULL, NULL, siocngetc, siocncheckc, siocnputc, NULL); 4207 4208int 4209siocnattach(port, speed) 4210 int port; 4211 int speed; 4212{ 4213 int s; 4214 u_char cfcr; 4215 u_int divisor; 4216 struct siocnstate sp; 4217 int unit = 0; /* XXX random value! */ 4218 4219 siocniobase = port; 4220 siocnunit = unit; 4221 comdefaultrate = speed; 4222 sio_consdev.cn_pri = CN_NORMAL; 4223 siocnset(&sio_consdev, unit); 4224 4225 s = spltty(); 4226 4227 /* 4228 * Initialize the divisor latch. We can't rely on 4229 * siocnopen() to do this the first time, since it 4230 * avoids writing to the latch if the latch appears 4231 * to have the correct value. Also, if we didn't 4232 * just read the speed from the hardware, then we 4233 * need to set the speed in hardware so that 4234 * switching it later is null. 4235 */ 4236 cfcr = inb(siocniobase + com_cfcr); 4237 outb(siocniobase + com_cfcr, CFCR_DLAB | cfcr); 4238 divisor = siodivisor(comdefaultrclk, comdefaultrate); 4239 outb(siocniobase + com_dlbl, divisor & 0xff); 4240 outb(siocniobase + com_dlbh, divisor >> 8); 4241 outb(siocniobase + com_cfcr, cfcr); 4242 4243 siocnopen(&sp, siocniobase, comdefaultrate); 4244 splx(s); 4245 4246 cnadd(&sio_consdev); 4247 return (0); 4248} 4249 4250int 4251siogdbattach(port, speed) 4252 int port; 4253 int speed; 4254{ 4255 int s; 4256 u_char cfcr; 4257 u_int divisor; 4258 struct siocnstate sp; 4259 int unit = 1; /* XXX random value! */ 4260 4261 siogdbiobase = port; 4262 gdbdefaultrate = speed; 4263 4264 printf("sio%d: gdb debugging port\n", unit); 4265 siogdbunit = unit; 4266#if DDB > 0 4267 siocnset(&gdbconsdev, unit); 4268 gdb_arg = &gdbconsdev; 4269 gdb_getc = siocngetc; 4270 gdb_putc = siocnputc; 4271#endif 4272 4273 s = spltty(); 4274 4275 /* 4276 * Initialize the divisor latch. We can't rely on 4277 * siocnopen() to do this the first time, since it 4278 * avoids writing to the latch if the latch appears 4279 * to have the correct value. Also, if we didn't 4280 * just read the speed from the hardware, then we 4281 * need to set the speed in hardware so that 4282 * switching it later is null. 4283 */ 4284 cfcr = inb(siogdbiobase + com_cfcr); 4285 outb(siogdbiobase + com_cfcr, CFCR_DLAB | cfcr); 4286 divisor = siodivisor(comdefaultrclk, gdbdefaultrate); 4287 outb(siogdbiobase + com_dlbl, divisor & 0xff); 4288 outb(siogdbiobase + com_dlbh, divisor >> 8); 4289 outb(siogdbiobase + com_cfcr, cfcr); 4290 4291 siocnopen(&sp, siogdbiobase, gdbdefaultrate); 4292 splx(s); 4293 4294 return (0); 4295} 4296 4297#endif 4298 4299static int 4300siocncheckc(struct consdev *cd) 4301{ 4302 int c; 4303 Port_t iobase; 4304 int s; 4305 struct siocnstate sp; 4306 speed_t speed; 4307 4308 if (cd->cn_unit == siocnunit) { 4309 iobase = siocniobase; 4310 speed = comdefaultrate; 4311 } else { 4312 iobase = siogdbiobase; 4313 speed = gdbdefaultrate; 4314 } 4315 s = spltty(); 4316 siocnopen(&sp, iobase, speed); 4317 if (inb(iobase + com_lsr) & LSR_RXRDY) 4318 c = inb(iobase + com_data); 4319 else 4320 c = -1; 4321 siocnclose(&sp, iobase); 4322 splx(s); 4323 return (c); 4324} 4325 4326static int 4327siocngetc(struct consdev *cd) 4328{ 4329 int c; 4330 Port_t iobase; 4331 int s; 4332 struct siocnstate sp; 4333 speed_t speed; 4334 4335 if (cd->cn_unit == siocnunit) { 4336 iobase = siocniobase; 4337 speed = comdefaultrate; 4338 } else { 4339 iobase = siogdbiobase; 4340 speed = gdbdefaultrate; 4341 } 4342 s = spltty(); 4343 siocnopen(&sp, iobase, speed); 4344 while (!(inb(iobase + com_lsr) & LSR_RXRDY)) 4345 ; 4346 c = inb(iobase + com_data); 4347 siocnclose(&sp, iobase); 4348 splx(s); 4349 return (c); 4350} 4351 4352static void 4353siocnputc(struct consdev *cd, int c) 4354{ 4355 int need_unlock; 4356 int s; 4357 struct siocnstate sp; 4358 Port_t iobase; 4359 speed_t speed; 4360 4361 if (cd->cn_unit == siocnunit) { 4362 iobase = siocniobase; 4363 speed = comdefaultrate; 4364 } else { 4365 iobase = siogdbiobase; 4366 speed = gdbdefaultrate; 4367 } 4368 s = spltty(); 4369 need_unlock = 0; 4370 if (sio_inited == 2 && !mtx_owned(&sio_lock)) { 4371 mtx_lock_spin(&sio_lock); 4372 need_unlock = 1; 4373 } 4374 siocnopen(&sp, iobase, speed); 4375 siocntxwait(iobase); 4376 outb(iobase + com_data, c); 4377 siocnclose(&sp, iobase); 4378 if (need_unlock) 4379 mtx_unlock_spin(&sio_lock); 4380 splx(s); 4381} 4382 4383#ifdef __alpha__ 4384int 4385siogdbgetc() 4386{ 4387 int c; 4388 Port_t iobase; 4389 speed_t speed; 4390 int s; 4391 struct siocnstate sp; 4392 4393 if (siogdbunit == siocnunit) { 4394 iobase = siocniobase; 4395 speed = comdefaultrate; 4396 } else { 4397 iobase = siogdbiobase; 4398 speed = gdbdefaultrate; 4399 } 4400 4401 s = spltty(); 4402 siocnopen(&sp, iobase, speed); 4403 while (!(inb(iobase + com_lsr) & LSR_RXRDY)) 4404 ; 4405 c = inb(iobase + com_data); 4406 siocnclose(&sp, iobase); 4407 splx(s); 4408 return (c); 4409} 4410 4411void 4412siogdbputc(c) 4413 int c; 4414{ 4415 Port_t iobase; 4416 speed_t speed; 4417 int s; 4418 struct siocnstate sp; 4419 4420 if (siogdbunit == siocnunit) { 4421 iobase = siocniobase; 4422 speed = comdefaultrate; 4423 } else { 4424 iobase = siogdbiobase; 4425 speed = gdbdefaultrate; 4426 } 4427 4428 s = spltty(); 4429 siocnopen(&sp, iobase, speed); 4430 siocntxwait(siogdbiobase); 4431 outb(siogdbiobase + com_data, c); 4432 siocnclose(&sp, siogdbiobase); 4433 splx(s); 4434} 4435#endif 4436 4437#ifdef PC98 4438/* 4439 * pc98 local function 4440 */ 4441 4442static void 4443com_tiocm_set(struct com_s *com, int msr) 4444{ 4445 int s; 4446 int tmp = 0; 4447 int mask = CMD8251_TxEN|CMD8251_RxEN|CMD8251_DTR|CMD8251_RTS; 4448 4449 s=spltty(); 4450 com->pc98_prev_modem_status = ( msr & (TIOCM_LE|TIOCM_DTR|TIOCM_RTS) ) 4451 | ( com->pc98_prev_modem_status & ~(TIOCM_LE|TIOCM_DTR|TIOCM_RTS) ); 4452 tmp |= (CMD8251_TxEN|CMD8251_RxEN); 4453 if ( msr & TIOCM_DTR ) tmp |= CMD8251_DTR; 4454 if ( msr & TIOCM_RTS ) tmp |= CMD8251_RTS; 4455 pc98_i8251_clear_or_cmd( com, mask, tmp ); 4456 splx(s); 4457} 4458 4459static void 4460com_tiocm_bis(struct com_s *com, int msr) 4461{ 4462 int s; 4463 int tmp = 0; 4464 4465 s=spltty(); 4466 com->pc98_prev_modem_status |= ( msr & (TIOCM_LE|TIOCM_DTR|TIOCM_RTS) ); 4467 tmp |= CMD8251_TxEN|CMD8251_RxEN; 4468 if ( msr & TIOCM_DTR ) tmp |= CMD8251_DTR; 4469 if ( msr & TIOCM_RTS ) tmp |= CMD8251_RTS; 4470 4471 pc98_i8251_or_cmd( com, tmp ); 4472 splx(s); 4473} 4474 4475static void 4476com_tiocm_bic(struct com_s *com, int msr) 4477{ 4478 int s; 4479 int tmp = msr; 4480 4481 s=spltty(); 4482 com->pc98_prev_modem_status &= ~( msr & (TIOCM_LE|TIOCM_DTR|TIOCM_RTS) ); 4483 if ( msr & TIOCM_DTR ) tmp |= CMD8251_DTR; 4484 if ( msr & TIOCM_RTS ) tmp |= CMD8251_RTS; 4485 4486 pc98_i8251_clear_cmd( com, tmp ); 4487 splx(s); 4488} 4489 4490static int 4491com_tiocm_get(struct com_s *com) 4492{ 4493 return( com->pc98_prev_modem_status ); 4494} 4495 4496static int 4497com_tiocm_get_delta(struct com_s *com) 4498{ 4499 int tmp; 4500 4501 tmp = com->pc98_modem_delta; 4502 com->pc98_modem_delta = 0; 4503 return( tmp ); 4504} 4505 4506/* convert to TIOCM_?? ( ioctl.h ) */ 4507static int 4508pc98_get_modem_status(struct com_s *com) 4509{ 4510 register int msr; 4511 4512 msr = com->pc98_prev_modem_status 4513 & ~(TIOCM_CAR|TIOCM_RI|TIOCM_DSR|TIOCM_CTS); 4514 if (com->pc98_8251fifo_enable) { 4515 int stat2; 4516 4517 stat2 = inb(I8251F_msr); 4518 if ( stat2 & CICSCDF_CD ) msr |= TIOCM_CAR; 4519 if ( stat2 & CICSCDF_CI ) msr |= TIOCM_RI; 4520 if ( stat2 & CICSCDF_DR ) msr |= TIOCM_DSR; 4521 if ( stat2 & CICSCDF_CS ) msr |= TIOCM_CTS; 4522#if COM_CARRIER_DETECT_EMULATE 4523 if ( msr & (TIOCM_DSR|TIOCM_CTS) ) { 4524 msr |= TIOCM_CAR; 4525 } 4526#endif 4527 } else { 4528 int stat, stat2; 4529 4530 stat = inb(com->sts_port); 4531 stat2 = inb(com->in_modem_port); 4532 if ( !(stat2 & CICSCD_CD) ) msr |= TIOCM_CAR; 4533 if ( !(stat2 & CICSCD_CI) ) msr |= TIOCM_RI; 4534 if ( stat & STS8251_DSR ) msr |= TIOCM_DSR; 4535 if ( !(stat2 & CICSCD_CS) ) msr |= TIOCM_CTS; 4536#if COM_CARRIER_DETECT_EMULATE 4537 if ( msr & (TIOCM_DSR|TIOCM_CTS) ) { 4538 msr |= TIOCM_CAR; 4539 } 4540#endif 4541 } 4542 return(msr); 4543} 4544 4545static void 4546pc98_check_msr(void* chan) 4547{ 4548 int msr, delta; 4549 int s; 4550 register struct tty *tp; 4551 struct com_s *com; 4552 int mynor; 4553 int unit; 4554 dev_t dev; 4555 4556 dev=(dev_t)chan; 4557 mynor = minor(dev); 4558 unit = MINOR_TO_UNIT(mynor); 4559 com = com_addr(unit); 4560 tp = com->tp; 4561 4562 s = spltty(); 4563 msr = pc98_get_modem_status(com); 4564 /* make change flag */ 4565 delta = msr ^ com->pc98_prev_modem_status; 4566 if ( delta & TIOCM_CAR ) { 4567 if ( com->modem_car_chg_timer ) { 4568 if ( -- com->modem_car_chg_timer ) 4569 msr ^= TIOCM_CAR; 4570 } else { 4571 if ((com->modem_car_chg_timer = (msr & TIOCM_CAR) ? 4572 DCD_ON_RECOGNITION : DCD_OFF_TOLERANCE) != 0) 4573 msr ^= TIOCM_CAR; 4574 } 4575 } else 4576 com->modem_car_chg_timer = 0; 4577 delta = ( msr ^ com->pc98_prev_modem_status ) & 4578 (TIOCM_CAR|TIOCM_RI|TIOCM_DSR|TIOCM_CTS); 4579 com->pc98_prev_modem_status = msr; 4580 delta = ( com->pc98_modem_delta |= delta ); 4581 splx(s); 4582 if ( com->modem_checking || (tp->t_state & (TS_ISOPEN)) ) { 4583 if ( delta ) { 4584 commint(dev); 4585 } 4586 timeout(pc98_check_msr, (caddr_t)dev, 4587 PC98_CHECK_MODEM_INTERVAL); 4588 } else { 4589 com->modem_checking = 0; 4590 } 4591} 4592 4593static void 4594pc98_msrint_start(dev_t dev) 4595{ 4596 struct com_s *com; 4597 int mynor; 4598 int unit; 4599 int s = spltty(); 4600 4601 mynor = minor(dev); 4602 unit = MINOR_TO_UNIT(mynor); 4603 com = com_addr(unit); 4604 /* modem control line check routine envoke interval is 1/10 sec */ 4605 if ( com->modem_checking == 0 ) { 4606 com->pc98_prev_modem_status = pc98_get_modem_status(com); 4607 com->pc98_modem_delta = 0; 4608 timeout(pc98_check_msr, (caddr_t)dev, 4609 PC98_CHECK_MODEM_INTERVAL); 4610 com->modem_checking = 1; 4611 } 4612 splx(s); 4613} 4614 4615static void 4616pc98_disable_i8251_interrupt(struct com_s *com, int mod) 4617{ 4618 /* disable interrupt */ 4619 register int tmp; 4620 4621 mod |= ~(IEN_Tx|IEN_TxEMP|IEN_Rx); 4622 COM_INT_DISABLE 4623 tmp = inb( com->intr_ctrl_port ) & ~(IEN_Tx|IEN_TxEMP|IEN_Rx); 4624 outb( com->intr_ctrl_port, (com->intr_enable&=~mod) | tmp ); 4625 COM_INT_ENABLE 4626} 4627 4628static void 4629pc98_enable_i8251_interrupt(struct com_s *com, int mod) 4630{ 4631 register int tmp; 4632 4633 COM_INT_DISABLE 4634 tmp = inb( com->intr_ctrl_port ) & ~(IEN_Tx|IEN_TxEMP|IEN_Rx); 4635 outb( com->intr_ctrl_port, (com->intr_enable|=mod) | tmp ); 4636 COM_INT_ENABLE 4637} 4638 4639static int 4640pc98_check_i8251_interrupt(struct com_s *com) 4641{ 4642 return ( com->intr_enable & 0x07 ); 4643} 4644 4645static void 4646pc98_i8251_clear_cmd(struct com_s *com, int x) 4647{ 4648 int tmp; 4649 4650 COM_INT_DISABLE 4651 tmp = com->pc98_prev_siocmd & ~(x); 4652 if (com->pc98_8251fifo_enable) 4653 outb(I8251F_fcr, 0); 4654 outb(com->cmd_port, tmp); 4655 com->pc98_prev_siocmd = tmp & ~(CMD8251_ER|CMD8251_RESET|CMD8251_EH); 4656 if (com->pc98_8251fifo_enable) 4657 outb(I8251F_fcr, CTRL8251F_ENABLE); 4658 COM_INT_ENABLE 4659} 4660 4661static void 4662pc98_i8251_or_cmd(struct com_s *com, int x) 4663{ 4664 int tmp; 4665 4666 COM_INT_DISABLE 4667 if (com->pc98_8251fifo_enable) 4668 outb(I8251F_fcr, 0); 4669 tmp = com->pc98_prev_siocmd | (x); 4670 outb(com->cmd_port, tmp); 4671 com->pc98_prev_siocmd = tmp & ~(CMD8251_ER|CMD8251_RESET|CMD8251_EH); 4672 if (com->pc98_8251fifo_enable) 4673 outb(I8251F_fcr, CTRL8251F_ENABLE); 4674 COM_INT_ENABLE 4675} 4676 4677static void 4678pc98_i8251_set_cmd(struct com_s *com, int x) 4679{ 4680 int tmp; 4681 4682 COM_INT_DISABLE 4683 if (com->pc98_8251fifo_enable) 4684 outb(I8251F_fcr, 0); 4685 tmp = (x); 4686 outb(com->cmd_port, tmp); 4687 com->pc98_prev_siocmd = tmp & ~(CMD8251_ER|CMD8251_RESET|CMD8251_EH); 4688 if (com->pc98_8251fifo_enable) 4689 outb(I8251F_fcr, CTRL8251F_ENABLE); 4690 COM_INT_ENABLE 4691} 4692 4693static void 4694pc98_i8251_clear_or_cmd(struct com_s *com, int clr, int x) 4695{ 4696 int tmp; 4697 COM_INT_DISABLE 4698 if (com->pc98_8251fifo_enable) 4699 outb(I8251F_fcr, 0); 4700 tmp = com->pc98_prev_siocmd & ~(clr); 4701 tmp |= (x); 4702 outb(com->cmd_port, tmp); 4703 com->pc98_prev_siocmd = tmp & ~(CMD8251_ER|CMD8251_RESET|CMD8251_EH); 4704 if (com->pc98_8251fifo_enable) 4705 outb(I8251F_fcr, CTRL8251F_ENABLE); 4706 COM_INT_ENABLE 4707} 4708 4709static int 4710pc98_i8251_get_cmd(struct com_s *com) 4711{ 4712 return com->pc98_prev_siocmd; 4713} 4714 4715static int 4716pc98_i8251_get_mod(struct com_s *com) 4717{ 4718 return com->pc98_prev_siomod; 4719} 4720 4721static void 4722pc98_i8251_reset(struct com_s *com, int mode, int command) 4723{ 4724 if (com->pc98_8251fifo_enable) 4725 outb(I8251F_fcr, 0); 4726 outb(com->cmd_port, 0); /* dummy */ 4727 DELAY(2); 4728 outb(com->cmd_port, 0); /* dummy */ 4729 DELAY(2); 4730 outb(com->cmd_port, 0); /* dummy */ 4731 DELAY(2); 4732 outb(com->cmd_port, CMD8251_RESET); /* internal reset */ 4733 DELAY(2); 4734 outb(com->cmd_port, mode ); /* mode register */ 4735 com->pc98_prev_siomod = mode; 4736 DELAY(2); 4737 pc98_i8251_set_cmd( com, (command|CMD8251_ER) ); 4738 DELAY(10); 4739 if (com->pc98_8251fifo_enable) 4740 outb(I8251F_fcr, CTRL8251F_ENABLE | 4741 CTRL8251F_XMT_RST | CTRL8251F_RCV_RST); 4742} 4743 4744static void 4745pc98_check_sysclock(void) 4746{ 4747 /* get system clock from port */ 4748 if ( pc98_machine_type & M_8M ) { 4749 /* 8 MHz system & H98 */ 4750 sysclock = 8; 4751 } else { 4752 /* 5 MHz system */ 4753 sysclock = 5; 4754 } 4755} 4756 4757static void 4758com_cflag_and_speed_set( struct com_s *com, int cflag, int speed) 4759{ 4760 int cfcr=0; 4761 int previnterrupt; 4762 u_int count; 4763 4764 if (pc98_ttspeedtab(com, speed, &count) != 0) 4765 return; 4766 4767 previnterrupt = pc98_check_i8251_interrupt(com); 4768 pc98_disable_i8251_interrupt( com, IEN_Tx|IEN_TxEMP|IEN_Rx ); 4769 4770 switch ( cflag&CSIZE ) { 4771 case CS5: 4772 cfcr = MOD8251_5BITS; break; 4773 case CS6: 4774 cfcr = MOD8251_6BITS; break; 4775 case CS7: 4776 cfcr = MOD8251_7BITS; break; 4777 case CS8: 4778 cfcr = MOD8251_8BITS; break; 4779 } 4780 if ( cflag&PARENB ) { 4781 if ( cflag&PARODD ) 4782 cfcr |= MOD8251_PODD; 4783 else 4784 cfcr |= MOD8251_PEVEN; 4785 } else 4786 cfcr |= MOD8251_PDISAB; 4787 4788 if ( cflag&CSTOPB ) 4789 cfcr |= MOD8251_STOP2; 4790 else 4791 cfcr |= MOD8251_STOP1; 4792 4793 if ( count & 0x10000 ) 4794 cfcr |= MOD8251_CLKX1; 4795 else 4796 cfcr |= MOD8251_CLKX16; 4797 4798 if (epson_machine_id != 0x20) { /* XXX */ 4799 int tmp; 4800 while (!((tmp = inb(com->sts_port)) & STS8251_TxEMP)) 4801 ; 4802 } 4803 /* set baud rate from ospeed */ 4804 pc98_set_baud_rate( com, count ); 4805 4806 if ( cfcr != pc98_i8251_get_mod(com) ) 4807 pc98_i8251_reset(com, cfcr, pc98_i8251_get_cmd(com) ); 4808 4809 pc98_enable_i8251_interrupt( com, previnterrupt ); 4810} 4811 4812static int 4813pc98_ttspeedtab(struct com_s *com, int speed, u_int *divisor) 4814{ 4815 int if_type, effect_sp, count = -1, mod; 4816 4817 if_type = com->pc98_if_type & 0x0f; 4818 4819 switch (com->pc98_if_type) { 4820 case COM_IF_INTERNAL: 4821 if (PC98SIO_baud_rate_port(if_type) != -1) { 4822 count = ttspeedtab(speed, if_8251_type[if_type].speedtab); 4823 if (count > 0) { 4824 count |= COM1_EXT_CLOCK; 4825 break; 4826 } 4827 } 4828 4829 /* for *1CLK asynchronous! mode, TEFUTEFU */ 4830 mod = (sysclock == 5) ? 2457600 : 1996800; 4831 effect_sp = ttspeedtab( speed, pc98speedtab ); 4832 if ( effect_sp < 0 ) /* XXX */ 4833 effect_sp = ttspeedtab( (speed - 1), pc98speedtab ); 4834 if ( effect_sp <= 0 ) 4835 return effect_sp; 4836 if ( effect_sp == speed ) 4837 mod /= 16; 4838 if ( mod % effect_sp ) 4839 return(-1); 4840 count = mod / effect_sp; 4841 if ( count > 65535 ) 4842 return(-1); 4843 if ( effect_sp != speed ) 4844 count |= 0x10000; 4845 break; 4846 case COM_IF_PC9861K_1: 4847 case COM_IF_PC9861K_2: 4848 count = 1; 4849 break; 4850 case COM_IF_IND_SS_1: 4851 case COM_IF_IND_SS_2: 4852 case COM_IF_PIO9032B_1: 4853 case COM_IF_PIO9032B_2: 4854 count = ttspeedtab( speed, if_8251_type[if_type].speedtab ); 4855 break; 4856 case COM_IF_B98_01_1: 4857 case COM_IF_B98_01_2: 4858 count = ttspeedtab( speed, if_8251_type[if_type].speedtab ); 4859#ifdef B98_01_OLD 4860 if (count == 0 || count == 1) { 4861 count += 4; 4862 count |= 0x20000; /* x1 mode for 76800 and 153600 */ 4863 } 4864#endif 4865 break; 4866 } 4867 4868 if (count < 0) 4869 return count; 4870 4871 *divisor = (u_int) count; 4872 return 0; 4873} 4874 4875static void 4876pc98_set_baud_rate( struct com_s *com, u_int count ) 4877{ 4878 int if_type, io, s; 4879 4880 if_type = com->pc98_if_type & 0x0f; 4881 io = rman_get_start(com->ioportres) & 0xff00; 4882 4883 switch (com->pc98_if_type) { 4884 case COM_IF_INTERNAL: 4885 if (PC98SIO_baud_rate_port(if_type) != -1) { 4886 if (count & COM1_EXT_CLOCK) { 4887 outb((Port_t)PC98SIO_baud_rate_port(if_type), count & 0xff); 4888 break; 4889 } else { 4890 outb((Port_t)PC98SIO_baud_rate_port(if_type), 0x09); 4891 } 4892 } 4893 4894 if (count == 0) 4895 return; 4896 4897 /* set i8253 */ 4898 s = splclock(); 4899 if (count != 3) 4900 outb( 0x77, 0xb6 ); 4901 else 4902 outb( 0x77, 0xb4 ); 4903 outb( 0x5f, 0); 4904 outb( 0x75, count & 0xff ); 4905 outb( 0x5f, 0); 4906 outb( 0x75, (count >> 8) & 0xff ); 4907 splx(s); 4908 break; 4909 case COM_IF_IND_SS_1: 4910 case COM_IF_IND_SS_2: 4911 outb(io | PC98SIO_intr_ctrl_port(if_type), 0); 4912 outb(io | PC98SIO_baud_rate_port(if_type), 0); 4913 outb(io | PC98SIO_baud_rate_port(if_type), 0xc0); 4914 outb(io | PC98SIO_baud_rate_port(if_type), (count >> 8) | 0x80); 4915 outb(io | PC98SIO_baud_rate_port(if_type), count & 0xff); 4916 break; 4917 case COM_IF_PIO9032B_1: 4918 case COM_IF_PIO9032B_2: 4919 outb(io | PC98SIO_baud_rate_port(if_type), count); 4920 break; 4921 case COM_IF_B98_01_1: 4922 case COM_IF_B98_01_2: 4923 outb(io | PC98SIO_baud_rate_port(if_type), count & 0x0f); 4924#ifdef B98_01_OLD 4925 /* 4926 * Some old B98_01 board should be controlled 4927 * in different way, but this hasn't been tested yet. 4928 */ 4929 outb(io | PC98SIO_func_port(if_type), 4930 (count & 0x20000) ? 0xf0 : 0xf2); 4931#endif 4932 break; 4933 } 4934} 4935static int 4936pc98_check_if_type(device_t dev, struct siodev *iod) 4937{ 4938 int irr, io, if_type, tmp; 4939 static short irq_tab[2][8] = { 4940 { 3, 5, 6, 9, 10, 12, 13, -1}, 4941 { 3, 10, 12, 13, 5, 6, 9, -1} 4942 }; 4943 4944 if_type = iod->if_type & 0x0f; 4945 iod->irq = 0; 4946 io = isa_get_port(dev) & 0xff00; 4947 4948 if (IS_8251(iod->if_type)) { 4949 if (PC98SIO_func_port(if_type) != -1) { 4950 outb(io | PC98SIO_func_port(if_type), 0xf2); 4951 tmp = ttspeedtab(9600, if_8251_type[if_type].speedtab); 4952 if (tmp != -1 && PC98SIO_baud_rate_port(if_type) != -1) 4953 outb(io | PC98SIO_baud_rate_port(if_type), tmp); 4954 } 4955 4956 iod->cmd = io | PC98SIO_cmd_port(if_type); 4957 iod->sts = io | PC98SIO_sts_port(if_type); 4958 iod->mod = io | PC98SIO_in_modem_port(if_type); 4959 iod->ctrl = io | PC98SIO_intr_ctrl_port(if_type); 4960 4961 if (iod->if_type == COM_IF_INTERNAL) { 4962 iod->irq = 4; 4963 4964 if (pc98_check_8251vfast()) { 4965 PC98SIO_baud_rate_port(if_type) = I8251F_div; 4966 if_8251_type[if_type].speedtab = pc98fast_speedtab; 4967 } 4968 } else { 4969 tmp = inb( iod->mod ) & if_8251_type[if_type].irr_mask; 4970 if ((isa_get_port(dev) & 0xff) == IO_COM2) 4971 iod->irq = irq_tab[0][tmp]; 4972 else 4973 iod->irq = irq_tab[1][tmp]; 4974 } 4975 } else { 4976 irr = if_16550a_type[if_type].irr_read; 4977#ifdef COM_MULTIPORT 4978 if (!COM_ISMULTIPORT(device_get_flags(dev)) || 4979 device_get_unit(dev) == COM_MPMASTER(device_get_flags(dev))) 4980#endif 4981 if (irr != -1) { 4982 tmp = inb(io | irr); 4983 if (isa_get_port(dev) & 0x01) /* XXX depend on RSB-384 */ 4984 iod->irq = irq_tab[1][tmp >> 3]; 4985 else 4986 iod->irq = irq_tab[0][tmp & 0x07]; 4987 } 4988 } 4989 if ( iod->irq == -1 ) return -1; 4990 4991 return 0; 4992} 4993static void 4994pc98_set_ioport(struct com_s *com) 4995{ 4996 int if_type = com->pc98_if_type & 0x0f; 4997 Port_t io = rman_get_start(com->ioportres) & 0xff00; 4998 4999 pc98_check_sysclock(); 5000 com->data_port = io | PC98SIO_data_port(if_type); 5001 com->cmd_port = io | PC98SIO_cmd_port(if_type); 5002 com->sts_port = io | PC98SIO_sts_port(if_type); 5003 com->in_modem_port = io | PC98SIO_in_modem_port(if_type); 5004 com->intr_ctrl_port = io | PC98SIO_intr_ctrl_port(if_type); 5005} 5006static int 5007pc98_check_8251vfast(void) 5008{ 5009 int i; 5010 5011 outb(I8251F_div, 0x8c); 5012 DELAY(10); 5013 for (i = 0; i < 100; i++) { 5014 if ((inb(I8251F_div) & 0x80) != 0) { 5015 i = 0; 5016 break; 5017 } 5018 DELAY(1); 5019 } 5020 outb(I8251F_div, 0); 5021 DELAY(10); 5022 for (; i < 100; i++) { 5023 if ((inb(I8251F_div) & 0x80) == 0) 5024 return 1; 5025 DELAY(1); 5026 } 5027 5028 return 0; 5029} 5030static int 5031pc98_check_8251fifo(void) 5032{ 5033 u_char tmp1, tmp2; 5034 5035 tmp1 = inb(I8251F_iir); 5036 DELAY(10); 5037 tmp2 = inb(I8251F_iir); 5038 if (((tmp1 ^ tmp2) & 0x40) != 0 && ((tmp1 | tmp2) & 0x20) == 0) 5039 return 1; 5040 5041 return 0; 5042} 5043#endif /* PC98 defined */ 5044