cbus_dma.c revision 92793
1/*- 2 * Copyright (c) 1991 The Regents of the University of California. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to Berkeley by 6 * William Jolitz. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by the University of 19 * California, Berkeley and its contributors. 20 * 4. Neither the name of the University nor the names of its contributors 21 * may be used to endorse or promote products derived from this software 22 * without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 * 36 * from: @(#)isa.c 7.2 (Berkeley) 5/13/91 37 * $FreeBSD: head/sys/pc98/cbus/cbus_dma.c 92793 2002-03-20 12:22:31Z kato $ 38 */ 39 40/* 41 * code to manage AT bus 42 * 43 * 92/08/18 Frank P. MacLachlan (fpm@crash.cts.com): 44 * Fixed uninitialized variable problem and added code to deal 45 * with DMA page boundaries in isa_dmarangecheck(). Fixed word 46 * mode DMA count compution and reorganized DMA setup code in 47 * isa_dmastart() 48 */ 49 50#ifdef PC98 51#include "opt_pc98.h" 52#endif 53 54#include <sys/param.h> 55#include <sys/systm.h> 56#include <sys/bus.h> 57#include <sys/kernel.h> 58#include <sys/malloc.h> 59#include <sys/lock.h> 60#include <sys/proc.h> 61#include <sys/mutex.h> 62#include <sys/module.h> 63#ifdef PC98 64#include <machine/md_var.h> 65#endif 66#include <vm/vm.h> 67#include <vm/vm_param.h> 68#include <vm/pmap.h> 69#ifdef PC98 70#include <pc98/pc98/pc98.h> 71#else 72#include <i386/isa/isa.h> 73#endif 74#include <dev/ic/i8237.h> 75#include <isa/isavar.h> 76 77/* 78** Register definitions for DMA controller 1 (channels 0..3): 79*/ 80#ifdef PC98 81#define DMA1_CHN(c) (IO_DMA + (4*(c))) /* addr reg for channel c */ 82#define DMA1_SMSK (IO_DMA + 0x14) /* single mask register */ 83#define DMA1_MODE (IO_DMA + 0x16) /* mode register */ 84#define DMA1_FFC (IO_DMA + 0x18) /* clear first/last FF */ 85#else 86#define DMA1_CHN(c) (IO_DMA1 + 1*(2*(c))) /* addr reg for channel c */ 87#define DMA1_SMSK (IO_DMA1 + 1*10) /* single mask register */ 88#define DMA1_MODE (IO_DMA1 + 1*11) /* mode register */ 89#define DMA1_FFC (IO_DMA1 + 1*12) /* clear first/last FF */ 90#endif 91 92/* 93** Register definitions for DMA controller 2 (channels 4..7): 94*/ 95#define DMA2_CHN(c) (IO_DMA2 + 2*(2*(c))) /* addr reg for channel c */ 96#define DMA2_SMSK (IO_DMA2 + 2*10) /* single mask register */ 97#define DMA2_MODE (IO_DMA2 + 2*11) /* mode register */ 98#define DMA2_FFC (IO_DMA2 + 2*12) /* clear first/last FF */ 99 100static int isa_dmarangecheck(caddr_t va, u_int length, int chan); 101 102#ifdef PC98 103static caddr_t dma_bouncebuf[4]; 104static u_int dma_bouncebufsize[4]; 105#else 106static caddr_t dma_bouncebuf[8]; 107static u_int dma_bouncebufsize[8]; 108#endif 109static u_int8_t dma_bounced = 0; 110static u_int8_t dma_busy = 0; /* Used in isa_dmastart() */ 111static u_int8_t dma_inuse = 0; /* User for acquire/release */ 112static u_int8_t dma_auto_mode = 0; 113 114#ifdef PC98 115#define VALID_DMA_MASK (3) 116#else 117#define VALID_DMA_MASK (7) 118#endif 119 120/* high byte of address is stored in this port for i-th dma channel */ 121#ifdef PC98 122static int dmapageport[4] = { 0x27, 0x21, 0x23, 0x25 }; 123#else 124static int dmapageport[8] = { 0x87, 0x83, 0x81, 0x82, 0x8f, 0x8b, 0x89, 0x8a }; 125#endif 126 127/* 128 * Setup a DMA channel's bounce buffer. 129 */ 130void 131isa_dmainit(chan, bouncebufsize) 132 int chan; 133 u_int bouncebufsize; 134{ 135 void *buf; 136 137#ifdef DIAGNOSTIC 138 if (chan & ~VALID_DMA_MASK) 139 panic("isa_dmainit: channel out of range"); 140 141 if (dma_bouncebuf[chan] != NULL) 142 panic("isa_dmainit: impossible request"); 143#endif 144 145 dma_bouncebufsize[chan] = bouncebufsize; 146 147 /* Try malloc() first. It works better if it works. */ 148 buf = malloc(bouncebufsize, M_DEVBUF, M_NOWAIT); 149 if (buf != NULL) { 150 if (isa_dmarangecheck(buf, bouncebufsize, chan) == 0) { 151 dma_bouncebuf[chan] = buf; 152 return; 153 } 154 free(buf, M_DEVBUF); 155 } 156 buf = contigmalloc(bouncebufsize, M_DEVBUF, M_NOWAIT, 0ul, 0xfffffful, 157 1ul, chan & 4 ? 0x20000ul : 0x10000ul); 158 if (buf == NULL) 159 printf("isa_dmainit(%d, %d) failed\n", chan, bouncebufsize); 160 else 161 dma_bouncebuf[chan] = buf; 162} 163 164/* 165 * Register a DMA channel's usage. Usually called from a device driver 166 * in open() or during its initialization. 167 */ 168int 169isa_dma_acquire(chan) 170 int chan; 171{ 172#ifdef DIAGNOSTIC 173 if (chan & ~VALID_DMA_MASK) 174 panic("isa_dma_acquire: channel out of range"); 175#endif 176 177 if (dma_inuse & (1 << chan)) { 178 printf("isa_dma_acquire: channel %d already in use\n", chan); 179 return (EBUSY); 180 } 181 dma_inuse |= (1 << chan); 182 dma_auto_mode &= ~(1 << chan); 183 184 return (0); 185} 186 187/* 188 * Unregister a DMA channel's usage. Usually called from a device driver 189 * during close() or during its shutdown. 190 */ 191void 192isa_dma_release(chan) 193 int chan; 194{ 195#ifdef DIAGNOSTIC 196 if (chan & ~VALID_DMA_MASK) 197 panic("isa_dma_release: channel out of range"); 198 199 if ((dma_inuse & (1 << chan)) == 0) 200 printf("isa_dma_release: channel %d not in use\n", chan); 201#endif 202 203 if (dma_busy & (1 << chan)) { 204 dma_busy &= ~(1 << chan); 205 /* 206 * XXX We should also do "dma_bounced &= (1 << chan);" 207 * because we are acting on behalf of isa_dmadone() which 208 * was not called to end the last DMA operation. This does 209 * not matter now, but it may in the future. 210 */ 211 } 212 213 dma_inuse &= ~(1 << chan); 214 dma_auto_mode &= ~(1 << chan); 215} 216 217#ifndef PC98 218/* 219 * isa_dmacascade(): program 8237 DMA controller channel to accept 220 * external dma control by a board. 221 */ 222void 223isa_dmacascade(chan) 224 int chan; 225{ 226#ifdef DIAGNOSTIC 227 if (chan & ~VALID_DMA_MASK) 228 panic("isa_dmacascade: channel out of range"); 229#endif 230 231 /* set dma channel mode, and set dma channel mode */ 232 if ((chan & 4) == 0) { 233 outb(DMA1_MODE, DMA37MD_CASCADE | chan); 234 outb(DMA1_SMSK, chan); 235 } else { 236 outb(DMA2_MODE, DMA37MD_CASCADE | (chan & 3)); 237 outb(DMA2_SMSK, chan & 3); 238 } 239} 240#endif 241 242/* 243 * isa_dmastart(): program 8237 DMA controller channel, avoid page alignment 244 * problems by using a bounce buffer. 245 */ 246void 247isa_dmastart(int flags, caddr_t addr, u_int nbytes, int chan) 248{ 249 vm_offset_t phys; 250 int waport; 251 caddr_t newaddr; 252 253 GIANT_REQUIRED; 254 255#ifdef DIAGNOSTIC 256 if (chan & ~VALID_DMA_MASK) 257 panic("isa_dmastart: channel out of range"); 258 259 if ((chan < 4 && nbytes > (1<<16)) 260 || (chan >= 4 && (nbytes > (1<<17) || (u_int)addr & 1))) 261 panic("isa_dmastart: impossible request"); 262 263 if ((dma_inuse & (1 << chan)) == 0) 264 printf("isa_dmastart: channel %d not acquired\n", chan); 265#endif 266 267#if 0 268 /* 269 * XXX This should be checked, but drivers like ad1848 only call 270 * isa_dmastart() once because they use Auto DMA mode. If we 271 * leave this in, drivers that do this will print this continuously. 272 */ 273 if (dma_busy & (1 << chan)) 274 printf("isa_dmastart: channel %d busy\n", chan); 275#endif 276 277 dma_busy |= (1 << chan); 278 279 if (isa_dmarangecheck(addr, nbytes, chan)) { 280 if (dma_bouncebuf[chan] == NULL 281 || dma_bouncebufsize[chan] < nbytes) 282 panic("isa_dmastart: bad bounce buffer"); 283 dma_bounced |= (1 << chan); 284 newaddr = dma_bouncebuf[chan]; 285 286 /* copy bounce buffer on write */ 287 if (!(flags & ISADMA_READ)) 288 bcopy(addr, newaddr, nbytes); 289 addr = newaddr; 290 } 291 292 /* translate to physical */ 293 phys = pmap_extract(pmap_kernel(), (vm_offset_t)addr); 294 295 if (flags & ISADMA_RAW) { 296 dma_auto_mode |= (1 << chan); 297 } else { 298 dma_auto_mode &= ~(1 << chan); 299 } 300 301#ifdef PC98 302 if (need_pre_dma_flush) 303 wbinvd(); /* wbinvd (WB cache flush) */ 304#endif 305 306#ifndef PC98 307 if ((chan & 4) == 0) { 308 /* 309 * Program one of DMA channels 0..3. These are 310 * byte mode channels. 311 */ 312#endif 313 /* set dma channel mode, and reset address ff */ 314 315 /* If ISADMA_RAW flag is set, then use autoinitialise mode */ 316 if (flags & ISADMA_RAW) { 317 if (flags & ISADMA_READ) 318 outb(DMA1_MODE, DMA37MD_AUTO|DMA37MD_WRITE|chan); 319 else 320 outb(DMA1_MODE, DMA37MD_AUTO|DMA37MD_READ|chan); 321 } 322 else 323 if (flags & ISADMA_READ) 324 outb(DMA1_MODE, DMA37MD_SINGLE|DMA37MD_WRITE|chan); 325 else 326 outb(DMA1_MODE, DMA37MD_SINGLE|DMA37MD_READ|chan); 327 outb(DMA1_FFC, 0); 328 329 /* send start address */ 330 waport = DMA1_CHN(chan); 331 outb(waport, phys); 332 outb(waport, phys>>8); 333 outb(dmapageport[chan], phys>>16); 334 335 /* send count */ 336#ifdef PC98 337 outb(waport + 2, --nbytes); 338 outb(waport + 2, nbytes>>8); 339#else 340 outb(waport + 1, --nbytes); 341 outb(waport + 1, nbytes>>8); 342#endif 343 344 /* unmask channel */ 345 outb(DMA1_SMSK, chan); 346#ifndef PC98 347 } else { 348 /* 349 * Program one of DMA channels 4..7. These are 350 * word mode channels. 351 */ 352 /* set dma channel mode, and reset address ff */ 353 354 /* If ISADMA_RAW flag is set, then use autoinitialise mode */ 355 if (flags & ISADMA_RAW) { 356 if (flags & ISADMA_READ) 357 outb(DMA2_MODE, DMA37MD_AUTO|DMA37MD_WRITE|(chan&3)); 358 else 359 outb(DMA2_MODE, DMA37MD_AUTO|DMA37MD_READ|(chan&3)); 360 } 361 else 362 if (flags & ISADMA_READ) 363 outb(DMA2_MODE, DMA37MD_SINGLE|DMA37MD_WRITE|(chan&3)); 364 else 365 outb(DMA2_MODE, DMA37MD_SINGLE|DMA37MD_READ|(chan&3)); 366 outb(DMA2_FFC, 0); 367 368 /* send start address */ 369 waport = DMA2_CHN(chan - 4); 370 outb(waport, phys>>1); 371 outb(waport, phys>>9); 372 outb(dmapageport[chan], phys>>16); 373 374 /* send count */ 375 nbytes >>= 1; 376 outb(waport + 2, --nbytes); 377 outb(waport + 2, nbytes>>8); 378 379 /* unmask channel */ 380 outb(DMA2_SMSK, chan & 3); 381 } 382#endif 383} 384 385void 386isa_dmadone(int flags, caddr_t addr, int nbytes, int chan) 387{ 388#ifdef PC98 389 if (flags & ISADMA_READ) { 390 /* cache flush only after reading 92/12/9 by A.Kojima */ 391 if (need_post_dma_flush) 392 invd(); 393 } 394#endif 395 396#ifdef DIAGNOSTIC 397 if (chan & ~VALID_DMA_MASK) 398 panic("isa_dmadone: channel out of range"); 399 400 if ((dma_inuse & (1 << chan)) == 0) 401 printf("isa_dmadone: channel %d not acquired\n", chan); 402#endif 403 404 if (((dma_busy & (1 << chan)) == 0) && 405 (dma_auto_mode & (1 << chan)) == 0 ) 406 printf("isa_dmadone: channel %d not busy\n", chan); 407 408#ifdef PC98 409 if ((dma_auto_mode & (1 << chan)) == 0) 410 outb(DMA1_SMSK, (chan & 3) | 4); 411#else 412 if ((dma_auto_mode & (1 << chan)) == 0) 413 outb(chan & 4 ? DMA2_SMSK : DMA1_SMSK, (chan & 3) | 4); 414#endif 415 416 if (dma_bounced & (1 << chan)) { 417 /* copy bounce buffer on read */ 418 if (flags & ISADMA_READ) 419 bcopy(dma_bouncebuf[chan], addr, nbytes); 420 421 dma_bounced &= ~(1 << chan); 422 } 423 dma_busy &= ~(1 << chan); 424} 425 426/* 427 * Check for problems with the address range of a DMA transfer 428 * (non-contiguous physical pages, outside of bus address space, 429 * crossing DMA page boundaries). 430 * Return true if special handling needed. 431 */ 432 433static int 434isa_dmarangecheck(caddr_t va, u_int length, int chan) 435{ 436 vm_offset_t phys, priorpage = 0, endva; 437 u_int dma_pgmsk = (chan & 4) ? ~(128*1024-1) : ~(64*1024-1); 438 439 GIANT_REQUIRED; 440 441 endva = (vm_offset_t)round_page((vm_offset_t)va + length); 442 for (; va < (caddr_t) endva ; va += PAGE_SIZE) { 443 phys = trunc_page(pmap_extract(pmap_kernel(), (vm_offset_t)va)); 444#ifdef EPSON_BOUNCEDMA 445#define ISARAM_END 0xf00000 446#else 447#define ISARAM_END RAM_END 448#endif 449 if (phys == 0) 450 panic("isa_dmacheck: no physical page present"); 451 if (phys >= ISARAM_END) 452 return (1); 453 if (priorpage) { 454 if (priorpage + PAGE_SIZE != phys) 455 return (1); 456 /* check if crossing a DMA page boundary */ 457 if (((u_int)priorpage ^ (u_int)phys) & dma_pgmsk) 458 return (1); 459 } 460 priorpage = phys; 461 } 462 return (0); 463} 464 465/* 466 * Query the progress of a transfer on a DMA channel. 467 * 468 * To avoid having to interrupt a transfer in progress, we sample 469 * each of the high and low databytes twice, and apply the following 470 * logic to determine the correct count. 471 * 472 * Reads are performed with interrupts disabled, thus it is to be 473 * expected that the time between reads is very small. At most 474 * one rollover in the low count byte can be expected within the 475 * four reads that are performed. 476 * 477 * There are three gaps in which a rollover can occur : 478 * 479 * - read low1 480 * gap1 481 * - read high1 482 * gap2 483 * - read low2 484 * gap3 485 * - read high2 486 * 487 * If a rollover occurs in gap1 or gap2, the low2 value will be 488 * greater than the low1 value. In this case, low2 and high2 are a 489 * corresponding pair. 490 * 491 * In any other case, low1 and high1 can be considered to be correct. 492 * 493 * The function returns the number of bytes remaining in the transfer, 494 * or -1 if the channel requested is not active. 495 * 496 */ 497int 498isa_dmastatus(int chan) 499{ 500 u_long cnt = 0; 501 int ffport, waport; 502 u_long low1, high1, low2, high2; 503 504 /* channel active? */ 505 if ((dma_inuse & (1 << chan)) == 0) { 506 printf("isa_dmastatus: channel %d not active\n", chan); 507 return(-1); 508 } 509 /* channel busy? */ 510 511 if (((dma_busy & (1 << chan)) == 0) && 512 (dma_auto_mode & (1 << chan)) == 0 ) { 513 printf("chan %d not busy\n", chan); 514 return -2 ; 515 } 516#ifdef PC98 517 ffport = DMA1_FFC; 518 waport = DMA1_CHN(chan) + 2; 519#else 520 if (chan < 4) { /* low DMA controller */ 521 ffport = DMA1_FFC; 522 waport = DMA1_CHN(chan) + 1; 523 } else { /* high DMA controller */ 524 ffport = DMA2_FFC; 525 waport = DMA2_CHN(chan - 4) + 2; 526 } 527#endif 528 529 disable_intr(); /* no interrupts Mr Jones! */ 530 outb(ffport, 0); /* clear register LSB flipflop */ 531 low1 = inb(waport); 532 high1 = inb(waport); 533 outb(ffport, 0); /* clear again */ 534 low2 = inb(waport); 535 high2 = inb(waport); 536 enable_intr(); /* enable interrupts again */ 537 538 /* 539 * Now decide if a wrap has tried to skew our results. 540 * Note that after TC, the count will read 0xffff, while we want 541 * to return zero, so we add and then mask to compensate. 542 */ 543 if (low1 >= low2) { 544 cnt = (low1 + (high1 << 8) + 1) & 0xffff; 545 } else { 546 cnt = (low2 + (high2 << 8) + 1) & 0xffff; 547 } 548 549 if (chan >= 4) /* high channels move words */ 550 cnt *= 2; 551 return(cnt); 552} 553 554/* 555 * Stop a DMA transfer currently in progress. 556 */ 557int 558isa_dmastop(int chan) 559{ 560 if ((dma_inuse & (1 << chan)) == 0) 561 printf("isa_dmastop: channel %d not acquired\n", chan); 562 563 if (((dma_busy & (1 << chan)) == 0) && 564 ((dma_auto_mode & (1 << chan)) == 0)) { 565 printf("chan %d not busy\n", chan); 566 return -2 ; 567 } 568 569 if ((chan & 4) == 0) { 570 outb(DMA1_SMSK, (chan & 3) | 4 /* disable mask */); 571 } else { 572#ifndef PC98 573 outb(DMA2_SMSK, (chan & 3) | 4 /* disable mask */); 574#endif 575 } 576 return(isa_dmastatus(chan)); 577} 578 579/* 580 * Attach to the ISA PnP descriptor for the AT DMA controller 581 */ 582static struct isa_pnp_id atdma_ids[] = { 583 { 0x0002d041 /* PNP0200 */, "AT DMA controller" }, 584 { 0 } 585}; 586 587static int 588atdma_probe(device_t dev) 589{ 590 int result; 591 592 if ((result = ISA_PNP_PROBE(device_get_parent(dev), dev, atdma_ids)) <= 0) 593 device_quiet(dev); 594 return(result); 595} 596 597static int 598atdma_attach(device_t dev) 599{ 600 return(0); 601} 602 603static device_method_t atdma_methods[] = { 604 /* Device interface */ 605 DEVMETHOD(device_probe, atdma_probe), 606 DEVMETHOD(device_attach, atdma_attach), 607 DEVMETHOD(device_detach, bus_generic_detach), 608 DEVMETHOD(device_shutdown, bus_generic_shutdown), 609 DEVMETHOD(device_suspend, bus_generic_suspend), 610 DEVMETHOD(device_resume, bus_generic_resume), 611 { 0, 0 } 612}; 613 614static driver_t atdma_driver = { 615 "atdma", 616 atdma_methods, 617 1, /* no softc */ 618}; 619 620static devclass_t atdma_devclass; 621 622DRIVER_MODULE(atdma, isa, atdma_driver, atdma_devclass, 0, 0); 623#ifndef PC98 624DRIVER_MODULE(atdma, acpi, atdma_driver, atdma_devclass, 0, 0); 625#endif 626