cbus_dma.c revision 79224
1/*- 2 * Copyright (c) 1991 The Regents of the University of California. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to Berkeley by 6 * William Jolitz. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by the University of 19 * California, Berkeley and its contributors. 20 * 4. Neither the name of the University nor the names of its contributors 21 * may be used to endorse or promote products derived from this software 22 * without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 * 36 * from: @(#)isa.c 7.2 (Berkeley) 5/13/91 37 * $FreeBSD: head/sys/pc98/cbus/cbus_dma.c 79224 2001-07-04 16:20:28Z dillon $ 38 */ 39 40/* 41 * code to manage AT bus 42 * 43 * 92/08/18 Frank P. MacLachlan (fpm@crash.cts.com): 44 * Fixed uninitialized variable problem and added code to deal 45 * with DMA page boundaries in isa_dmarangecheck(). Fixed word 46 * mode DMA count compution and reorganized DMA setup code in 47 * isa_dmastart() 48 */ 49 50#ifdef PC98 51#include "opt_pc98.h" 52#endif 53 54#include <sys/param.h> 55#include <sys/systm.h> 56#include <sys/bus.h> 57#include <sys/kernel.h> 58#include <sys/malloc.h> 59#include <sys/lock.h> 60#include <sys/mutex.h> 61#include <sys/module.h> 62#ifdef PC98 63#include <machine/md_var.h> 64#endif 65#include <vm/vm.h> 66#include <vm/vm_param.h> 67#include <vm/pmap.h> 68#ifdef PC98 69#include <pc98/pc98/pc98.h> 70#else 71#include <i386/isa/isa.h> 72#endif 73#include <dev/ic/i8237.h> 74#include <isa/isavar.h> 75 76/* 77** Register definitions for DMA controller 1 (channels 0..3): 78*/ 79#ifdef PC98 80#define DMA1_CHN(c) (IO_DMA + (4*(c))) /* addr reg for channel c */ 81#define DMA1_SMSK (IO_DMA + 0x14) /* single mask register */ 82#define DMA1_MODE (IO_DMA + 0x16) /* mode register */ 83#define DMA1_FFC (IO_DMA + 0x18) /* clear first/last FF */ 84#else 85#define DMA1_CHN(c) (IO_DMA1 + 1*(2*(c))) /* addr reg for channel c */ 86#define DMA1_SMSK (IO_DMA1 + 1*10) /* single mask register */ 87#define DMA1_MODE (IO_DMA1 + 1*11) /* mode register */ 88#define DMA1_FFC (IO_DMA1 + 1*12) /* clear first/last FF */ 89#endif 90 91/* 92** Register definitions for DMA controller 2 (channels 4..7): 93*/ 94#define DMA2_CHN(c) (IO_DMA2 + 2*(2*(c))) /* addr reg for channel c */ 95#define DMA2_SMSK (IO_DMA2 + 2*10) /* single mask register */ 96#define DMA2_MODE (IO_DMA2 + 2*11) /* mode register */ 97#define DMA2_FFC (IO_DMA2 + 2*12) /* clear first/last FF */ 98 99static int isa_dmarangecheck __P((caddr_t va, u_int length, int chan)); 100 101#ifdef PC98 102static caddr_t dma_bouncebuf[4]; 103static u_int dma_bouncebufsize[4]; 104#else 105static caddr_t dma_bouncebuf[8]; 106static u_int dma_bouncebufsize[8]; 107#endif 108static u_int8_t dma_bounced = 0; 109static u_int8_t dma_busy = 0; /* Used in isa_dmastart() */ 110static u_int8_t dma_inuse = 0; /* User for acquire/release */ 111static u_int8_t dma_auto_mode = 0; 112 113#ifdef PC98 114#define VALID_DMA_MASK (3) 115#else 116#define VALID_DMA_MASK (7) 117#endif 118 119/* high byte of address is stored in this port for i-th dma channel */ 120#ifdef PC98 121static int dmapageport[4] = { 0x27, 0x21, 0x23, 0x25 }; 122#else 123static int dmapageport[8] = { 0x87, 0x83, 0x81, 0x82, 0x8f, 0x8b, 0x89, 0x8a }; 124#endif 125 126/* 127 * Setup a DMA channel's bounce buffer. 128 */ 129void 130isa_dmainit(chan, bouncebufsize) 131 int chan; 132 u_int bouncebufsize; 133{ 134 void *buf; 135 136#ifdef DIAGNOSTIC 137 if (chan & ~VALID_DMA_MASK) 138 panic("isa_dmainit: channel out of range"); 139 140 if (dma_bouncebuf[chan] != NULL) 141 panic("isa_dmainit: impossible request"); 142#endif 143 144 dma_bouncebufsize[chan] = bouncebufsize; 145 146 /* Try malloc() first. It works better if it works. */ 147 buf = malloc(bouncebufsize, M_DEVBUF, M_NOWAIT); 148 if (buf != NULL) { 149 if (isa_dmarangecheck(buf, bouncebufsize, chan) == 0) { 150 dma_bouncebuf[chan] = buf; 151 return; 152 } 153 free(buf, M_DEVBUF); 154 } 155 buf = contigmalloc(bouncebufsize, M_DEVBUF, M_NOWAIT, 0ul, 0xfffffful, 156 1ul, chan & 4 ? 0x20000ul : 0x10000ul); 157 if (buf == NULL) 158 printf("isa_dmainit(%d, %d) failed\n", chan, bouncebufsize); 159 else 160 dma_bouncebuf[chan] = buf; 161} 162 163/* 164 * Register a DMA channel's usage. Usually called from a device driver 165 * in open() or during its initialization. 166 */ 167int 168isa_dma_acquire(chan) 169 int chan; 170{ 171#ifdef DIAGNOSTIC 172 if (chan & ~VALID_DMA_MASK) 173 panic("isa_dma_acquire: channel out of range"); 174#endif 175 176 if (dma_inuse & (1 << chan)) { 177 printf("isa_dma_acquire: channel %d already in use\n", chan); 178 return (EBUSY); 179 } 180 dma_inuse |= (1 << chan); 181 dma_auto_mode &= ~(1 << chan); 182 183 return (0); 184} 185 186/* 187 * Unregister a DMA channel's usage. Usually called from a device driver 188 * during close() or during its shutdown. 189 */ 190void 191isa_dma_release(chan) 192 int chan; 193{ 194#ifdef DIAGNOSTIC 195 if (chan & ~VALID_DMA_MASK) 196 panic("isa_dma_release: channel out of range"); 197 198 if ((dma_inuse & (1 << chan)) == 0) 199 printf("isa_dma_release: channel %d not in use\n", chan); 200#endif 201 202 if (dma_busy & (1 << chan)) { 203 dma_busy &= ~(1 << chan); 204 /* 205 * XXX We should also do "dma_bounced &= (1 << chan);" 206 * because we are acting on behalf of isa_dmadone() which 207 * was not called to end the last DMA operation. This does 208 * not matter now, but it may in the future. 209 */ 210 } 211 212 dma_inuse &= ~(1 << chan); 213 dma_auto_mode &= ~(1 << chan); 214} 215 216#ifndef PC98 217/* 218 * isa_dmacascade(): program 8237 DMA controller channel to accept 219 * external dma control by a board. 220 */ 221void 222isa_dmacascade(chan) 223 int chan; 224{ 225#ifdef DIAGNOSTIC 226 if (chan & ~VALID_DMA_MASK) 227 panic("isa_dmacascade: channel out of range"); 228#endif 229 230 /* set dma channel mode, and set dma channel mode */ 231 if ((chan & 4) == 0) { 232 outb(DMA1_MODE, DMA37MD_CASCADE | chan); 233 outb(DMA1_SMSK, chan); 234 } else { 235 outb(DMA2_MODE, DMA37MD_CASCADE | (chan & 3)); 236 outb(DMA2_SMSK, chan & 3); 237 } 238} 239#endif 240 241/* 242 * isa_dmastart(): program 8237 DMA controller channel, avoid page alignment 243 * problems by using a bounce buffer. 244 */ 245void 246isa_dmastart(int flags, caddr_t addr, u_int nbytes, int chan) 247{ 248 vm_offset_t phys; 249 int waport; 250 caddr_t newaddr; 251 252 GIANT_REQUIRED; 253 254#ifdef DIAGNOSTIC 255 if (chan & ~VALID_DMA_MASK) 256 panic("isa_dmastart: channel out of range"); 257 258 if ((chan < 4 && nbytes > (1<<16)) 259 || (chan >= 4 && (nbytes > (1<<17) || (u_int)addr & 1))) 260 panic("isa_dmastart: impossible request"); 261 262 if ((dma_inuse & (1 << chan)) == 0) 263 printf("isa_dmastart: channel %d not acquired\n", chan); 264#endif 265 266#if 0 267 /* 268 * XXX This should be checked, but drivers like ad1848 only call 269 * isa_dmastart() once because they use Auto DMA mode. If we 270 * leave this in, drivers that do this will print this continuously. 271 */ 272 if (dma_busy & (1 << chan)) 273 printf("isa_dmastart: channel %d busy\n", chan); 274#endif 275 276 dma_busy |= (1 << chan); 277 278 if (isa_dmarangecheck(addr, nbytes, chan)) { 279 if (dma_bouncebuf[chan] == NULL 280 || dma_bouncebufsize[chan] < nbytes) 281 panic("isa_dmastart: bad bounce buffer"); 282 dma_bounced |= (1 << chan); 283 newaddr = dma_bouncebuf[chan]; 284 285 /* copy bounce buffer on write */ 286 if (!(flags & ISADMA_READ)) 287 bcopy(addr, newaddr, nbytes); 288 addr = newaddr; 289 } 290 291 /* translate to physical */ 292 phys = pmap_extract(pmap_kernel(), (vm_offset_t)addr); 293 294 if (flags & ISADMA_RAW) { 295 dma_auto_mode |= (1 << chan); 296 } else { 297 dma_auto_mode &= ~(1 << chan); 298 } 299 300#ifdef PC98 301 if (need_pre_dma_flush) 302 wbinvd(); /* wbinvd (WB cache flush) */ 303#endif 304 305#ifndef PC98 306 if ((chan & 4) == 0) { 307 /* 308 * Program one of DMA channels 0..3. These are 309 * byte mode channels. 310 */ 311#endif 312 /* set dma channel mode, and reset address ff */ 313 314 /* If ISADMA_RAW flag is set, then use autoinitialise mode */ 315 if (flags & ISADMA_RAW) { 316 if (flags & ISADMA_READ) 317 outb(DMA1_MODE, DMA37MD_AUTO|DMA37MD_WRITE|chan); 318 else 319 outb(DMA1_MODE, DMA37MD_AUTO|DMA37MD_READ|chan); 320 } 321 else 322 if (flags & ISADMA_READ) 323 outb(DMA1_MODE, DMA37MD_SINGLE|DMA37MD_WRITE|chan); 324 else 325 outb(DMA1_MODE, DMA37MD_SINGLE|DMA37MD_READ|chan); 326 outb(DMA1_FFC, 0); 327 328 /* send start address */ 329 waport = DMA1_CHN(chan); 330 outb(waport, phys); 331 outb(waport, phys>>8); 332 outb(dmapageport[chan], phys>>16); 333 334 /* send count */ 335#ifdef PC98 336 outb(waport + 2, --nbytes); 337 outb(waport + 2, nbytes>>8); 338#else 339 outb(waport + 1, --nbytes); 340 outb(waport + 1, nbytes>>8); 341#endif 342 343 /* unmask channel */ 344 outb(DMA1_SMSK, chan); 345#ifndef PC98 346 } else { 347 /* 348 * Program one of DMA channels 4..7. These are 349 * word mode channels. 350 */ 351 /* set dma channel mode, and reset address ff */ 352 353 /* If ISADMA_RAW flag is set, then use autoinitialise mode */ 354 if (flags & ISADMA_RAW) { 355 if (flags & ISADMA_READ) 356 outb(DMA2_MODE, DMA37MD_AUTO|DMA37MD_WRITE|(chan&3)); 357 else 358 outb(DMA2_MODE, DMA37MD_AUTO|DMA37MD_READ|(chan&3)); 359 } 360 else 361 if (flags & ISADMA_READ) 362 outb(DMA2_MODE, DMA37MD_SINGLE|DMA37MD_WRITE|(chan&3)); 363 else 364 outb(DMA2_MODE, DMA37MD_SINGLE|DMA37MD_READ|(chan&3)); 365 outb(DMA2_FFC, 0); 366 367 /* send start address */ 368 waport = DMA2_CHN(chan - 4); 369 outb(waport, phys>>1); 370 outb(waport, phys>>9); 371 outb(dmapageport[chan], phys>>16); 372 373 /* send count */ 374 nbytes >>= 1; 375 outb(waport + 2, --nbytes); 376 outb(waport + 2, nbytes>>8); 377 378 /* unmask channel */ 379 outb(DMA2_SMSK, chan & 3); 380 } 381#endif 382} 383 384void 385isa_dmadone(int flags, caddr_t addr, int nbytes, int chan) 386{ 387#ifdef PC98 388 if (flags & ISADMA_READ) { 389 /* cache flush only after reading 92/12/9 by A.Kojima */ 390 if (need_post_dma_flush) 391 invd(); 392 } 393#endif 394 395#ifdef DIAGNOSTIC 396 if (chan & ~VALID_DMA_MASK) 397 panic("isa_dmadone: channel out of range"); 398 399 if ((dma_inuse & (1 << chan)) == 0) 400 printf("isa_dmadone: channel %d not acquired\n", chan); 401#endif 402 403 if (((dma_busy & (1 << chan)) == 0) && 404 (dma_auto_mode & (1 << chan)) == 0 ) 405 printf("isa_dmadone: channel %d not busy\n", chan); 406 407#ifdef PC98 408 if ((dma_auto_mode & (1 << chan)) == 0) 409 outb(DMA1_SMSK, (chan & 3) | 4); 410#else 411 if ((dma_auto_mode & (1 << chan)) == 0) 412 outb(chan & 4 ? DMA2_SMSK : DMA1_SMSK, (chan & 3) | 4); 413#endif 414 415 if (dma_bounced & (1 << chan)) { 416 /* copy bounce buffer on read */ 417 if (flags & ISADMA_READ) 418 bcopy(dma_bouncebuf[chan], addr, nbytes); 419 420 dma_bounced &= ~(1 << chan); 421 } 422 dma_busy &= ~(1 << chan); 423} 424 425/* 426 * Check for problems with the address range of a DMA transfer 427 * (non-contiguous physical pages, outside of bus address space, 428 * crossing DMA page boundaries). 429 * Return true if special handling needed. 430 */ 431 432static int 433isa_dmarangecheck(caddr_t va, u_int length, int chan) 434{ 435 vm_offset_t phys, priorpage = 0, endva; 436 u_int dma_pgmsk = (chan & 4) ? ~(128*1024-1) : ~(64*1024-1); 437 438 GIANT_REQUIRED; 439 440 endva = (vm_offset_t)round_page((vm_offset_t)va + length); 441 for (; va < (caddr_t) endva ; va += PAGE_SIZE) { 442 phys = trunc_page(pmap_extract(pmap_kernel(), (vm_offset_t)va)); 443#ifdef EPSON_BOUNCEDMA 444#define ISARAM_END 0xf00000 445#else 446#define ISARAM_END RAM_END 447#endif 448 if (phys == 0) 449 panic("isa_dmacheck: no physical page present"); 450 if (phys >= ISARAM_END) 451 return (1); 452 if (priorpage) { 453 if (priorpage + PAGE_SIZE != phys) 454 return (1); 455 /* check if crossing a DMA page boundary */ 456 if (((u_int)priorpage ^ (u_int)phys) & dma_pgmsk) 457 return (1); 458 } 459 priorpage = phys; 460 } 461 return (0); 462} 463 464/* 465 * Query the progress of a transfer on a DMA channel. 466 * 467 * To avoid having to interrupt a transfer in progress, we sample 468 * each of the high and low databytes twice, and apply the following 469 * logic to determine the correct count. 470 * 471 * Reads are performed with interrupts disabled, thus it is to be 472 * expected that the time between reads is very small. At most 473 * one rollover in the low count byte can be expected within the 474 * four reads that are performed. 475 * 476 * There are three gaps in which a rollover can occur : 477 * 478 * - read low1 479 * gap1 480 * - read high1 481 * gap2 482 * - read low2 483 * gap3 484 * - read high2 485 * 486 * If a rollover occurs in gap1 or gap2, the low2 value will be 487 * greater than the low1 value. In this case, low2 and high2 are a 488 * corresponding pair. 489 * 490 * In any other case, low1 and high1 can be considered to be correct. 491 * 492 * The function returns the number of bytes remaining in the transfer, 493 * or -1 if the channel requested is not active. 494 * 495 */ 496int 497isa_dmastatus(int chan) 498{ 499 u_long cnt = 0; 500 int ffport, waport; 501 u_long low1, high1, low2, high2; 502 503 /* channel active? */ 504 if ((dma_inuse & (1 << chan)) == 0) { 505 printf("isa_dmastatus: channel %d not active\n", chan); 506 return(-1); 507 } 508 /* channel busy? */ 509 510 if (((dma_busy & (1 << chan)) == 0) && 511 (dma_auto_mode & (1 << chan)) == 0 ) { 512 printf("chan %d not busy\n", chan); 513 return -2 ; 514 } 515#ifdef PC98 516 ffport = DMA1_FFC; 517 waport = DMA1_CHN(chan) + 2; 518#else 519 if (chan < 4) { /* low DMA controller */ 520 ffport = DMA1_FFC; 521 waport = DMA1_CHN(chan) + 1; 522 } else { /* high DMA controller */ 523 ffport = DMA2_FFC; 524 waport = DMA2_CHN(chan - 4) + 2; 525 } 526#endif 527 528 disable_intr(); /* no interrupts Mr Jones! */ 529 outb(ffport, 0); /* clear register LSB flipflop */ 530 low1 = inb(waport); 531 high1 = inb(waport); 532 outb(ffport, 0); /* clear again */ 533 low2 = inb(waport); 534 high2 = inb(waport); 535 enable_intr(); /* enable interrupts again */ 536 537 /* 538 * Now decide if a wrap has tried to skew our results. 539 * Note that after TC, the count will read 0xffff, while we want 540 * to return zero, so we add and then mask to compensate. 541 */ 542 if (low1 >= low2) { 543 cnt = (low1 + (high1 << 8) + 1) & 0xffff; 544 } else { 545 cnt = (low2 + (high2 << 8) + 1) & 0xffff; 546 } 547 548 if (chan >= 4) /* high channels move words */ 549 cnt *= 2; 550 return(cnt); 551} 552 553/* 554 * Stop a DMA transfer currently in progress. 555 */ 556int 557isa_dmastop(int chan) 558{ 559 if ((dma_inuse & (1 << chan)) == 0) 560 printf("isa_dmastop: channel %d not acquired\n", chan); 561 562 if (((dma_busy & (1 << chan)) == 0) && 563 ((dma_auto_mode & (1 << chan)) == 0)) { 564 printf("chan %d not busy\n", chan); 565 return -2 ; 566 } 567 568 if ((chan & 4) == 0) { 569 outb(DMA1_SMSK, (chan & 3) | 4 /* disable mask */); 570 } else { 571#ifndef PC98 572 outb(DMA2_SMSK, (chan & 3) | 4 /* disable mask */); 573#endif 574 } 575 return(isa_dmastatus(chan)); 576} 577 578/* 579 * Attach to the ISA PnP descriptor for the AT DMA controller 580 */ 581static struct isa_pnp_id atdma_ids[] = { 582 { 0x0002d041 /* PNP0200 */, "AT DMA controller" }, 583 { 0 } 584}; 585 586static int 587atdma_probe(device_t dev) 588{ 589 int result; 590 591 if ((result = ISA_PNP_PROBE(device_get_parent(dev), dev, atdma_ids)) <= 0) 592 device_quiet(dev); 593 return(result); 594} 595 596static int 597atdma_attach(device_t dev) 598{ 599 return(0); 600} 601 602static device_method_t atdma_methods[] = { 603 /* Device interface */ 604 DEVMETHOD(device_probe, atdma_probe), 605 DEVMETHOD(device_attach, atdma_attach), 606 DEVMETHOD(device_detach, bus_generic_detach), 607 DEVMETHOD(device_shutdown, bus_generic_shutdown), 608 DEVMETHOD(device_suspend, bus_generic_suspend), 609 DEVMETHOD(device_resume, bus_generic_resume), 610 { 0, 0 } 611}; 612 613static driver_t atdma_driver = { 614 "atdma", 615 atdma_methods, 616 1, /* no softc */ 617}; 618 619static devclass_t atdma_devclass; 620 621DRIVER_MODULE(atdma, isa, atdma_driver, atdma_devclass, 0, 0); 622