cbus_dma.c revision 57973
1/*- 2 * Copyright (c) 1991 The Regents of the University of California. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to Berkeley by 6 * William Jolitz. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by the University of 19 * California, Berkeley and its contributors. 20 * 4. Neither the name of the University nor the names of its contributors 21 * may be used to endorse or promote products derived from this software 22 * without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 * 36 * from: @(#)isa.c 7.2 (Berkeley) 5/13/91 37 * $FreeBSD: head/sys/pc98/cbus/cbus_dma.c 57973 2000-03-13 10:19:32Z phk $ 38 */ 39 40/* 41 * code to manage AT bus 42 * 43 * 92/08/18 Frank P. MacLachlan (fpm@crash.cts.com): 44 * Fixed uninitialized variable problem and added code to deal 45 * with DMA page boundaries in isa_dmarangecheck(). Fixed word 46 * mode DMA count compution and reorganized DMA setup code in 47 * isa_dmastart() 48 */ 49 50#ifdef PC98 51#include "opt_pc98.h" 52#endif 53 54#include <sys/param.h> 55#include <sys/systm.h> 56#include <sys/malloc.h> 57#ifdef PC98 58#include <machine/md_var.h> 59#endif 60#include <vm/vm.h> 61#include <vm/vm_param.h> 62#include <vm/pmap.h> 63#ifdef PC98 64#include <pc98/pc98/pc98.h> 65#else 66#include <i386/isa/isa.h> 67#endif 68#include <i386/isa/isa_dma.h> 69#include <i386/isa/ic/i8237.h> 70 71/* 72** Register definitions for DMA controller 1 (channels 0..3): 73*/ 74#ifdef PC98 75#define DMA1_CHN(c) (IO_DMA + (4*(c))) /* addr reg for channel c */ 76#define DMA1_SMSK (IO_DMA + 0x14) /* single mask register */ 77#define DMA1_MODE (IO_DMA + 0x16) /* mode register */ 78#define DMA1_FFC (IO_DMA + 0x18) /* clear first/last FF */ 79#else 80#define DMA1_CHN(c) (IO_DMA1 + 1*(2*(c))) /* addr reg for channel c */ 81#define DMA1_SMSK (IO_DMA1 + 1*10) /* single mask register */ 82#define DMA1_MODE (IO_DMA1 + 1*11) /* mode register */ 83#define DMA1_FFC (IO_DMA1 + 1*12) /* clear first/last FF */ 84#endif 85 86/* 87** Register definitions for DMA controller 2 (channels 4..7): 88*/ 89#define DMA2_CHN(c) (IO_DMA2 + 2*(2*(c))) /* addr reg for channel c */ 90#define DMA2_SMSK (IO_DMA2 + 2*10) /* single mask register */ 91#define DMA2_MODE (IO_DMA2 + 2*11) /* mode register */ 92#define DMA2_FFC (IO_DMA2 + 2*12) /* clear first/last FF */ 93 94static int isa_dmarangecheck __P((caddr_t va, u_int length, int chan)); 95 96#ifdef PC98 97static caddr_t dma_bouncebuf[4]; 98static u_int dma_bouncebufsize[4]; 99#else 100static caddr_t dma_bouncebuf[8]; 101static u_int dma_bouncebufsize[8]; 102#endif 103static u_int8_t dma_bounced = 0; 104static u_int8_t dma_busy = 0; /* Used in isa_dmastart() */ 105static u_int8_t dma_inuse = 0; /* User for acquire/release */ 106static u_int8_t dma_auto_mode = 0; 107 108#ifdef PC98 109#define VALID_DMA_MASK (3) 110#else 111#define VALID_DMA_MASK (7) 112#endif 113 114/* high byte of address is stored in this port for i-th dma channel */ 115#ifdef PC98 116static int dmapageport[4] = { 0x27, 0x21, 0x23, 0x25 }; 117#else 118static int dmapageport[8] = { 0x87, 0x83, 0x81, 0x82, 0x8f, 0x8b, 0x89, 0x8a }; 119#endif 120 121/* 122 * Setup a DMA channel's bounce buffer. 123 */ 124void 125isa_dmainit(chan, bouncebufsize) 126 int chan; 127 u_int bouncebufsize; 128{ 129 void *buf; 130 131#ifdef DIAGNOSTIC 132 if (chan & ~VALID_DMA_MASK) 133 panic("isa_dmainit: channel out of range"); 134 135 if (dma_bouncebuf[chan] != NULL) 136 panic("isa_dmainit: impossible request"); 137#endif 138 139 dma_bouncebufsize[chan] = bouncebufsize; 140 141 /* Try malloc() first. It works better if it works. */ 142 buf = malloc(bouncebufsize, M_DEVBUF, M_NOWAIT); 143 if (buf != NULL) { 144 if (isa_dmarangecheck(buf, bouncebufsize, chan) == 0) { 145 dma_bouncebuf[chan] = buf; 146 return; 147 } 148 free(buf, M_DEVBUF); 149 } 150 buf = contigmalloc(bouncebufsize, M_DEVBUF, M_NOWAIT, 0ul, 0xfffffful, 151 1ul, chan & 4 ? 0x20000ul : 0x10000ul); 152 if (buf == NULL) 153 printf("isa_dmainit(%d, %d) failed\n", chan, bouncebufsize); 154 else 155 dma_bouncebuf[chan] = buf; 156} 157 158/* 159 * Register a DMA channel's usage. Usually called from a device driver 160 * in open() or during its initialization. 161 */ 162int 163isa_dma_acquire(chan) 164 int chan; 165{ 166#ifdef DIAGNOSTIC 167 if (chan & ~VALID_DMA_MASK) 168 panic("isa_dma_acquire: channel out of range"); 169#endif 170 171 if (dma_inuse & (1 << chan)) { 172 printf("isa_dma_acquire: channel %d already in use\n", chan); 173 return (EBUSY); 174 } 175 dma_inuse |= (1 << chan); 176 dma_auto_mode &= ~(1 << chan); 177 178 return (0); 179} 180 181/* 182 * Unregister a DMA channel's usage. Usually called from a device driver 183 * during close() or during its shutdown. 184 */ 185void 186isa_dma_release(chan) 187 int chan; 188{ 189#ifdef DIAGNOSTIC 190 if (chan & ~VALID_DMA_MASK) 191 panic("isa_dma_release: channel out of range"); 192 193 if ((dma_inuse & (1 << chan)) == 0) 194 printf("isa_dma_release: channel %d not in use\n", chan); 195#endif 196 197 if (dma_busy & (1 << chan)) { 198 dma_busy &= ~(1 << chan); 199 /* 200 * XXX We should also do "dma_bounced &= (1 << chan);" 201 * because we are acting on behalf of isa_dmadone() which 202 * was not called to end the last DMA operation. This does 203 * not matter now, but it may in the future. 204 */ 205 } 206 207 dma_inuse &= ~(1 << chan); 208 dma_auto_mode &= ~(1 << chan); 209} 210 211#ifndef PC98 212/* 213 * isa_dmacascade(): program 8237 DMA controller channel to accept 214 * external dma control by a board. 215 */ 216void 217isa_dmacascade(chan) 218 int chan; 219{ 220#ifdef DIAGNOSTIC 221 if (chan & ~VALID_DMA_MASK) 222 panic("isa_dmacascade: channel out of range"); 223#endif 224 225 /* set dma channel mode, and set dma channel mode */ 226 if ((chan & 4) == 0) { 227 outb(DMA1_MODE, DMA37MD_CASCADE | chan); 228 outb(DMA1_SMSK, chan); 229 } else { 230 outb(DMA2_MODE, DMA37MD_CASCADE | (chan & 3)); 231 outb(DMA2_SMSK, chan & 3); 232 } 233} 234#endif 235 236/* 237 * isa_dmastart(): program 8237 DMA controller channel, avoid page alignment 238 * problems by using a bounce buffer. 239 */ 240void 241isa_dmastart(int flags, caddr_t addr, u_int nbytes, int chan) 242{ 243 vm_offset_t phys; 244 int waport; 245 caddr_t newaddr; 246 247#ifdef DIAGNOSTIC 248 if (chan & ~VALID_DMA_MASK) 249 panic("isa_dmastart: channel out of range"); 250 251 if ((chan < 4 && nbytes > (1<<16)) 252 || (chan >= 4 && (nbytes > (1<<17) || (u_int)addr & 1))) 253 panic("isa_dmastart: impossible request"); 254 255 if ((dma_inuse & (1 << chan)) == 0) 256 printf("isa_dmastart: channel %d not acquired\n", chan); 257#endif 258 259#if 0 260 /* 261 * XXX This should be checked, but drivers like ad1848 only call 262 * isa_dmastart() once because they use Auto DMA mode. If we 263 * leave this in, drivers that do this will print this continuously. 264 */ 265 if (dma_busy & (1 << chan)) 266 printf("isa_dmastart: channel %d busy\n", chan); 267#endif 268 269 dma_busy |= (1 << chan); 270 271 if (isa_dmarangecheck(addr, nbytes, chan)) { 272 if (dma_bouncebuf[chan] == NULL 273 || dma_bouncebufsize[chan] < nbytes) 274 panic("isa_dmastart: bad bounce buffer"); 275 dma_bounced |= (1 << chan); 276 newaddr = dma_bouncebuf[chan]; 277 278 /* copy bounce buffer on write */ 279 if (!(flags & ISADMA_READ)) 280 bcopy(addr, newaddr, nbytes); 281 addr = newaddr; 282 } 283 284 /* translate to physical */ 285 phys = pmap_extract(pmap_kernel(), (vm_offset_t)addr); 286 287 if (flags & ISADMA_RAW) { 288 dma_auto_mode |= (1 << chan); 289 } else { 290 dma_auto_mode &= ~(1 << chan); 291 } 292 293#ifdef PC98 294 if (need_pre_dma_flush) 295 wbinvd(); /* wbinvd (WB cache flush) */ 296#endif 297 298#ifndef PC98 299 if ((chan & 4) == 0) { 300 /* 301 * Program one of DMA channels 0..3. These are 302 * byte mode channels. 303 */ 304#endif 305 /* set dma channel mode, and reset address ff */ 306 307 /* If ISADMA_RAW flag is set, then use autoinitialise mode */ 308 if (flags & ISADMA_RAW) { 309 if (flags & ISADMA_READ) 310 outb(DMA1_MODE, DMA37MD_AUTO|DMA37MD_WRITE|chan); 311 else 312 outb(DMA1_MODE, DMA37MD_AUTO|DMA37MD_READ|chan); 313 } 314 else 315 if (flags & ISADMA_READ) 316 outb(DMA1_MODE, DMA37MD_SINGLE|DMA37MD_WRITE|chan); 317 else 318 outb(DMA1_MODE, DMA37MD_SINGLE|DMA37MD_READ|chan); 319 outb(DMA1_FFC, 0); 320 321 /* send start address */ 322 waport = DMA1_CHN(chan); 323 outb(waport, phys); 324 outb(waport, phys>>8); 325 outb(dmapageport[chan], phys>>16); 326 327 /* send count */ 328#ifdef PC98 329 outb(waport + 2, --nbytes); 330 outb(waport + 2, nbytes>>8); 331#else 332 outb(waport + 1, --nbytes); 333 outb(waport + 1, nbytes>>8); 334#endif 335 336 /* unmask channel */ 337 outb(DMA1_SMSK, chan); 338#ifndef PC98 339 } else { 340 /* 341 * Program one of DMA channels 4..7. These are 342 * word mode channels. 343 */ 344 /* set dma channel mode, and reset address ff */ 345 346 /* If ISADMA_RAW flag is set, then use autoinitialise mode */ 347 if (flags & ISADMA_RAW) { 348 if (flags & ISADMA_READ) 349 outb(DMA2_MODE, DMA37MD_AUTO|DMA37MD_WRITE|(chan&3)); 350 else 351 outb(DMA2_MODE, DMA37MD_AUTO|DMA37MD_READ|(chan&3)); 352 } 353 else 354 if (flags & ISADMA_READ) 355 outb(DMA2_MODE, DMA37MD_SINGLE|DMA37MD_WRITE|(chan&3)); 356 else 357 outb(DMA2_MODE, DMA37MD_SINGLE|DMA37MD_READ|(chan&3)); 358 outb(DMA2_FFC, 0); 359 360 /* send start address */ 361 waport = DMA2_CHN(chan - 4); 362 outb(waport, phys>>1); 363 outb(waport, phys>>9); 364 outb(dmapageport[chan], phys>>16); 365 366 /* send count */ 367 nbytes >>= 1; 368 outb(waport + 2, --nbytes); 369 outb(waport + 2, nbytes>>8); 370 371 /* unmask channel */ 372 outb(DMA2_SMSK, chan & 3); 373 } 374#endif 375} 376 377void 378isa_dmadone(int flags, caddr_t addr, int nbytes, int chan) 379{ 380#ifdef PC98 381 if (flags & ISADMA_READ) { 382 /* cache flush only after reading 92/12/9 by A.Kojima */ 383 if (need_post_dma_flush) 384 invd(); 385 } 386#endif 387 388#ifdef DIAGNOSTIC 389 if (chan & ~VALID_DMA_MASK) 390 panic("isa_dmadone: channel out of range"); 391 392 if ((dma_inuse & (1 << chan)) == 0) 393 printf("isa_dmadone: channel %d not acquired\n", chan); 394#endif 395 396 if (((dma_busy & (1 << chan)) == 0) && 397 (dma_auto_mode & (1 << chan)) == 0 ) 398 printf("isa_dmadone: channel %d not busy\n", chan); 399 400#ifdef PC98 401 if ((dma_auto_mode & (1 << chan)) == 0) 402 outb(DMA1_SMSK, (chan & 3) | 4); 403#else 404 if ((dma_auto_mode & (1 << chan)) == 0) 405 outb(chan & 4 ? DMA2_SMSK : DMA1_SMSK, (chan & 3) | 4); 406#endif 407 408 if (dma_bounced & (1 << chan)) { 409 /* copy bounce buffer on read */ 410 if (flags & ISADMA_READ) 411 bcopy(dma_bouncebuf[chan], addr, nbytes); 412 413 dma_bounced &= ~(1 << chan); 414 } 415 dma_busy &= ~(1 << chan); 416} 417 418/* 419 * Check for problems with the address range of a DMA transfer 420 * (non-contiguous physical pages, outside of bus address space, 421 * crossing DMA page boundaries). 422 * Return true if special handling needed. 423 */ 424 425static int 426isa_dmarangecheck(caddr_t va, u_int length, int chan) 427{ 428 vm_offset_t phys, priorpage = 0, endva; 429 u_int dma_pgmsk = (chan & 4) ? ~(128*1024-1) : ~(64*1024-1); 430 431 endva = (vm_offset_t)round_page((vm_offset_t)va + length); 432 for (; va < (caddr_t) endva ; va += PAGE_SIZE) { 433 phys = trunc_page(pmap_extract(pmap_kernel(), (vm_offset_t)va)); 434#ifdef EPSON_BOUNCEDMA 435#define ISARAM_END 0xf00000 436#else 437#define ISARAM_END RAM_END 438#endif 439 if (phys == 0) 440 panic("isa_dmacheck: no physical page present"); 441 if (phys >= ISARAM_END) 442 return (1); 443 if (priorpage) { 444 if (priorpage + PAGE_SIZE != phys) 445 return (1); 446 /* check if crossing a DMA page boundary */ 447 if (((u_int)priorpage ^ (u_int)phys) & dma_pgmsk) 448 return (1); 449 } 450 priorpage = phys; 451 } 452 return (0); 453} 454 455/* 456 * Query the progress of a transfer on a DMA channel. 457 * 458 * To avoid having to interrupt a transfer in progress, we sample 459 * each of the high and low databytes twice, and apply the following 460 * logic to determine the correct count. 461 * 462 * Reads are performed with interrupts disabled, thus it is to be 463 * expected that the time between reads is very small. At most 464 * one rollover in the low count byte can be expected within the 465 * four reads that are performed. 466 * 467 * There are three gaps in which a rollover can occur : 468 * 469 * - read low1 470 * gap1 471 * - read high1 472 * gap2 473 * - read low2 474 * gap3 475 * - read high2 476 * 477 * If a rollover occurs in gap1 or gap2, the low2 value will be 478 * greater than the low1 value. In this case, low2 and high2 are a 479 * corresponding pair. 480 * 481 * In any other case, low1 and high1 can be considered to be correct. 482 * 483 * The function returns the number of bytes remaining in the transfer, 484 * or -1 if the channel requested is not active. 485 * 486 */ 487int 488isa_dmastatus(int chan) 489{ 490 u_long cnt = 0; 491 int ffport, waport; 492 u_long low1, high1, low2, high2; 493 494 /* channel active? */ 495 if ((dma_inuse & (1 << chan)) == 0) { 496 printf("isa_dmastatus: channel %d not active\n", chan); 497 return(-1); 498 } 499 /* channel busy? */ 500 501 if (((dma_busy & (1 << chan)) == 0) && 502 (dma_auto_mode & (1 << chan)) == 0 ) { 503 printf("chan %d not busy\n", chan); 504 return -2 ; 505 } 506#ifdef PC98 507 ffport = DMA1_FFC; 508 waport = DMA1_CHN(chan) + 2; 509#else 510 if (chan < 4) { /* low DMA controller */ 511 ffport = DMA1_FFC; 512 waport = DMA1_CHN(chan) + 1; 513 } else { /* high DMA controller */ 514 ffport = DMA2_FFC; 515 waport = DMA2_CHN(chan - 4) + 2; 516 } 517#endif 518 519 disable_intr(); /* no interrupts Mr Jones! */ 520 outb(ffport, 0); /* clear register LSB flipflop */ 521 low1 = inb(waport); 522 high1 = inb(waport); 523 outb(ffport, 0); /* clear again */ 524 low2 = inb(waport); 525 high2 = inb(waport); 526 enable_intr(); /* enable interrupts again */ 527 528 /* 529 * Now decide if a wrap has tried to skew our results. 530 * Note that after TC, the count will read 0xffff, while we want 531 * to return zero, so we add and then mask to compensate. 532 */ 533 if (low1 >= low2) { 534 cnt = (low1 + (high1 << 8) + 1) & 0xffff; 535 } else { 536 cnt = (low2 + (high2 << 8) + 1) & 0xffff; 537 } 538 539 if (chan >= 4) /* high channels move words */ 540 cnt *= 2; 541 return(cnt); 542} 543 544/* 545 * Stop a DMA transfer currently in progress. 546 */ 547int 548isa_dmastop(int chan) 549{ 550 if ((dma_inuse & (1 << chan)) == 0) 551 printf("isa_dmastop: channel %d not acquired\n", chan); 552 553 if (((dma_busy & (1 << chan)) == 0) && 554 ((dma_auto_mode & (1 << chan)) == 0)) { 555 printf("chan %d not busy\n", chan); 556 return -2 ; 557 } 558 559 if ((chan & 4) == 0) { 560 outb(DMA1_SMSK, (chan & 3) | 4 /* disable mask */); 561 } else { 562#ifndef PC98 563 outb(DMA2_SMSK, (chan & 3) | 4 /* disable mask */); 564#endif 565 } 566 return(isa_dmastatus(chan)); 567} 568