cbus_dma.c revision 53121
1/*- 2 * Copyright (c) 1991 The Regents of the University of California. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to Berkeley by 6 * William Jolitz. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by the University of 19 * California, Berkeley and its contributors. 20 * 4. Neither the name of the University nor the names of its contributors 21 * may be used to endorse or promote products derived from this software 22 * without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 * 36 * from: @(#)isa.c 7.2 (Berkeley) 5/13/91 37 * $FreeBSD: head/sys/pc98/cbus/cbus_dma.c 53121 1999-11-13 14:09:08Z nyan $ 38 */ 39 40/* 41 * code to manage AT bus 42 * 43 * 92/08/18 Frank P. MacLachlan (fpm@crash.cts.com): 44 * Fixed uninitialized variable problem and added code to deal 45 * with DMA page boundaries in isa_dmarangecheck(). Fixed word 46 * mode DMA count compution and reorganized DMA setup code in 47 * isa_dmastart() 48 */ 49 50#ifdef PC98 51#include "opt_pc98.h" 52#endif 53 54#include <sys/param.h> 55#include <sys/systm.h> 56#include <sys/buf.h> /* B_READ and B_RAW */ 57#include <sys/malloc.h> 58#ifdef PC98 59#include <machine/md_var.h> 60#endif 61#include <vm/vm.h> 62#include <vm/vm_param.h> 63#include <vm/pmap.h> 64#ifdef PC98 65#include <pc98/pc98/pc98.h> 66#else 67#include <i386/isa/isa.h> 68#endif 69#include <i386/isa/isa_dma.h> 70#include <i386/isa/ic/i8237.h> 71 72/* 73** Register definitions for DMA controller 1 (channels 0..3): 74*/ 75#ifdef PC98 76#define DMA1_CHN(c) (IO_DMA + (4*(c))) /* addr reg for channel c */ 77#define DMA1_SMSK (IO_DMA + 0x14) /* single mask register */ 78#define DMA1_MODE (IO_DMA + 0x16) /* mode register */ 79#define DMA1_FFC (IO_DMA + 0x18) /* clear first/last FF */ 80#else 81#define DMA1_CHN(c) (IO_DMA1 + 1*(2*(c))) /* addr reg for channel c */ 82#define DMA1_SMSK (IO_DMA1 + 1*10) /* single mask register */ 83#define DMA1_MODE (IO_DMA1 + 1*11) /* mode register */ 84#define DMA1_FFC (IO_DMA1 + 1*12) /* clear first/last FF */ 85#endif 86 87/* 88** Register definitions for DMA controller 2 (channels 4..7): 89*/ 90#define DMA2_CHN(c) (IO_DMA2 + 2*(2*(c))) /* addr reg for channel c */ 91#define DMA2_SMSK (IO_DMA2 + 2*10) /* single mask register */ 92#define DMA2_MODE (IO_DMA2 + 2*11) /* mode register */ 93#define DMA2_FFC (IO_DMA2 + 2*12) /* clear first/last FF */ 94 95static int isa_dmarangecheck __P((caddr_t va, u_int length, int chan)); 96 97#ifdef PC98 98static caddr_t dma_bouncebuf[4]; 99static u_int dma_bouncebufsize[4]; 100#else 101static caddr_t dma_bouncebuf[8]; 102static u_int dma_bouncebufsize[8]; 103#endif 104static u_int8_t dma_bounced = 0; 105static u_int8_t dma_busy = 0; /* Used in isa_dmastart() */ 106static u_int8_t dma_inuse = 0; /* User for acquire/release */ 107static u_int8_t dma_auto_mode = 0; 108 109#ifdef PC98 110#define VALID_DMA_MASK (3) 111#else 112#define VALID_DMA_MASK (7) 113#endif 114 115/* high byte of address is stored in this port for i-th dma channel */ 116#ifdef PC98 117static int dmapageport[4] = { 0x27, 0x21, 0x23, 0x25 }; 118#else 119static int dmapageport[8] = { 0x87, 0x83, 0x81, 0x82, 0x8f, 0x8b, 0x89, 0x8a }; 120#endif 121 122/* 123 * Setup a DMA channel's bounce buffer. 124 */ 125void 126isa_dmainit(chan, bouncebufsize) 127 int chan; 128 u_int bouncebufsize; 129{ 130 void *buf; 131 132#ifdef DIAGNOSTIC 133 if (chan & ~VALID_DMA_MASK) 134 panic("isa_dmainit: channel out of range"); 135 136 if (dma_bouncebuf[chan] != NULL) 137 panic("isa_dmainit: impossible request"); 138#endif 139 140 dma_bouncebufsize[chan] = bouncebufsize; 141 142 /* Try malloc() first. It works better if it works. */ 143 buf = malloc(bouncebufsize, M_DEVBUF, M_NOWAIT); 144 if (buf != NULL) { 145 if (isa_dmarangecheck(buf, bouncebufsize, chan) == 0) { 146 dma_bouncebuf[chan] = buf; 147 return; 148 } 149 free(buf, M_DEVBUF); 150 } 151 buf = contigmalloc(bouncebufsize, M_DEVBUF, M_NOWAIT, 0ul, 0xfffffful, 152 1ul, chan & 4 ? 0x20000ul : 0x10000ul); 153 if (buf == NULL) 154 printf("isa_dmainit(%d, %d) failed\n", chan, bouncebufsize); 155 else 156 dma_bouncebuf[chan] = buf; 157} 158 159/* 160 * Register a DMA channel's usage. Usually called from a device driver 161 * in open() or during its initialization. 162 */ 163int 164isa_dma_acquire(chan) 165 int chan; 166{ 167#ifdef DIAGNOSTIC 168 if (chan & ~VALID_DMA_MASK) 169 panic("isa_dma_acquire: channel out of range"); 170#endif 171 172 if (dma_inuse & (1 << chan)) { 173 printf("isa_dma_acquire: channel %d already in use\n", chan); 174 return (EBUSY); 175 } 176 dma_inuse |= (1 << chan); 177 dma_auto_mode &= ~(1 << chan); 178 179 return (0); 180} 181 182/* 183 * Unregister a DMA channel's usage. Usually called from a device driver 184 * during close() or during its shutdown. 185 */ 186void 187isa_dma_release(chan) 188 int chan; 189{ 190#ifdef DIAGNOSTIC 191 if (chan & ~VALID_DMA_MASK) 192 panic("isa_dma_release: channel out of range"); 193 194 if ((dma_inuse & (1 << chan)) == 0) 195 printf("isa_dma_release: channel %d not in use\n", chan); 196#endif 197 198 if (dma_busy & (1 << chan)) { 199 dma_busy &= ~(1 << chan); 200 /* 201 * XXX We should also do "dma_bounced &= (1 << chan);" 202 * because we are acting on behalf of isa_dmadone() which 203 * was not called to end the last DMA operation. This does 204 * not matter now, but it may in the future. 205 */ 206 } 207 208 dma_inuse &= ~(1 << chan); 209 dma_auto_mode &= ~(1 << chan); 210} 211 212#ifndef PC98 213/* 214 * isa_dmacascade(): program 8237 DMA controller channel to accept 215 * external dma control by a board. 216 */ 217void 218isa_dmacascade(chan) 219 int chan; 220{ 221#ifdef DIAGNOSTIC 222 if (chan & ~VALID_DMA_MASK) 223 panic("isa_dmacascade: channel out of range"); 224#endif 225 226 /* set dma channel mode, and set dma channel mode */ 227 if ((chan & 4) == 0) { 228 outb(DMA1_MODE, DMA37MD_CASCADE | chan); 229 outb(DMA1_SMSK, chan); 230 } else { 231 outb(DMA2_MODE, DMA37MD_CASCADE | (chan & 3)); 232 outb(DMA2_SMSK, chan & 3); 233 } 234} 235#endif 236 237/* 238 * isa_dmastart(): program 8237 DMA controller channel, avoid page alignment 239 * problems by using a bounce buffer. 240 */ 241void 242isa_dmastart(int flags, caddr_t addr, u_int nbytes, int chan) 243{ 244 vm_offset_t phys; 245 int waport; 246 caddr_t newaddr; 247 248#ifdef DIAGNOSTIC 249 if (chan & ~VALID_DMA_MASK) 250 panic("isa_dmastart: channel out of range"); 251 252 if ((chan < 4 && nbytes > (1<<16)) 253 || (chan >= 4 && (nbytes > (1<<17) || (u_int)addr & 1))) 254 panic("isa_dmastart: impossible request"); 255 256 if ((dma_inuse & (1 << chan)) == 0) 257 printf("isa_dmastart: channel %d not acquired\n", chan); 258#endif 259 260#if 0 261 /* 262 * XXX This should be checked, but drivers like ad1848 only call 263 * isa_dmastart() once because they use Auto DMA mode. If we 264 * leave this in, drivers that do this will print this continuously. 265 */ 266 if (dma_busy & (1 << chan)) 267 printf("isa_dmastart: channel %d busy\n", chan); 268#endif 269 270 dma_busy |= (1 << chan); 271 272 if (isa_dmarangecheck(addr, nbytes, chan)) { 273 if (dma_bouncebuf[chan] == NULL 274 || dma_bouncebufsize[chan] < nbytes) 275 panic("isa_dmastart: bad bounce buffer"); 276 dma_bounced |= (1 << chan); 277 newaddr = dma_bouncebuf[chan]; 278 279 /* copy bounce buffer on write */ 280 if (!(flags & B_READ)) 281 bcopy(addr, newaddr, nbytes); 282 addr = newaddr; 283 } 284 285 /* translate to physical */ 286 phys = pmap_extract(pmap_kernel(), (vm_offset_t)addr); 287 288 if (flags & B_RAW) { 289 dma_auto_mode |= (1 << chan); 290 } else { 291 dma_auto_mode &= ~(1 << chan); 292 } 293 294#ifdef PC98 295 if (need_pre_dma_flush) 296 wbinvd(); /* wbinvd (WB cache flush) */ 297#endif 298 299#ifndef PC98 300 if ((chan & 4) == 0) { 301 /* 302 * Program one of DMA channels 0..3. These are 303 * byte mode channels. 304 */ 305#endif 306 /* set dma channel mode, and reset address ff */ 307 308 /* If B_RAW flag is set, then use autoinitialise mode */ 309 if (flags & B_RAW) { 310 if (flags & B_READ) 311 outb(DMA1_MODE, DMA37MD_AUTO|DMA37MD_WRITE|chan); 312 else 313 outb(DMA1_MODE, DMA37MD_AUTO|DMA37MD_READ|chan); 314 } 315 else 316 if (flags & B_READ) 317 outb(DMA1_MODE, DMA37MD_SINGLE|DMA37MD_WRITE|chan); 318 else 319 outb(DMA1_MODE, DMA37MD_SINGLE|DMA37MD_READ|chan); 320 outb(DMA1_FFC, 0); 321 322 /* send start address */ 323 waport = DMA1_CHN(chan); 324 outb(waport, phys); 325 outb(waport, phys>>8); 326 outb(dmapageport[chan], phys>>16); 327 328 /* send count */ 329#ifdef PC98 330 outb(waport + 2, --nbytes); 331 outb(waport + 2, nbytes>>8); 332#else 333 outb(waport + 1, --nbytes); 334 outb(waport + 1, nbytes>>8); 335#endif 336 337 /* unmask channel */ 338 outb(DMA1_SMSK, chan); 339#ifndef PC98 340 } else { 341 /* 342 * Program one of DMA channels 4..7. These are 343 * word mode channels. 344 */ 345 /* set dma channel mode, and reset address ff */ 346 347 /* If B_RAW flag is set, then use autoinitialise mode */ 348 if (flags & B_RAW) { 349 if (flags & B_READ) 350 outb(DMA2_MODE, DMA37MD_AUTO|DMA37MD_WRITE|(chan&3)); 351 else 352 outb(DMA2_MODE, DMA37MD_AUTO|DMA37MD_READ|(chan&3)); 353 } 354 else 355 if (flags & B_READ) 356 outb(DMA2_MODE, DMA37MD_SINGLE|DMA37MD_WRITE|(chan&3)); 357 else 358 outb(DMA2_MODE, DMA37MD_SINGLE|DMA37MD_READ|(chan&3)); 359 outb(DMA2_FFC, 0); 360 361 /* send start address */ 362 waport = DMA2_CHN(chan - 4); 363 outb(waport, phys>>1); 364 outb(waport, phys>>9); 365 outb(dmapageport[chan], phys>>16); 366 367 /* send count */ 368 nbytes >>= 1; 369 outb(waport + 2, --nbytes); 370 outb(waport + 2, nbytes>>8); 371 372 /* unmask channel */ 373 outb(DMA2_SMSK, chan & 3); 374 } 375#endif 376} 377 378void 379isa_dmadone(int flags, caddr_t addr, int nbytes, int chan) 380{ 381#ifdef PC98 382 if (flags & B_READ) { 383 /* cache flush only after reading 92/12/9 by A.Kojima */ 384 if (need_post_dma_flush) 385 invd(); 386 } 387#endif 388 389#ifdef DIAGNOSTIC 390 if (chan & ~VALID_DMA_MASK) 391 panic("isa_dmadone: channel out of range"); 392 393 if ((dma_inuse & (1 << chan)) == 0) 394 printf("isa_dmadone: channel %d not acquired\n", chan); 395#endif 396 397 if (((dma_busy & (1 << chan)) == 0) && 398 (dma_auto_mode & (1 << chan)) == 0 ) 399 printf("isa_dmadone: channel %d not busy\n", chan); 400 401#ifdef PC98 402 if ((dma_auto_mode & (1 << chan)) == 0) 403 outb(DMA1_SMSK, (chan & 3) | 4); 404#else 405 if ((dma_auto_mode & (1 << chan)) == 0) 406 outb(chan & 4 ? DMA2_SMSK : DMA1_SMSK, (chan & 3) | 4); 407#endif 408 409 if (dma_bounced & (1 << chan)) { 410 /* copy bounce buffer on read */ 411 if (flags & B_READ) 412 bcopy(dma_bouncebuf[chan], addr, nbytes); 413 414 dma_bounced &= ~(1 << chan); 415 } 416 dma_busy &= ~(1 << chan); 417} 418 419/* 420 * Check for problems with the address range of a DMA transfer 421 * (non-contiguous physical pages, outside of bus address space, 422 * crossing DMA page boundaries). 423 * Return true if special handling needed. 424 */ 425 426static int 427isa_dmarangecheck(caddr_t va, u_int length, int chan) 428{ 429 vm_offset_t phys, priorpage = 0, endva; 430 u_int dma_pgmsk = (chan & 4) ? ~(128*1024-1) : ~(64*1024-1); 431 432 endva = (vm_offset_t)round_page((vm_offset_t)va + length); 433 for (; va < (caddr_t) endva ; va += PAGE_SIZE) { 434 phys = trunc_page(pmap_extract(pmap_kernel(), (vm_offset_t)va)); 435#ifdef EPSON_BOUNCEDMA 436#define ISARAM_END 0xf00000 437#else 438#define ISARAM_END RAM_END 439#endif 440 if (phys == 0) 441 panic("isa_dmacheck: no physical page present"); 442 if (phys >= ISARAM_END) 443 return (1); 444 if (priorpage) { 445 if (priorpage + PAGE_SIZE != phys) 446 return (1); 447 /* check if crossing a DMA page boundary */ 448 if (((u_int)priorpage ^ (u_int)phys) & dma_pgmsk) 449 return (1); 450 } 451 priorpage = phys; 452 } 453 return (0); 454} 455 456/* 457 * Query the progress of a transfer on a DMA channel. 458 * 459 * To avoid having to interrupt a transfer in progress, we sample 460 * each of the high and low databytes twice, and apply the following 461 * logic to determine the correct count. 462 * 463 * Reads are performed with interrupts disabled, thus it is to be 464 * expected that the time between reads is very small. At most 465 * one rollover in the low count byte can be expected within the 466 * four reads that are performed. 467 * 468 * There are three gaps in which a rollover can occur : 469 * 470 * - read low1 471 * gap1 472 * - read high1 473 * gap2 474 * - read low2 475 * gap3 476 * - read high2 477 * 478 * If a rollover occurs in gap1 or gap2, the low2 value will be 479 * greater than the low1 value. In this case, low2 and high2 are a 480 * corresponding pair. 481 * 482 * In any other case, low1 and high1 can be considered to be correct. 483 * 484 * The function returns the number of bytes remaining in the transfer, 485 * or -1 if the channel requested is not active. 486 * 487 */ 488int 489isa_dmastatus(int chan) 490{ 491 u_long cnt = 0; 492 int ffport, waport; 493 u_long low1, high1, low2, high2; 494 495 /* channel active? */ 496 if ((dma_inuse & (1 << chan)) == 0) { 497 printf("isa_dmastatus: channel %d not active\n", chan); 498 return(-1); 499 } 500 /* channel busy? */ 501 502 if (((dma_busy & (1 << chan)) == 0) && 503 (dma_auto_mode & (1 << chan)) == 0 ) { 504 printf("chan %d not busy\n", chan); 505 return -2 ; 506 } 507#ifdef PC98 508 ffport = DMA1_FFC; 509 waport = DMA1_CHN(chan) + 2; 510#else 511 if (chan < 4) { /* low DMA controller */ 512 ffport = DMA1_FFC; 513 waport = DMA1_CHN(chan) + 1; 514 } else { /* high DMA controller */ 515 ffport = DMA2_FFC; 516 waport = DMA2_CHN(chan - 4) + 2; 517 } 518#endif 519 520 disable_intr(); /* no interrupts Mr Jones! */ 521 outb(ffport, 0); /* clear register LSB flipflop */ 522 low1 = inb(waport); 523 high1 = inb(waport); 524 outb(ffport, 0); /* clear again */ 525 low2 = inb(waport); 526 high2 = inb(waport); 527 enable_intr(); /* enable interrupts again */ 528 529 /* 530 * Now decide if a wrap has tried to skew our results. 531 * Note that after TC, the count will read 0xffff, while we want 532 * to return zero, so we add and then mask to compensate. 533 */ 534 if (low1 >= low2) { 535 cnt = (low1 + (high1 << 8) + 1) & 0xffff; 536 } else { 537 cnt = (low2 + (high2 << 8) + 1) & 0xffff; 538 } 539 540 if (chan >= 4) /* high channels move words */ 541 cnt *= 2; 542 return(cnt); 543} 544 545/* 546 * Stop a DMA transfer currently in progress. 547 */ 548int 549isa_dmastop(int chan) 550{ 551 if ((dma_inuse & (1 << chan)) == 0) 552 printf("isa_dmastop: channel %d not acquired\n", chan); 553 554 if (((dma_busy & (1 << chan)) == 0) && 555 ((dma_auto_mode & (1 << chan)) == 0)) { 556 printf("chan %d not busy\n", chan); 557 return -2 ; 558 } 559 560 if ((chan & 4) == 0) { 561 outb(DMA1_SMSK, (chan & 3) | 4 /* disable mask */); 562 } else { 563#ifndef PC98 564 outb(DMA2_SMSK, (chan & 3) | 4 /* disable mask */); 565#endif 566 } 567 return(isa_dmastatus(chan)); 568} 569