cbus_dma.c revision 48961
1189251Ssam/*- 2189251Ssam * Copyright (c) 1991 The Regents of the University of California. 3189251Ssam * All rights reserved. 4189251Ssam * 5189251Ssam * This code is derived from software contributed to Berkeley by 6189251Ssam * William Jolitz. 7189251Ssam * 8189251Ssam * Redistribution and use in source and binary forms, with or without 9189251Ssam * modification, are permitted provided that the following conditions 10189251Ssam * are met: 11189251Ssam * 1. Redistributions of source code must retain the above copyright 12189251Ssam * notice, this list of conditions and the following disclaimer. 13189251Ssam * 2. Redistributions in binary form must reproduce the above copyright 14189251Ssam * notice, this list of conditions and the following disclaimer in the 15189251Ssam * documentation and/or other materials provided with the distribution. 16189251Ssam * 3. All advertising materials mentioning features or use of this software 17189251Ssam * must display the following acknowledgement: 18214734Srpaulo * This product includes software developed by the University of 19214734Srpaulo * California, Berkeley and its contributors. 20214734Srpaulo * 4. Neither the name of the University nor the names of its contributors 21189251Ssam * may be used to endorse or promote products derived from this software 22189251Ssam * without specific prior written permission. 23189251Ssam * 24189251Ssam * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 25189251Ssam * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26189251Ssam * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27189251Ssam * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 28214734Srpaulo * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29189251Ssam * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 30214734Srpaulo * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31214734Srpaulo * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32189251Ssam * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33189251Ssam * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34214734Srpaulo * SUCH DAMAGE. 35189251Ssam * 36189251Ssam * from: @(#)isa.c 7.2 (Berkeley) 5/13/91 37189251Ssam * $Id: isa_dma.c,v 1.3 1999/05/10 09:09:08 kato Exp $ 38189251Ssam */ 39189251Ssam 40189251Ssam/* 41189251Ssam * code to manage AT bus 42189251Ssam * 43189251Ssam * 92/08/18 Frank P. MacLachlan (fpm@crash.cts.com): 44189251Ssam * Fixed uninitialized variable problem and added code to deal 45189251Ssam * with DMA page boundaries in isa_dmarangecheck(). Fixed word 46189251Ssam * mode DMA count compution and reorganized DMA setup code in 47189251Ssam * isa_dmastart() 48189251Ssam */ 49189251Ssam 50189251Ssam#ifdef PC98 51189251Ssam#include "opt_pc98.h" 52189251Ssam#endif 53189251Ssam 54189251Ssam#include <sys/param.h> 55189251Ssam#include <sys/systm.h> 56189251Ssam#include <sys/buf.h> /* B_READ and B_RAW */ 57214734Srpaulo#include <sys/malloc.h> 58189251Ssam#ifdef PC98 59189251Ssam#include <machine/md_var.h> 60189251Ssam#endif 61189251Ssam#include <vm/vm.h> 62189251Ssam#include <vm/vm_param.h> 63189251Ssam#include <vm/pmap.h> 64189251Ssam#ifdef PC98 65189251Ssam#include <pc98/pc98/pc98.h> 66189251Ssam#else 67189251Ssam#include <i386/isa/isa.h> 68189251Ssam#endif 69189251Ssam#include <i386/isa/isa_dma.h> 70214734Srpaulo#include <i386/isa/ic/i8237.h> 71214734Srpaulo 72189251Ssam/* 73189251Ssam** Register definitions for DMA controller 1 (channels 0..3): 74189251Ssam*/ 75189251Ssam#ifdef PC98 76189251Ssam#define DMA1_CHN(c) (IO_DMA + (4*(c))) /* addr reg for channel c */ 77189251Ssam#define DMA1_SMSK (IO_DMA + 0x14) /* single mask register */ 78189251Ssam#define DMA1_MODE (IO_DMA + 0x16) /* mode register */ 79189251Ssam#define DMA1_FFC (IO_DMA + 0x18) /* clear first/last FF */ 80189251Ssam#else 81189251Ssam#define DMA1_CHN(c) (IO_DMA1 + 1*(2*(c))) /* addr reg for channel c */ 82189251Ssam#define DMA1_SMSK (IO_DMA1 + 1*10) /* single mask register */ 83189251Ssam#define DMA1_MODE (IO_DMA1 + 1*11) /* mode register */ 84189251Ssam#define DMA1_FFC (IO_DMA1 + 1*12) /* clear first/last FF */ 85189251Ssam#endif 86189251Ssam 87189251Ssam/* 88189251Ssam** Register definitions for DMA controller 2 (channels 4..7): 89189251Ssam*/ 90189251Ssam#define DMA2_CHN(c) (IO_DMA2 + 2*(2*(c))) /* addr reg for channel c */ 91189251Ssam#define DMA2_SMSK (IO_DMA2 + 2*10) /* single mask register */ 92189251Ssam#define DMA2_MODE (IO_DMA2 + 2*11) /* mode register */ 93189251Ssam#define DMA2_FFC (IO_DMA2 + 2*12) /* clear first/last FF */ 94189251Ssam 95189251Ssamstatic int isa_dmarangecheck __P((caddr_t va, u_int length, int chan)); 96189251Ssam 97189251Ssam#ifdef PC98 98189251Ssamstatic caddr_t dma_bouncebuf[4]; 99189251Ssamstatic u_int dma_bouncebufsize[4]; 100189251Ssam#else 101189251Ssamstatic caddr_t dma_bouncebuf[8]; 102189251Ssamstatic u_int dma_bouncebufsize[8]; 103189251Ssam#endif 104189251Ssamstatic u_int8_t dma_bounced = 0; 105189251Ssamstatic u_int8_t dma_busy = 0; /* Used in isa_dmastart() */ 106189251Ssamstatic u_int8_t dma_inuse = 0; /* User for acquire/release */ 107189251Ssamstatic u_int8_t dma_auto_mode = 0; 108189251Ssam 109189251Ssam#ifdef PC98 110189251Ssam#define VALID_DMA_MASK (3) 111189251Ssam#else 112189251Ssam#define VALID_DMA_MASK (7) 113189251Ssam#endif 114189251Ssam 115189251Ssam/* high byte of address is stored in this port for i-th dma channel */ 116189251Ssam#ifdef PC98 117189251Ssamstatic int dmapageport[8] = { 0x27, 0x21, 0x23, 0x25 }; 118189251Ssam#else 119189251Ssamstatic int dmapageport[8] = { 0x87, 0x83, 0x81, 0x82, 0x8f, 0x8b, 0x89, 0x8a }; 120189251Ssam#endif 121189251Ssam 122189251Ssam/* 123189251Ssam * Setup a DMA channel's bounce buffer. 124189251Ssam */ 125214734Srpaulovoid 126214734Srpauloisa_dmainit(chan, bouncebufsize) 127214734Srpaulo int chan; 128189251Ssam u_int bouncebufsize; 129189251Ssam{ 130189251Ssam void *buf; 131189251Ssam 132189251Ssam#ifdef DIAGNOSTIC 133189251Ssam if (chan & ~VALID_DMA_MASK) 134189251Ssam panic("isa_dmainit: channel out of range"); 135189251Ssam 136189251Ssam if (dma_bouncebuf[chan] != NULL) 137189251Ssam panic("isa_dmainit: impossible request"); 138189251Ssam#endif 139189251Ssam 140189251Ssam dma_bouncebufsize[chan] = bouncebufsize; 141189251Ssam 142189251Ssam /* Try malloc() first. It works better if it works. */ 143189251Ssam buf = malloc(bouncebufsize, M_DEVBUF, M_NOWAIT); 144189251Ssam if (buf != NULL) { 145189251Ssam if (isa_dmarangecheck(buf, bouncebufsize, chan) == 0) { 146189251Ssam dma_bouncebuf[chan] = buf; 147189251Ssam return; 148189251Ssam } 149189251Ssam free(buf, M_DEVBUF); 150189251Ssam } 151189251Ssam buf = contigmalloc(bouncebufsize, M_DEVBUF, M_NOWAIT, 0ul, 0xfffffful, 152189251Ssam 1ul, chan & 4 ? 0x20000ul : 0x10000ul); 153189251Ssam if (buf == NULL) 154189251Ssam printf("isa_dmainit(%d, %d) failed\n", chan, bouncebufsize); 155189251Ssam else 156189251Ssam dma_bouncebuf[chan] = buf; 157189251Ssam} 158189251Ssam 159189251Ssam/* 160189251Ssam * Register a DMA channel's usage. Usually called from a device driver 161189251Ssam * in open() or during its initialization. 162189251Ssam */ 163189251Ssamint 164189251Ssamisa_dma_acquire(chan) 165189251Ssam int chan; 166189251Ssam{ 167189251Ssam#ifdef DIAGNOSTIC 168189251Ssam if (chan & ~VALID_DMA_MASK) 169189251Ssam panic("isa_dma_acquire: channel out of range"); 170189251Ssam#endif 171189251Ssam 172189251Ssam if (dma_inuse & (1 << chan)) { 173189251Ssam printf("isa_dma_acquire: channel %d already in use\n", chan); 174189251Ssam return (EBUSY); 175189251Ssam } 176189251Ssam dma_inuse |= (1 << chan); 177189251Ssam dma_auto_mode &= ~(1 << chan); 178189251Ssam 179189251Ssam return (0); 180189251Ssam} 181189251Ssam 182189251Ssam/* 183189251Ssam * Unregister a DMA channel's usage. Usually called from a device driver 184189251Ssam * during close() or during its shutdown. 185189251Ssam */ 186189251Ssamvoid 187189251Ssamisa_dma_release(chan) 188189251Ssam int chan; 189189251Ssam{ 190189251Ssam#ifdef DIAGNOSTIC 191189251Ssam if (chan & ~VALID_DMA_MASK) 192189251Ssam panic("isa_dma_release: channel out of range"); 193189251Ssam 194189251Ssam if ((dma_inuse & (1 << chan)) == 0) 195189251Ssam printf("isa_dma_release: channel %d not in use\n", chan); 196189251Ssam#endif 197189251Ssam 198189251Ssam if (dma_busy & (1 << chan)) { 199189251Ssam dma_busy &= ~(1 << chan); 200189251Ssam /* 201189251Ssam * XXX We should also do "dma_bounced &= (1 << chan);" 202189251Ssam * because we are acting on behalf of isa_dmadone() which 203189251Ssam * was not called to end the last DMA operation. This does 204189251Ssam * not matter now, but it may in the future. 205189251Ssam */ 206189251Ssam } 207189251Ssam 208189251Ssam dma_inuse &= ~(1 << chan); 209189251Ssam dma_auto_mode &= ~(1 << chan); 210189251Ssam} 211189251Ssam 212189251Ssam#ifndef PC98 213189251Ssam/* 214189251Ssam * isa_dmacascade(): program 8237 DMA controller channel to accept 215189251Ssam * external dma control by a board. 216189251Ssam */ 217189251Ssamvoid 218189251Ssamisa_dmacascade(chan) 219189251Ssam int chan; 220189251Ssam{ 221189251Ssam#ifdef DIAGNOSTIC 222189251Ssam if (chan & ~VALID_DMA_MASK) 223189251Ssam panic("isa_dmacascade: channel out of range"); 224189251Ssam#endif 225189251Ssam 226189251Ssam /* set dma channel mode, and set dma channel mode */ 227189251Ssam if ((chan & 4) == 0) { 228189251Ssam outb(DMA1_MODE, DMA37MD_CASCADE | chan); 229189251Ssam outb(DMA1_SMSK, chan); 230189251Ssam } else { 231189251Ssam outb(DMA2_MODE, DMA37MD_CASCADE | (chan & 3)); 232189251Ssam outb(DMA2_SMSK, chan & 3); 233189251Ssam } 234189251Ssam} 235189251Ssam#endif 236189251Ssam 237189251Ssam/* 238189251Ssam * isa_dmastart(): program 8237 DMA controller channel, avoid page alignment 239189251Ssam * problems by using a bounce buffer. 240189251Ssam */ 241189251Ssamvoid 242189251Ssamisa_dmastart(int flags, caddr_t addr, u_int nbytes, int chan) 243189251Ssam{ 244189251Ssam vm_offset_t phys; 245189251Ssam int waport; 246189251Ssam caddr_t newaddr; 247189251Ssam 248189251Ssam#ifdef DIAGNOSTIC 249189251Ssam if (chan & ~VALID_DMA_MASK) 250189251Ssam panic("isa_dmastart: channel out of range"); 251189251Ssam 252189251Ssam if ((chan < 4 && nbytes > (1<<16)) 253189251Ssam || (chan >= 4 && (nbytes > (1<<17) || (u_int)addr & 1))) 254189251Ssam panic("isa_dmastart: impossible request"); 255189251Ssam 256189251Ssam if ((dma_inuse & (1 << chan)) == 0) 257189251Ssam printf("isa_dmastart: channel %d not acquired\n", chan); 258189251Ssam#endif 259214734Srpaulo 260214734Srpaulo#if 0 261214734Srpaulo /* 262214734Srpaulo * XXX This should be checked, but drivers like ad1848 only call 263214734Srpaulo * isa_dmastart() once because they use Auto DMA mode. If we 264214734Srpaulo * leave this in, drivers that do this will print this continuously. 265214734Srpaulo */ 266214734Srpaulo if (dma_busy & (1 << chan)) 267214734Srpaulo printf("isa_dmastart: channel %d busy\n", chan); 268214734Srpaulo#endif 269214734Srpaulo 270214734Srpaulo dma_busy |= (1 << chan); 271214734Srpaulo 272214734Srpaulo if (isa_dmarangecheck(addr, nbytes, chan)) { 273214734Srpaulo if (dma_bouncebuf[chan] == NULL 274189251Ssam || dma_bouncebufsize[chan] < nbytes) 275189251Ssam panic("isa_dmastart: bad bounce buffer"); 276189251Ssam dma_bounced |= (1 << chan); 277189251Ssam newaddr = dma_bouncebuf[chan]; 278189251Ssam 279189251Ssam /* copy bounce buffer on write */ 280189251Ssam if (!(flags & B_READ)) 281189251Ssam bcopy(addr, newaddr, nbytes); 282189251Ssam addr = newaddr; 283189251Ssam } 284189251Ssam 285189251Ssam /* translate to physical */ 286189251Ssam phys = pmap_extract(pmap_kernel(), (vm_offset_t)addr); 287214734Srpaulo 288214734Srpaulo if (flags & B_RAW) { 289189251Ssam dma_auto_mode |= (1 << chan); 290214734Srpaulo } else { 291214734Srpaulo dma_auto_mode &= ~(1 << chan); 292189251Ssam } 293189251Ssam 294189251Ssam#ifdef PC98 295214734Srpaulo if (need_pre_dma_flush) 296214734Srpaulo wbinvd(); /* wbinvd (WB cache flush) */ 297189251Ssam#endif 298189251Ssam 299189251Ssam#ifndef PC98 300189251Ssam if ((chan & 4) == 0) { 301214734Srpaulo /* 302189251Ssam * Program one of DMA channels 0..3. These are 303189251Ssam * byte mode channels. 304189251Ssam */ 305189251Ssam#endif 306214734Srpaulo /* set dma channel mode, and reset address ff */ 307214734Srpaulo 308189251Ssam /* If B_RAW flag is set, then use autoinitialise mode */ 309189251Ssam if (flags & B_RAW) { 310189251Ssam if (flags & B_READ) 311189251Ssam outb(DMA1_MODE, DMA37MD_AUTO|DMA37MD_WRITE|chan); 312189251Ssam else 313189251Ssam outb(DMA1_MODE, DMA37MD_AUTO|DMA37MD_READ|chan); 314189251Ssam } 315189251Ssam else 316189251Ssam if (flags & B_READ) 317189251Ssam outb(DMA1_MODE, DMA37MD_SINGLE|DMA37MD_WRITE|chan); 318189251Ssam else 319189251Ssam outb(DMA1_MODE, DMA37MD_SINGLE|DMA37MD_READ|chan); 320189251Ssam outb(DMA1_FFC, 0); 321189251Ssam 322189251Ssam /* send start address */ 323189251Ssam waport = DMA1_CHN(chan); 324189251Ssam outb(waport, phys); 325189251Ssam outb(waport, phys>>8); 326189251Ssam outb(dmapageport[chan], phys>>16); 327189251Ssam 328189251Ssam /* send count */ 329189251Ssam#ifdef PC98 330189251Ssam outb(waport + 2, --nbytes); 331189251Ssam outb(waport + 2, nbytes>>8); 332189251Ssam#else 333189251Ssam outb(waport + 1, --nbytes); 334 outb(waport + 1, nbytes>>8); 335#endif 336 337 /* unmask channel */ 338 outb(DMA1_SMSK, chan); 339#ifndef PC98 340 } else { 341 /* 342 * Program one of DMA channels 4..7. These are 343 * word mode channels. 344 */ 345 /* set dma channel mode, and reset address ff */ 346 347 /* If B_RAW flag is set, then use autoinitialise mode */ 348 if (flags & B_RAW) { 349 if (flags & B_READ) 350 outb(DMA2_MODE, DMA37MD_AUTO|DMA37MD_WRITE|(chan&3)); 351 else 352 outb(DMA2_MODE, DMA37MD_AUTO|DMA37MD_READ|(chan&3)); 353 } 354 else 355 if (flags & B_READ) 356 outb(DMA2_MODE, DMA37MD_SINGLE|DMA37MD_WRITE|(chan&3)); 357 else 358 outb(DMA2_MODE, DMA37MD_SINGLE|DMA37MD_READ|(chan&3)); 359 outb(DMA2_FFC, 0); 360 361 /* send start address */ 362 waport = DMA2_CHN(chan - 4); 363 outb(waport, phys>>1); 364 outb(waport, phys>>9); 365 outb(dmapageport[chan], phys>>16); 366 367 /* send count */ 368 nbytes >>= 1; 369 outb(waport + 2, --nbytes); 370 outb(waport + 2, nbytes>>8); 371 372 /* unmask channel */ 373 outb(DMA2_SMSK, chan & 3); 374 } 375#endif 376} 377 378void 379isa_dmadone(int flags, caddr_t addr, int nbytes, int chan) 380{ 381#ifdef PC98 382 if (flags & B_READ) { 383 /* cache flush only after reading 92/12/9 by A.Kojima */ 384 if (need_post_dma_flush) 385 invd(); 386 } 387#endif 388 389#ifdef DIAGNOSTIC 390 if (chan & ~VALID_DMA_MASK) 391 panic("isa_dmadone: channel out of range"); 392 393 if ((dma_inuse & (1 << chan)) == 0) 394 printf("isa_dmadone: channel %d not acquired\n", chan); 395#endif 396 397 if (((dma_busy & (1 << chan)) == 0) && 398 (dma_auto_mode & (1 << chan)) == 0 ) 399 printf("isa_dmadone: channel %d not busy\n", chan); 400 401#ifdef PC98 402 if ((dma_auto_mode & (1 << chan)) == 0) 403 outb(DMA1_SMSK, (chan & 3) | 4); 404#else 405 if ((dma_auto_mode & (1 << chan)) == 0) 406 outb(chan & 4 ? DMA2_SMSK : DMA1_SMSK, (chan & 3) | 4); 407#endif 408 409 if (dma_bounced & (1 << chan)) { 410 /* copy bounce buffer on read */ 411 if (flags & B_READ) 412 bcopy(dma_bouncebuf[chan], addr, nbytes); 413 414 dma_bounced &= ~(1 << chan); 415 } 416 dma_busy &= ~(1 << chan); 417} 418 419/* 420 * Check for problems with the address range of a DMA transfer 421 * (non-contiguous physical pages, outside of bus address space, 422 * crossing DMA page boundaries). 423 * Return true if special handling needed. 424 */ 425 426static int 427isa_dmarangecheck(caddr_t va, u_int length, int chan) 428{ 429 vm_offset_t phys, priorpage = 0, endva; 430 u_int dma_pgmsk = (chan & 4) ? ~(128*1024-1) : ~(64*1024-1); 431 432 endva = (vm_offset_t)round_page((vm_offset_t)va + length); 433 for (; va < (caddr_t) endva ; va += PAGE_SIZE) { 434 phys = trunc_page(pmap_extract(pmap_kernel(), (vm_offset_t)va)); 435#ifdef EPSON_BOUNCEDMA 436#define ISARAM_END 0xf00000 437#else 438#define ISARAM_END RAM_END 439#endif 440 if (phys == 0) 441 panic("isa_dmacheck: no physical page present"); 442 if (phys >= ISARAM_END) 443 return (1); 444 if (priorpage) { 445 if (priorpage + PAGE_SIZE != phys) 446 return (1); 447 /* check if crossing a DMA page boundary */ 448 if (((u_int)priorpage ^ (u_int)phys) & dma_pgmsk) 449 return (1); 450 } 451 priorpage = phys; 452 } 453 return (0); 454} 455 456/* 457 * Query the progress of a transfer on a DMA channel. 458 * 459 * To avoid having to interrupt a transfer in progress, we sample 460 * each of the high and low databytes twice, and apply the following 461 * logic to determine the correct count. 462 * 463 * Reads are performed with interrupts disabled, thus it is to be 464 * expected that the time between reads is very small. At most 465 * one rollover in the low count byte can be expected within the 466 * four reads that are performed. 467 * 468 * There are three gaps in which a rollover can occur : 469 * 470 * - read low1 471 * gap1 472 * - read high1 473 * gap2 474 * - read low2 475 * gap3 476 * - read high2 477 * 478 * If a rollover occurs in gap1 or gap2, the low2 value will be 479 * greater than the low1 value. In this case, low2 and high2 are a 480 * corresponding pair. 481 * 482 * In any other case, low1 and high1 can be considered to be correct. 483 * 484 * The function returns the number of bytes remaining in the transfer, 485 * or -1 if the channel requested is not active. 486 * 487 */ 488int 489isa_dmastatus(int chan) 490{ 491 u_long cnt = 0; 492 int ffport, waport; 493 u_long low1, high1, low2, high2; 494 495 /* channel active? */ 496 if ((dma_inuse & (1 << chan)) == 0) { 497 printf("isa_dmastatus: channel %d not active\n", chan); 498 return(-1); 499 } 500 /* channel busy? */ 501 502 if (((dma_busy & (1 << chan)) == 0) && 503 (dma_auto_mode & (1 << chan)) == 0 ) { 504 printf("chan %d not busy\n", chan); 505 return -2 ; 506 } 507#ifdef PC98 508 ffport = DMA1_FFC; 509 waport = DMA1_CHN(chan) + 2; 510#else 511 if (chan < 4) { /* low DMA controller */ 512 ffport = DMA1_FFC; 513 waport = DMA1_CHN(chan) + 1; 514 } else { /* high DMA controller */ 515 ffport = DMA2_FFC; 516 waport = DMA2_CHN(chan - 4) + 2; 517 } 518#endif 519 520 disable_intr(); /* no interrupts Mr Jones! */ 521 outb(ffport, 0); /* clear register LSB flipflop */ 522 low1 = inb(waport); 523 high1 = inb(waport); 524 outb(ffport, 0); /* clear again */ 525 low2 = inb(waport); 526 high2 = inb(waport); 527 enable_intr(); /* enable interrupts again */ 528 529 /* 530 * Now decide if a wrap has tried to skew our results. 531 * Note that after TC, the count will read 0xffff, while we want 532 * to return zero, so we add and then mask to compensate. 533 */ 534 if (low1 >= low2) { 535 cnt = (low1 + (high1 << 8) + 1) & 0xffff; 536 } else { 537 cnt = (low2 + (high2 << 8) + 1) & 0xffff; 538 } 539 540 if (chan >= 4) /* high channels move words */ 541 cnt *= 2; 542 return(cnt); 543} 544 545/* 546 * Stop a DMA transfer currently in progress. 547 */ 548int 549isa_dmastop(int chan) 550{ 551 if ((dma_inuse & (1 << chan)) == 0) 552 printf("isa_dmastop: channel %d not acquired\n", chan); 553 554 if (((dma_busy & (1 << chan)) == 0) && 555 ((dma_auto_mode & (1 << chan)) == 0)) { 556 printf("chan %d not busy\n", chan); 557 return -2 ; 558 } 559 560 if ((chan & 4) == 0) { 561 outb(DMA1_SMSK, (chan & 3) | 4 /* disable mask */); 562 } else { 563#ifndef PC98 564 outb(DMA2_SMSK, (chan & 3) | 4 /* disable mask */); 565#endif 566 } 567 return(isa_dmastatus(chan)); 568} 569