cbus_dma.c revision 45919
1/*- 2 * Copyright (c) 1991 The Regents of the University of California. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to Berkeley by 6 * William Jolitz. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by the University of 19 * California, Berkeley and its contributors. 20 * 4. Neither the name of the University nor the names of its contributors 21 * may be used to endorse or promote products derived from this software 22 * without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 * 36 * from: @(#)isa.c 7.2 (Berkeley) 5/13/91 37 * $Id: isa_dma.c,v 1.1 1999/04/18 14:42:17 kato Exp $ 38 */ 39 40/* 41 * code to manage AT bus 42 * 43 * 92/08/18 Frank P. MacLachlan (fpm@crash.cts.com): 44 * Fixed uninitialized variable problem and added code to deal 45 * with DMA page boundaries in isa_dmarangecheck(). Fixed word 46 * mode DMA count compution and reorganized DMA setup code in 47 * isa_dmastart() 48 */ 49 50#ifdef PC98 51#include "opt_pc98.h" 52#endif 53 54#include <sys/param.h> 55#include <sys/systm.h> 56#include <sys/buf.h> 57#include <sys/malloc.h> 58#include <machine/ipl.h> 59#include <machine/md_var.h> 60#ifdef APIC_IO 61#include <machine/smp.h> 62#endif /* APIC_IO */ 63#include <vm/vm.h> 64#include <vm/vm_param.h> 65#include <vm/pmap.h> 66#include <i386/isa/isa_device.h> 67#ifdef PC98 68#include <pc98/pc98/pc98.h> 69#else 70#include <i386/isa/isa.h> 71#endif 72#include <i386/isa/ic/i8237.h> 73 74#include <sys/interrupt.h> 75 76#include "pnp.h" 77#if NPNP > 0 78#include <i386/isa/pnp.h> 79#endif 80 81/* 82** Register definitions for DMA controller 1 (channels 0..3): 83*/ 84#ifdef PC98 85#define DMA1_CHN(c) (IO_DMA + (4*(c))) /* addr reg for channel c */ 86#define DMA1_SMSK (IO_DMA + 0x14) /* single mask register */ 87#define DMA1_MODE (IO_DMA + 0x16) /* mode register */ 88#define DMA1_FFC (IO_DMA + 0x18) /* clear first/last FF */ 89#else 90#define DMA1_CHN(c) (IO_DMA1 + 1*(2*(c))) /* addr reg for channel c */ 91#define DMA1_SMSK (IO_DMA1 + 1*10) /* single mask register */ 92#define DMA1_MODE (IO_DMA1 + 1*11) /* mode register */ 93#define DMA1_FFC (IO_DMA1 + 1*12) /* clear first/last FF */ 94#endif 95 96/* 97** Register definitions for DMA controller 2 (channels 4..7): 98*/ 99#define DMA2_CHN(c) (IO_DMA2 + 2*(2*(c))) /* addr reg for channel c */ 100#define DMA2_SMSK (IO_DMA2 + 2*10) /* single mask register */ 101#define DMA2_MODE (IO_DMA2 + 2*11) /* mode register */ 102#define DMA2_FFC (IO_DMA2 + 2*12) /* clear first/last FF */ 103 104static int isa_dmarangecheck __P((caddr_t va, u_int length, int chan)); 105 106#ifdef PC98 107static caddr_t dma_bouncebuf[4]; 108static u_int dma_bouncebufsize[4]; 109#else 110static caddr_t dma_bouncebuf[8]; 111static u_int dma_bouncebufsize[8]; 112#endif 113static u_int8_t dma_bounced = 0; 114static u_int8_t dma_busy = 0; /* Used in isa_dmastart() */ 115static u_int8_t dma_inuse = 0; /* User for acquire/release */ 116static u_int8_t dma_auto_mode = 0; 117 118#ifdef PC98 119#define VALID_DMA_MASK (3) 120#else 121#define VALID_DMA_MASK (7) 122#endif 123 124/* high byte of address is stored in this port for i-th dma channel */ 125#ifdef PC98 126static int dmapageport[8] = { 0x27, 0x21, 0x23, 0x25 }; 127#else 128static int dmapageport[8] = { 0x87, 0x83, 0x81, 0x82, 0x8f, 0x8b, 0x89, 0x8a }; 129#endif 130 131/* 132 * Setup a DMA channel's bounce buffer. 133 */ 134void 135isa_dmainit(chan, bouncebufsize) 136 int chan; 137 u_int bouncebufsize; 138{ 139 void *buf; 140 141#ifdef DIAGNOSTIC 142 if (chan & ~VALID_DMA_MASK) 143 panic("isa_dmainit: channel out of range"); 144 145 if (dma_bouncebuf[chan] != NULL) 146 panic("isa_dmainit: impossible request"); 147#endif 148 149 dma_bouncebufsize[chan] = bouncebufsize; 150 151 /* Try malloc() first. It works better if it works. */ 152 buf = malloc(bouncebufsize, M_DEVBUF, M_NOWAIT); 153 if (buf != NULL) { 154 if (isa_dmarangecheck(buf, bouncebufsize, chan) == 0) { 155 dma_bouncebuf[chan] = buf; 156 return; 157 } 158 free(buf, M_DEVBUF); 159 } 160 buf = contigmalloc(bouncebufsize, M_DEVBUF, M_NOWAIT, 0ul, 0xfffffful, 161 1ul, chan & 4 ? 0x20000ul : 0x10000ul); 162 if (buf == NULL) 163 printf("isa_dmainit(%d, %d) failed\n", chan, bouncebufsize); 164 else 165 dma_bouncebuf[chan] = buf; 166} 167 168/* 169 * Register a DMA channel's usage. Usually called from a device driver 170 * in open() or during its initialization. 171 */ 172int 173isa_dma_acquire(chan) 174 int chan; 175{ 176#ifdef DIAGNOSTIC 177 if (chan & ~VALID_DMA_MASK) 178 panic("isa_dma_acquire: channel out of range"); 179#endif 180 181 if (dma_inuse & (1 << chan)) { 182 printf("isa_dma_acquire: channel %d already in use\n", chan); 183 return (EBUSY); 184 } 185 dma_inuse |= (1 << chan); 186 dma_auto_mode &= ~(1 << chan); 187 188 return (0); 189} 190 191/* 192 * Unregister a DMA channel's usage. Usually called from a device driver 193 * during close() or during its shutdown. 194 */ 195void 196isa_dma_release(chan) 197 int chan; 198{ 199#ifdef DIAGNOSTIC 200 if (chan & ~VALID_DMA_MASK) 201 panic("isa_dma_release: channel out of range"); 202 203 if ((dma_inuse & (1 << chan)) == 0) 204 printf("isa_dma_release: channel %d not in use\n", chan); 205#endif 206 207 if (dma_busy & (1 << chan)) { 208 dma_busy &= ~(1 << chan); 209 /* 210 * XXX We should also do "dma_bounced &= (1 << chan);" 211 * because we are acting on behalf of isa_dmadone() which 212 * was not called to end the last DMA operation. This does 213 * not matter now, but it may in the future. 214 */ 215 } 216 217 dma_inuse &= ~(1 << chan); 218 dma_auto_mode &= ~(1 << chan); 219} 220 221#ifndef PC98 222/* 223 * isa_dmacascade(): program 8237 DMA controller channel to accept 224 * external dma control by a board. 225 */ 226void 227isa_dmacascade(chan) 228 int chan; 229{ 230#ifdef DIAGNOSTIC 231 if (chan & ~VALID_DMA_MASK) 232 panic("isa_dmacascade: channel out of range"); 233#endif 234 235 /* set dma channel mode, and set dma channel mode */ 236 if ((chan & 4) == 0) { 237 outb(DMA1_MODE, DMA37MD_CASCADE | chan); 238 outb(DMA1_SMSK, chan); 239 } else { 240 outb(DMA2_MODE, DMA37MD_CASCADE | (chan & 3)); 241 outb(DMA2_SMSK, chan & 3); 242 } 243} 244#endif 245 246/* 247 * isa_dmastart(): program 8237 DMA controller channel, avoid page alignment 248 * problems by using a bounce buffer. 249 */ 250void 251isa_dmastart(int flags, caddr_t addr, u_int nbytes, int chan) 252{ 253 vm_offset_t phys; 254 int waport; 255 caddr_t newaddr; 256 257#ifdef DIAGNOSTIC 258 if (chan & ~VALID_DMA_MASK) 259 panic("isa_dmastart: channel out of range"); 260 261 if ((chan < 4 && nbytes > (1<<16)) 262 || (chan >= 4 && (nbytes > (1<<17) || (u_int)addr & 1))) 263 panic("isa_dmastart: impossible request"); 264 265 if ((dma_inuse & (1 << chan)) == 0) 266 printf("isa_dmastart: channel %d not acquired\n", chan); 267#endif 268 269#if 0 270 /* 271 * XXX This should be checked, but drivers like ad1848 only call 272 * isa_dmastart() once because they use Auto DMA mode. If we 273 * leave this in, drivers that do this will print this continuously. 274 */ 275 if (dma_busy & (1 << chan)) 276 printf("isa_dmastart: channel %d busy\n", chan); 277#endif 278 279 dma_busy |= (1 << chan); 280 281 if (isa_dmarangecheck(addr, nbytes, chan)) { 282 if (dma_bouncebuf[chan] == NULL 283 || dma_bouncebufsize[chan] < nbytes) 284 panic("isa_dmastart: bad bounce buffer"); 285 dma_bounced |= (1 << chan); 286 newaddr = dma_bouncebuf[chan]; 287 288 /* copy bounce buffer on write */ 289 if (!(flags & B_READ)) 290 bcopy(addr, newaddr, nbytes); 291 addr = newaddr; 292 } 293 294 /* translate to physical */ 295 phys = pmap_extract(pmap_kernel(), (vm_offset_t)addr); 296 297 if (flags & B_RAW) { 298 dma_auto_mode |= (1 << chan); 299 } else { 300 dma_auto_mode &= ~(1 << chan); 301 } 302 303#ifndef PC98 304 if ((chan & 4) == 0) { 305 /* 306 * Program one of DMA channels 0..3. These are 307 * byte mode channels. 308 */ 309#endif 310 /* set dma channel mode, and reset address ff */ 311 312 /* If B_RAW flag is set, then use autoinitialise mode */ 313 if (flags & B_RAW) { 314 if (flags & B_READ) 315 outb(DMA1_MODE, DMA37MD_AUTO|DMA37MD_WRITE|chan); 316 else 317 outb(DMA1_MODE, DMA37MD_AUTO|DMA37MD_READ|chan); 318 } 319 else 320 if (flags & B_READ) 321 outb(DMA1_MODE, DMA37MD_SINGLE|DMA37MD_WRITE|chan); 322 else 323 outb(DMA1_MODE, DMA37MD_SINGLE|DMA37MD_READ|chan); 324 outb(DMA1_FFC, 0); 325 326 /* send start address */ 327 waport = DMA1_CHN(chan); 328 outb(waport, phys); 329 outb(waport, phys>>8); 330 outb(dmapageport[chan], phys>>16); 331 332 /* send count */ 333 outb(waport + 1, --nbytes); 334 outb(waport + 1, nbytes>>8); 335 336 /* unmask channel */ 337 outb(DMA1_SMSK, chan); 338#ifndef PC98 339 } else { 340 /* 341 * Program one of DMA channels 4..7. These are 342 * word mode channels. 343 */ 344 /* set dma channel mode, and reset address ff */ 345 346 /* If B_RAW flag is set, then use autoinitialise mode */ 347 if (flags & B_RAW) { 348 if (flags & B_READ) 349 outb(DMA2_MODE, DMA37MD_AUTO|DMA37MD_WRITE|(chan&3)); 350 else 351 outb(DMA2_MODE, DMA37MD_AUTO|DMA37MD_READ|(chan&3)); 352 } 353 else 354 if (flags & B_READ) 355 outb(DMA2_MODE, DMA37MD_SINGLE|DMA37MD_WRITE|(chan&3)); 356 else 357 outb(DMA2_MODE, DMA37MD_SINGLE|DMA37MD_READ|(chan&3)); 358 outb(DMA2_FFC, 0); 359 360 /* send start address */ 361 waport = DMA2_CHN(chan - 4); 362 outb(waport, phys>>1); 363 outb(waport, phys>>9); 364 outb(dmapageport[chan], phys>>16); 365 366 /* send count */ 367 nbytes >>= 1; 368 outb(waport + 2, --nbytes); 369 outb(waport + 2, nbytes>>8); 370 371 /* unmask channel */ 372 outb(DMA2_SMSK, chan & 3); 373 } 374#endif 375} 376 377void 378isa_dmadone(int flags, caddr_t addr, int nbytes, int chan) 379{ 380#ifdef DIAGNOSTIC 381 if (chan & ~VALID_DMA_MASK) 382 panic("isa_dmadone: channel out of range"); 383 384 if ((dma_inuse & (1 << chan)) == 0) 385 printf("isa_dmadone: channel %d not acquired\n", chan); 386#endif 387 388 if (((dma_busy & (1 << chan)) == 0) && 389 (dma_auto_mode & (1 << chan)) == 0 ) 390 printf("isa_dmadone: channel %d not busy\n", chan); 391 392#ifdef PC98 393 if ((dma_auto_mode & (1 << chan)) == 0) 394 outb(DMA1_SMSK, (chan & 3) | 4); 395#else 396 if ((dma_auto_mode & (1 << chan)) == 0) 397 outb(chan & 4 ? DMA2_SMSK : DMA1_SMSK, (chan & 3) | 4); 398#endif 399 400 if (dma_bounced & (1 << chan)) { 401 /* copy bounce buffer on read */ 402 if (flags & B_READ) 403 bcopy(dma_bouncebuf[chan], addr, nbytes); 404 405 dma_bounced &= ~(1 << chan); 406 } 407 dma_busy &= ~(1 << chan); 408} 409 410/* 411 * Check for problems with the address range of a DMA transfer 412 * (non-contiguous physical pages, outside of bus address space, 413 * crossing DMA page boundaries). 414 * Return true if special handling needed. 415 */ 416 417static int 418isa_dmarangecheck(caddr_t va, u_int length, int chan) 419{ 420 vm_offset_t phys, priorpage = 0, endva; 421 u_int dma_pgmsk = (chan & 4) ? ~(128*1024-1) : ~(64*1024-1); 422 423 endva = (vm_offset_t)round_page((vm_offset_t)va + length); 424 for (; va < (caddr_t) endva ; va += PAGE_SIZE) { 425 phys = trunc_page(pmap_extract(pmap_kernel(), (vm_offset_t)va)); 426#ifdef EPSON_BOUNCEDMA 427#define ISARAM_END 0xf00000 428#else 429#define ISARAM_END RAM_END 430#endif 431 if (phys == 0) 432 panic("isa_dmacheck: no physical page present"); 433 if (phys >= ISARAM_END) 434 return (1); 435 if (priorpage) { 436 if (priorpage + PAGE_SIZE != phys) 437 return (1); 438 /* check if crossing a DMA page boundary */ 439 if (((u_int)priorpage ^ (u_int)phys) & dma_pgmsk) 440 return (1); 441 } 442 priorpage = phys; 443 } 444 return (0); 445} 446 447/* 448 * Query the progress of a transfer on a DMA channel. 449 * 450 * To avoid having to interrupt a transfer in progress, we sample 451 * each of the high and low databytes twice, and apply the following 452 * logic to determine the correct count. 453 * 454 * Reads are performed with interrupts disabled, thus it is to be 455 * expected that the time between reads is very small. At most 456 * one rollover in the low count byte can be expected within the 457 * four reads that are performed. 458 * 459 * There are three gaps in which a rollover can occur : 460 * 461 * - read low1 462 * gap1 463 * - read high1 464 * gap2 465 * - read low2 466 * gap3 467 * - read high2 468 * 469 * If a rollover occurs in gap1 or gap2, the low2 value will be 470 * greater than the low1 value. In this case, low2 and high2 are a 471 * corresponding pair. 472 * 473 * In any other case, low1 and high1 can be considered to be correct. 474 * 475 * The function returns the number of bytes remaining in the transfer, 476 * or -1 if the channel requested is not active. 477 * 478 */ 479int 480isa_dmastatus(int chan) 481{ 482 u_long cnt = 0; 483 int ffport, waport; 484 u_long low1, high1, low2, high2; 485 486 /* channel active? */ 487 if ((dma_inuse & (1 << chan)) == 0) { 488 printf("isa_dmastatus: channel %d not active\n", chan); 489 return(-1); 490 } 491 /* channel busy? */ 492 493 if (((dma_busy & (1 << chan)) == 0) && 494 (dma_auto_mode & (1 << chan)) == 0 ) { 495 printf("chan %d not busy\n", chan); 496 return -2 ; 497 } 498#ifdef PC98 499 ffport = DMA1_FFC; 500 waport = DMA1_CHN(chan) + 2; 501#else 502 if (chan < 4) { /* low DMA controller */ 503 ffport = DMA1_FFC; 504 waport = DMA1_CHN(chan) + 1; 505 } else { /* high DMA controller */ 506 ffport = DMA2_FFC; 507 waport = DMA2_CHN(chan - 4) + 2; 508 } 509#endif 510 511 disable_intr(); /* no interrupts Mr Jones! */ 512 outb(ffport, 0); /* clear register LSB flipflop */ 513 low1 = inb(waport); 514 high1 = inb(waport); 515 outb(ffport, 0); /* clear again */ 516 low2 = inb(waport); 517 high2 = inb(waport); 518 enable_intr(); /* enable interrupts again */ 519 520 /* 521 * Now decide if a wrap has tried to skew our results. 522 * Note that after TC, the count will read 0xffff, while we want 523 * to return zero, so we add and then mask to compensate. 524 */ 525 if (low1 >= low2) { 526 cnt = (low1 + (high1 << 8) + 1) & 0xffff; 527 } else { 528 cnt = (low2 + (high2 << 8) + 1) & 0xffff; 529 } 530 531 if (chan >= 4) /* high channels move words */ 532 cnt *= 2; 533 return(cnt); 534} 535 536/* 537 * Stop a DMA transfer currently in progress. 538 */ 539int 540isa_dmastop(int chan) 541{ 542 if ((dma_inuse & (1 << chan)) == 0) 543 printf("isa_dmastop: channel %d not acquired\n", chan); 544 545 if (((dma_busy & (1 << chan)) == 0) && 546 ((dma_auto_mode & (1 << chan)) == 0)) { 547 printf("chan %d not busy\n", chan); 548 return -2 ; 549 } 550 551 if ((chan & 4) == 0) { 552 outb(DMA1_SMSK, (chan & 3) | 4 /* disable mask */); 553 } else { 554#ifndef PC98 555 outb(DMA2_SMSK, (chan & 3) | 4 /* disable mask */); 556#endif 557 } 558 return(isa_dmastatus(chan)); 559} 560