cbus_dma.c revision 135262
1/*- 2 * Copyright (c) 1991 The Regents of the University of California. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to Berkeley by 6 * William Jolitz. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 4. Neither the name of the University nor the names of its contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 30 * SUCH DAMAGE. 31 * 32 * from: @(#)isa.c 7.2 (Berkeley) 5/13/91 33 * $FreeBSD: head/sys/pc98/cbus/cbus_dma.c 135262 2004-09-15 12:09:50Z phk $ 34 */ 35 36/* 37 * code to manage AT bus 38 * 39 * 92/08/18 Frank P. MacLachlan (fpm@crash.cts.com): 40 * Fixed uninitialized variable problem and added code to deal 41 * with DMA page boundaries in isa_dmarangecheck(). Fixed word 42 * mode DMA count compution and reorganized DMA setup code in 43 * isa_dmastart() 44 */ 45 46#ifdef PC98 47#include "opt_pc98.h" 48#endif 49 50#include <sys/param.h> 51#include <sys/systm.h> 52#include <sys/bus.h> 53#include <sys/kernel.h> 54#include <sys/malloc.h> 55#include <sys/lock.h> 56#include <sys/proc.h> 57#include <sys/mutex.h> 58#include <sys/module.h> 59#ifdef PC98 60#include <machine/md_var.h> 61#endif 62#include <vm/vm.h> 63#include <vm/vm_param.h> 64#include <vm/pmap.h> 65#ifdef PC98 66#include <pc98/pc98/pc98.h> 67#else 68#include <i386/isa/isa.h> 69#endif 70#include <dev/ic/i8237.h> 71#include <isa/isavar.h> 72 73/* 74** Register definitions for DMA controller 1 (channels 0..3): 75*/ 76#ifdef PC98 77#define DMA1_CHN(c) (IO_DMA + (4*(c))) /* addr reg for channel c */ 78#define DMA1_SMSK (IO_DMA + 0x14) /* single mask register */ 79#define DMA1_MODE (IO_DMA + 0x16) /* mode register */ 80#define DMA1_FFC (IO_DMA + 0x18) /* clear first/last FF */ 81#else 82#define DMA1_CHN(c) (IO_DMA1 + 1*(2*(c))) /* addr reg for channel c */ 83#define DMA1_SMSK (IO_DMA1 + 1*10) /* single mask register */ 84#define DMA1_MODE (IO_DMA1 + 1*11) /* mode register */ 85#define DMA1_FFC (IO_DMA1 + 1*12) /* clear first/last FF */ 86#endif 87 88/* 89** Register definitions for DMA controller 2 (channels 4..7): 90*/ 91#define DMA2_CHN(c) (IO_DMA2 + 2*(2*(c))) /* addr reg for channel c */ 92#define DMA2_SMSK (IO_DMA2 + 2*10) /* single mask register */ 93#define DMA2_MODE (IO_DMA2 + 2*11) /* mode register */ 94#define DMA2_FFC (IO_DMA2 + 2*12) /* clear first/last FF */ 95 96static int isa_dmarangecheck(caddr_t va, u_int length, int chan); 97 98#ifdef PC98 99static caddr_t dma_bouncebuf[4]; 100static u_int dma_bouncebufsize[4]; 101#else 102static caddr_t dma_bouncebuf[8]; 103static u_int dma_bouncebufsize[8]; 104#endif 105static u_int8_t dma_bounced = 0; 106static u_int8_t dma_busy = 0; /* Used in isa_dmastart() */ 107static u_int8_t dma_inuse = 0; /* User for acquire/release */ 108static u_int8_t dma_auto_mode = 0; 109 110#ifdef PC98 111#define VALID_DMA_MASK (3) 112#else 113#define VALID_DMA_MASK (7) 114#endif 115 116/* high byte of address is stored in this port for i-th dma channel */ 117#ifdef PC98 118static int dmapageport[4] = { 0x27, 0x21, 0x23, 0x25 }; 119#else 120static int dmapageport[8] = { 0x87, 0x83, 0x81, 0x82, 0x8f, 0x8b, 0x89, 0x8a }; 121#endif 122 123/* 124 * Setup a DMA channel's bounce buffer. 125 */ 126int 127isa_dma_init(int chan, u_int bouncebufsize, int flag) 128{ 129 void *buf; 130 131#ifndef PC98 132 /* 133 * If a DMA channel is shared, both drivers have to call isa_dma_init 134 * since they don't know that the other driver will do it. 135 * Just return if we're already set up good. 136 * XXX: this only works if they agree on the bouncebuf size. This 137 * XXX: is typically the case since they are multiple instances of 138 * XXX: the same driver. 139 */ 140 if (dma_bouncebuf[chan] != NULL) 141 return (0); 142#endif 143 144#ifdef DIAGNOSTIC 145 if (chan & ~VALID_DMA_MASK) 146 panic("isa_dma_init: channel out of range"); 147#ifdef PC98 148 if (dma_bouncebuf[chan] != NULL) 149 panic("isa_dma_init: impossible request"); 150#endif 151#endif 152 153 dma_bouncebufsize[chan] = bouncebufsize; 154 155 /* Try malloc() first. It works better if it works. */ 156 buf = malloc(bouncebufsize, M_DEVBUF, flag); 157 if (buf != NULL) { 158 if (isa_dmarangecheck(buf, bouncebufsize, chan) == 0) { 159 dma_bouncebuf[chan] = buf; 160 return (0); 161 } 162 free(buf, M_DEVBUF); 163 } 164 buf = contigmalloc(bouncebufsize, M_DEVBUF, flag, 0ul, 0xfffffful, 165 1ul, chan & 4 ? 0x20000ul : 0x10000ul); 166 if (buf == NULL) 167 return (ENOMEM); 168 dma_bouncebuf[chan] = buf; 169 return (0); 170} 171 172/* 173 * Register a DMA channel's usage. Usually called from a device driver 174 * in open() or during its initialization. 175 */ 176int 177isa_dma_acquire(chan) 178 int chan; 179{ 180#ifdef DIAGNOSTIC 181 if (chan & ~VALID_DMA_MASK) 182 panic("isa_dma_acquire: channel out of range"); 183#endif 184 185 if (dma_inuse & (1 << chan)) { 186 printf("isa_dma_acquire: channel %d already in use\n", chan); 187 return (EBUSY); 188 } 189 dma_inuse |= (1 << chan); 190 dma_auto_mode &= ~(1 << chan); 191 192 return (0); 193} 194 195/* 196 * Unregister a DMA channel's usage. Usually called from a device driver 197 * during close() or during its shutdown. 198 */ 199void 200isa_dma_release(chan) 201 int chan; 202{ 203#ifdef DIAGNOSTIC 204 if (chan & ~VALID_DMA_MASK) 205 panic("isa_dma_release: channel out of range"); 206 207 if ((dma_inuse & (1 << chan)) == 0) 208 printf("isa_dma_release: channel %d not in use\n", chan); 209#endif 210 211 if (dma_busy & (1 << chan)) { 212 dma_busy &= ~(1 << chan); 213 /* 214 * XXX We should also do "dma_bounced &= (1 << chan);" 215 * because we are acting on behalf of isa_dmadone() which 216 * was not called to end the last DMA operation. This does 217 * not matter now, but it may in the future. 218 */ 219 } 220 221 dma_inuse &= ~(1 << chan); 222 dma_auto_mode &= ~(1 << chan); 223} 224 225#ifndef PC98 226/* 227 * isa_dmacascade(): program 8237 DMA controller channel to accept 228 * external dma control by a board. 229 */ 230void 231isa_dmacascade(chan) 232 int chan; 233{ 234#ifdef DIAGNOSTIC 235 if (chan & ~VALID_DMA_MASK) 236 panic("isa_dmacascade: channel out of range"); 237#endif 238 239 /* set dma channel mode, and set dma channel mode */ 240 if ((chan & 4) == 0) { 241 outb(DMA1_MODE, DMA37MD_CASCADE | chan); 242 outb(DMA1_SMSK, chan); 243 } else { 244 outb(DMA2_MODE, DMA37MD_CASCADE | (chan & 3)); 245 outb(DMA2_SMSK, chan & 3); 246 } 247} 248#endif 249 250/* 251 * isa_dmastart(): program 8237 DMA controller channel, avoid page alignment 252 * problems by using a bounce buffer. 253 */ 254void 255isa_dmastart(int flags, caddr_t addr, u_int nbytes, int chan) 256{ 257 vm_offset_t phys; 258 int waport; 259 caddr_t newaddr; 260 261 GIANT_REQUIRED; 262 263#ifdef DIAGNOSTIC 264 if (chan & ~VALID_DMA_MASK) 265 panic("isa_dmastart: channel out of range"); 266 267 if ((chan < 4 && nbytes > (1<<16)) 268 || (chan >= 4 && (nbytes > (1<<17) || (u_int)addr & 1))) 269 panic("isa_dmastart: impossible request"); 270 271 if ((dma_inuse & (1 << chan)) == 0) 272 printf("isa_dmastart: channel %d not acquired\n", chan); 273#endif 274 275#if 0 276 /* 277 * XXX This should be checked, but drivers like ad1848 only call 278 * isa_dmastart() once because they use Auto DMA mode. If we 279 * leave this in, drivers that do this will print this continuously. 280 */ 281 if (dma_busy & (1 << chan)) 282 printf("isa_dmastart: channel %d busy\n", chan); 283#endif 284 285 dma_busy |= (1 << chan); 286 287 if (isa_dmarangecheck(addr, nbytes, chan)) { 288 if (dma_bouncebuf[chan] == NULL 289 || dma_bouncebufsize[chan] < nbytes) 290 panic("isa_dmastart: bad bounce buffer"); 291 dma_bounced |= (1 << chan); 292 newaddr = dma_bouncebuf[chan]; 293 294 /* copy bounce buffer on write */ 295 if (!(flags & ISADMA_READ)) 296 bcopy(addr, newaddr, nbytes); 297 addr = newaddr; 298 } 299 300 /* translate to physical */ 301 phys = pmap_extract(kernel_pmap, (vm_offset_t)addr); 302 303 if (flags & ISADMA_RAW) { 304 dma_auto_mode |= (1 << chan); 305 } else { 306 dma_auto_mode &= ~(1 << chan); 307 } 308 309#ifdef PC98 310 if (need_pre_dma_flush) 311 wbinvd(); /* wbinvd (WB cache flush) */ 312#endif 313 314#ifndef PC98 315 if ((chan & 4) == 0) { 316 /* 317 * Program one of DMA channels 0..3. These are 318 * byte mode channels. 319 */ 320#endif 321 /* set dma channel mode, and reset address ff */ 322 323 /* If ISADMA_RAW flag is set, then use autoinitialise mode */ 324 if (flags & ISADMA_RAW) { 325 if (flags & ISADMA_READ) 326 outb(DMA1_MODE, DMA37MD_AUTO|DMA37MD_WRITE|chan); 327 else 328 outb(DMA1_MODE, DMA37MD_AUTO|DMA37MD_READ|chan); 329 } 330 else 331 if (flags & ISADMA_READ) 332 outb(DMA1_MODE, DMA37MD_SINGLE|DMA37MD_WRITE|chan); 333 else 334 outb(DMA1_MODE, DMA37MD_SINGLE|DMA37MD_READ|chan); 335 outb(DMA1_FFC, 0); 336 337 /* send start address */ 338 waport = DMA1_CHN(chan); 339 outb(waport, phys); 340 outb(waport, phys>>8); 341 outb(dmapageport[chan], phys>>16); 342 343 /* send count */ 344#ifdef PC98 345 outb(waport + 2, --nbytes); 346 outb(waport + 2, nbytes>>8); 347#else 348 outb(waport + 1, --nbytes); 349 outb(waport + 1, nbytes>>8); 350#endif 351 352 /* unmask channel */ 353 outb(DMA1_SMSK, chan); 354#ifndef PC98 355 } else { 356 /* 357 * Program one of DMA channels 4..7. These are 358 * word mode channels. 359 */ 360 /* set dma channel mode, and reset address ff */ 361 362 /* If ISADMA_RAW flag is set, then use autoinitialise mode */ 363 if (flags & ISADMA_RAW) { 364 if (flags & ISADMA_READ) 365 outb(DMA2_MODE, DMA37MD_AUTO|DMA37MD_WRITE|(chan&3)); 366 else 367 outb(DMA2_MODE, DMA37MD_AUTO|DMA37MD_READ|(chan&3)); 368 } 369 else 370 if (flags & ISADMA_READ) 371 outb(DMA2_MODE, DMA37MD_SINGLE|DMA37MD_WRITE|(chan&3)); 372 else 373 outb(DMA2_MODE, DMA37MD_SINGLE|DMA37MD_READ|(chan&3)); 374 outb(DMA2_FFC, 0); 375 376 /* send start address */ 377 waport = DMA2_CHN(chan - 4); 378 outb(waport, phys>>1); 379 outb(waport, phys>>9); 380 outb(dmapageport[chan], phys>>16); 381 382 /* send count */ 383 nbytes >>= 1; 384 outb(waport + 2, --nbytes); 385 outb(waport + 2, nbytes>>8); 386 387 /* unmask channel */ 388 outb(DMA2_SMSK, chan & 3); 389 } 390#endif 391} 392 393void 394isa_dmadone(int flags, caddr_t addr, int nbytes, int chan) 395{ 396#ifdef PC98 397 if (flags & ISADMA_READ) { 398 /* cache flush only after reading 92/12/9 by A.Kojima */ 399 if (need_post_dma_flush) 400 invd(); 401 } 402#endif 403 404#ifdef DIAGNOSTIC 405 if (chan & ~VALID_DMA_MASK) 406 panic("isa_dmadone: channel out of range"); 407 408 if ((dma_inuse & (1 << chan)) == 0) 409 printf("isa_dmadone: channel %d not acquired\n", chan); 410#endif 411 412 if (((dma_busy & (1 << chan)) == 0) && 413 (dma_auto_mode & (1 << chan)) == 0 ) 414 printf("isa_dmadone: channel %d not busy\n", chan); 415 416#ifdef PC98 417 if ((dma_auto_mode & (1 << chan)) == 0) 418 outb(DMA1_SMSK, (chan & 3) | 4); 419#else 420 if ((dma_auto_mode & (1 << chan)) == 0) 421 outb(chan & 4 ? DMA2_SMSK : DMA1_SMSK, (chan & 3) | 4); 422#endif 423 424 if (dma_bounced & (1 << chan)) { 425 /* copy bounce buffer on read */ 426 if (flags & ISADMA_READ) 427 bcopy(dma_bouncebuf[chan], addr, nbytes); 428 429 dma_bounced &= ~(1 << chan); 430 } 431 dma_busy &= ~(1 << chan); 432} 433 434/* 435 * Check for problems with the address range of a DMA transfer 436 * (non-contiguous physical pages, outside of bus address space, 437 * crossing DMA page boundaries). 438 * Return true if special handling needed. 439 */ 440 441static int 442isa_dmarangecheck(caddr_t va, u_int length, int chan) 443{ 444 vm_offset_t phys, priorpage = 0, endva; 445 u_int dma_pgmsk = (chan & 4) ? ~(128*1024-1) : ~(64*1024-1); 446 447 GIANT_REQUIRED; 448 449 endva = (vm_offset_t)round_page((vm_offset_t)va + length); 450 for (; va < (caddr_t) endva ; va += PAGE_SIZE) { 451 phys = trunc_page(pmap_extract(kernel_pmap, (vm_offset_t)va)); 452#ifdef EPSON_BOUNCEDMA 453#define ISARAM_END 0xf00000 454#else 455#define ISARAM_END RAM_END 456#endif 457 if (phys == 0) 458 panic("isa_dmacheck: no physical page present"); 459 if (phys >= ISARAM_END) 460 return (1); 461 if (priorpage) { 462 if (priorpage + PAGE_SIZE != phys) 463 return (1); 464 /* check if crossing a DMA page boundary */ 465 if (((u_int)priorpage ^ (u_int)phys) & dma_pgmsk) 466 return (1); 467 } 468 priorpage = phys; 469 } 470 return (0); 471} 472 473/* 474 * Query the progress of a transfer on a DMA channel. 475 * 476 * To avoid having to interrupt a transfer in progress, we sample 477 * each of the high and low databytes twice, and apply the following 478 * logic to determine the correct count. 479 * 480 * Reads are performed with interrupts disabled, thus it is to be 481 * expected that the time between reads is very small. At most 482 * one rollover in the low count byte can be expected within the 483 * four reads that are performed. 484 * 485 * There are three gaps in which a rollover can occur : 486 * 487 * - read low1 488 * gap1 489 * - read high1 490 * gap2 491 * - read low2 492 * gap3 493 * - read high2 494 * 495 * If a rollover occurs in gap1 or gap2, the low2 value will be 496 * greater than the low1 value. In this case, low2 and high2 are a 497 * corresponding pair. 498 * 499 * In any other case, low1 and high1 can be considered to be correct. 500 * 501 * The function returns the number of bytes remaining in the transfer, 502 * or -1 if the channel requested is not active. 503 * 504 */ 505int 506isa_dmastatus(int chan) 507{ 508 u_long cnt = 0; 509 int ffport, waport; 510 u_long low1, high1, low2, high2; 511 512 /* channel active? */ 513 if ((dma_inuse & (1 << chan)) == 0) { 514 printf("isa_dmastatus: channel %d not active\n", chan); 515 return(-1); 516 } 517 /* channel busy? */ 518 519 if (((dma_busy & (1 << chan)) == 0) && 520 (dma_auto_mode & (1 << chan)) == 0 ) { 521 printf("chan %d not busy\n", chan); 522 return -2 ; 523 } 524#ifdef PC98 525 ffport = DMA1_FFC; 526 waport = DMA1_CHN(chan) + 2; 527#else 528 if (chan < 4) { /* low DMA controller */ 529 ffport = DMA1_FFC; 530 waport = DMA1_CHN(chan) + 1; 531 } else { /* high DMA controller */ 532 ffport = DMA2_FFC; 533 waport = DMA2_CHN(chan - 4) + 2; 534 } 535#endif 536 537 disable_intr(); /* no interrupts Mr Jones! */ 538 outb(ffport, 0); /* clear register LSB flipflop */ 539 low1 = inb(waport); 540 high1 = inb(waport); 541 outb(ffport, 0); /* clear again */ 542 low2 = inb(waport); 543 high2 = inb(waport); 544 enable_intr(); /* enable interrupts again */ 545 546 /* 547 * Now decide if a wrap has tried to skew our results. 548 * Note that after TC, the count will read 0xffff, while we want 549 * to return zero, so we add and then mask to compensate. 550 */ 551 if (low1 >= low2) { 552 cnt = (low1 + (high1 << 8) + 1) & 0xffff; 553 } else { 554 cnt = (low2 + (high2 << 8) + 1) & 0xffff; 555 } 556 557 if (chan >= 4) /* high channels move words */ 558 cnt *= 2; 559 return(cnt); 560} 561 562/* 563 * Stop a DMA transfer currently in progress. 564 */ 565int 566isa_dmastop(int chan) 567{ 568 if ((dma_inuse & (1 << chan)) == 0) 569 printf("isa_dmastop: channel %d not acquired\n", chan); 570 571 if (((dma_busy & (1 << chan)) == 0) && 572 ((dma_auto_mode & (1 << chan)) == 0)) { 573 printf("chan %d not busy\n", chan); 574 return -2 ; 575 } 576 577 if ((chan & 4) == 0) { 578 outb(DMA1_SMSK, (chan & 3) | 4 /* disable mask */); 579 } else { 580#ifndef PC98 581 outb(DMA2_SMSK, (chan & 3) | 4 /* disable mask */); 582#endif 583 } 584 return(isa_dmastatus(chan)); 585} 586 587/* 588 * Attach to the ISA PnP descriptor for the AT DMA controller 589 */ 590static struct isa_pnp_id atdma_ids[] = { 591 { 0x0002d041 /* PNP0200 */, "AT DMA controller" }, 592 { 0 } 593}; 594 595static int 596atdma_probe(device_t dev) 597{ 598 int result; 599 600 if ((result = ISA_PNP_PROBE(device_get_parent(dev), dev, atdma_ids)) <= 0) 601 device_quiet(dev); 602 return(result); 603} 604 605static int 606atdma_attach(device_t dev) 607{ 608 return(0); 609} 610 611static device_method_t atdma_methods[] = { 612 /* Device interface */ 613 DEVMETHOD(device_probe, atdma_probe), 614 DEVMETHOD(device_attach, atdma_attach), 615 DEVMETHOD(device_detach, bus_generic_detach), 616 DEVMETHOD(device_shutdown, bus_generic_shutdown), 617 DEVMETHOD(device_suspend, bus_generic_suspend), 618 DEVMETHOD(device_resume, bus_generic_resume), 619 { 0, 0 } 620}; 621 622static driver_t atdma_driver = { 623 "atdma", 624 atdma_methods, 625 1, /* no softc */ 626}; 627 628static devclass_t atdma_devclass; 629 630DRIVER_MODULE(atdma, isa, atdma_driver, atdma_devclass, 0, 0); 631#ifndef PC98 632DRIVER_MODULE(atdma, acpi, atdma_driver, atdma_devclass, 0, 0); 633#endif 634