cbus_dma.c revision 131817
1/*- 2 * Copyright (c) 1991 The Regents of the University of California. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to Berkeley by 6 * William Jolitz. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 4. Neither the name of the University nor the names of its contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 30 * SUCH DAMAGE. 31 * 32 * from: @(#)isa.c 7.2 (Berkeley) 5/13/91 33 * $FreeBSD: head/sys/pc98/cbus/cbus_dma.c 131817 2004-07-08 13:48:49Z nyan $ 34 */ 35 36/* 37 * code to manage AT bus 38 * 39 * 92/08/18 Frank P. MacLachlan (fpm@crash.cts.com): 40 * Fixed uninitialized variable problem and added code to deal 41 * with DMA page boundaries in isa_dmarangecheck(). Fixed word 42 * mode DMA count compution and reorganized DMA setup code in 43 * isa_dmastart() 44 */ 45 46#ifdef PC98 47#include "opt_pc98.h" 48#endif 49 50#include <sys/param.h> 51#include <sys/systm.h> 52#include <sys/bus.h> 53#include <sys/kernel.h> 54#include <sys/malloc.h> 55#include <sys/lock.h> 56#include <sys/proc.h> 57#include <sys/mutex.h> 58#include <sys/module.h> 59#ifdef PC98 60#include <machine/md_var.h> 61#endif 62#include <vm/vm.h> 63#include <vm/vm_param.h> 64#include <vm/pmap.h> 65#ifdef PC98 66#include <pc98/pc98/pc98.h> 67#else 68#include <i386/isa/isa.h> 69#endif 70#include <dev/ic/i8237.h> 71#include <isa/isavar.h> 72 73/* 74** Register definitions for DMA controller 1 (channels 0..3): 75*/ 76#ifdef PC98 77#define DMA1_CHN(c) (IO_DMA + (4*(c))) /* addr reg for channel c */ 78#define DMA1_SMSK (IO_DMA + 0x14) /* single mask register */ 79#define DMA1_MODE (IO_DMA + 0x16) /* mode register */ 80#define DMA1_FFC (IO_DMA + 0x18) /* clear first/last FF */ 81#else 82#define DMA1_CHN(c) (IO_DMA1 + 1*(2*(c))) /* addr reg for channel c */ 83#define DMA1_SMSK (IO_DMA1 + 1*10) /* single mask register */ 84#define DMA1_MODE (IO_DMA1 + 1*11) /* mode register */ 85#define DMA1_FFC (IO_DMA1 + 1*12) /* clear first/last FF */ 86#endif 87 88/* 89** Register definitions for DMA controller 2 (channels 4..7): 90*/ 91#define DMA2_CHN(c) (IO_DMA2 + 2*(2*(c))) /* addr reg for channel c */ 92#define DMA2_SMSK (IO_DMA2 + 2*10) /* single mask register */ 93#define DMA2_MODE (IO_DMA2 + 2*11) /* mode register */ 94#define DMA2_FFC (IO_DMA2 + 2*12) /* clear first/last FF */ 95 96static int isa_dmarangecheck(caddr_t va, u_int length, int chan); 97 98#ifdef PC98 99static caddr_t dma_bouncebuf[4]; 100static u_int dma_bouncebufsize[4]; 101#else 102static caddr_t dma_bouncebuf[8]; 103static u_int dma_bouncebufsize[8]; 104#endif 105static u_int8_t dma_bounced = 0; 106static u_int8_t dma_busy = 0; /* Used in isa_dmastart() */ 107static u_int8_t dma_inuse = 0; /* User for acquire/release */ 108static u_int8_t dma_auto_mode = 0; 109 110#ifdef PC98 111#define VALID_DMA_MASK (3) 112#else 113#define VALID_DMA_MASK (7) 114#endif 115 116/* high byte of address is stored in this port for i-th dma channel */ 117#ifdef PC98 118static int dmapageport[4] = { 0x27, 0x21, 0x23, 0x25 }; 119#else 120static int dmapageport[8] = { 0x87, 0x83, 0x81, 0x82, 0x8f, 0x8b, 0x89, 0x8a }; 121#endif 122 123/* 124 * Setup a DMA channel's bounce buffer. 125 */ 126void 127isa_dmainit(chan, bouncebufsize) 128 int chan; 129 u_int bouncebufsize; 130{ 131 void *buf; 132 133#ifndef PC98 134 /* 135 * If a DMA channel is shared, both drivers have to call isa_dmainit 136 * since they don't know that the other driver will do it. 137 * Just return if we're already set up good. 138 * XXX: this only works if they agree on the bouncebuf size. This 139 * XXX: is typically the case since they are multiple instances of 140 * XXX: the same driver. 141 */ 142 if (dma_bouncebuf[chan] != NULL) 143 return; 144#endif 145 146#ifdef DIAGNOSTIC 147 if (chan & ~VALID_DMA_MASK) 148 panic("isa_dmainit: channel out of range"); 149#ifdef PC98 150 if (dma_bouncebuf[chan] != NULL) 151 panic("isa_dmainit: impossible request"); 152#endif 153#endif 154 155 dma_bouncebufsize[chan] = bouncebufsize; 156 157 /* Try malloc() first. It works better if it works. */ 158 buf = malloc(bouncebufsize, M_DEVBUF, M_NOWAIT); 159 if (buf != NULL) { 160 if (isa_dmarangecheck(buf, bouncebufsize, chan) == 0) { 161 dma_bouncebuf[chan] = buf; 162 return; 163 } 164 free(buf, M_DEVBUF); 165 } 166 buf = contigmalloc(bouncebufsize, M_DEVBUF, M_NOWAIT, 0ul, 0xfffffful, 167 1ul, chan & 4 ? 0x20000ul : 0x10000ul); 168 if (buf == NULL) 169 printf("isa_dmainit(%d, %d) failed\n", chan, bouncebufsize); 170 else 171 dma_bouncebuf[chan] = buf; 172} 173 174/* 175 * Register a DMA channel's usage. Usually called from a device driver 176 * in open() or during its initialization. 177 */ 178int 179isa_dma_acquire(chan) 180 int chan; 181{ 182#ifdef DIAGNOSTIC 183 if (chan & ~VALID_DMA_MASK) 184 panic("isa_dma_acquire: channel out of range"); 185#endif 186 187 if (dma_inuse & (1 << chan)) { 188 printf("isa_dma_acquire: channel %d already in use\n", chan); 189 return (EBUSY); 190 } 191 dma_inuse |= (1 << chan); 192 dma_auto_mode &= ~(1 << chan); 193 194 return (0); 195} 196 197/* 198 * Unregister a DMA channel's usage. Usually called from a device driver 199 * during close() or during its shutdown. 200 */ 201void 202isa_dma_release(chan) 203 int chan; 204{ 205#ifdef DIAGNOSTIC 206 if (chan & ~VALID_DMA_MASK) 207 panic("isa_dma_release: channel out of range"); 208 209 if ((dma_inuse & (1 << chan)) == 0) 210 printf("isa_dma_release: channel %d not in use\n", chan); 211#endif 212 213 if (dma_busy & (1 << chan)) { 214 dma_busy &= ~(1 << chan); 215 /* 216 * XXX We should also do "dma_bounced &= (1 << chan);" 217 * because we are acting on behalf of isa_dmadone() which 218 * was not called to end the last DMA operation. This does 219 * not matter now, but it may in the future. 220 */ 221 } 222 223 dma_inuse &= ~(1 << chan); 224 dma_auto_mode &= ~(1 << chan); 225} 226 227#ifndef PC98 228/* 229 * isa_dmacascade(): program 8237 DMA controller channel to accept 230 * external dma control by a board. 231 */ 232void 233isa_dmacascade(chan) 234 int chan; 235{ 236#ifdef DIAGNOSTIC 237 if (chan & ~VALID_DMA_MASK) 238 panic("isa_dmacascade: channel out of range"); 239#endif 240 241 /* set dma channel mode, and set dma channel mode */ 242 if ((chan & 4) == 0) { 243 outb(DMA1_MODE, DMA37MD_CASCADE | chan); 244 outb(DMA1_SMSK, chan); 245 } else { 246 outb(DMA2_MODE, DMA37MD_CASCADE | (chan & 3)); 247 outb(DMA2_SMSK, chan & 3); 248 } 249} 250#endif 251 252/* 253 * isa_dmastart(): program 8237 DMA controller channel, avoid page alignment 254 * problems by using a bounce buffer. 255 */ 256void 257isa_dmastart(int flags, caddr_t addr, u_int nbytes, int chan) 258{ 259 vm_offset_t phys; 260 int waport; 261 caddr_t newaddr; 262 263 GIANT_REQUIRED; 264 265#ifdef DIAGNOSTIC 266 if (chan & ~VALID_DMA_MASK) 267 panic("isa_dmastart: channel out of range"); 268 269 if ((chan < 4 && nbytes > (1<<16)) 270 || (chan >= 4 && (nbytes > (1<<17) || (u_int)addr & 1))) 271 panic("isa_dmastart: impossible request"); 272 273 if ((dma_inuse & (1 << chan)) == 0) 274 printf("isa_dmastart: channel %d not acquired\n", chan); 275#endif 276 277#if 0 278 /* 279 * XXX This should be checked, but drivers like ad1848 only call 280 * isa_dmastart() once because they use Auto DMA mode. If we 281 * leave this in, drivers that do this will print this continuously. 282 */ 283 if (dma_busy & (1 << chan)) 284 printf("isa_dmastart: channel %d busy\n", chan); 285#endif 286 287 dma_busy |= (1 << chan); 288 289 if (isa_dmarangecheck(addr, nbytes, chan)) { 290 if (dma_bouncebuf[chan] == NULL 291 || dma_bouncebufsize[chan] < nbytes) 292 panic("isa_dmastart: bad bounce buffer"); 293 dma_bounced |= (1 << chan); 294 newaddr = dma_bouncebuf[chan]; 295 296 /* copy bounce buffer on write */ 297 if (!(flags & ISADMA_READ)) 298 bcopy(addr, newaddr, nbytes); 299 addr = newaddr; 300 } 301 302 /* translate to physical */ 303 phys = pmap_extract(kernel_pmap, (vm_offset_t)addr); 304 305 if (flags & ISADMA_RAW) { 306 dma_auto_mode |= (1 << chan); 307 } else { 308 dma_auto_mode &= ~(1 << chan); 309 } 310 311#ifdef PC98 312 if (need_pre_dma_flush) 313 wbinvd(); /* wbinvd (WB cache flush) */ 314#endif 315 316#ifndef PC98 317 if ((chan & 4) == 0) { 318 /* 319 * Program one of DMA channels 0..3. These are 320 * byte mode channels. 321 */ 322#endif 323 /* set dma channel mode, and reset address ff */ 324 325 /* If ISADMA_RAW flag is set, then use autoinitialise mode */ 326 if (flags & ISADMA_RAW) { 327 if (flags & ISADMA_READ) 328 outb(DMA1_MODE, DMA37MD_AUTO|DMA37MD_WRITE|chan); 329 else 330 outb(DMA1_MODE, DMA37MD_AUTO|DMA37MD_READ|chan); 331 } 332 else 333 if (flags & ISADMA_READ) 334 outb(DMA1_MODE, DMA37MD_SINGLE|DMA37MD_WRITE|chan); 335 else 336 outb(DMA1_MODE, DMA37MD_SINGLE|DMA37MD_READ|chan); 337 outb(DMA1_FFC, 0); 338 339 /* send start address */ 340 waport = DMA1_CHN(chan); 341 outb(waport, phys); 342 outb(waport, phys>>8); 343 outb(dmapageport[chan], phys>>16); 344 345 /* send count */ 346#ifdef PC98 347 outb(waport + 2, --nbytes); 348 outb(waport + 2, nbytes>>8); 349#else 350 outb(waport + 1, --nbytes); 351 outb(waport + 1, nbytes>>8); 352#endif 353 354 /* unmask channel */ 355 outb(DMA1_SMSK, chan); 356#ifndef PC98 357 } else { 358 /* 359 * Program one of DMA channels 4..7. These are 360 * word mode channels. 361 */ 362 /* set dma channel mode, and reset address ff */ 363 364 /* If ISADMA_RAW flag is set, then use autoinitialise mode */ 365 if (flags & ISADMA_RAW) { 366 if (flags & ISADMA_READ) 367 outb(DMA2_MODE, DMA37MD_AUTO|DMA37MD_WRITE|(chan&3)); 368 else 369 outb(DMA2_MODE, DMA37MD_AUTO|DMA37MD_READ|(chan&3)); 370 } 371 else 372 if (flags & ISADMA_READ) 373 outb(DMA2_MODE, DMA37MD_SINGLE|DMA37MD_WRITE|(chan&3)); 374 else 375 outb(DMA2_MODE, DMA37MD_SINGLE|DMA37MD_READ|(chan&3)); 376 outb(DMA2_FFC, 0); 377 378 /* send start address */ 379 waport = DMA2_CHN(chan - 4); 380 outb(waport, phys>>1); 381 outb(waport, phys>>9); 382 outb(dmapageport[chan], phys>>16); 383 384 /* send count */ 385 nbytes >>= 1; 386 outb(waport + 2, --nbytes); 387 outb(waport + 2, nbytes>>8); 388 389 /* unmask channel */ 390 outb(DMA2_SMSK, chan & 3); 391 } 392#endif 393} 394 395void 396isa_dmadone(int flags, caddr_t addr, int nbytes, int chan) 397{ 398#ifdef PC98 399 if (flags & ISADMA_READ) { 400 /* cache flush only after reading 92/12/9 by A.Kojima */ 401 if (need_post_dma_flush) 402 invd(); 403 } 404#endif 405 406#ifdef DIAGNOSTIC 407 if (chan & ~VALID_DMA_MASK) 408 panic("isa_dmadone: channel out of range"); 409 410 if ((dma_inuse & (1 << chan)) == 0) 411 printf("isa_dmadone: channel %d not acquired\n", chan); 412#endif 413 414 if (((dma_busy & (1 << chan)) == 0) && 415 (dma_auto_mode & (1 << chan)) == 0 ) 416 printf("isa_dmadone: channel %d not busy\n", chan); 417 418#ifdef PC98 419 if ((dma_auto_mode & (1 << chan)) == 0) 420 outb(DMA1_SMSK, (chan & 3) | 4); 421#else 422 if ((dma_auto_mode & (1 << chan)) == 0) 423 outb(chan & 4 ? DMA2_SMSK : DMA1_SMSK, (chan & 3) | 4); 424#endif 425 426 if (dma_bounced & (1 << chan)) { 427 /* copy bounce buffer on read */ 428 if (flags & ISADMA_READ) 429 bcopy(dma_bouncebuf[chan], addr, nbytes); 430 431 dma_bounced &= ~(1 << chan); 432 } 433 dma_busy &= ~(1 << chan); 434} 435 436/* 437 * Check for problems with the address range of a DMA transfer 438 * (non-contiguous physical pages, outside of bus address space, 439 * crossing DMA page boundaries). 440 * Return true if special handling needed. 441 */ 442 443static int 444isa_dmarangecheck(caddr_t va, u_int length, int chan) 445{ 446 vm_offset_t phys, priorpage = 0, endva; 447 u_int dma_pgmsk = (chan & 4) ? ~(128*1024-1) : ~(64*1024-1); 448 449 GIANT_REQUIRED; 450 451 endva = (vm_offset_t)round_page((vm_offset_t)va + length); 452 for (; va < (caddr_t) endva ; va += PAGE_SIZE) { 453 phys = trunc_page(pmap_extract(kernel_pmap, (vm_offset_t)va)); 454#ifdef EPSON_BOUNCEDMA 455#define ISARAM_END 0xf00000 456#else 457#define ISARAM_END RAM_END 458#endif 459 if (phys == 0) 460 panic("isa_dmacheck: no physical page present"); 461 if (phys >= ISARAM_END) 462 return (1); 463 if (priorpage) { 464 if (priorpage + PAGE_SIZE != phys) 465 return (1); 466 /* check if crossing a DMA page boundary */ 467 if (((u_int)priorpage ^ (u_int)phys) & dma_pgmsk) 468 return (1); 469 } 470 priorpage = phys; 471 } 472 return (0); 473} 474 475/* 476 * Query the progress of a transfer on a DMA channel. 477 * 478 * To avoid having to interrupt a transfer in progress, we sample 479 * each of the high and low databytes twice, and apply the following 480 * logic to determine the correct count. 481 * 482 * Reads are performed with interrupts disabled, thus it is to be 483 * expected that the time between reads is very small. At most 484 * one rollover in the low count byte can be expected within the 485 * four reads that are performed. 486 * 487 * There are three gaps in which a rollover can occur : 488 * 489 * - read low1 490 * gap1 491 * - read high1 492 * gap2 493 * - read low2 494 * gap3 495 * - read high2 496 * 497 * If a rollover occurs in gap1 or gap2, the low2 value will be 498 * greater than the low1 value. In this case, low2 and high2 are a 499 * corresponding pair. 500 * 501 * In any other case, low1 and high1 can be considered to be correct. 502 * 503 * The function returns the number of bytes remaining in the transfer, 504 * or -1 if the channel requested is not active. 505 * 506 */ 507int 508isa_dmastatus(int chan) 509{ 510 u_long cnt = 0; 511 int ffport, waport; 512 u_long low1, high1, low2, high2; 513 514 /* channel active? */ 515 if ((dma_inuse & (1 << chan)) == 0) { 516 printf("isa_dmastatus: channel %d not active\n", chan); 517 return(-1); 518 } 519 /* channel busy? */ 520 521 if (((dma_busy & (1 << chan)) == 0) && 522 (dma_auto_mode & (1 << chan)) == 0 ) { 523 printf("chan %d not busy\n", chan); 524 return -2 ; 525 } 526#ifdef PC98 527 ffport = DMA1_FFC; 528 waport = DMA1_CHN(chan) + 2; 529#else 530 if (chan < 4) { /* low DMA controller */ 531 ffport = DMA1_FFC; 532 waport = DMA1_CHN(chan) + 1; 533 } else { /* high DMA controller */ 534 ffport = DMA2_FFC; 535 waport = DMA2_CHN(chan - 4) + 2; 536 } 537#endif 538 539 disable_intr(); /* no interrupts Mr Jones! */ 540 outb(ffport, 0); /* clear register LSB flipflop */ 541 low1 = inb(waport); 542 high1 = inb(waport); 543 outb(ffport, 0); /* clear again */ 544 low2 = inb(waport); 545 high2 = inb(waport); 546 enable_intr(); /* enable interrupts again */ 547 548 /* 549 * Now decide if a wrap has tried to skew our results. 550 * Note that after TC, the count will read 0xffff, while we want 551 * to return zero, so we add and then mask to compensate. 552 */ 553 if (low1 >= low2) { 554 cnt = (low1 + (high1 << 8) + 1) & 0xffff; 555 } else { 556 cnt = (low2 + (high2 << 8) + 1) & 0xffff; 557 } 558 559 if (chan >= 4) /* high channels move words */ 560 cnt *= 2; 561 return(cnt); 562} 563 564/* 565 * Stop a DMA transfer currently in progress. 566 */ 567int 568isa_dmastop(int chan) 569{ 570 if ((dma_inuse & (1 << chan)) == 0) 571 printf("isa_dmastop: channel %d not acquired\n", chan); 572 573 if (((dma_busy & (1 << chan)) == 0) && 574 ((dma_auto_mode & (1 << chan)) == 0)) { 575 printf("chan %d not busy\n", chan); 576 return -2 ; 577 } 578 579 if ((chan & 4) == 0) { 580 outb(DMA1_SMSK, (chan & 3) | 4 /* disable mask */); 581 } else { 582#ifndef PC98 583 outb(DMA2_SMSK, (chan & 3) | 4 /* disable mask */); 584#endif 585 } 586 return(isa_dmastatus(chan)); 587} 588 589/* 590 * Attach to the ISA PnP descriptor for the AT DMA controller 591 */ 592static struct isa_pnp_id atdma_ids[] = { 593 { 0x0002d041 /* PNP0200 */, "AT DMA controller" }, 594 { 0 } 595}; 596 597static int 598atdma_probe(device_t dev) 599{ 600 int result; 601 602 if ((result = ISA_PNP_PROBE(device_get_parent(dev), dev, atdma_ids)) <= 0) 603 device_quiet(dev); 604 return(result); 605} 606 607static int 608atdma_attach(device_t dev) 609{ 610 return(0); 611} 612 613static device_method_t atdma_methods[] = { 614 /* Device interface */ 615 DEVMETHOD(device_probe, atdma_probe), 616 DEVMETHOD(device_attach, atdma_attach), 617 DEVMETHOD(device_detach, bus_generic_detach), 618 DEVMETHOD(device_shutdown, bus_generic_shutdown), 619 DEVMETHOD(device_suspend, bus_generic_suspend), 620 DEVMETHOD(device_resume, bus_generic_resume), 621 { 0, 0 } 622}; 623 624static driver_t atdma_driver = { 625 "atdma", 626 atdma_methods, 627 1, /* no softc */ 628}; 629 630static devclass_t atdma_devclass; 631 632DRIVER_MODULE(atdma, isa, atdma_driver, atdma_devclass, 0, 0); 633#ifndef PC98 634DRIVER_MODULE(atdma, acpi, atdma_driver, atdma_devclass, 0, 0); 635#endif 636