1/*- 2 * Copyright (c) 2014-2018, Matthew Macy <mmacy@mattmacy.io> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Neither the name of Matthew Macy nor the names of its 12 * contributors may be used to endorse or promote products derived from 13 * this software without specific prior written permission. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28#include <sys/cdefs.h> 29__FBSDID("$FreeBSD: stable/11/sys/net/iflib.c 361063 2020-05-14 21:59:23Z erj $"); 30 31#include "opt_inet.h" 32#include "opt_inet6.h" 33#include "opt_acpi.h" 34#include "opt_sched.h" 35 36#include <sys/param.h> 37#include <sys/types.h> 38#include <sys/bus.h> 39#include <sys/eventhandler.h> 40#include <sys/sockio.h> 41#include <sys/kernel.h> 42#include <sys/lock.h> 43#include <sys/mutex.h> 44#include <sys/module.h> 45#include <sys/kobj.h> 46#include <sys/rman.h> 47#include <sys/sbuf.h> 48#include <sys/smp.h> 49#include <sys/socket.h> 50#include <sys/sysctl.h> 51#include <sys/syslog.h> 52#include <sys/taskqueue.h> 53#include <sys/limits.h> 54 55 56#include <net/if.h> 57#include <net/if_var.h> 58#include <net/if_types.h> 59#include <net/if_media.h> 60#include <net/bpf.h> 61#include <net/ethernet.h> 62#include <net/mp_ring.h> 63#include <net/vnet.h> 64 65#include <netinet/in.h> 66#include <netinet/in_pcb.h> 67#include <netinet/tcp_lro.h> 68#include <netinet/in_systm.h> 69#include <netinet/if_ether.h> 70#include <netinet/ip.h> 71#include <netinet/ip6.h> 72#include <netinet/tcp.h> 73#include <netinet/ip_var.h> 74#include <netinet6/ip6_var.h> 75 76#include <machine/bus.h> 77#include <machine/in_cksum.h> 78 79#include <vm/vm.h> 80#include <vm/pmap.h> 81 82#include <dev/led/led.h> 83#include <dev/pci/pcireg.h> 84#include <dev/pci/pcivar.h> 85#include <dev/pci/pci_private.h> 86 87#include <net/iflib.h> 88 89#include "ifdi_if.h" 90 91#if defined(__i386__) || defined(__amd64__) 92#include <sys/memdesc.h> 93#include <machine/bus.h> 94#include <machine/md_var.h> 95#include <machine/specialreg.h> 96#include <x86/include/busdma_impl.h> 97#include <x86/iommu/busdma_dmar.h> 98#endif 99 100#ifdef PCI_IOV 101#include <dev/pci/pci_iov.h> 102#endif 103 104 105#include <sys/bitstring.h> 106/* 107 * enable accounting of every mbuf as it comes in to and goes out of 108 * iflib's software descriptor references 109 */ 110#define MEMORY_LOGGING 0 111/* 112 * Enable mbuf vectors for compressing long mbuf chains 113 */ 114 115/* 116 * NB: 117 * - Prefetching in tx cleaning should perhaps be a tunable. The distance ahead 118 * we prefetch needs to be determined by the time spent in m_free vis a vis 119 * the cost of a prefetch. This will of course vary based on the workload: 120 * - NFLX's m_free path is dominated by vm-based M_EXT manipulation which 121 * is quite expensive, thus suggesting very little prefetch. 122 * - small packet forwarding which is just returning a single mbuf to 123 * UMA will typically be very fast vis a vis the cost of a memory 124 * access. 125 */ 126 127 128/* 129 * File organization: 130 * - private structures 131 * - iflib private utility functions 132 * - ifnet functions 133 * - vlan registry and other exported functions 134 * - iflib public core functions 135 * 136 * 137 */ 138static MALLOC_DEFINE(M_IFLIB, "iflib", "ifnet library"); 139 140#define IFLIB_RXEOF_MORE (1U << 0) 141#define IFLIB_RXEOF_EMPTY (2U << 0) 142 143struct iflib_txq; 144typedef struct iflib_txq *iflib_txq_t; 145struct iflib_rxq; 146typedef struct iflib_rxq *iflib_rxq_t; 147struct iflib_fl; 148typedef struct iflib_fl *iflib_fl_t; 149 150static void iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid); 151 152typedef struct iflib_filter_info { 153 driver_filter_t *ifi_filter; 154 void *ifi_filter_arg; 155 struct grouptask *ifi_task; 156 void *ifi_ctx; 157} *iflib_filter_info_t; 158 159struct iflib_ctx { 160 KOBJ_FIELDS; 161 /* 162 * Pointer to hardware driver's softc 163 */ 164 void *ifc_softc; 165 device_t ifc_dev; 166 if_t ifc_ifp; 167 168 cpuset_t ifc_cpus; 169 if_shared_ctx_t ifc_sctx; 170 struct if_softc_ctx ifc_softc_ctx; 171 172 struct mtx ifc_ctx_mtx; 173 struct mtx ifc_state_mtx; 174 175 uint16_t ifc_nhwtxqs; 176 177 iflib_txq_t ifc_txqs; 178 iflib_rxq_t ifc_rxqs; 179 uint32_t ifc_if_flags; 180 uint32_t ifc_flags; 181 uint32_t ifc_max_fl_buf_size; 182 uint32_t ifc_rx_mbuf_sz; 183 184 int ifc_link_state; 185 int ifc_link_irq; 186 int ifc_watchdog_events; 187 struct cdev *ifc_led_dev; 188 struct resource *ifc_msix_mem; 189 190 struct if_irq ifc_legacy_irq; 191 struct grouptask ifc_admin_task; 192 struct grouptask ifc_vflr_task; 193 struct iflib_filter_info ifc_filter_info; 194 struct ifmedia ifc_media; 195 196 struct sysctl_oid *ifc_sysctl_node; 197 uint16_t ifc_sysctl_ntxqs; 198 uint16_t ifc_sysctl_nrxqs; 199 uint16_t ifc_sysctl_qs_eq_override; 200 uint16_t ifc_sysctl_rx_budget; 201 202 qidx_t ifc_sysctl_ntxds[8]; 203 qidx_t ifc_sysctl_nrxds[8]; 204 struct if_txrx ifc_txrx; 205#define isc_txd_encap ifc_txrx.ift_txd_encap 206#define isc_txd_flush ifc_txrx.ift_txd_flush 207#define isc_txd_credits_update ifc_txrx.ift_txd_credits_update 208#define isc_rxd_available ifc_txrx.ift_rxd_available 209#define isc_rxd_pkt_get ifc_txrx.ift_rxd_pkt_get 210#define isc_rxd_refill ifc_txrx.ift_rxd_refill 211#define isc_rxd_flush ifc_txrx.ift_rxd_flush 212#define isc_rxd_refill ifc_txrx.ift_rxd_refill 213#define isc_rxd_refill ifc_txrx.ift_rxd_refill 214#define isc_legacy_intr ifc_txrx.ift_legacy_intr 215 eventhandler_tag ifc_vlan_attach_event; 216 eventhandler_tag ifc_vlan_detach_event; 217 uint8_t ifc_mac[ETHER_ADDR_LEN]; 218 char ifc_mtx_name[16]; 219}; 220 221 222void * 223iflib_get_softc(if_ctx_t ctx) 224{ 225 226 return (ctx->ifc_softc); 227} 228 229device_t 230iflib_get_dev(if_ctx_t ctx) 231{ 232 233 return (ctx->ifc_dev); 234} 235 236if_t 237iflib_get_ifp(if_ctx_t ctx) 238{ 239 240 return (ctx->ifc_ifp); 241} 242 243struct ifmedia * 244iflib_get_media(if_ctx_t ctx) 245{ 246 247 return (&ctx->ifc_media); 248} 249 250void 251iflib_set_mac(if_ctx_t ctx, uint8_t mac[ETHER_ADDR_LEN]) 252{ 253 254 bcopy(mac, ctx->ifc_mac, ETHER_ADDR_LEN); 255} 256 257if_softc_ctx_t 258iflib_get_softc_ctx(if_ctx_t ctx) 259{ 260 261 return (&ctx->ifc_softc_ctx); 262} 263 264if_shared_ctx_t 265iflib_get_sctx(if_ctx_t ctx) 266{ 267 268 return (ctx->ifc_sctx); 269} 270 271#define IP_ALIGNED(m) ((((uintptr_t)(m)->m_data) & 0x3) == 0x2) 272#define CACHE_PTR_INCREMENT (CACHE_LINE_SIZE/sizeof(void*)) 273#define CACHE_PTR_NEXT(ptr) ((void *)(((uintptr_t)(ptr)+CACHE_LINE_SIZE-1) & (CACHE_LINE_SIZE-1))) 274 275#define LINK_ACTIVE(ctx) ((ctx)->ifc_link_state == LINK_STATE_UP) 276#define CTX_IS_VF(ctx) ((ctx)->ifc_sctx->isc_flags & IFLIB_IS_VF) 277 278#define RX_SW_DESC_MAP_CREATED (1 << 0) 279#define TX_SW_DESC_MAP_CREATED (1 << 1) 280#define RX_SW_DESC_INUSE (1 << 3) 281#define TX_SW_DESC_MAPPED (1 << 4) 282 283#define M_TOOBIG M_PROTO1 284 285typedef struct iflib_sw_rx_desc_array { 286 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */ 287 struct mbuf **ifsd_m; /* pkthdr mbufs */ 288 caddr_t *ifsd_cl; /* direct cluster pointer for rx */ 289 uint8_t *ifsd_flags; 290} iflib_rxsd_array_t; 291 292typedef struct iflib_sw_tx_desc_array { 293 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */ 294 struct mbuf **ifsd_m; /* pkthdr mbufs */ 295 uint8_t *ifsd_flags; 296} if_txsd_vec_t; 297 298 299/* magic number that should be high enough for any hardware */ 300#define IFLIB_MAX_TX_SEGS 128 301/* bnxt supports 64 with hardware LRO enabled */ 302#define IFLIB_MAX_RX_SEGS 64 303#define IFLIB_RX_COPY_THRESH 128 304#define IFLIB_MAX_RX_REFRESH 32 305/* The minimum descriptors per second before we start coalescing */ 306#define IFLIB_MIN_DESC_SEC 16384 307#define IFLIB_DEFAULT_TX_UPDATE_FREQ 16 308#define IFLIB_QUEUE_IDLE 0 309#define IFLIB_QUEUE_HUNG 1 310#define IFLIB_QUEUE_WORKING 2 311/* maximum number of txqs that can share an rx interrupt */ 312#define IFLIB_MAX_TX_SHARED_INTR 4 313 314/* this should really scale with ring size - this is a fairly arbitrary value */ 315#define TX_BATCH_SIZE 32 316 317#define IFLIB_RESTART_BUDGET 8 318 319#define IFC_LEGACY 0x001 320#define IFC_QFLUSH 0x002 321#define IFC_MULTISEG 0x004 322#define IFC_DMAR 0x008 323#define IFC_SC_ALLOCATED 0x010 324#define IFC_INIT_DONE 0x020 325#define IFC_PREFETCH 0x040 326#define IFC_DO_RESET 0x080 327#define IFC_DO_WATCHDOG 0x100 328#define IFC_CHECK_HUNG 0x200 329#define IFC_IN_DETACH 0x800 330 331 332#define CSUM_OFFLOAD (CSUM_IP_TSO|CSUM_IP6_TSO|CSUM_IP| \ 333 CSUM_IP_UDP|CSUM_IP_TCP|CSUM_IP_SCTP| \ 334 CSUM_IP6_UDP|CSUM_IP6_TCP|CSUM_IP6_SCTP) 335struct iflib_txq { 336 qidx_t ift_in_use; 337 qidx_t ift_cidx; 338 qidx_t ift_cidx_processed; 339 qidx_t ift_pidx; 340 uint8_t ift_gen; 341 uint8_t ift_br_offset; 342 uint16_t ift_npending; 343 uint16_t ift_db_pending; 344 uint16_t ift_rs_pending; 345 /* implicit pad */ 346 uint8_t ift_txd_size[8]; 347 uint64_t ift_processed; 348 uint64_t ift_cleaned; 349 uint64_t ift_cleaned_prev; 350#if MEMORY_LOGGING 351 uint64_t ift_enqueued; 352 uint64_t ift_dequeued; 353#endif 354 uint64_t ift_no_tx_dma_setup; 355 uint64_t ift_no_desc_avail; 356 uint64_t ift_mbuf_defrag_failed; 357 uint64_t ift_mbuf_defrag; 358 uint64_t ift_map_failed; 359 uint64_t ift_txd_encap_efbig; 360 uint64_t ift_pullups; 361 362 struct mtx ift_mtx; 363 struct mtx ift_db_mtx; 364 365 /* constant values */ 366 if_ctx_t ift_ctx; 367 struct ifmp_ring *ift_br; 368 struct grouptask ift_task; 369 qidx_t ift_size; 370 uint16_t ift_id; 371 struct callout ift_timer; 372 373 if_txsd_vec_t ift_sds; 374 uint8_t ift_qstatus; 375 uint8_t ift_closed; 376 uint8_t ift_update_freq; 377 struct iflib_filter_info ift_filter_info; 378 bus_dma_tag_t ift_desc_tag; 379 bus_dma_tag_t ift_tso_desc_tag; 380 iflib_dma_info_t ift_ifdi; 381#define MTX_NAME_LEN 16 382 char ift_mtx_name[MTX_NAME_LEN]; 383 char ift_db_mtx_name[MTX_NAME_LEN]; 384 bus_dma_segment_t ift_segs[IFLIB_MAX_TX_SEGS] __aligned(CACHE_LINE_SIZE); 385#ifdef IFLIB_DIAGNOSTICS 386 uint64_t ift_cpu_exec_count[256]; 387#endif 388} __aligned(CACHE_LINE_SIZE); 389 390struct iflib_fl { 391 qidx_t ifl_cidx; 392 qidx_t ifl_pidx; 393 qidx_t ifl_credits; 394 uint8_t ifl_gen; 395 uint8_t ifl_rxd_size; 396#if MEMORY_LOGGING 397 uint64_t ifl_m_enqueued; 398 uint64_t ifl_m_dequeued; 399 uint64_t ifl_cl_enqueued; 400 uint64_t ifl_cl_dequeued; 401#endif 402 /* implicit pad */ 403 404 bitstr_t *ifl_rx_bitmap; 405 qidx_t ifl_fragidx; 406 /* constant */ 407 qidx_t ifl_size; 408 uint16_t ifl_buf_size; 409 uint16_t ifl_cltype; 410 uma_zone_t ifl_zone; 411 iflib_rxsd_array_t ifl_sds; 412 iflib_rxq_t ifl_rxq; 413 uint8_t ifl_id; 414 bus_dma_tag_t ifl_desc_tag; 415 iflib_dma_info_t ifl_ifdi; 416 uint64_t ifl_bus_addrs[IFLIB_MAX_RX_REFRESH] __aligned(CACHE_LINE_SIZE); 417 caddr_t ifl_vm_addrs[IFLIB_MAX_RX_REFRESH]; 418 qidx_t ifl_rxd_idxs[IFLIB_MAX_RX_REFRESH]; 419} __aligned(CACHE_LINE_SIZE); 420 421static inline qidx_t 422get_inuse(int size, qidx_t cidx, qidx_t pidx, uint8_t gen) 423{ 424 qidx_t used; 425 426 if (pidx > cidx) 427 used = pidx - cidx; 428 else if (pidx < cidx) 429 used = size - cidx + pidx; 430 else if (gen == 0 && pidx == cidx) 431 used = 0; 432 else if (gen == 1 && pidx == cidx) 433 used = size; 434 else 435 panic("bad state"); 436 437 return (used); 438} 439 440#define TXQ_AVAIL(txq) (txq->ift_size - get_inuse(txq->ift_size, txq->ift_cidx, txq->ift_pidx, txq->ift_gen)) 441 442#define IDXDIFF(head, tail, wrap) \ 443 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head)) 444 445struct iflib_rxq { 446 /* If there is a separate completion queue - 447 * these are the cq cidx and pidx. Otherwise 448 * these are unused. 449 */ 450 qidx_t ifr_size; 451 qidx_t ifr_cq_cidx; 452 qidx_t ifr_cq_pidx; 453 uint8_t ifr_cq_gen; 454 uint8_t ifr_fl_offset; 455 456 if_ctx_t ifr_ctx; 457 iflib_fl_t ifr_fl; 458 uint64_t ifr_rx_irq; 459 uint16_t ifr_id; 460 uint8_t ifr_lro_enabled; 461 uint8_t ifr_nfl; 462 uint8_t ifr_ntxqirq; 463 uint8_t ifr_txqid[IFLIB_MAX_TX_SHARED_INTR]; 464 struct lro_ctrl ifr_lc; 465 struct grouptask ifr_task; 466 struct callout ifr_watchdog; 467 struct iflib_filter_info ifr_filter_info; 468 iflib_dma_info_t ifr_ifdi; 469 470 /* dynamically allocate if any drivers need a value substantially larger than this */ 471 struct if_rxd_frag ifr_frags[IFLIB_MAX_RX_SEGS] __aligned(CACHE_LINE_SIZE); 472#ifdef IFLIB_DIAGNOSTICS 473 uint64_t ifr_cpu_exec_count[256]; 474#endif 475} __aligned(CACHE_LINE_SIZE); 476 477typedef struct if_rxsd { 478 caddr_t *ifsd_cl; 479 struct mbuf **ifsd_m; 480 iflib_fl_t ifsd_fl; 481 qidx_t ifsd_cidx; 482} *if_rxsd_t; 483 484/* multiple of word size */ 485#ifdef __LP64__ 486#define PKT_INFO_SIZE 6 487#define RXD_INFO_SIZE 5 488#define PKT_TYPE uint64_t 489#else 490#define PKT_INFO_SIZE 11 491#define RXD_INFO_SIZE 8 492#define PKT_TYPE uint32_t 493#endif 494#define PKT_LOOP_BOUND ((PKT_INFO_SIZE/3)*3) 495#define RXD_LOOP_BOUND ((RXD_INFO_SIZE/4)*4) 496 497typedef struct if_pkt_info_pad { 498 PKT_TYPE pkt_val[PKT_INFO_SIZE]; 499} *if_pkt_info_pad_t; 500typedef struct if_rxd_info_pad { 501 PKT_TYPE rxd_val[RXD_INFO_SIZE]; 502} *if_rxd_info_pad_t; 503 504CTASSERT(sizeof(struct if_pkt_info_pad) == sizeof(struct if_pkt_info)); 505CTASSERT(sizeof(struct if_rxd_info_pad) == sizeof(struct if_rxd_info)); 506 507 508static inline void 509pkt_info_zero(if_pkt_info_t pi) 510{ 511 if_pkt_info_pad_t pi_pad; 512 513 pi_pad = (if_pkt_info_pad_t)pi; 514 pi_pad->pkt_val[0] = 0; pi_pad->pkt_val[1] = 0; pi_pad->pkt_val[2] = 0; 515 pi_pad->pkt_val[3] = 0; pi_pad->pkt_val[4] = 0; pi_pad->pkt_val[5] = 0; 516#ifndef __LP64__ 517 pi_pad->pkt_val[6] = 0; pi_pad->pkt_val[7] = 0; pi_pad->pkt_val[8] = 0; 518 pi_pad->pkt_val[9] = 0; pi_pad->pkt_val[10] = 0; 519#endif 520} 521 522static inline void 523rxd_info_zero(if_rxd_info_t ri) 524{ 525 if_rxd_info_pad_t ri_pad; 526 int i; 527 528 ri_pad = (if_rxd_info_pad_t)ri; 529 for (i = 0; i < RXD_LOOP_BOUND; i += 4) { 530 ri_pad->rxd_val[i] = 0; 531 ri_pad->rxd_val[i+1] = 0; 532 ri_pad->rxd_val[i+2] = 0; 533 ri_pad->rxd_val[i+3] = 0; 534 } 535#ifdef __LP64__ 536 ri_pad->rxd_val[RXD_INFO_SIZE-1] = 0; 537#endif 538} 539 540/* 541 * Only allow a single packet to take up most 1/nth of the tx ring 542 */ 543#define MAX_SINGLE_PACKET_FRACTION 12 544#define IF_BAD_DMA (bus_addr_t)-1 545 546#define CTX_ACTIVE(ctx) ((if_getdrvflags((ctx)->ifc_ifp) & IFF_DRV_RUNNING)) 547 548#define CTX_LOCK_INIT(_sc, _name) mtx_init(&(_sc)->ifc_ctx_mtx, _name, "iflib ctx lock", MTX_DEF) 549#define CTX_LOCK(ctx) mtx_lock(&(ctx)->ifc_ctx_mtx) 550#define CTX_UNLOCK(ctx) mtx_unlock(&(ctx)->ifc_ctx_mtx) 551#define CTX_LOCK_DESTROY(ctx) mtx_destroy(&(ctx)->ifc_ctx_mtx) 552 553 554#define STATE_LOCK_INIT(_sc, _name) mtx_init(&(_sc)->ifc_state_mtx, _name, "iflib state lock", MTX_DEF) 555#define STATE_LOCK(ctx) mtx_lock(&(ctx)->ifc_state_mtx) 556#define STATE_UNLOCK(ctx) mtx_unlock(&(ctx)->ifc_state_mtx) 557#define STATE_LOCK_DESTROY(ctx) mtx_destroy(&(ctx)->ifc_state_mtx) 558 559 560 561#define CALLOUT_LOCK(txq) mtx_lock(&txq->ift_mtx) 562#define CALLOUT_UNLOCK(txq) mtx_unlock(&txq->ift_mtx) 563 564/* Our boot-time initialization hook */ 565static int iflib_module_event_handler(module_t, int, void *); 566 567static moduledata_t iflib_moduledata = { 568 "iflib", 569 iflib_module_event_handler, 570 NULL 571}; 572 573DECLARE_MODULE(iflib, iflib_moduledata, SI_SUB_INIT_IF, SI_ORDER_ANY); 574MODULE_VERSION(iflib, 1); 575 576MODULE_DEPEND(iflib, pci, 1, 1, 1); 577MODULE_DEPEND(iflib, ether, 1, 1, 1); 578 579TASKQGROUP_DEFINE(if_io_tqg, mp_ncpus, 1); 580TASKQGROUP_DEFINE(if_config_tqg, 1, 1); 581 582#ifndef IFLIB_DEBUG_COUNTERS 583#ifdef INVARIANTS 584#define IFLIB_DEBUG_COUNTERS 1 585#else 586#define IFLIB_DEBUG_COUNTERS 0 587#endif /* !INVARIANTS */ 588#endif 589 590static SYSCTL_NODE(_net, OID_AUTO, iflib, CTLFLAG_RD, 0, 591 "iflib driver parameters"); 592 593/* 594 * XXX need to ensure that this can't accidentally cause the head to be moved backwards 595 */ 596static int iflib_min_tx_latency = 0; 597SYSCTL_INT(_net_iflib, OID_AUTO, min_tx_latency, CTLFLAG_RW, 598 &iflib_min_tx_latency, 0, "minimize transmit latency at the possible expense of throughput"); 599static int iflib_no_tx_batch = 0; 600SYSCTL_INT(_net_iflib, OID_AUTO, no_tx_batch, CTLFLAG_RW, 601 &iflib_no_tx_batch, 0, "minimize transmit latency at the possible expense of throughput"); 602 603 604#if IFLIB_DEBUG_COUNTERS 605 606static int iflib_tx_seen; 607static int iflib_tx_sent; 608static int iflib_tx_encap; 609static int iflib_rx_allocs; 610static int iflib_fl_refills; 611static int iflib_fl_refills_large; 612static int iflib_tx_frees; 613 614SYSCTL_INT(_net_iflib, OID_AUTO, tx_seen, CTLFLAG_RD, 615 &iflib_tx_seen, 0, "# tx mbufs seen"); 616SYSCTL_INT(_net_iflib, OID_AUTO, tx_sent, CTLFLAG_RD, 617 &iflib_tx_sent, 0, "# tx mbufs sent"); 618SYSCTL_INT(_net_iflib, OID_AUTO, tx_encap, CTLFLAG_RD, 619 &iflib_tx_encap, 0, "# tx mbufs encapped"); 620SYSCTL_INT(_net_iflib, OID_AUTO, tx_frees, CTLFLAG_RD, 621 &iflib_tx_frees, 0, "# tx frees"); 622SYSCTL_INT(_net_iflib, OID_AUTO, rx_allocs, CTLFLAG_RD, 623 &iflib_rx_allocs, 0, "# rx allocations"); 624SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills, CTLFLAG_RD, 625 &iflib_fl_refills, 0, "# refills"); 626SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills_large, CTLFLAG_RD, 627 &iflib_fl_refills_large, 0, "# large refills"); 628 629 630static int iflib_txq_drain_flushing; 631static int iflib_txq_drain_oactive; 632static int iflib_txq_drain_notready; 633static int iflib_txq_drain_encapfail; 634 635SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_flushing, CTLFLAG_RD, 636 &iflib_txq_drain_flushing, 0, "# drain flushes"); 637SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_oactive, CTLFLAG_RD, 638 &iflib_txq_drain_oactive, 0, "# drain oactives"); 639SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_notready, CTLFLAG_RD, 640 &iflib_txq_drain_notready, 0, "# drain notready"); 641SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_encapfail, CTLFLAG_RD, 642 &iflib_txq_drain_encapfail, 0, "# drain encap fails"); 643 644 645static int iflib_encap_load_mbuf_fail; 646static int iflib_encap_pad_mbuf_fail; 647static int iflib_encap_txq_avail_fail; 648static int iflib_encap_txd_encap_fail; 649 650SYSCTL_INT(_net_iflib, OID_AUTO, encap_load_mbuf_fail, CTLFLAG_RD, 651 &iflib_encap_load_mbuf_fail, 0, "# busdma load failures"); 652SYSCTL_INT(_net_iflib, OID_AUTO, encap_pad_mbuf_fail, CTLFLAG_RD, 653 &iflib_encap_pad_mbuf_fail, 0, "# runt frame pad failures"); 654SYSCTL_INT(_net_iflib, OID_AUTO, encap_txq_avail_fail, CTLFLAG_RD, 655 &iflib_encap_txq_avail_fail, 0, "# txq avail failures"); 656SYSCTL_INT(_net_iflib, OID_AUTO, encap_txd_encap_fail, CTLFLAG_RD, 657 &iflib_encap_txd_encap_fail, 0, "# driver encap failures"); 658 659static int iflib_task_fn_rxs; 660static int iflib_rx_intr_enables; 661static int iflib_fast_intrs; 662static int iflib_intr_link; 663static int iflib_intr_msix; 664static int iflib_rx_unavail; 665static int iflib_rx_ctx_inactive; 666static int iflib_rx_zero_len; 667static int iflib_rx_if_input; 668static int iflib_rx_mbuf_null; 669static int iflib_rxd_flush; 670 671static int iflib_verbose_debug; 672 673SYSCTL_INT(_net_iflib, OID_AUTO, intr_link, CTLFLAG_RD, 674 &iflib_intr_link, 0, "# intr link calls"); 675SYSCTL_INT(_net_iflib, OID_AUTO, intr_msix, CTLFLAG_RD, 676 &iflib_intr_msix, 0, "# intr msix calls"); 677SYSCTL_INT(_net_iflib, OID_AUTO, task_fn_rx, CTLFLAG_RD, 678 &iflib_task_fn_rxs, 0, "# task_fn_rx calls"); 679SYSCTL_INT(_net_iflib, OID_AUTO, rx_intr_enables, CTLFLAG_RD, 680 &iflib_rx_intr_enables, 0, "# rx intr enables"); 681SYSCTL_INT(_net_iflib, OID_AUTO, fast_intrs, CTLFLAG_RD, 682 &iflib_fast_intrs, 0, "# fast_intr calls"); 683SYSCTL_INT(_net_iflib, OID_AUTO, rx_unavail, CTLFLAG_RD, 684 &iflib_rx_unavail, 0, "# times rxeof called with no available data"); 685SYSCTL_INT(_net_iflib, OID_AUTO, rx_ctx_inactive, CTLFLAG_RD, 686 &iflib_rx_ctx_inactive, 0, "# times rxeof called with inactive context"); 687SYSCTL_INT(_net_iflib, OID_AUTO, rx_zero_len, CTLFLAG_RD, 688 &iflib_rx_zero_len, 0, "# times rxeof saw zero len mbuf"); 689SYSCTL_INT(_net_iflib, OID_AUTO, rx_if_input, CTLFLAG_RD, 690 &iflib_rx_if_input, 0, "# times rxeof called if_input"); 691SYSCTL_INT(_net_iflib, OID_AUTO, rx_mbuf_null, CTLFLAG_RD, 692 &iflib_rx_mbuf_null, 0, "# times rxeof got null mbuf"); 693SYSCTL_INT(_net_iflib, OID_AUTO, rxd_flush, CTLFLAG_RD, 694 &iflib_rxd_flush, 0, "# times rxd_flush called"); 695SYSCTL_INT(_net_iflib, OID_AUTO, verbose_debug, CTLFLAG_RW, 696 &iflib_verbose_debug, 0, "enable verbose debugging"); 697 698#define DBG_COUNTER_INC(name) atomic_add_int(&(iflib_ ## name), 1) 699static void 700iflib_debug_reset(void) 701{ 702 iflib_tx_seen = iflib_tx_sent = iflib_tx_encap = iflib_rx_allocs = 703 iflib_fl_refills = iflib_fl_refills_large = iflib_tx_frees = 704 iflib_txq_drain_flushing = iflib_txq_drain_oactive = 705 iflib_txq_drain_notready = iflib_txq_drain_encapfail = 706 iflib_encap_load_mbuf_fail = iflib_encap_pad_mbuf_fail = 707 iflib_encap_txq_avail_fail = iflib_encap_txd_encap_fail = 708 iflib_task_fn_rxs = iflib_rx_intr_enables = iflib_fast_intrs = 709 iflib_intr_link = iflib_intr_msix = iflib_rx_unavail = 710 iflib_rx_ctx_inactive = iflib_rx_zero_len = iflib_rx_if_input = 711 iflib_rx_mbuf_null = iflib_rxd_flush = 0; 712} 713 714#else 715#define DBG_COUNTER_INC(name) 716static void iflib_debug_reset(void) {} 717#endif 718 719 720 721#define IFLIB_DEBUG 0 722 723static void iflib_tx_structures_free(if_ctx_t ctx); 724static void iflib_rx_structures_free(if_ctx_t ctx); 725static int iflib_queues_alloc(if_ctx_t ctx); 726static int iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq); 727static int iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget); 728static int iflib_qset_structures_setup(if_ctx_t ctx); 729static int iflib_msix_init(if_ctx_t ctx); 730static int iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filterarg, int *rid, char *str); 731static void iflib_txq_check_drain(iflib_txq_t txq, int budget); 732static uint32_t iflib_txq_can_drain(struct ifmp_ring *); 733static int iflib_register(if_ctx_t); 734static void iflib_unregister_vlan_handlers(if_ctx_t ctx); 735static void iflib_init_locked(if_ctx_t ctx); 736static void iflib_add_device_sysctl_pre(if_ctx_t ctx); 737static void iflib_add_device_sysctl_post(if_ctx_t ctx); 738static void iflib_ifmp_purge(iflib_txq_t txq); 739static void _iflib_pre_assert(if_softc_ctx_t scctx); 740static void iflib_stop(if_ctx_t ctx); 741static void iflib_if_init_locked(if_ctx_t ctx); 742static void iflib_free_intr_mem(if_ctx_t ctx); 743#ifndef __NO_STRICT_ALIGNMENT 744static struct mbuf * iflib_fixup_rx(struct mbuf *m); 745#endif 746 747#ifdef DEV_NETMAP 748#include <sys/selinfo.h> 749#include <net/netmap.h> 750#include <dev/netmap/netmap_kern.h> 751 752MODULE_DEPEND(iflib, netmap, 1, 1, 1); 753 754static int netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, uint32_t nm_i, bool init); 755 756/* 757 * device-specific sysctl variables: 758 * 759 * iflib_crcstrip: 0: keep CRC in rx frames (default), 1: strip it. 760 * During regular operations the CRC is stripped, but on some 761 * hardware reception of frames not multiple of 64 is slower, 762 * so using crcstrip=0 helps in benchmarks. 763 * 764 * iflib_rx_miss, iflib_rx_miss_bufs: 765 * count packets that might be missed due to lost interrupts. 766 */ 767SYSCTL_DECL(_dev_netmap); 768/* 769 * The xl driver by default strips CRCs and we do not override it. 770 */ 771 772int iflib_crcstrip = 1; 773SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_crcstrip, 774 CTLFLAG_RW, &iflib_crcstrip, 1, "strip CRC on rx frames"); 775 776int iflib_rx_miss, iflib_rx_miss_bufs; 777SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss, 778 CTLFLAG_RW, &iflib_rx_miss, 0, "potentially missed rx intr"); 779SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss_bufs, 780 CTLFLAG_RW, &iflib_rx_miss_bufs, 0, "potentially missed rx intr bufs"); 781 782/* 783 * Register/unregister. We are already under netmap lock. 784 * Only called on the first register or the last unregister. 785 */ 786static int 787iflib_netmap_register(struct netmap_adapter *na, int onoff) 788{ 789 struct ifnet *ifp = na->ifp; 790 if_ctx_t ctx = ifp->if_softc; 791 int status; 792 793 CTX_LOCK(ctx); 794 IFDI_INTR_DISABLE(ctx); 795 796 /* Tell the stack that the interface is no longer active */ 797 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 798 799 if (!CTX_IS_VF(ctx)) 800 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); 801 802 /* enable or disable flags and callbacks in na and ifp */ 803 if (onoff) { 804 nm_set_native_flags(na); 805 } else { 806 nm_clear_native_flags(na); 807 } 808 iflib_stop(ctx); 809 iflib_init_locked(ctx); 810 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); // XXX why twice ? 811 status = ifp->if_drv_flags & IFF_DRV_RUNNING ? 0 : 1; 812 if (status) 813 nm_clear_native_flags(na); 814 CTX_UNLOCK(ctx); 815 return (status); 816} 817 818static int 819netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, uint32_t nm_i, bool init) 820{ 821 struct netmap_adapter *na = kring->na; 822 u_int const lim = kring->nkr_num_slots - 1; 823 u_int head = kring->rhead; 824 struct netmap_ring *ring = kring->ring; 825 bus_dmamap_t *map; 826 struct if_rxd_update iru; 827 if_ctx_t ctx = rxq->ifr_ctx; 828 iflib_fl_t fl = &rxq->ifr_fl[0]; 829 uint32_t refill_pidx, nic_i; 830 831 if (nm_i == head && __predict_true(!init)) 832 return 0; 833 iru_init(&iru, rxq, 0 /* flid */); 834 map = fl->ifl_sds.ifsd_map; 835 refill_pidx = netmap_idx_k2n(kring, nm_i); 836 /* 837 * IMPORTANT: we must leave one free slot in the ring, 838 * so move head back by one unit 839 */ 840 head = nm_prev(head, lim); 841 while (nm_i != head) { 842 for (int tmp_pidx = 0; tmp_pidx < IFLIB_MAX_RX_REFRESH && nm_i != head; tmp_pidx++) { 843 struct netmap_slot *slot = &ring->slot[nm_i]; 844 void *addr = PNMB(na, slot, &fl->ifl_bus_addrs[tmp_pidx]); 845 uint32_t nic_i_dma = refill_pidx; 846 nic_i = netmap_idx_k2n(kring, nm_i); 847 848 MPASS(tmp_pidx < IFLIB_MAX_RX_REFRESH); 849 850 if (addr == NETMAP_BUF_BASE(na)) /* bad buf */ 851 return netmap_ring_reinit(kring); 852 853 fl->ifl_vm_addrs[tmp_pidx] = addr; 854 if (__predict_false(init) && map) { 855 netmap_load_map(na, fl->ifl_ifdi->idi_tag, map[nic_i], addr); 856 } else if (map && (slot->flags & NS_BUF_CHANGED)) { 857 /* buffer has changed, reload map */ 858 netmap_reload_map(na, fl->ifl_ifdi->idi_tag, map[nic_i], addr); 859 } 860 slot->flags &= ~NS_BUF_CHANGED; 861 862 nm_i = nm_next(nm_i, lim); 863 fl->ifl_rxd_idxs[tmp_pidx] = nic_i = nm_next(nic_i, lim); 864 if (nm_i != head && tmp_pidx < IFLIB_MAX_RX_REFRESH-1) 865 continue; 866 867 iru.iru_pidx = refill_pidx; 868 iru.iru_count = tmp_pidx+1; 869 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 870 871 refill_pidx = nic_i; 872 if (map == NULL) 873 continue; 874 875 for (int n = 0; n < iru.iru_count; n++) { 876 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, map[nic_i_dma], 877 BUS_DMASYNC_PREREAD); 878 /* XXX - change this to not use the netmap func*/ 879 nic_i_dma = nm_next(nic_i_dma, lim); 880 } 881 } 882 } 883 kring->nr_hwcur = head; 884 885 if (map) 886 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 887 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 888 ctx->isc_rxd_flush(ctx->ifc_softc, rxq->ifr_id, fl->ifl_id, nic_i); 889 return (0); 890} 891 892/* 893 * Reconcile kernel and user view of the transmit ring. 894 * 895 * All information is in the kring. 896 * Userspace wants to send packets up to the one before kring->rhead, 897 * kernel knows kring->nr_hwcur is the first unsent packet. 898 * 899 * Here we push packets out (as many as possible), and possibly 900 * reclaim buffers from previously completed transmission. 901 * 902 * The caller (netmap) guarantees that there is only one instance 903 * running at any time. Any interference with other driver 904 * methods should be handled by the individual drivers. 905 */ 906static int 907iflib_netmap_txsync(struct netmap_kring *kring, int flags) 908{ 909 struct netmap_adapter *na = kring->na; 910 struct ifnet *ifp = na->ifp; 911 struct netmap_ring *ring = kring->ring; 912 u_int nm_i; /* index into the netmap ring */ 913 u_int nic_i; /* index into the NIC ring */ 914 u_int n; 915 u_int const lim = kring->nkr_num_slots - 1; 916 u_int const head = kring->rhead; 917 struct if_pkt_info pi; 918 919 /* 920 * interrupts on every tx packet are expensive so request 921 * them every half ring, or where NS_REPORT is set 922 */ 923 u_int report_frequency = kring->nkr_num_slots >> 1; 924 /* device-specific */ 925 if_ctx_t ctx = ifp->if_softc; 926 iflib_txq_t txq = &ctx->ifc_txqs[kring->ring_id]; 927 928 if (txq->ift_sds.ifsd_map) 929 bus_dmamap_sync(txq->ift_desc_tag, txq->ift_ifdi->idi_map, 930 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 931 932 933 /* 934 * First part: process new packets to send. 935 * nm_i is the current index in the netmap ring, 936 * nic_i is the corresponding index in the NIC ring. 937 * 938 * If we have packets to send (nm_i != head) 939 * iterate over the netmap ring, fetch length and update 940 * the corresponding slot in the NIC ring. Some drivers also 941 * need to update the buffer's physical address in the NIC slot 942 * even NS_BUF_CHANGED is not set (PNMB computes the addresses). 943 * 944 * The netmap_reload_map() calls is especially expensive, 945 * even when (as in this case) the tag is 0, so do only 946 * when the buffer has actually changed. 947 * 948 * If possible do not set the report/intr bit on all slots, 949 * but only a few times per ring or when NS_REPORT is set. 950 * 951 * Finally, on 10G and faster drivers, it might be useful 952 * to prefetch the next slot and txr entry. 953 */ 954 955 nm_i = netmap_idx_n2k(kring, kring->nr_hwcur); 956 pkt_info_zero(&pi); 957 pi.ipi_segs = txq->ift_segs; 958 pi.ipi_qsidx = kring->ring_id; 959 if (nm_i != head) { /* we have new packets to send */ 960 nic_i = netmap_idx_k2n(kring, nm_i); 961 962 __builtin_prefetch(&ring->slot[nm_i]); 963 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i]); 964 if (txq->ift_sds.ifsd_map) 965 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i]); 966 967 for (n = 0; nm_i != head; n++) { 968 struct netmap_slot *slot = &ring->slot[nm_i]; 969 u_int len = slot->len; 970 uint64_t paddr; 971 void *addr = PNMB(na, slot, &paddr); 972 int flags = (slot->flags & NS_REPORT || 973 nic_i == 0 || nic_i == report_frequency) ? 974 IPI_TX_INTR : 0; 975 976 /* device-specific */ 977 pi.ipi_len = len; 978 pi.ipi_segs[0].ds_addr = paddr; 979 pi.ipi_segs[0].ds_len = len; 980 pi.ipi_nsegs = 1; 981 pi.ipi_ndescs = 0; 982 pi.ipi_pidx = nic_i; 983 pi.ipi_flags = flags; 984 985 /* Fill the slot in the NIC ring. */ 986 ctx->isc_txd_encap(ctx->ifc_softc, &pi); 987 988 /* prefetch for next round */ 989 __builtin_prefetch(&ring->slot[nm_i + 1]); 990 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i + 1]); 991 if (txq->ift_sds.ifsd_map) { 992 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i + 1]); 993 994 NM_CHECK_ADDR_LEN(na, addr, len); 995 996 if (slot->flags & NS_BUF_CHANGED) { 997 /* buffer has changed, reload map */ 998 netmap_reload_map(na, txq->ift_desc_tag, txq->ift_sds.ifsd_map[nic_i], addr); 999 } 1000 /* make sure changes to the buffer are synced */ 1001 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_sds.ifsd_map[nic_i], 1002 BUS_DMASYNC_PREWRITE); 1003 } 1004 slot->flags &= ~(NS_REPORT | NS_BUF_CHANGED); 1005 nm_i = nm_next(nm_i, lim); 1006 nic_i = nm_next(nic_i, lim); 1007 } 1008 kring->nr_hwcur = head; 1009 1010 /* synchronize the NIC ring */ 1011 if (txq->ift_sds.ifsd_map) 1012 bus_dmamap_sync(txq->ift_desc_tag, txq->ift_ifdi->idi_map, 1013 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1014 1015 /* (re)start the tx unit up to slot nic_i (excluded) */ 1016 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, nic_i); 1017 } 1018 1019 /* 1020 * Second part: reclaim buffers for completed transmissions. 1021 */ 1022 if (iflib_tx_credits_update(ctx, txq)) { 1023 /* some tx completed, increment avail */ 1024 nic_i = txq->ift_cidx_processed; 1025 kring->nr_hwtail = nm_prev(netmap_idx_n2k(kring, nic_i), lim); 1026 } 1027 return (0); 1028} 1029 1030/* 1031 * Reconcile kernel and user view of the receive ring. 1032 * Same as for the txsync, this routine must be efficient. 1033 * The caller guarantees a single invocations, but races against 1034 * the rest of the driver should be handled here. 1035 * 1036 * On call, kring->rhead is the first packet that userspace wants 1037 * to keep, and kring->rcur is the wakeup point. 1038 * The kernel has previously reported packets up to kring->rtail. 1039 * 1040 * If (flags & NAF_FORCE_READ) also check for incoming packets irrespective 1041 * of whether or not we received an interrupt. 1042 */ 1043static int 1044iflib_netmap_rxsync(struct netmap_kring *kring, int flags) 1045{ 1046 struct netmap_adapter *na = kring->na; 1047 struct netmap_ring *ring = kring->ring; 1048 uint32_t nm_i; /* index into the netmap ring */ 1049 uint32_t nic_i; /* index into the NIC ring */ 1050 u_int i, n; 1051 u_int const lim = kring->nkr_num_slots - 1; 1052 u_int const head = netmap_idx_n2k(kring, kring->rhead); 1053 int force_update = (flags & NAF_FORCE_READ) || kring->nr_kflags & NKR_PENDINTR; 1054 struct if_rxd_info ri; 1055 1056 struct ifnet *ifp = na->ifp; 1057 if_ctx_t ctx = ifp->if_softc; 1058 iflib_rxq_t rxq = &ctx->ifc_rxqs[kring->ring_id]; 1059 iflib_fl_t fl = rxq->ifr_fl; 1060 if (head > lim) 1061 return netmap_ring_reinit(kring); 1062 1063 /* XXX check sync modes */ 1064 for (i = 0, fl = rxq->ifr_fl; i < rxq->ifr_nfl; i++, fl++) { 1065 if (fl->ifl_sds.ifsd_map == NULL) 1066 continue; 1067 bus_dmamap_sync(rxq->ifr_fl[i].ifl_desc_tag, fl->ifl_ifdi->idi_map, 1068 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1069 } 1070 /* 1071 * First part: import newly received packets. 1072 * 1073 * nm_i is the index of the next free slot in the netmap ring, 1074 * nic_i is the index of the next received packet in the NIC ring, 1075 * and they may differ in case if_init() has been called while 1076 * in netmap mode. For the receive ring we have 1077 * 1078 * nic_i = rxr->next_check; 1079 * nm_i = kring->nr_hwtail (previous) 1080 * and 1081 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size 1082 * 1083 * rxr->next_check is set to 0 on a ring reinit 1084 */ 1085 if (netmap_no_pendintr || force_update) { 1086 int crclen = iflib_crcstrip ? 0 : 4; 1087 int error, avail; 1088 1089 for (i = 0; i < rxq->ifr_nfl; i++) { 1090 fl = &rxq->ifr_fl[i]; 1091 nic_i = fl->ifl_cidx; 1092 nm_i = netmap_idx_n2k(kring, nic_i); 1093 avail = iflib_rxd_avail(ctx, rxq, nic_i, USHRT_MAX); 1094 for (n = 0; avail > 0; n++, avail--) { 1095 rxd_info_zero(&ri); 1096 ri.iri_frags = rxq->ifr_frags; 1097 ri.iri_qsidx = kring->ring_id; 1098 ri.iri_ifp = ctx->ifc_ifp; 1099 ri.iri_cidx = nic_i; 1100 1101 error = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri); 1102 ring->slot[nm_i].len = error ? 0 : ri.iri_len - crclen; 1103 ring->slot[nm_i].flags = 0; 1104 if (fl->ifl_sds.ifsd_map) 1105 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, 1106 fl->ifl_sds.ifsd_map[nic_i], BUS_DMASYNC_POSTREAD); 1107 nm_i = nm_next(nm_i, lim); 1108 nic_i = nm_next(nic_i, lim); 1109 } 1110 if (n) { /* update the state variables */ 1111 if (netmap_no_pendintr && !force_update) { 1112 /* diagnostics */ 1113 iflib_rx_miss ++; 1114 iflib_rx_miss_bufs += n; 1115 } 1116 fl->ifl_cidx = nic_i; 1117 kring->nr_hwtail = netmap_idx_k2n(kring, nm_i); 1118 } 1119 kring->nr_kflags &= ~NKR_PENDINTR; 1120 } 1121 } 1122 /* 1123 * Second part: skip past packets that userspace has released. 1124 * (kring->nr_hwcur to head excluded), 1125 * and make the buffers available for reception. 1126 * As usual nm_i is the index in the netmap ring, 1127 * nic_i is the index in the NIC ring, and 1128 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size 1129 */ 1130 /* XXX not sure how this will work with multiple free lists */ 1131 nm_i = netmap_idx_n2k(kring, kring->nr_hwcur); 1132 1133 return (netmap_fl_refill(rxq, kring, nm_i, false)); 1134} 1135 1136static int 1137iflib_netmap_attach(if_ctx_t ctx) 1138{ 1139 struct netmap_adapter na; 1140 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1141 1142 bzero(&na, sizeof(na)); 1143 1144 na.ifp = ctx->ifc_ifp; 1145 na.na_flags = NAF_BDG_MAYSLEEP; 1146 MPASS(ctx->ifc_softc_ctx.isc_ntxqsets); 1147 MPASS(ctx->ifc_softc_ctx.isc_nrxqsets); 1148 1149 na.num_tx_desc = scctx->isc_ntxd[0]; 1150 na.num_rx_desc = scctx->isc_nrxd[0]; 1151 na.nm_txsync = iflib_netmap_txsync; 1152 na.nm_rxsync = iflib_netmap_rxsync; 1153 na.nm_register = iflib_netmap_register; 1154 na.num_tx_rings = ctx->ifc_softc_ctx.isc_ntxqsets; 1155 na.num_rx_rings = ctx->ifc_softc_ctx.isc_nrxqsets; 1156 return (netmap_attach(&na)); 1157} 1158 1159static void 1160iflib_netmap_txq_init(if_ctx_t ctx, iflib_txq_t txq) 1161{ 1162 struct netmap_adapter *na = NA(ctx->ifc_ifp); 1163 struct netmap_slot *slot; 1164 1165 slot = netmap_reset(na, NR_TX, txq->ift_id, 0); 1166 if (slot == NULL) 1167 return; 1168 if (txq->ift_sds.ifsd_map == NULL) 1169 return; 1170 1171 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxd[0]; i++) { 1172 1173 /* 1174 * In netmap mode, set the map for the packet buffer. 1175 * NOTE: Some drivers (not this one) also need to set 1176 * the physical buffer address in the NIC ring. 1177 * netmap_idx_n2k() maps a nic index, i, into the corresponding 1178 * netmap slot index, si 1179 */ 1180 int si = netmap_idx_n2k(na->tx_rings[txq->ift_id], i); 1181 netmap_load_map(na, txq->ift_desc_tag, txq->ift_sds.ifsd_map[i], NMB(na, slot + si)); 1182 } 1183} 1184 1185static void 1186iflib_netmap_rxq_init(if_ctx_t ctx, iflib_rxq_t rxq) 1187{ 1188 struct netmap_adapter *na = NA(ctx->ifc_ifp); 1189 struct netmap_kring *kring = na->rx_rings[rxq->ifr_id]; 1190 struct netmap_slot *slot; 1191 uint32_t nm_i; 1192 1193 slot = netmap_reset(na, NR_RX, rxq->ifr_id, 0); 1194 if (slot == NULL) 1195 return; 1196 nm_i = netmap_idx_n2k(kring, 0); 1197 netmap_fl_refill(rxq, kring, nm_i, true); 1198} 1199 1200#define iflib_netmap_detach(ifp) netmap_detach(ifp) 1201 1202#else 1203#define iflib_netmap_txq_init(ctx, txq) 1204#define iflib_netmap_rxq_init(ctx, rxq) 1205#define iflib_netmap_detach(ifp) 1206 1207#define iflib_netmap_attach(ctx) (0) 1208#define netmap_rx_irq(ifp, qid, budget) (0) 1209#define netmap_tx_irq(ifp, qid) do {} while (0) 1210 1211#endif 1212 1213#if defined(__i386__) || defined(__amd64__) 1214static __inline void 1215prefetch(void *x) 1216{ 1217 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 1218} 1219static __inline void 1220prefetch2cachelines(void *x) 1221{ 1222 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 1223#if (CACHE_LINE_SIZE < 128) 1224 __asm volatile("prefetcht0 %0" :: "m" (*(((unsigned long *)x)+CACHE_LINE_SIZE/(sizeof(unsigned long))))); 1225#endif 1226} 1227#else 1228#define prefetch(x) 1229#define prefetch2cachelines(x) 1230#endif 1231 1232static void 1233iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid) 1234{ 1235 iflib_fl_t fl; 1236 1237 fl = &rxq->ifr_fl[flid]; 1238 iru->iru_paddrs = fl->ifl_bus_addrs; 1239 iru->iru_vaddrs = &fl->ifl_vm_addrs[0]; 1240 iru->iru_idxs = fl->ifl_rxd_idxs; 1241 iru->iru_qsidx = rxq->ifr_id; 1242 iru->iru_buf_size = fl->ifl_buf_size; 1243 iru->iru_flidx = fl->ifl_id; 1244} 1245 1246static void 1247_iflib_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err) 1248{ 1249 if (err) 1250 return; 1251 *(bus_addr_t *) arg = segs[0].ds_addr; 1252} 1253 1254int 1255iflib_dma_alloc(if_ctx_t ctx, int size, iflib_dma_info_t dma, int mapflags) 1256{ 1257 int err; 1258 if_shared_ctx_t sctx = ctx->ifc_sctx; 1259 device_t dev = ctx->ifc_dev; 1260 1261 KASSERT(sctx->isc_q_align != 0, ("alignment value not initialized")); 1262 1263 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 1264 sctx->isc_q_align, 0, /* alignment, bounds */ 1265 BUS_SPACE_MAXADDR, /* lowaddr */ 1266 BUS_SPACE_MAXADDR, /* highaddr */ 1267 NULL, NULL, /* filter, filterarg */ 1268 size, /* maxsize */ 1269 1, /* nsegments */ 1270 size, /* maxsegsize */ 1271 BUS_DMA_ALLOCNOW, /* flags */ 1272 NULL, /* lockfunc */ 1273 NULL, /* lockarg */ 1274 &dma->idi_tag); 1275 if (err) { 1276 device_printf(dev, 1277 "%s: bus_dma_tag_create failed: %d\n", 1278 __func__, err); 1279 goto fail_0; 1280 } 1281 1282 err = bus_dmamem_alloc(dma->idi_tag, (void**) &dma->idi_vaddr, 1283 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &dma->idi_map); 1284 if (err) { 1285 device_printf(dev, 1286 "%s: bus_dmamem_alloc(%ju) failed: %d\n", 1287 __func__, (uintmax_t)size, err); 1288 goto fail_1; 1289 } 1290 1291 dma->idi_paddr = IF_BAD_DMA; 1292 err = bus_dmamap_load(dma->idi_tag, dma->idi_map, dma->idi_vaddr, 1293 size, _iflib_dmamap_cb, &dma->idi_paddr, mapflags | BUS_DMA_NOWAIT); 1294 if (err || dma->idi_paddr == IF_BAD_DMA) { 1295 device_printf(dev, 1296 "%s: bus_dmamap_load failed: %d\n", 1297 __func__, err); 1298 goto fail_2; 1299 } 1300 1301 dma->idi_size = size; 1302 return (0); 1303 1304fail_2: 1305 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map); 1306fail_1: 1307 bus_dma_tag_destroy(dma->idi_tag); 1308fail_0: 1309 dma->idi_tag = NULL; 1310 1311 return (err); 1312} 1313 1314int 1315iflib_dma_alloc_multi(if_ctx_t ctx, int *sizes, iflib_dma_info_t *dmalist, int mapflags, int count) 1316{ 1317 int i, err; 1318 iflib_dma_info_t *dmaiter; 1319 1320 dmaiter = dmalist; 1321 for (i = 0; i < count; i++, dmaiter++) { 1322 if ((err = iflib_dma_alloc(ctx, sizes[i], *dmaiter, mapflags)) != 0) 1323 break; 1324 } 1325 if (err) 1326 iflib_dma_free_multi(dmalist, i); 1327 return (err); 1328} 1329 1330void 1331iflib_dma_free(iflib_dma_info_t dma) 1332{ 1333 if (dma->idi_tag == NULL) 1334 return; 1335 if (dma->idi_paddr != IF_BAD_DMA) { 1336 bus_dmamap_sync(dma->idi_tag, dma->idi_map, 1337 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1338 bus_dmamap_unload(dma->idi_tag, dma->idi_map); 1339 dma->idi_paddr = IF_BAD_DMA; 1340 } 1341 if (dma->idi_vaddr != NULL) { 1342 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map); 1343 dma->idi_vaddr = NULL; 1344 } 1345 bus_dma_tag_destroy(dma->idi_tag); 1346 dma->idi_tag = NULL; 1347} 1348 1349void 1350iflib_dma_free_multi(iflib_dma_info_t *dmalist, int count) 1351{ 1352 int i; 1353 iflib_dma_info_t *dmaiter = dmalist; 1354 1355 for (i = 0; i < count; i++, dmaiter++) 1356 iflib_dma_free(*dmaiter); 1357} 1358 1359#ifdef EARLY_AP_STARTUP 1360static const int iflib_started = 1; 1361#else 1362/* 1363 * We used to abuse the smp_started flag to decide if the queues have been 1364 * fully initialized (by late taskqgroup_adjust() calls in a SYSINIT()). 1365 * That gave bad races, since the SYSINIT() runs strictly after smp_started 1366 * is set. Run a SYSINIT() strictly after that to just set a usable 1367 * completion flag. 1368 */ 1369 1370static int iflib_started; 1371 1372static void 1373iflib_record_started(void *arg) 1374{ 1375 iflib_started = 1; 1376} 1377 1378SYSINIT(iflib_record_started, SI_SUB_SMP + 1, SI_ORDER_FIRST, 1379 iflib_record_started, NULL); 1380#endif 1381 1382static int 1383iflib_fast_intr(void *arg) 1384{ 1385 iflib_filter_info_t info = arg; 1386 struct grouptask *gtask = info->ifi_task; 1387 if (!iflib_started) 1388 return (FILTER_HANDLED); 1389 1390 DBG_COUNTER_INC(fast_intrs); 1391 if (info->ifi_filter != NULL && info->ifi_filter(info->ifi_filter_arg) == FILTER_HANDLED) 1392 return (FILTER_HANDLED); 1393 1394 GROUPTASK_ENQUEUE(gtask); 1395 return (FILTER_HANDLED); 1396} 1397 1398static int 1399iflib_fast_intr_rxtx(void *arg) 1400{ 1401 iflib_filter_info_t info = arg; 1402 struct grouptask *gtask = info->ifi_task; 1403 iflib_rxq_t rxq = (iflib_rxq_t)info->ifi_ctx; 1404 if_ctx_t ctx; 1405 int i, cidx; 1406 1407 if (!iflib_started) 1408 return (FILTER_HANDLED); 1409 1410 DBG_COUNTER_INC(fast_intrs); 1411 if (info->ifi_filter != NULL && info->ifi_filter(info->ifi_filter_arg) == FILTER_HANDLED) 1412 return (FILTER_HANDLED); 1413 1414 for (i = 0; i < rxq->ifr_ntxqirq; i++) { 1415 qidx_t txqid = rxq->ifr_txqid[i]; 1416 1417 ctx = rxq->ifr_ctx; 1418 1419 if (!ctx->isc_txd_credits_update(ctx->ifc_softc, txqid, false)) { 1420 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txqid); 1421 continue; 1422 } 1423 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task); 1424 } 1425 if (ctx->ifc_sctx->isc_flags & IFLIB_HAS_RXCQ) 1426 cidx = rxq->ifr_cq_cidx; 1427 else 1428 cidx = rxq->ifr_fl[0].ifl_cidx; 1429 if (iflib_rxd_avail(ctx, rxq, cidx, 1)) 1430 GROUPTASK_ENQUEUE(gtask); 1431 else 1432 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id); 1433 return (FILTER_HANDLED); 1434} 1435 1436 1437static int 1438iflib_fast_intr_ctx(void *arg) 1439{ 1440 iflib_filter_info_t info = arg; 1441 struct grouptask *gtask = info->ifi_task; 1442 1443 if (!iflib_started) 1444 return (FILTER_HANDLED); 1445 1446 DBG_COUNTER_INC(fast_intrs); 1447 if (info->ifi_filter != NULL && info->ifi_filter(info->ifi_filter_arg) == FILTER_HANDLED) 1448 return (FILTER_HANDLED); 1449 1450 GROUPTASK_ENQUEUE(gtask); 1451 return (FILTER_HANDLED); 1452} 1453 1454static int 1455_iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid, 1456 driver_filter_t filter, driver_intr_t handler, void *arg, 1457 char *name) 1458{ 1459 int rc, flags; 1460 struct resource *res; 1461 void *tag = NULL; 1462 device_t dev = ctx->ifc_dev; 1463 1464 flags = RF_ACTIVE; 1465 if (ctx->ifc_flags & IFC_LEGACY) 1466 flags |= RF_SHAREABLE; 1467 MPASS(rid < 512); 1468 irq->ii_rid = rid; 1469 res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &irq->ii_rid, flags); 1470 if (res == NULL) { 1471 device_printf(dev, 1472 "failed to allocate IRQ for rid %d, name %s.\n", rid, name); 1473 return (ENOMEM); 1474 } 1475 irq->ii_res = res; 1476 KASSERT(filter == NULL || handler == NULL, ("filter and handler can't both be non-NULL")); 1477 rc = bus_setup_intr(dev, res, INTR_MPSAFE | INTR_TYPE_NET, 1478 filter, handler, arg, &tag); 1479 if (rc != 0) { 1480 device_printf(dev, 1481 "failed to setup interrupt for rid %d, name %s: %d\n", 1482 rid, name ? name : "unknown", rc); 1483 return (rc); 1484 } else if (name) 1485 bus_describe_intr(dev, res, tag, "%s", name); 1486 1487 irq->ii_tag = tag; 1488 return (0); 1489} 1490 1491 1492/********************************************************************* 1493 * 1494 * Allocate memory for tx_buffer structures. The tx_buffer stores all 1495 * the information needed to transmit a packet on the wire. This is 1496 * called only once at attach, setup is done every reset. 1497 * 1498 **********************************************************************/ 1499 1500static int 1501iflib_txsd_alloc(iflib_txq_t txq) 1502{ 1503 if_ctx_t ctx = txq->ift_ctx; 1504 if_shared_ctx_t sctx = ctx->ifc_sctx; 1505 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1506 device_t dev = ctx->ifc_dev; 1507 int err, nsegments, ntsosegments; 1508 1509 nsegments = scctx->isc_tx_nsegments; 1510 ntsosegments = scctx->isc_tx_tso_segments_max; 1511 MPASS(scctx->isc_ntxd[0] > 0); 1512 MPASS(scctx->isc_ntxd[txq->ift_br_offset] > 0); 1513 MPASS(nsegments > 0); 1514 MPASS(ntsosegments > 0); 1515 /* 1516 * Setup DMA descriptor areas. 1517 */ 1518 if ((err = bus_dma_tag_create(bus_get_dma_tag(dev), 1519 1, 0, /* alignment, bounds */ 1520 BUS_SPACE_MAXADDR, /* lowaddr */ 1521 BUS_SPACE_MAXADDR, /* highaddr */ 1522 NULL, NULL, /* filter, filterarg */ 1523 sctx->isc_tx_maxsize, /* maxsize */ 1524 nsegments, /* nsegments */ 1525 sctx->isc_tx_maxsegsize, /* maxsegsize */ 1526 0, /* flags */ 1527 NULL, /* lockfunc */ 1528 NULL, /* lockfuncarg */ 1529 &txq->ift_desc_tag))) { 1530 device_printf(dev,"Unable to allocate TX DMA tag: %d\n", err); 1531 device_printf(dev,"maxsize: %ju nsegments: %d maxsegsize: %ju\n", 1532 (uintmax_t)sctx->isc_tx_maxsize, nsegments, (uintmax_t)sctx->isc_tx_maxsegsize); 1533 goto fail; 1534 } 1535 if ((err = bus_dma_tag_create(bus_get_dma_tag(dev), 1536 1, 0, /* alignment, bounds */ 1537 BUS_SPACE_MAXADDR, /* lowaddr */ 1538 BUS_SPACE_MAXADDR, /* highaddr */ 1539 NULL, NULL, /* filter, filterarg */ 1540 scctx->isc_tx_tso_size_max, /* maxsize */ 1541 ntsosegments, /* nsegments */ 1542 scctx->isc_tx_tso_segsize_max, /* maxsegsize */ 1543 0, /* flags */ 1544 NULL, /* lockfunc */ 1545 NULL, /* lockfuncarg */ 1546 &txq->ift_tso_desc_tag))) { 1547 device_printf(dev,"Unable to allocate TX TSO DMA tag: %d\n", err); 1548 1549 goto fail; 1550 } 1551 if (!(txq->ift_sds.ifsd_flags = 1552 (uint8_t *) malloc(sizeof(uint8_t) * 1553 scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1554 device_printf(dev, "Unable to allocate tx_buffer memory\n"); 1555 err = ENOMEM; 1556 goto fail; 1557 } 1558 if (!(txq->ift_sds.ifsd_m = 1559 (struct mbuf **) malloc(sizeof(struct mbuf *) * 1560 scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1561 device_printf(dev, "Unable to allocate tx_buffer memory\n"); 1562 err = ENOMEM; 1563 goto fail; 1564 } 1565 1566 /* Create the descriptor buffer dma maps */ 1567#if defined(ACPI_DMAR) || (! (defined(__i386__) || defined(__amd64__))) 1568 if ((ctx->ifc_flags & IFC_DMAR) == 0) 1569 return (0); 1570 1571 if (!(txq->ift_sds.ifsd_map = 1572 (bus_dmamap_t *) malloc(sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1573 device_printf(dev, "Unable to allocate tx_buffer map memory\n"); 1574 err = ENOMEM; 1575 goto fail; 1576 } 1577 1578 for (int i = 0; i < scctx->isc_ntxd[txq->ift_br_offset]; i++) { 1579 err = bus_dmamap_create(txq->ift_desc_tag, 0, &txq->ift_sds.ifsd_map[i]); 1580 if (err != 0) { 1581 device_printf(dev, "Unable to create TX DMA map\n"); 1582 goto fail; 1583 } 1584 } 1585#endif 1586 return (0); 1587fail: 1588 /* We free all, it handles case where we are in the middle */ 1589 iflib_tx_structures_free(ctx); 1590 return (err); 1591} 1592 1593static void 1594iflib_txsd_destroy(if_ctx_t ctx, iflib_txq_t txq, int i) 1595{ 1596 bus_dmamap_t map; 1597 1598 if (txq->ift_sds.ifsd_map != NULL) { 1599 map = txq->ift_sds.ifsd_map[i]; 1600 bus_dmamap_unload(txq->ift_desc_tag, map); 1601 bus_dmamap_destroy(txq->ift_desc_tag, map); 1602 txq->ift_sds.ifsd_map[i] = NULL; 1603 } 1604} 1605 1606static void 1607iflib_txq_destroy(iflib_txq_t txq) 1608{ 1609 if_ctx_t ctx = txq->ift_ctx; 1610 1611 for (int i = 0; i < txq->ift_size; i++) 1612 iflib_txsd_destroy(ctx, txq, i); 1613 1614 if (txq->ift_br != NULL) { 1615 ifmp_ring_free(txq->ift_br); 1616 txq->ift_br = NULL; 1617 } 1618 1619 mtx_destroy(&txq->ift_mtx); 1620 1621 if (txq->ift_sds.ifsd_map != NULL) { 1622 free(txq->ift_sds.ifsd_map, M_IFLIB); 1623 txq->ift_sds.ifsd_map = NULL; 1624 } 1625 if (txq->ift_sds.ifsd_m != NULL) { 1626 free(txq->ift_sds.ifsd_m, M_IFLIB); 1627 txq->ift_sds.ifsd_m = NULL; 1628 } 1629 if (txq->ift_sds.ifsd_flags != NULL) { 1630 free(txq->ift_sds.ifsd_flags, M_IFLIB); 1631 txq->ift_sds.ifsd_flags = NULL; 1632 } 1633 if (txq->ift_desc_tag != NULL) { 1634 bus_dma_tag_destroy(txq->ift_desc_tag); 1635 txq->ift_desc_tag = NULL; 1636 } 1637 if (txq->ift_tso_desc_tag != NULL) { 1638 bus_dma_tag_destroy(txq->ift_tso_desc_tag); 1639 txq->ift_tso_desc_tag = NULL; 1640 } 1641 if (txq->ift_ifdi != NULL) { 1642 free(txq->ift_ifdi, M_IFLIB); 1643 } 1644} 1645 1646static void 1647iflib_txsd_free(if_ctx_t ctx, iflib_txq_t txq, int i) 1648{ 1649 struct mbuf **mp; 1650 1651 mp = &txq->ift_sds.ifsd_m[i]; 1652 if (*mp == NULL) 1653 return; 1654 1655 if (txq->ift_sds.ifsd_map != NULL) { 1656 bus_dmamap_sync(txq->ift_desc_tag, 1657 txq->ift_sds.ifsd_map[i], 1658 BUS_DMASYNC_POSTWRITE); 1659 bus_dmamap_unload(txq->ift_desc_tag, 1660 txq->ift_sds.ifsd_map[i]); 1661 } 1662 m_free(*mp); 1663 DBG_COUNTER_INC(tx_frees); 1664 *mp = NULL; 1665} 1666 1667static int 1668iflib_txq_setup(iflib_txq_t txq) 1669{ 1670 if_ctx_t ctx = txq->ift_ctx; 1671 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1672 iflib_dma_info_t di; 1673 int i; 1674 1675 /* Set number of descriptors available */ 1676 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 1677 /* XXX make configurable */ 1678 txq->ift_update_freq = IFLIB_DEFAULT_TX_UPDATE_FREQ; 1679 1680 /* Reset indices */ 1681 txq->ift_cidx_processed = 0; 1682 txq->ift_pidx = txq->ift_cidx = txq->ift_npending = 0; 1683 txq->ift_size = scctx->isc_ntxd[txq->ift_br_offset]; 1684 1685 for (i = 0, di = txq->ift_ifdi; i < ctx->ifc_nhwtxqs; i++, di++) 1686 bzero((void *)di->idi_vaddr, di->idi_size); 1687 1688 IFDI_TXQ_SETUP(ctx, txq->ift_id); 1689 for (i = 0, di = txq->ift_ifdi; i < ctx->ifc_nhwtxqs; i++, di++) 1690 bus_dmamap_sync(di->idi_tag, di->idi_map, 1691 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1692 return (0); 1693} 1694 1695/********************************************************************* 1696 * 1697 * Allocate memory for rx_buffer structures. Since we use one 1698 * rx_buffer per received packet, the maximum number of rx_buffer's 1699 * that we'll need is equal to the number of receive descriptors 1700 * that we've allocated. 1701 * 1702 **********************************************************************/ 1703static int 1704iflib_rxsd_alloc(iflib_rxq_t rxq) 1705{ 1706 if_ctx_t ctx = rxq->ifr_ctx; 1707 if_shared_ctx_t sctx = ctx->ifc_sctx; 1708 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1709 device_t dev = ctx->ifc_dev; 1710 iflib_fl_t fl; 1711 int err; 1712 1713 MPASS(scctx->isc_nrxd[0] > 0); 1714 MPASS(scctx->isc_nrxd[rxq->ifr_fl_offset] > 0); 1715 1716 fl = rxq->ifr_fl; 1717 for (int i = 0; i < rxq->ifr_nfl; i++, fl++) { 1718 fl->ifl_size = scctx->isc_nrxd[rxq->ifr_fl_offset]; /* this isn't necessarily the same */ 1719 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 1720 1, 0, /* alignment, bounds */ 1721 BUS_SPACE_MAXADDR, /* lowaddr */ 1722 BUS_SPACE_MAXADDR, /* highaddr */ 1723 NULL, NULL, /* filter, filterarg */ 1724 sctx->isc_rx_maxsize, /* maxsize */ 1725 sctx->isc_rx_nsegments, /* nsegments */ 1726 sctx->isc_rx_maxsegsize, /* maxsegsize */ 1727 0, /* flags */ 1728 NULL, /* lockfunc */ 1729 NULL, /* lockarg */ 1730 &fl->ifl_desc_tag); 1731 if (err) { 1732 device_printf(dev, "%s: bus_dma_tag_create failed %d\n", 1733 __func__, err); 1734 goto fail; 1735 } 1736 if (!(fl->ifl_sds.ifsd_flags = 1737 (uint8_t *) malloc(sizeof(uint8_t) * 1738 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1739 device_printf(dev, "Unable to allocate tx_buffer memory\n"); 1740 err = ENOMEM; 1741 goto fail; 1742 } 1743 if (!(fl->ifl_sds.ifsd_m = 1744 (struct mbuf **) malloc(sizeof(struct mbuf *) * 1745 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1746 device_printf(dev, "Unable to allocate tx_buffer memory\n"); 1747 err = ENOMEM; 1748 goto fail; 1749 } 1750 if (!(fl->ifl_sds.ifsd_cl = 1751 (caddr_t *) malloc(sizeof(caddr_t) * 1752 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1753 device_printf(dev, "Unable to allocate tx_buffer memory\n"); 1754 err = ENOMEM; 1755 goto fail; 1756 } 1757 1758 /* Create the descriptor buffer dma maps */ 1759#if defined(ACPI_DMAR) || (! (defined(__i386__) || defined(__amd64__))) 1760 if ((ctx->ifc_flags & IFC_DMAR) == 0) 1761 continue; 1762 1763 if (!(fl->ifl_sds.ifsd_map = 1764 (bus_dmamap_t *) malloc(sizeof(bus_dmamap_t) * scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1765 device_printf(dev, "Unable to allocate tx_buffer map memory\n"); 1766 err = ENOMEM; 1767 goto fail; 1768 } 1769 1770 for (int i = 0; i < scctx->isc_nrxd[rxq->ifr_fl_offset]; i++) { 1771 err = bus_dmamap_create(fl->ifl_desc_tag, 0, &fl->ifl_sds.ifsd_map[i]); 1772 if (err != 0) { 1773 device_printf(dev, "Unable to create RX buffer DMA map\n"); 1774 goto fail; 1775 } 1776 } 1777#endif 1778 } 1779 return (0); 1780 1781fail: 1782 iflib_rx_structures_free(ctx); 1783 return (err); 1784} 1785 1786 1787/* 1788 * Internal service routines 1789 */ 1790 1791struct rxq_refill_cb_arg { 1792 int error; 1793 bus_dma_segment_t seg; 1794 int nseg; 1795}; 1796 1797static void 1798_rxq_refill_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1799{ 1800 struct rxq_refill_cb_arg *cb_arg = arg; 1801 1802 cb_arg->error = error; 1803 cb_arg->seg = segs[0]; 1804 cb_arg->nseg = nseg; 1805} 1806 1807 1808#ifdef ACPI_DMAR 1809#define IS_DMAR(ctx) (ctx->ifc_flags & IFC_DMAR) 1810#else 1811#define IS_DMAR(ctx) (0) 1812#endif 1813 1814/** 1815 * rxq_refill - refill an rxq free-buffer list 1816 * @ctx: the iflib context 1817 * @rxq: the free-list to refill 1818 * @n: the number of new buffers to allocate 1819 * 1820 * (Re)populate an rxq free-buffer list with up to @n new packet buffers. 1821 * The caller must assure that @n does not exceed the queue's capacity. 1822 */ 1823static uint8_t 1824_iflib_fl_refill(if_ctx_t ctx, iflib_fl_t fl, int count) 1825{ 1826 struct mbuf *m; 1827 int idx, frag_idx = fl->ifl_fragidx; 1828 int pidx = fl->ifl_pidx; 1829 caddr_t cl, *sd_cl; 1830 struct mbuf **sd_m; 1831 uint8_t *sd_flags; 1832 struct if_rxd_update iru; 1833 bus_dmamap_t *sd_map; 1834 int n, i = 0; 1835 uint64_t bus_addr; 1836 int err; 1837 qidx_t credits; 1838 1839 sd_m = fl->ifl_sds.ifsd_m; 1840 sd_map = fl->ifl_sds.ifsd_map; 1841 sd_cl = fl->ifl_sds.ifsd_cl; 1842 sd_flags = fl->ifl_sds.ifsd_flags; 1843 idx = pidx; 1844 credits = fl->ifl_credits; 1845 1846 n = count; 1847 MPASS(n > 0); 1848 MPASS(credits + n <= fl->ifl_size); 1849 1850 if (pidx < fl->ifl_cidx) 1851 MPASS(pidx + n <= fl->ifl_cidx); 1852 if (pidx == fl->ifl_cidx && (credits < fl->ifl_size)) 1853 MPASS(fl->ifl_gen == 0); 1854 if (pidx > fl->ifl_cidx) 1855 MPASS(n <= fl->ifl_size - pidx + fl->ifl_cidx); 1856 1857 DBG_COUNTER_INC(fl_refills); 1858 if (n > 8) 1859 DBG_COUNTER_INC(fl_refills_large); 1860 iru_init(&iru, fl->ifl_rxq, fl->ifl_id); 1861 while (n--) { 1862 /* 1863 * We allocate an uninitialized mbuf + cluster, mbuf is 1864 * initialized after rx. 1865 * 1866 * If the cluster is still set then we know a minimum sized packet was received 1867 */ 1868 bit_ffc_at(fl->ifl_rx_bitmap, frag_idx, fl->ifl_size, &frag_idx); 1869 if ((frag_idx < 0) || (frag_idx >= fl->ifl_size)) 1870 bit_ffc(fl->ifl_rx_bitmap, fl->ifl_size, &frag_idx); 1871 if ((cl = sd_cl[frag_idx]) == NULL) { 1872 if ((cl = sd_cl[frag_idx] = m_cljget(NULL, M_NOWAIT, fl->ifl_buf_size)) == NULL) 1873 break; 1874#if MEMORY_LOGGING 1875 fl->ifl_cl_enqueued++; 1876#endif 1877 } 1878 if ((m = m_gethdr(M_NOWAIT, MT_NOINIT)) == NULL) { 1879 break; 1880 } 1881#if MEMORY_LOGGING 1882 fl->ifl_m_enqueued++; 1883#endif 1884 1885 DBG_COUNTER_INC(rx_allocs); 1886#if defined(__i386__) || defined(__amd64__) 1887 if (!IS_DMAR(ctx)) { 1888 bus_addr = pmap_kextract((vm_offset_t)cl); 1889 } else 1890#endif 1891 { 1892 struct rxq_refill_cb_arg cb_arg; 1893 iflib_rxq_t q; 1894 1895 cb_arg.error = 0; 1896 q = fl->ifl_rxq; 1897 MPASS(sd_map != NULL); 1898 MPASS(sd_map[frag_idx] != NULL); 1899 err = bus_dmamap_load(fl->ifl_desc_tag, sd_map[frag_idx], 1900 cl, fl->ifl_buf_size, _rxq_refill_cb, &cb_arg, 0); 1901 bus_dmamap_sync(fl->ifl_desc_tag, sd_map[frag_idx], 1902 BUS_DMASYNC_PREREAD); 1903 1904 if (err != 0 || cb_arg.error) { 1905 /* 1906 * !zone_pack ? 1907 */ 1908 if (fl->ifl_zone == zone_pack) 1909 uma_zfree(fl->ifl_zone, cl); 1910 m_free(m); 1911 n = 0; 1912 goto done; 1913 } 1914 bus_addr = cb_arg.seg.ds_addr; 1915 } 1916 bit_set(fl->ifl_rx_bitmap, frag_idx); 1917 sd_flags[frag_idx] |= RX_SW_DESC_INUSE; 1918 1919 MPASS(sd_m[frag_idx] == NULL); 1920 sd_cl[frag_idx] = cl; 1921 sd_m[frag_idx] = m; 1922 fl->ifl_rxd_idxs[i] = frag_idx; 1923 fl->ifl_bus_addrs[i] = bus_addr; 1924 fl->ifl_vm_addrs[i] = cl; 1925 credits++; 1926 i++; 1927 MPASS(credits <= fl->ifl_size); 1928 if (++idx == fl->ifl_size) { 1929 fl->ifl_gen = 1; 1930 idx = 0; 1931 } 1932 if (n == 0 || i == IFLIB_MAX_RX_REFRESH) { 1933 iru.iru_pidx = pidx; 1934 iru.iru_count = i; 1935 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 1936 i = 0; 1937 pidx = idx; 1938 fl->ifl_pidx = idx; 1939 fl->ifl_credits = credits; 1940 } 1941 1942 } 1943done: 1944 if (i) { 1945 iru.iru_pidx = pidx; 1946 iru.iru_count = i; 1947 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 1948 fl->ifl_pidx = idx; 1949 fl->ifl_credits = credits; 1950 } 1951 DBG_COUNTER_INC(rxd_flush); 1952 if (fl->ifl_pidx == 0) 1953 pidx = fl->ifl_size - 1; 1954 else 1955 pidx = fl->ifl_pidx - 1; 1956 1957 if (sd_map) 1958 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 1959 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1960 ctx->isc_rxd_flush(ctx->ifc_softc, fl->ifl_rxq->ifr_id, fl->ifl_id, pidx); 1961 fl->ifl_fragidx = frag_idx; 1962 1963 return (n == -1 ? 0 : IFLIB_RXEOF_EMPTY); 1964} 1965 1966static __inline uint8_t 1967__iflib_fl_refill_lt(if_ctx_t ctx, iflib_fl_t fl, int max) 1968{ 1969 /* we avoid allowing pidx to catch up with cidx as it confuses ixl */ 1970 int32_t reclaimable = fl->ifl_size - fl->ifl_credits - 1; 1971#ifdef INVARIANTS 1972 int32_t delta = fl->ifl_size - get_inuse(fl->ifl_size, fl->ifl_cidx, fl->ifl_pidx, fl->ifl_gen) - 1; 1973#endif 1974 1975 MPASS(fl->ifl_credits <= fl->ifl_size); 1976 MPASS(reclaimable == delta); 1977 1978 if (reclaimable > 0) 1979 return (_iflib_fl_refill(ctx, fl, min(max, reclaimable))); 1980 return (0); 1981} 1982 1983uint8_t 1984iflib_in_detach(if_ctx_t ctx) 1985{ 1986 bool in_detach; 1987 STATE_LOCK(ctx); 1988 in_detach = !!(ctx->ifc_flags & IFC_IN_DETACH); 1989 STATE_UNLOCK(ctx); 1990 return (in_detach); 1991} 1992 1993static void 1994iflib_fl_bufs_free(iflib_fl_t fl) 1995{ 1996 iflib_dma_info_t idi = fl->ifl_ifdi; 1997 uint32_t i; 1998 1999 for (i = 0; i < fl->ifl_size; i++) { 2000 struct mbuf **sd_m = &fl->ifl_sds.ifsd_m[i]; 2001 uint8_t *sd_flags = &fl->ifl_sds.ifsd_flags[i]; 2002 caddr_t *sd_cl = &fl->ifl_sds.ifsd_cl[i]; 2003 2004 if (*sd_flags & RX_SW_DESC_INUSE) { 2005 if (fl->ifl_sds.ifsd_map != NULL) { 2006 bus_dmamap_t sd_map = fl->ifl_sds.ifsd_map[i]; 2007 bus_dmamap_unload(fl->ifl_desc_tag, sd_map); 2008 } 2009 if (*sd_m != NULL) { 2010 m_init(*sd_m, M_NOWAIT, MT_DATA, 0); 2011 uma_zfree(zone_mbuf, *sd_m); 2012 } 2013 if (*sd_cl != NULL) 2014 uma_zfree(fl->ifl_zone, *sd_cl); 2015 *sd_flags = 0; 2016 } else { 2017 MPASS(*sd_cl == NULL); 2018 MPASS(*sd_m == NULL); 2019 } 2020#if MEMORY_LOGGING 2021 fl->ifl_m_dequeued++; 2022 fl->ifl_cl_dequeued++; 2023#endif 2024 *sd_cl = NULL; 2025 *sd_m = NULL; 2026 } 2027#ifdef INVARIANTS 2028 for (i = 0; i < fl->ifl_size; i++) { 2029 MPASS(fl->ifl_sds.ifsd_flags[i] == 0); 2030 MPASS(fl->ifl_sds.ifsd_cl[i] == NULL); 2031 MPASS(fl->ifl_sds.ifsd_m[i] == NULL); 2032 } 2033#endif 2034 /* 2035 * Reset free list values 2036 */ 2037 fl->ifl_credits = fl->ifl_cidx = fl->ifl_pidx = fl->ifl_gen = fl->ifl_fragidx = 0; 2038 bzero(idi->idi_vaddr, idi->idi_size); 2039} 2040 2041/********************************************************************* 2042 * 2043 * Initialize a receive ring and its buffers. 2044 * 2045 **********************************************************************/ 2046static int 2047iflib_fl_setup(iflib_fl_t fl) 2048{ 2049 iflib_rxq_t rxq = fl->ifl_rxq; 2050 if_ctx_t ctx = rxq->ifr_ctx; 2051 2052 bit_nclear(fl->ifl_rx_bitmap, 0, fl->ifl_size - 1); 2053 /* 2054 ** Free current RX buffer structs and their mbufs 2055 */ 2056 iflib_fl_bufs_free(fl); 2057 /* Now replenish the mbufs */ 2058 MPASS(fl->ifl_credits == 0); 2059 fl->ifl_buf_size = ctx->ifc_rx_mbuf_sz; 2060 if (fl->ifl_buf_size > ctx->ifc_max_fl_buf_size) 2061 ctx->ifc_max_fl_buf_size = fl->ifl_buf_size; 2062 fl->ifl_cltype = m_gettype(fl->ifl_buf_size); 2063 fl->ifl_zone = m_getzone(fl->ifl_buf_size); 2064 2065 2066 /* avoid pre-allocating zillions of clusters to an idle card 2067 * potentially speeding up attach 2068 */ 2069 (void) _iflib_fl_refill(ctx, fl, min(128, fl->ifl_size)); 2070 MPASS(min(128, fl->ifl_size) == fl->ifl_credits); 2071 if (min(128, fl->ifl_size) != fl->ifl_credits) 2072 return (ENOBUFS); 2073 /* 2074 * handle failure 2075 */ 2076 MPASS(rxq != NULL); 2077 MPASS(fl->ifl_ifdi != NULL); 2078 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 2079 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2080 return (0); 2081} 2082 2083/********************************************************************* 2084 * 2085 * Free receive ring data structures 2086 * 2087 **********************************************************************/ 2088static void 2089iflib_rx_sds_free(iflib_rxq_t rxq) 2090{ 2091 iflib_fl_t fl; 2092 int i; 2093 2094 if (rxq->ifr_fl != NULL) { 2095 for (i = 0; i < rxq->ifr_nfl; i++) { 2096 fl = &rxq->ifr_fl[i]; 2097 if (fl->ifl_desc_tag != NULL) { 2098 bus_dma_tag_destroy(fl->ifl_desc_tag); 2099 fl->ifl_desc_tag = NULL; 2100 } 2101 free(fl->ifl_sds.ifsd_m, M_IFLIB); 2102 free(fl->ifl_sds.ifsd_cl, M_IFLIB); 2103 /* XXX destroy maps first */ 2104 free(fl->ifl_sds.ifsd_map, M_IFLIB); 2105 fl->ifl_sds.ifsd_m = NULL; 2106 fl->ifl_sds.ifsd_cl = NULL; 2107 fl->ifl_sds.ifsd_map = NULL; 2108 } 2109 free(rxq->ifr_fl, M_IFLIB); 2110 rxq->ifr_fl = NULL; 2111 rxq->ifr_cq_gen = rxq->ifr_cq_cidx = rxq->ifr_cq_pidx = 0; 2112 free(rxq->ifr_ifdi, M_IFLIB); 2113 rxq->ifr_ifdi = NULL; 2114 } 2115} 2116 2117/* 2118 * MI independent logic 2119 * 2120 */ 2121static void 2122iflib_timer(void *arg) 2123{ 2124 iflib_txq_t txq = arg; 2125 if_ctx_t ctx = txq->ift_ctx; 2126 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2127 2128 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) 2129 return; 2130 /* 2131 ** Check on the state of the TX queue(s), this 2132 ** can be done without the lock because its RO 2133 ** and the HUNG state will be static if set. 2134 */ 2135 IFDI_TIMER(ctx, txq->ift_id); 2136 if ((txq->ift_qstatus == IFLIB_QUEUE_HUNG) && 2137 ((txq->ift_cleaned_prev == txq->ift_cleaned) || 2138 (sctx->isc_pause_frames == 0))) 2139 goto hung; 2140 2141 if (txq->ift_qstatus != IFLIB_QUEUE_IDLE && 2142 ifmp_ring_is_stalled(txq->ift_br)) { 2143 KASSERT(ctx->ifc_link_state == LINK_STATE_UP, ("queue can't be marked as hung if interface is down")); 2144 txq->ift_qstatus = IFLIB_QUEUE_HUNG; 2145 } 2146 txq->ift_cleaned_prev = txq->ift_cleaned; 2147 /* handle any laggards */ 2148 if (txq->ift_db_pending) 2149 GROUPTASK_ENQUEUE(&txq->ift_task); 2150 2151 sctx->isc_pause_frames = 0; 2152 if (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING) 2153 callout_reset_on(&txq->ift_timer, hz/2, iflib_timer, txq, txq->ift_timer.c_cpu); 2154 return; 2155 hung: 2156 device_printf(ctx->ifc_dev, "TX(%d) desc avail = %d, pidx = %d\n", 2157 txq->ift_id, TXQ_AVAIL(txq), txq->ift_pidx); 2158 STATE_LOCK(ctx); 2159 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2160 ctx->ifc_flags |= (IFC_DO_WATCHDOG|IFC_DO_RESET); 2161 iflib_admin_intr_deferred(ctx); 2162 STATE_UNLOCK(ctx); 2163} 2164 2165static void 2166iflib_calc_rx_mbuf_sz(if_ctx_t ctx) 2167{ 2168 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2169 2170 /* 2171 * XXX don't set the max_frame_size to larger 2172 * than the hardware can handle 2173 */ 2174 if (sctx->isc_max_frame_size <= MCLBYTES) 2175 ctx->ifc_rx_mbuf_sz = MCLBYTES; 2176 else 2177 ctx->ifc_rx_mbuf_sz = MJUMPAGESIZE; 2178} 2179 2180uint32_t 2181iflib_get_rx_mbuf_sz(if_ctx_t ctx) 2182{ 2183 return (ctx->ifc_rx_mbuf_sz); 2184} 2185 2186static void 2187iflib_init_locked(if_ctx_t ctx) 2188{ 2189 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2190 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2191 if_t ifp = ctx->ifc_ifp; 2192 iflib_fl_t fl; 2193 iflib_txq_t txq; 2194 iflib_rxq_t rxq; 2195 int i, j, tx_ip_csum_flags, tx_ip6_csum_flags; 2196 2197 2198 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2199 IFDI_INTR_DISABLE(ctx); 2200 2201 tx_ip_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_SCTP); 2202 tx_ip6_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_UDP | CSUM_IP6_SCTP); 2203 /* Set hardware offload abilities */ 2204 if_clearhwassist(ifp); 2205 if (if_getcapenable(ifp) & IFCAP_TXCSUM) 2206 if_sethwassistbits(ifp, tx_ip_csum_flags, 0); 2207 if (if_getcapenable(ifp) & IFCAP_TXCSUM_IPV6) 2208 if_sethwassistbits(ifp, tx_ip6_csum_flags, 0); 2209 if (if_getcapenable(ifp) & IFCAP_TSO4) 2210 if_sethwassistbits(ifp, CSUM_IP_TSO, 0); 2211 if (if_getcapenable(ifp) & IFCAP_TSO6) 2212 if_sethwassistbits(ifp, CSUM_IP6_TSO, 0); 2213 2214 for (i = 0, txq = ctx->ifc_txqs; i < sctx->isc_ntxqsets; i++, txq++) { 2215 CALLOUT_LOCK(txq); 2216 callout_stop(&txq->ift_timer); 2217 CALLOUT_UNLOCK(txq); 2218 iflib_netmap_txq_init(ctx, txq); 2219 } 2220 2221 /* 2222 * Calculate a suitable Rx mbuf size prior to calling IFDI_INIT, so 2223 * that drivers can use the value when setting up the hardware receive 2224 * buffers. 2225 */ 2226 iflib_calc_rx_mbuf_sz(ctx); 2227 2228#ifdef INVARIANTS 2229 i = if_getdrvflags(ifp); 2230#endif 2231 IFDI_INIT(ctx); 2232 MPASS(if_getdrvflags(ifp) == i); 2233 for (i = 0, rxq = ctx->ifc_rxqs; i < sctx->isc_nrxqsets; i++, rxq++) { 2234 /* XXX this should really be done on a per-queue basis */ 2235 if (if_getcapenable(ifp) & IFCAP_NETMAP) { 2236 MPASS(rxq->ifr_id == i); 2237 iflib_netmap_rxq_init(ctx, rxq); 2238 continue; 2239 } 2240 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) { 2241 if (iflib_fl_setup(fl)) { 2242 device_printf(ctx->ifc_dev, "freelist setup failed - check cluster settings\n"); 2243 goto done; 2244 } 2245 } 2246 } 2247done: 2248 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_RUNNING, IFF_DRV_OACTIVE); 2249 IFDI_INTR_ENABLE(ctx); 2250 txq = ctx->ifc_txqs; 2251 for (i = 0; i < sctx->isc_ntxqsets; i++, txq++) 2252 callout_reset_on(&txq->ift_timer, hz/2, iflib_timer, txq, 2253 txq->ift_timer.c_cpu); 2254} 2255 2256static int 2257iflib_media_change(if_t ifp) 2258{ 2259 if_ctx_t ctx = if_getsoftc(ifp); 2260 int err; 2261 2262 CTX_LOCK(ctx); 2263 if ((err = IFDI_MEDIA_CHANGE(ctx)) == 0) 2264 iflib_init_locked(ctx); 2265 CTX_UNLOCK(ctx); 2266 return (err); 2267} 2268 2269static void 2270iflib_media_status(if_t ifp, struct ifmediareq *ifmr) 2271{ 2272 if_ctx_t ctx = if_getsoftc(ifp); 2273 2274 CTX_LOCK(ctx); 2275 IFDI_UPDATE_ADMIN_STATUS(ctx); 2276 IFDI_MEDIA_STATUS(ctx, ifmr); 2277 CTX_UNLOCK(ctx); 2278} 2279 2280static void 2281iflib_stop(if_ctx_t ctx) 2282{ 2283 iflib_txq_t txq = ctx->ifc_txqs; 2284 iflib_rxq_t rxq = ctx->ifc_rxqs; 2285 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2286 iflib_dma_info_t di; 2287 iflib_fl_t fl; 2288 int i, j; 2289 2290 /* Tell the stack that the interface is no longer active */ 2291 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2292 2293 IFDI_INTR_DISABLE(ctx); 2294 DELAY(1000); 2295 IFDI_STOP(ctx); 2296 DELAY(1000); 2297 2298 iflib_debug_reset(); 2299 /* Wait for current tx queue users to exit to disarm watchdog timer. */ 2300 for (i = 0; i < scctx->isc_ntxqsets; i++, txq++) { 2301 /* make sure all transmitters have completed before proceeding XXX */ 2302 2303 CALLOUT_LOCK(txq); 2304 callout_stop(&txq->ift_timer); 2305 CALLOUT_UNLOCK(txq); 2306 2307 /* clean any enqueued buffers */ 2308 iflib_ifmp_purge(txq); 2309 /* Free any existing tx buffers. */ 2310 for (j = 0; j < txq->ift_size; j++) { 2311 iflib_txsd_free(ctx, txq, j); 2312 } 2313 txq->ift_processed = txq->ift_cleaned = txq->ift_cidx_processed = 0; 2314 txq->ift_in_use = txq->ift_gen = txq->ift_cidx = txq->ift_pidx = txq->ift_no_desc_avail = 0; 2315 txq->ift_closed = txq->ift_mbuf_defrag = txq->ift_mbuf_defrag_failed = 0; 2316 txq->ift_no_tx_dma_setup = txq->ift_txd_encap_efbig = txq->ift_map_failed = 0; 2317 txq->ift_pullups = 0; 2318 ifmp_ring_reset_stats(txq->ift_br); 2319 for (j = 0, di = txq->ift_ifdi; j < ctx->ifc_nhwtxqs; j++, di++) 2320 bzero((void *)di->idi_vaddr, di->idi_size); 2321 } 2322 for (i = 0; i < scctx->isc_nrxqsets; i++, rxq++) { 2323 /* make sure all transmitters have completed before proceeding XXX */ 2324 2325 for (j = 0, di = rxq->ifr_ifdi; j < rxq->ifr_nfl; j++, di++) 2326 bzero((void *)di->idi_vaddr, di->idi_size); 2327 /* also resets the free lists pidx/cidx */ 2328 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 2329 iflib_fl_bufs_free(fl); 2330 } 2331} 2332 2333static inline caddr_t 2334calc_next_rxd(iflib_fl_t fl, int cidx) 2335{ 2336 qidx_t size; 2337 int nrxd; 2338 caddr_t start, end, cur, next; 2339 2340 nrxd = fl->ifl_size; 2341 size = fl->ifl_rxd_size; 2342 start = fl->ifl_ifdi->idi_vaddr; 2343 2344 if (__predict_false(size == 0)) 2345 return (start); 2346 cur = start + size*cidx; 2347 end = start + size*nrxd; 2348 next = CACHE_PTR_NEXT(cur); 2349 return (next < end ? next : start); 2350} 2351 2352static inline void 2353prefetch_pkts(iflib_fl_t fl, int cidx) 2354{ 2355 int nextptr; 2356 int nrxd = fl->ifl_size; 2357 caddr_t next_rxd; 2358 2359 2360 nextptr = (cidx + CACHE_PTR_INCREMENT) & (nrxd-1); 2361 prefetch(&fl->ifl_sds.ifsd_m[nextptr]); 2362 prefetch(&fl->ifl_sds.ifsd_cl[nextptr]); 2363 next_rxd = calc_next_rxd(fl, cidx); 2364 prefetch(next_rxd); 2365 prefetch(fl->ifl_sds.ifsd_m[(cidx + 1) & (nrxd-1)]); 2366 prefetch(fl->ifl_sds.ifsd_m[(cidx + 2) & (nrxd-1)]); 2367 prefetch(fl->ifl_sds.ifsd_m[(cidx + 3) & (nrxd-1)]); 2368 prefetch(fl->ifl_sds.ifsd_m[(cidx + 4) & (nrxd-1)]); 2369 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 1) & (nrxd-1)]); 2370 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 2) & (nrxd-1)]); 2371 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 3) & (nrxd-1)]); 2372 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 4) & (nrxd-1)]); 2373} 2374 2375static void 2376rxd_frag_to_sd(iflib_rxq_t rxq, if_rxd_frag_t irf, int unload, if_rxsd_t sd) 2377{ 2378 int flid, cidx; 2379 bus_dmamap_t map; 2380 iflib_fl_t fl; 2381 iflib_dma_info_t di; 2382 int next; 2383 2384 map = NULL; 2385 flid = irf->irf_flid; 2386 cidx = irf->irf_idx; 2387 fl = &rxq->ifr_fl[flid]; 2388 sd->ifsd_fl = fl; 2389 sd->ifsd_cidx = cidx; 2390 sd->ifsd_m = &fl->ifl_sds.ifsd_m[cidx]; 2391 sd->ifsd_cl = &fl->ifl_sds.ifsd_cl[cidx]; 2392 fl->ifl_credits--; 2393#if MEMORY_LOGGING 2394 fl->ifl_m_dequeued++; 2395#endif 2396 if (rxq->ifr_ctx->ifc_flags & IFC_PREFETCH) 2397 prefetch_pkts(fl, cidx); 2398 if (fl->ifl_sds.ifsd_map != NULL) { 2399 next = (cidx + CACHE_PTR_INCREMENT) & (fl->ifl_size-1); 2400 prefetch(&fl->ifl_sds.ifsd_map[next]); 2401 map = fl->ifl_sds.ifsd_map[cidx]; 2402 di = fl->ifl_ifdi; 2403 next = (cidx + CACHE_LINE_SIZE) & (fl->ifl_size-1); 2404 prefetch(&fl->ifl_sds.ifsd_flags[next]); 2405 bus_dmamap_sync(di->idi_tag, di->idi_map, 2406 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2407 2408 /* not valid assert if bxe really does SGE from non-contiguous elements */ 2409 MPASS(fl->ifl_cidx == cidx); 2410 if (unload) 2411 bus_dmamap_unload(fl->ifl_desc_tag, map); 2412 } 2413 fl->ifl_cidx = (fl->ifl_cidx + 1) & (fl->ifl_size-1); 2414 if (__predict_false(fl->ifl_cidx == 0)) 2415 fl->ifl_gen = 0; 2416 if (map != NULL) 2417 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 2418 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2419 bit_clear(fl->ifl_rx_bitmap, cidx); 2420} 2421 2422static struct mbuf * 2423assemble_segments(iflib_rxq_t rxq, if_rxd_info_t ri, if_rxsd_t sd) 2424{ 2425 int i, padlen , flags; 2426 struct mbuf *m, *mh, *mt; 2427 caddr_t cl; 2428 2429 i = 0; 2430 mh = NULL; 2431 do { 2432 rxd_frag_to_sd(rxq, &ri->iri_frags[i], TRUE, sd); 2433 2434 MPASS(*sd->ifsd_cl != NULL); 2435 MPASS(*sd->ifsd_m != NULL); 2436 2437 /* Don't include zero-length frags */ 2438 if (ri->iri_frags[i].irf_len == 0) { 2439 /* XXX we can save the cluster here, but not the mbuf */ 2440 m_init(*sd->ifsd_m, M_NOWAIT, MT_DATA, 0); 2441 m_free(*sd->ifsd_m); 2442 *sd->ifsd_m = NULL; 2443 continue; 2444 } 2445 m = *sd->ifsd_m; 2446 *sd->ifsd_m = NULL; 2447 if (mh == NULL) { 2448 flags = M_PKTHDR|M_EXT; 2449 mh = mt = m; 2450 padlen = ri->iri_pad; 2451 } else { 2452 flags = M_EXT; 2453 mt->m_next = m; 2454 mt = m; 2455 /* assuming padding is only on the first fragment */ 2456 padlen = 0; 2457 } 2458 cl = *sd->ifsd_cl; 2459 *sd->ifsd_cl = NULL; 2460 2461 /* Can these two be made one ? */ 2462 m_init(m, M_NOWAIT, MT_DATA, flags); 2463 m_cljset(m, cl, sd->ifsd_fl->ifl_cltype); 2464 /* 2465 * These must follow m_init and m_cljset 2466 */ 2467 m->m_data += padlen; 2468 ri->iri_len -= padlen; 2469 m->m_len = ri->iri_frags[i].irf_len; 2470 } while (++i < ri->iri_nfrags); 2471 2472 return (mh); 2473} 2474 2475/* 2476 * Process one software descriptor 2477 */ 2478static struct mbuf * 2479iflib_rxd_pkt_get(iflib_rxq_t rxq, if_rxd_info_t ri) 2480{ 2481 struct if_rxsd sd; 2482 struct mbuf *m; 2483 2484 /* should I merge this back in now that the two paths are basically duplicated? */ 2485 if (ri->iri_nfrags == 1 && 2486 ri->iri_frags[0].irf_len <= MIN(IFLIB_RX_COPY_THRESH, MHLEN)) { 2487 rxd_frag_to_sd(rxq, &ri->iri_frags[0], FALSE, &sd); 2488 m = *sd.ifsd_m; 2489 *sd.ifsd_m = NULL; 2490 m_init(m, M_NOWAIT, MT_DATA, M_PKTHDR); 2491#ifndef __NO_STRICT_ALIGNMENT 2492 if (!IP_ALIGNED(m)) 2493 m->m_data += 2; 2494#endif 2495 memcpy(m->m_data, *sd.ifsd_cl, ri->iri_len); 2496 m->m_len = ri->iri_frags[0].irf_len; 2497 } else { 2498 m = assemble_segments(rxq, ri, &sd); 2499 } 2500 m->m_pkthdr.len = ri->iri_len; 2501 m->m_pkthdr.rcvif = ri->iri_ifp; 2502 m->m_flags |= ri->iri_flags; 2503 m->m_pkthdr.ether_vtag = ri->iri_vtag; 2504 m->m_pkthdr.flowid = ri->iri_flowid; 2505 M_HASHTYPE_SET(m, ri->iri_rsstype); 2506 m->m_pkthdr.csum_flags = ri->iri_csum_flags; 2507 m->m_pkthdr.csum_data = ri->iri_csum_data; 2508 return (m); 2509} 2510 2511#if defined(INET6) || defined(INET) 2512static void 2513iflib_get_ip_forwarding(struct lro_ctrl *lc, bool *v4, bool *v6) 2514{ 2515 CURVNET_SET(lc->ifp->if_vnet); 2516#if defined(INET6) 2517 *v6 = VNET(ip6_forwarding); 2518#endif 2519#if defined(INET) 2520 *v4 = VNET(ipforwarding); 2521#endif 2522 CURVNET_RESTORE(); 2523} 2524 2525/* 2526 * Returns true if it's possible this packet could be LROed. 2527 * if it returns false, it is guaranteed that tcp_lro_rx() 2528 * would not return zero. 2529 */ 2530static bool 2531iflib_check_lro_possible(struct mbuf *m, bool v4_forwarding, bool v6_forwarding) 2532{ 2533 struct ether_header *eh; 2534 uint16_t eh_type; 2535 2536 eh = mtod(m, struct ether_header *); 2537 eh_type = ntohs(eh->ether_type); 2538 switch (eh_type) { 2539#if defined(INET6) 2540 case ETHERTYPE_IPV6: 2541 return !v6_forwarding; 2542#endif 2543#if defined (INET) 2544 case ETHERTYPE_IP: 2545 return !v4_forwarding; 2546#endif 2547 } 2548 2549 return false; 2550} 2551#else 2552static void 2553iflib_get_ip_forwarding(struct lro_ctrl *lc __unused, bool *v4 __unused, bool *v6 __unused) 2554{ 2555} 2556#endif 2557 2558static void 2559_task_fn_rx_watchdog(void *context) 2560{ 2561 iflib_rxq_t rxq = context; 2562 2563 GROUPTASK_ENQUEUE(&rxq->ifr_task); 2564} 2565 2566static uint8_t 2567iflib_rxeof(iflib_rxq_t rxq, qidx_t budget) 2568{ 2569 if_ctx_t ctx = rxq->ifr_ctx; 2570 if_shared_ctx_t sctx = ctx->ifc_sctx; 2571 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2572 int avail, i; 2573 qidx_t *cidxp; 2574 struct if_rxd_info ri; 2575 int err, budget_left, rx_bytes, rx_pkts; 2576 iflib_fl_t fl; 2577 struct ifnet *ifp; 2578 int lro_enabled; 2579 bool lro_possible = false; 2580 bool v4_forwarding, v6_forwarding; 2581 uint8_t retval = 0; 2582 2583 /* 2584 * XXX early demux data packets so that if_input processing only handles 2585 * acks in interrupt context 2586 */ 2587 struct mbuf *m, *mh, *mt, *mf; 2588 2589 ifp = ctx->ifc_ifp; 2590 mh = mt = NULL; 2591 MPASS(budget > 0); 2592 rx_pkts = rx_bytes = 0; 2593 if (sctx->isc_flags & IFLIB_HAS_RXCQ) 2594 cidxp = &rxq->ifr_cq_cidx; 2595 else 2596 cidxp = &rxq->ifr_fl[0].ifl_cidx; 2597 if ((avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget)) == 0) { 2598 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++) 2599 retval |= __iflib_fl_refill_lt(ctx, fl, budget + 8); 2600 DBG_COUNTER_INC(rx_unavail); 2601 return (retval); 2602 } 2603 2604 for (budget_left = budget; (budget_left > 0) && (avail > 0); budget_left--, avail--) { 2605 if (__predict_false(!CTX_ACTIVE(ctx))) { 2606 DBG_COUNTER_INC(rx_ctx_inactive); 2607 break; 2608 } 2609 /* 2610 * Reset client set fields to their default values 2611 */ 2612 rxd_info_zero(&ri); 2613 ri.iri_qsidx = rxq->ifr_id; 2614 ri.iri_cidx = *cidxp; 2615 ri.iri_ifp = ifp; 2616 ri.iri_frags = rxq->ifr_frags; 2617 err = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri); 2618 2619 if (err) 2620 goto err; 2621 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 2622 *cidxp = ri.iri_cidx; 2623 /* Update our consumer index */ 2624 /* XXX NB: shurd - check if this is still safe */ 2625 while (rxq->ifr_cq_cidx >= scctx->isc_nrxd[0]) { 2626 rxq->ifr_cq_cidx -= scctx->isc_nrxd[0]; 2627 rxq->ifr_cq_gen = 0; 2628 } 2629 /* was this only a completion queue message? */ 2630 if (__predict_false(ri.iri_nfrags == 0)) 2631 continue; 2632 } 2633 MPASS(ri.iri_nfrags != 0); 2634 MPASS(ri.iri_len != 0); 2635 2636 /* will advance the cidx on the corresponding free lists */ 2637 m = iflib_rxd_pkt_get(rxq, &ri); 2638 if (avail == 0 && budget_left) 2639 avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget_left); 2640 2641 if (__predict_false(m == NULL)) { 2642 DBG_COUNTER_INC(rx_mbuf_null); 2643 continue; 2644 } 2645 /* imm_pkt: -- cxgb */ 2646 if (mh == NULL) 2647 mh = mt = m; 2648 else { 2649 mt->m_nextpkt = m; 2650 mt = m; 2651 } 2652 } 2653 /* make sure that we can refill faster than drain */ 2654 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++) 2655 retval |= __iflib_fl_refill_lt(ctx, fl, budget + 8); 2656 2657 lro_enabled = (if_getcapenable(ifp) & IFCAP_LRO); 2658 if (lro_enabled) 2659 iflib_get_ip_forwarding(&rxq->ifr_lc, &v4_forwarding, &v6_forwarding); 2660 mt = mf = NULL; 2661 while (mh != NULL) { 2662 m = mh; 2663 mh = mh->m_nextpkt; 2664 m->m_nextpkt = NULL; 2665#ifndef __NO_STRICT_ALIGNMENT 2666 if (!IP_ALIGNED(m) && (m = iflib_fixup_rx(m)) == NULL) 2667 continue; 2668#endif 2669 rx_bytes += m->m_pkthdr.len; 2670 rx_pkts++; 2671#if defined(INET6) || defined(INET) 2672 if (lro_enabled) { 2673 if (!lro_possible) { 2674 lro_possible = iflib_check_lro_possible(m, v4_forwarding, v6_forwarding); 2675 if (lro_possible && mf != NULL) { 2676 ifp->if_input(ifp, mf); 2677 DBG_COUNTER_INC(rx_if_input); 2678 mt = mf = NULL; 2679 } 2680 } 2681 if ((m->m_pkthdr.csum_flags & (CSUM_L4_CALC|CSUM_L4_VALID)) == 2682 (CSUM_L4_CALC|CSUM_L4_VALID)) { 2683 if (lro_possible && tcp_lro_rx(&rxq->ifr_lc, m, 0) == 0) 2684 continue; 2685 } 2686 } 2687#endif 2688 if (lro_possible) { 2689 ifp->if_input(ifp, m); 2690 DBG_COUNTER_INC(rx_if_input); 2691 continue; 2692 } 2693 2694 if (mf == NULL) 2695 mf = m; 2696 if (mt != NULL) 2697 mt->m_nextpkt = m; 2698 mt = m; 2699 } 2700 if (mf != NULL) { 2701 ifp->if_input(ifp, mf); 2702 DBG_COUNTER_INC(rx_if_input); 2703 } 2704 2705 if_inc_counter(ifp, IFCOUNTER_IBYTES, rx_bytes); 2706 if_inc_counter(ifp, IFCOUNTER_IPACKETS, rx_pkts); 2707 2708 /* 2709 * Flush any outstanding LRO work 2710 */ 2711#if defined(INET6) || defined(INET) 2712 tcp_lro_flush_all(&rxq->ifr_lc); 2713#endif 2714 if (avail != 0 || iflib_rxd_avail(ctx, rxq, *cidxp, 1) != 0) 2715 retval |= IFLIB_RXEOF_MORE; 2716 return (retval); 2717err: 2718 STATE_LOCK(ctx); 2719 ctx->ifc_flags |= IFC_DO_RESET; 2720 iflib_admin_intr_deferred(ctx); 2721 STATE_UNLOCK(ctx); 2722 return (0); 2723} 2724 2725#define TXD_NOTIFY_COUNT(txq) (((txq)->ift_size / (txq)->ift_update_freq)-1) 2726static inline qidx_t 2727txq_max_db_deferred(iflib_txq_t txq, qidx_t in_use) 2728{ 2729 qidx_t notify_count = TXD_NOTIFY_COUNT(txq); 2730 qidx_t minthresh = txq->ift_size / 8; 2731 if (in_use > 4*minthresh) 2732 return (notify_count); 2733 if (in_use > 2*minthresh) 2734 return (notify_count >> 1); 2735 if (in_use > minthresh) 2736 return (notify_count >> 3); 2737 return (0); 2738} 2739 2740static inline qidx_t 2741txq_max_rs_deferred(iflib_txq_t txq) 2742{ 2743 qidx_t notify_count = TXD_NOTIFY_COUNT(txq); 2744 qidx_t minthresh = txq->ift_size / 8; 2745 if (txq->ift_in_use > 4*minthresh) 2746 return (notify_count); 2747 if (txq->ift_in_use > 2*minthresh) 2748 return (notify_count >> 1); 2749 if (txq->ift_in_use > minthresh) 2750 return (notify_count >> 2); 2751 return (2); 2752} 2753 2754#define M_CSUM_FLAGS(m) ((m)->m_pkthdr.csum_flags) 2755#define M_HAS_VLANTAG(m) (m->m_flags & M_VLANTAG) 2756 2757#define TXQ_MAX_DB_DEFERRED(txq, in_use) txq_max_db_deferred((txq), (in_use)) 2758#define TXQ_MAX_RS_DEFERRED(txq) txq_max_rs_deferred(txq) 2759#define TXQ_MAX_DB_CONSUMED(size) (size >> 4) 2760 2761/* forward compatibility for cxgb */ 2762#define FIRST_QSET(ctx) 0 2763#define NTXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_ntxqsets) 2764#define NRXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_nrxqsets) 2765#define QIDX(ctx, m) ((((m)->m_pkthdr.flowid & ctx->ifc_softc_ctx.isc_rss_table_mask) % NTXQSETS(ctx)) + FIRST_QSET(ctx)) 2766#define DESC_RECLAIMABLE(q) ((int)((q)->ift_processed - (q)->ift_cleaned - (q)->ift_ctx->ifc_softc_ctx.isc_tx_nsegments)) 2767 2768/* XXX we should be setting this to something other than zero */ 2769#define RECLAIM_THRESH(ctx) ((ctx)->ifc_sctx->isc_tx_reclaim_thresh) 2770#define MAX_TX_DESC(ctx) ((ctx)->ifc_softc_ctx.isc_tx_tso_segments_max) 2771 2772static inline bool 2773iflib_txd_db_check(if_ctx_t ctx, iflib_txq_t txq, int ring, qidx_t in_use) 2774{ 2775 qidx_t dbval, max; 2776 bool rang; 2777 2778 rang = false; 2779 max = TXQ_MAX_DB_DEFERRED(txq, in_use); 2780 if (ring || txq->ift_db_pending >= max) { 2781 dbval = txq->ift_npending ? txq->ift_npending : txq->ift_pidx; 2782 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, dbval); 2783 txq->ift_db_pending = txq->ift_npending = 0; 2784 rang = true; 2785 } 2786 return (rang); 2787} 2788 2789#ifdef PKT_DEBUG 2790static void 2791print_pkt(if_pkt_info_t pi) 2792{ 2793 printf("pi len: %d qsidx: %d nsegs: %d ndescs: %d flags: %x pidx: %d\n", 2794 pi->ipi_len, pi->ipi_qsidx, pi->ipi_nsegs, pi->ipi_ndescs, pi->ipi_flags, pi->ipi_pidx); 2795 printf("pi new_pidx: %d csum_flags: %lx tso_segsz: %d mflags: %x vtag: %d\n", 2796 pi->ipi_new_pidx, pi->ipi_csum_flags, pi->ipi_tso_segsz, pi->ipi_mflags, pi->ipi_vtag); 2797 printf("pi etype: %d ehdrlen: %d ip_hlen: %d ipproto: %d\n", 2798 pi->ipi_etype, pi->ipi_ehdrlen, pi->ipi_ip_hlen, pi->ipi_ipproto); 2799} 2800#endif 2801 2802#define IS_TSO4(pi) ((pi)->ipi_csum_flags & CSUM_IP_TSO) 2803#define IS_TX_OFFLOAD4(pi) ((pi)->ipi_csum_flags & (CSUM_IP_TCP | CSUM_IP_TSO)) 2804#define IS_TSO6(pi) ((pi)->ipi_csum_flags & CSUM_IP6_TSO) 2805#define IS_TX_OFFLOAD6(pi) ((pi)->ipi_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_TSO)) 2806 2807static int 2808iflib_parse_header(iflib_txq_t txq, if_pkt_info_t pi, struct mbuf **mp) 2809{ 2810 if_shared_ctx_t sctx = txq->ift_ctx->ifc_sctx; 2811 struct ether_vlan_header *eh; 2812 struct mbuf *m, *n; 2813 2814 n = m = *mp; 2815 if ((sctx->isc_flags & IFLIB_NEED_SCRATCH) && 2816 M_WRITABLE(m) == 0) { 2817 if ((m = m_dup(m, M_NOWAIT)) == NULL) { 2818 return (ENOMEM); 2819 } else { 2820 m_freem(*mp); 2821 n = *mp = m; 2822 } 2823 } 2824 2825 /* 2826 * Determine where frame payload starts. 2827 * Jump over vlan headers if already present, 2828 * helpful for QinQ too. 2829 */ 2830 if (__predict_false(m->m_len < sizeof(*eh))) { 2831 txq->ift_pullups++; 2832 if (__predict_false((m = m_pullup(m, sizeof(*eh))) == NULL)) 2833 return (ENOMEM); 2834 } 2835 eh = mtod(m, struct ether_vlan_header *); 2836 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) { 2837 pi->ipi_etype = ntohs(eh->evl_proto); 2838 pi->ipi_ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 2839 } else { 2840 pi->ipi_etype = ntohs(eh->evl_encap_proto); 2841 pi->ipi_ehdrlen = ETHER_HDR_LEN; 2842 } 2843 2844 switch (pi->ipi_etype) { 2845#ifdef INET 2846 case ETHERTYPE_IP: 2847 { 2848 struct ip *ip = NULL; 2849 struct tcphdr *th = NULL; 2850 int minthlen; 2851 2852 minthlen = min(m->m_pkthdr.len, pi->ipi_ehdrlen + sizeof(*ip) + sizeof(*th)); 2853 if (__predict_false(m->m_len < minthlen)) { 2854 /* 2855 * if this code bloat is causing too much of a hit 2856 * move it to a separate function and mark it noinline 2857 */ 2858 if (m->m_len == pi->ipi_ehdrlen) { 2859 n = m->m_next; 2860 MPASS(n); 2861 if (n->m_len >= sizeof(*ip)) { 2862 ip = (struct ip *)n->m_data; 2863 if (n->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 2864 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 2865 } else { 2866 txq->ift_pullups++; 2867 if (__predict_false((m = m_pullup(m, minthlen)) == NULL)) 2868 return (ENOMEM); 2869 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 2870 } 2871 } else { 2872 txq->ift_pullups++; 2873 if (__predict_false((m = m_pullup(m, minthlen)) == NULL)) 2874 return (ENOMEM); 2875 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 2876 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 2877 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 2878 } 2879 } else { 2880 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 2881 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 2882 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 2883 } 2884 pi->ipi_ip_hlen = ip->ip_hl << 2; 2885 pi->ipi_ipproto = ip->ip_p; 2886 pi->ipi_flags |= IPI_TX_IPV4; 2887 2888 /* TCP checksum offload may require TCP header length */ 2889 if (IS_TX_OFFLOAD4(pi)) { 2890 if (__predict_true(pi->ipi_ipproto == IPPROTO_TCP)) { 2891 if (__predict_false(th == NULL)) { 2892 txq->ift_pullups++; 2893 if (__predict_false((m = m_pullup(m, (ip->ip_hl << 2) + sizeof(*th))) == NULL)) 2894 return (ENOMEM); 2895 th = (struct tcphdr *)((caddr_t)ip + pi->ipi_ip_hlen); 2896 } 2897 pi->ipi_tcp_hflags = th->th_flags; 2898 pi->ipi_tcp_hlen = th->th_off << 2; 2899 pi->ipi_tcp_seq = th->th_seq; 2900 } 2901 if (IS_TSO4(pi)) { 2902 if (__predict_false(ip->ip_p != IPPROTO_TCP)) 2903 return (ENXIO); 2904 /* 2905 * TSO always requires hardware checksum offload. 2906 */ 2907 pi->ipi_csum_flags |= (CSUM_IP_TCP | CSUM_IP); 2908 th->th_sum = in_pseudo(ip->ip_src.s_addr, 2909 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 2910 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz; 2911 if (sctx->isc_flags & IFLIB_TSO_INIT_IP) { 2912 ip->ip_sum = 0; 2913 ip->ip_len = htons(pi->ipi_ip_hlen + pi->ipi_tcp_hlen + pi->ipi_tso_segsz); 2914 } 2915 } 2916 } 2917 if ((sctx->isc_flags & IFLIB_NEED_ZERO_CSUM) && (pi->ipi_csum_flags & CSUM_IP)) 2918 ip->ip_sum = 0; 2919 2920 break; 2921 } 2922#endif 2923#ifdef INET6 2924 case ETHERTYPE_IPV6: 2925 { 2926 struct ip6_hdr *ip6 = (struct ip6_hdr *)(m->m_data + pi->ipi_ehdrlen); 2927 struct tcphdr *th; 2928 pi->ipi_ip_hlen = sizeof(struct ip6_hdr); 2929 2930 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) { 2931 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) == NULL)) 2932 return (ENOMEM); 2933 } 2934 th = (struct tcphdr *)((caddr_t)ip6 + pi->ipi_ip_hlen); 2935 2936 /* XXX-BZ this will go badly in case of ext hdrs. */ 2937 pi->ipi_ipproto = ip6->ip6_nxt; 2938 pi->ipi_flags |= IPI_TX_IPV6; 2939 2940 /* TCP checksum offload may require TCP header length */ 2941 if (IS_TX_OFFLOAD6(pi)) { 2942 if (pi->ipi_ipproto == IPPROTO_TCP) { 2943 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) { 2944 txq->ift_pullups++; 2945 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) == NULL)) 2946 return (ENOMEM); 2947 } 2948 pi->ipi_tcp_hflags = th->th_flags; 2949 pi->ipi_tcp_hlen = th->th_off << 2; 2950 pi->ipi_tcp_seq = th->th_seq; 2951 } 2952 if (IS_TSO6(pi)) { 2953 if (__predict_false(ip6->ip6_nxt != IPPROTO_TCP)) 2954 return (ENXIO); 2955 /* 2956 * TSO always requires hardware checksum offload. 2957 */ 2958 pi->ipi_csum_flags |= CSUM_IP6_TCP; 2959 th->th_sum = in6_cksum_pseudo(ip6, 0, IPPROTO_TCP, 0); 2960 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz; 2961 } 2962 } 2963 break; 2964 } 2965#endif 2966 default: 2967 pi->ipi_csum_flags &= ~CSUM_OFFLOAD; 2968 pi->ipi_ip_hlen = 0; 2969 break; 2970 } 2971 *mp = m; 2972 2973 return (0); 2974} 2975 2976static __noinline struct mbuf * 2977collapse_pkthdr(struct mbuf *m0) 2978{ 2979 struct mbuf *m, *m_next, *tmp; 2980 2981 m = m0; 2982 m_next = m->m_next; 2983 while (m_next != NULL && m_next->m_len == 0) { 2984 m = m_next; 2985 m->m_next = NULL; 2986 m_free(m); 2987 m_next = m_next->m_next; 2988 } 2989 m = m0; 2990 m->m_next = m_next; 2991 if ((m_next->m_flags & M_EXT) == 0) { 2992 m = m_defrag(m, M_NOWAIT); 2993 } else { 2994 tmp = m_next->m_next; 2995 memcpy(m_next, m, MPKTHSIZE); 2996 m = m_next; 2997 m->m_next = tmp; 2998 } 2999 return (m); 3000} 3001 3002/* 3003 * If dodgy hardware rejects the scatter gather chain we've handed it 3004 * we'll need to remove the mbuf chain from ifsg_m[] before we can add the 3005 * m_defrag'd mbufs 3006 */ 3007static __noinline struct mbuf * 3008iflib_remove_mbuf(iflib_txq_t txq) 3009{ 3010 int ntxd, i, pidx; 3011 struct mbuf *m, *mh, **ifsd_m; 3012 3013 pidx = txq->ift_pidx; 3014 ifsd_m = txq->ift_sds.ifsd_m; 3015 ntxd = txq->ift_size; 3016 mh = m = ifsd_m[pidx]; 3017 ifsd_m[pidx] = NULL; 3018#if MEMORY_LOGGING 3019 txq->ift_dequeued++; 3020#endif 3021 i = 1; 3022 3023 while (m) { 3024 ifsd_m[(pidx + i) & (ntxd -1)] = NULL; 3025#if MEMORY_LOGGING 3026 txq->ift_dequeued++; 3027#endif 3028 m = m->m_next; 3029 i++; 3030 } 3031 return (mh); 3032} 3033 3034static int 3035iflib_busdma_load_mbuf_sg(iflib_txq_t txq, bus_dma_tag_t tag, bus_dmamap_t map, 3036 struct mbuf **m0, bus_dma_segment_t *segs, int *nsegs, 3037 int max_segs, int flags) 3038{ 3039 if_ctx_t ctx; 3040 if_shared_ctx_t sctx; 3041 if_softc_ctx_t scctx; 3042 int i, next, pidx, err, ntxd, count; 3043 struct mbuf *m, *tmp, **ifsd_m; 3044 3045 m = *m0; 3046 3047 /* 3048 * Please don't ever do this 3049 */ 3050 if (__predict_false(m->m_len == 0)) 3051 *m0 = m = collapse_pkthdr(m); 3052 3053 ctx = txq->ift_ctx; 3054 sctx = ctx->ifc_sctx; 3055 scctx = &ctx->ifc_softc_ctx; 3056 ifsd_m = txq->ift_sds.ifsd_m; 3057 ntxd = txq->ift_size; 3058 pidx = txq->ift_pidx; 3059 if (map != NULL) { 3060 uint8_t *ifsd_flags = txq->ift_sds.ifsd_flags; 3061 3062 err = bus_dmamap_load_mbuf_sg(tag, map, 3063 *m0, segs, nsegs, BUS_DMA_NOWAIT); 3064 if (err) 3065 return (err); 3066 ifsd_flags[pidx] |= TX_SW_DESC_MAPPED; 3067 count = 0; 3068 m = *m0; 3069 do { 3070 if (__predict_false(m->m_len <= 0)) { 3071 tmp = m; 3072 m = m->m_next; 3073 tmp->m_next = NULL; 3074 m_free(tmp); 3075 continue; 3076 } 3077 m = m->m_next; 3078 count++; 3079 } while (m != NULL); 3080 if (count > *nsegs) { 3081 ifsd_m[pidx] = *m0; 3082 ifsd_m[pidx]->m_flags |= M_TOOBIG; 3083 return (0); 3084 } 3085 m = *m0; 3086 count = 0; 3087 do { 3088 next = (pidx + count) & (ntxd-1); 3089 MPASS(ifsd_m[next] == NULL); 3090 ifsd_m[next] = m; 3091 count++; 3092 tmp = m; 3093 m = m->m_next; 3094 } while (m != NULL); 3095 } else { 3096 int buflen, sgsize, maxsegsz, max_sgsize; 3097 vm_offset_t vaddr; 3098 vm_paddr_t curaddr; 3099 3100 count = i = 0; 3101 m = *m0; 3102 if (m->m_pkthdr.csum_flags & CSUM_TSO) 3103 maxsegsz = scctx->isc_tx_tso_segsize_max; 3104 else 3105 maxsegsz = sctx->isc_tx_maxsegsize; 3106 3107 do { 3108 if (__predict_false(m->m_len <= 0)) { 3109 tmp = m; 3110 m = m->m_next; 3111 tmp->m_next = NULL; 3112 m_free(tmp); 3113 continue; 3114 } 3115 buflen = m->m_len; 3116 vaddr = (vm_offset_t)m->m_data; 3117 /* 3118 * see if we can't be smarter about physically 3119 * contiguous mappings 3120 */ 3121 next = (pidx + count) & (ntxd-1); 3122 MPASS(ifsd_m[next] == NULL); 3123#if MEMORY_LOGGING 3124 txq->ift_enqueued++; 3125#endif 3126 ifsd_m[next] = m; 3127 while (buflen > 0) { 3128 if (i >= max_segs) 3129 goto err; 3130 max_sgsize = MIN(buflen, maxsegsz); 3131 curaddr = pmap_kextract(vaddr); 3132 sgsize = PAGE_SIZE - (curaddr & PAGE_MASK); 3133 sgsize = MIN(sgsize, max_sgsize); 3134 segs[i].ds_addr = curaddr; 3135 segs[i].ds_len = sgsize; 3136 vaddr += sgsize; 3137 buflen -= sgsize; 3138 i++; 3139 } 3140 count++; 3141 tmp = m; 3142 m = m->m_next; 3143 } while (m != NULL); 3144 *nsegs = i; 3145 } 3146 return (0); 3147err: 3148 *m0 = iflib_remove_mbuf(txq); 3149 return (EFBIG); 3150} 3151 3152static inline caddr_t 3153calc_next_txd(iflib_txq_t txq, int cidx, uint8_t qid) 3154{ 3155 qidx_t size; 3156 int ntxd; 3157 caddr_t start, end, cur, next; 3158 3159 ntxd = txq->ift_size; 3160 size = txq->ift_txd_size[qid]; 3161 start = txq->ift_ifdi[qid].idi_vaddr; 3162 3163 if (__predict_false(size == 0)) 3164 return (start); 3165 cur = start + size*cidx; 3166 end = start + size*ntxd; 3167 next = CACHE_PTR_NEXT(cur); 3168 return (next < end ? next : start); 3169} 3170 3171/* 3172 * Pad an mbuf to ensure a minimum ethernet frame size. 3173 * min_frame_size is the frame size (less CRC) to pad the mbuf to 3174 */ 3175static __noinline int 3176iflib_ether_pad(device_t dev, struct mbuf **m_head, uint16_t min_frame_size) 3177{ 3178 /* 3179 * 18 is enough bytes to pad an ARP packet to 46 bytes, and 3180 * and ARP message is the smallest common payload I can think of 3181 */ 3182 static char pad[18]; /* just zeros */ 3183 int n; 3184 struct mbuf *new_head; 3185 3186 if (!M_WRITABLE(*m_head)) { 3187 new_head = m_dup(*m_head, M_NOWAIT); 3188 if (new_head == NULL) { 3189 m_freem(*m_head); 3190 device_printf(dev, "cannot pad short frame, m_dup() failed"); 3191 DBG_COUNTER_INC(encap_pad_mbuf_fail); 3192 return ENOMEM; 3193 } 3194 m_freem(*m_head); 3195 *m_head = new_head; 3196 } 3197 3198 for (n = min_frame_size - (*m_head)->m_pkthdr.len; 3199 n > 0; n -= sizeof(pad)) 3200 if (!m_append(*m_head, min(n, sizeof(pad)), pad)) 3201 break; 3202 3203 if (n > 0) { 3204 m_freem(*m_head); 3205 device_printf(dev, "cannot pad short frame\n"); 3206 DBG_COUNTER_INC(encap_pad_mbuf_fail); 3207 return (ENOBUFS); 3208 } 3209 3210 return 0; 3211} 3212 3213static int 3214iflib_encap(iflib_txq_t txq, struct mbuf **m_headp) 3215{ 3216 if_ctx_t ctx; 3217 if_shared_ctx_t sctx; 3218 if_softc_ctx_t scctx; 3219 bus_dma_segment_t *segs; 3220 struct mbuf *m_head; 3221 void *next_txd; 3222 bus_dmamap_t map; 3223 struct if_pkt_info pi; 3224 int remap = 0; 3225 int err, nsegs, ndesc, max_segs, pidx, cidx, next, ntxd; 3226 bus_dma_tag_t desc_tag; 3227 3228 segs = txq->ift_segs; 3229 ctx = txq->ift_ctx; 3230 sctx = ctx->ifc_sctx; 3231 scctx = &ctx->ifc_softc_ctx; 3232 segs = txq->ift_segs; 3233 ntxd = txq->ift_size; 3234 m_head = *m_headp; 3235 map = NULL; 3236 3237 /* 3238 * If we're doing TSO the next descriptor to clean may be quite far ahead 3239 */ 3240 cidx = txq->ift_cidx; 3241 pidx = txq->ift_pidx; 3242 if (ctx->ifc_flags & IFC_PREFETCH) { 3243 next = (cidx + CACHE_PTR_INCREMENT) & (ntxd-1); 3244 if (!(ctx->ifc_flags & IFLIB_HAS_TXCQ)) { 3245 next_txd = calc_next_txd(txq, cidx, 0); 3246 prefetch(next_txd); 3247 } 3248 3249 /* prefetch the next cache line of mbuf pointers and flags */ 3250 prefetch(&txq->ift_sds.ifsd_m[next]); 3251 if (txq->ift_sds.ifsd_map != NULL) { 3252 prefetch(&txq->ift_sds.ifsd_map[next]); 3253 next = (cidx + CACHE_LINE_SIZE) & (ntxd-1); 3254 prefetch(&txq->ift_sds.ifsd_flags[next]); 3255 } 3256 } else if (txq->ift_sds.ifsd_map != NULL) 3257 map = txq->ift_sds.ifsd_map[pidx]; 3258 3259 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) { 3260 desc_tag = txq->ift_tso_desc_tag; 3261 max_segs = scctx->isc_tx_tso_segments_max; 3262 } else { 3263 desc_tag = txq->ift_desc_tag; 3264 max_segs = scctx->isc_tx_nsegments; 3265 } 3266 if ((sctx->isc_flags & IFLIB_NEED_ETHER_PAD) && 3267 __predict_false(m_head->m_pkthdr.len < scctx->isc_min_frame_size)) { 3268 err = iflib_ether_pad(ctx->ifc_dev, m_headp, scctx->isc_min_frame_size); 3269 if (err) 3270 return err; 3271 } 3272 m_head = *m_headp; 3273 3274 pkt_info_zero(&pi); 3275 pi.ipi_mflags = (m_head->m_flags & (M_VLANTAG|M_BCAST|M_MCAST)); 3276 pi.ipi_pidx = pidx; 3277 pi.ipi_qsidx = txq->ift_id; 3278 pi.ipi_len = m_head->m_pkthdr.len; 3279 pi.ipi_csum_flags = m_head->m_pkthdr.csum_flags; 3280 pi.ipi_vtag = (m_head->m_flags & M_VLANTAG) ? m_head->m_pkthdr.ether_vtag : 0; 3281 3282 /* deliberate bitwise OR to make one condition */ 3283 if (__predict_true((pi.ipi_csum_flags | pi.ipi_vtag))) { 3284 if (__predict_false((err = iflib_parse_header(txq, &pi, m_headp)) != 0)) 3285 return (err); 3286 m_head = *m_headp; 3287 } 3288 3289retry: 3290 err = iflib_busdma_load_mbuf_sg(txq, desc_tag, map, m_headp, segs, &nsegs, max_segs, BUS_DMA_NOWAIT); 3291defrag: 3292 if (__predict_false(err)) { 3293 switch (err) { 3294 case EFBIG: 3295 /* try collapse once and defrag once */ 3296 if (remap == 0) { 3297 m_head = m_collapse(*m_headp, M_NOWAIT, max_segs); 3298 /* try defrag if collapsing fails */ 3299 if (m_head == NULL) 3300 remap++; 3301 } 3302 if (remap == 1) 3303 m_head = m_defrag(*m_headp, M_NOWAIT); 3304 /* 3305 * remap should never be >1 unless bus_dmamap_load_mbuf_sg 3306 * failed to map an mbuf that was run through m_defrag 3307 */ 3308 MPASS(remap <= 1); 3309 if (__predict_false(m_head == NULL || remap > 1)) 3310 goto defrag_failed; 3311 remap++; 3312 txq->ift_mbuf_defrag++; 3313 *m_headp = m_head; 3314 goto retry; 3315 break; 3316 case ENOMEM: 3317 txq->ift_no_tx_dma_setup++; 3318 break; 3319 default: 3320 txq->ift_no_tx_dma_setup++; 3321 m_freem(*m_headp); 3322 DBG_COUNTER_INC(tx_frees); 3323 *m_headp = NULL; 3324 break; 3325 } 3326 txq->ift_map_failed++; 3327 DBG_COUNTER_INC(encap_load_mbuf_fail); 3328 return (err); 3329 } 3330 3331 /* 3332 * XXX assumes a 1 to 1 relationship between segments and 3333 * descriptors - this does not hold true on all drivers, e.g. 3334 * cxgb 3335 */ 3336 if (__predict_false(nsegs + 2 > TXQ_AVAIL(txq))) { 3337 txq->ift_no_desc_avail++; 3338 if (map != NULL) 3339 bus_dmamap_unload(desc_tag, map); 3340 DBG_COUNTER_INC(encap_txq_avail_fail); 3341 if ((txq->ift_task.gt_task.ta_flags & TASK_ENQUEUED) == 0) 3342 GROUPTASK_ENQUEUE(&txq->ift_task); 3343 return (ENOBUFS); 3344 } 3345 /* 3346 * On Intel cards we can greatly reduce the number of TX interrupts 3347 * we see by only setting report status on every Nth descriptor. 3348 * However, this also means that the driver will need to keep track 3349 * of the descriptors that RS was set on to check them for the DD bit. 3350 */ 3351 txq->ift_rs_pending += nsegs + 1; 3352 if (txq->ift_rs_pending > TXQ_MAX_RS_DEFERRED(txq) || 3353 iflib_no_tx_batch || (TXQ_AVAIL(txq) - nsegs) <= MAX_TX_DESC(ctx) + 2) { 3354 pi.ipi_flags |= IPI_TX_INTR; 3355 txq->ift_rs_pending = 0; 3356 } 3357 3358 pi.ipi_segs = segs; 3359 pi.ipi_nsegs = nsegs; 3360 3361 MPASS(pidx >= 0 && pidx < txq->ift_size); 3362#ifdef PKT_DEBUG 3363 print_pkt(&pi); 3364#endif 3365 if (map != NULL) 3366 bus_dmamap_sync(desc_tag, map, BUS_DMASYNC_PREWRITE); 3367 if ((err = ctx->isc_txd_encap(ctx->ifc_softc, &pi)) == 0) { 3368 if (map != NULL) 3369 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 3370 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3371 DBG_COUNTER_INC(tx_encap); 3372 MPASS(pi.ipi_new_pidx < txq->ift_size); 3373 3374 ndesc = pi.ipi_new_pidx - pi.ipi_pidx; 3375 if (pi.ipi_new_pidx < pi.ipi_pidx) { 3376 ndesc += txq->ift_size; 3377 txq->ift_gen = 1; 3378 } 3379 /* 3380 * drivers can need as many as 3381 * two sentinels 3382 */ 3383 MPASS(ndesc <= pi.ipi_nsegs + 2); 3384 MPASS(pi.ipi_new_pidx != pidx); 3385 MPASS(ndesc > 0); 3386 txq->ift_in_use += ndesc; 3387 3388 /* 3389 * We update the last software descriptor again here because there may 3390 * be a sentinel and/or there may be more mbufs than segments 3391 */ 3392 txq->ift_pidx = pi.ipi_new_pidx; 3393 txq->ift_npending += pi.ipi_ndescs; 3394 } else { 3395 *m_headp = m_head = iflib_remove_mbuf(txq); 3396 if (err == EFBIG) { 3397 txq->ift_txd_encap_efbig++; 3398 if (remap < 2) { 3399 remap = 1; 3400 goto defrag; 3401 } 3402 } 3403 DBG_COUNTER_INC(encap_txd_encap_fail); 3404 goto defrag_failed; 3405 } 3406 return (err); 3407 3408defrag_failed: 3409 txq->ift_mbuf_defrag_failed++; 3410 txq->ift_map_failed++; 3411 m_freem(*m_headp); 3412 DBG_COUNTER_INC(tx_frees); 3413 *m_headp = NULL; 3414 return (ENOMEM); 3415} 3416 3417static void 3418iflib_tx_desc_free(iflib_txq_t txq, int n) 3419{ 3420 int hasmap; 3421 uint32_t qsize, cidx, mask, gen; 3422 struct mbuf *m, **ifsd_m; 3423 uint8_t *ifsd_flags; 3424 bus_dmamap_t *ifsd_map; 3425 bool do_prefetch; 3426 3427 cidx = txq->ift_cidx; 3428 gen = txq->ift_gen; 3429 qsize = txq->ift_size; 3430 mask = qsize-1; 3431 hasmap = txq->ift_sds.ifsd_map != NULL; 3432 ifsd_flags = txq->ift_sds.ifsd_flags; 3433 ifsd_m = txq->ift_sds.ifsd_m; 3434 ifsd_map = txq->ift_sds.ifsd_map; 3435 do_prefetch = (txq->ift_ctx->ifc_flags & IFC_PREFETCH); 3436 3437 while (n--) { 3438 if (do_prefetch) { 3439 prefetch(ifsd_m[(cidx + 3) & mask]); 3440 prefetch(ifsd_m[(cidx + 4) & mask]); 3441 } 3442 if (ifsd_m[cidx] != NULL) { 3443 prefetch(&ifsd_m[(cidx + CACHE_PTR_INCREMENT) & mask]); 3444 prefetch(&ifsd_flags[(cidx + CACHE_PTR_INCREMENT) & mask]); 3445 if (hasmap && (ifsd_flags[cidx] & TX_SW_DESC_MAPPED)) { 3446 /* 3447 * does it matter if it's not the TSO tag? If so we'll 3448 * have to add the type to flags 3449 */ 3450 bus_dmamap_unload(txq->ift_desc_tag, ifsd_map[cidx]); 3451 ifsd_flags[cidx] &= ~TX_SW_DESC_MAPPED; 3452 } 3453 if ((m = ifsd_m[cidx]) != NULL) { 3454 /* XXX we don't support any drivers that batch packets yet */ 3455 MPASS(m->m_nextpkt == NULL); 3456 /* if the number of clusters exceeds the number of segments 3457 * there won't be space on the ring to save a pointer to each 3458 * cluster so we simply free the list here 3459 */ 3460 if (m->m_flags & M_TOOBIG) { 3461 m_freem(m); 3462 } else { 3463 m_free(m); 3464 } 3465 ifsd_m[cidx] = NULL; 3466#if MEMORY_LOGGING 3467 txq->ift_dequeued++; 3468#endif 3469 DBG_COUNTER_INC(tx_frees); 3470 } 3471 } 3472 if (__predict_false(++cidx == qsize)) { 3473 cidx = 0; 3474 gen = 0; 3475 } 3476 } 3477 txq->ift_cidx = cidx; 3478 txq->ift_gen = gen; 3479} 3480 3481static __inline int 3482iflib_completed_tx_reclaim(iflib_txq_t txq, int thresh) 3483{ 3484 int reclaim; 3485 if_ctx_t ctx = txq->ift_ctx; 3486 3487 KASSERT(thresh >= 0, ("invalid threshold to reclaim")); 3488 MPASS(thresh /*+ MAX_TX_DESC(txq->ift_ctx) */ < txq->ift_size); 3489 3490 /* 3491 * Need a rate-limiting check so that this isn't called every time 3492 */ 3493 iflib_tx_credits_update(ctx, txq); 3494 reclaim = DESC_RECLAIMABLE(txq); 3495 3496 if (reclaim <= thresh /* + MAX_TX_DESC(txq->ift_ctx) */) { 3497#ifdef INVARIANTS 3498 if (iflib_verbose_debug) { 3499 printf("%s processed=%ju cleaned=%ju tx_nsegments=%d reclaim=%d thresh=%d\n", __FUNCTION__, 3500 txq->ift_processed, txq->ift_cleaned, txq->ift_ctx->ifc_softc_ctx.isc_tx_nsegments, 3501 reclaim, thresh); 3502 3503 } 3504#endif 3505 return (0); 3506 } 3507 iflib_tx_desc_free(txq, reclaim); 3508 txq->ift_cleaned += reclaim; 3509 txq->ift_in_use -= reclaim; 3510 3511 return (reclaim); 3512} 3513 3514static struct mbuf ** 3515_ring_peek_one(struct ifmp_ring *r, int cidx, int offset, int remaining) 3516{ 3517 int next, size; 3518 struct mbuf **items; 3519 3520 size = r->size; 3521 next = (cidx + CACHE_PTR_INCREMENT) & (size-1); 3522 items = __DEVOLATILE(struct mbuf **, &r->items[0]); 3523 3524 prefetch(items[(cidx + offset) & (size-1)]); 3525 if (remaining > 1) { 3526 prefetch2cachelines(&items[next]); 3527 prefetch2cachelines(items[(cidx + offset + 1) & (size-1)]); 3528 prefetch2cachelines(items[(cidx + offset + 2) & (size-1)]); 3529 prefetch2cachelines(items[(cidx + offset + 3) & (size-1)]); 3530 } 3531 return (__DEVOLATILE(struct mbuf **, &r->items[(cidx + offset) & (size-1)])); 3532} 3533 3534static void 3535iflib_txq_check_drain(iflib_txq_t txq, int budget) 3536{ 3537 3538 ifmp_ring_check_drainage(txq->ift_br, budget); 3539} 3540 3541static uint32_t 3542iflib_txq_can_drain(struct ifmp_ring *r) 3543{ 3544 iflib_txq_t txq = r->cookie; 3545 if_ctx_t ctx = txq->ift_ctx; 3546 3547 return ((TXQ_AVAIL(txq) > MAX_TX_DESC(ctx) + 2) || 3548 ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, false)); 3549} 3550 3551static uint32_t 3552iflib_txq_drain(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx) 3553{ 3554 iflib_txq_t txq = r->cookie; 3555 if_ctx_t ctx = txq->ift_ctx; 3556 struct ifnet *ifp = ctx->ifc_ifp; 3557 struct mbuf **mp, *m; 3558 int i, count, consumed, pkt_sent, bytes_sent, mcast_sent, avail; 3559 int reclaimed, err, in_use_prev, desc_used; 3560 bool do_prefetch, ring, rang; 3561 3562 if (__predict_false(!(if_getdrvflags(ifp) & IFF_DRV_RUNNING) || 3563 !LINK_ACTIVE(ctx))) { 3564 DBG_COUNTER_INC(txq_drain_notready); 3565 return (0); 3566 } 3567 reclaimed = iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx)); 3568 rang = iflib_txd_db_check(ctx, txq, reclaimed, txq->ift_in_use); 3569 avail = IDXDIFF(pidx, cidx, r->size); 3570 if (__predict_false(ctx->ifc_flags & IFC_QFLUSH)) { 3571 DBG_COUNTER_INC(txq_drain_flushing); 3572 for (i = 0; i < avail; i++) { 3573 m_free(r->items[(cidx + i) & (r->size-1)]); 3574 r->items[(cidx + i) & (r->size-1)] = NULL; 3575 } 3576 return (avail); 3577 } 3578 3579 if (__predict_false(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE)) { 3580 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3581 CALLOUT_LOCK(txq); 3582 callout_stop(&txq->ift_timer); 3583 CALLOUT_UNLOCK(txq); 3584 DBG_COUNTER_INC(txq_drain_oactive); 3585 return (0); 3586 } 3587 if (reclaimed) 3588 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3589 consumed = mcast_sent = bytes_sent = pkt_sent = 0; 3590 count = MIN(avail, TX_BATCH_SIZE); 3591#ifdef INVARIANTS 3592 if (iflib_verbose_debug) 3593 printf("%s avail=%d ifc_flags=%x txq_avail=%d ", __FUNCTION__, 3594 avail, ctx->ifc_flags, TXQ_AVAIL(txq)); 3595#endif 3596 do_prefetch = (ctx->ifc_flags & IFC_PREFETCH); 3597 avail = TXQ_AVAIL(txq); 3598 for (desc_used = i = 0; i < count && avail > MAX_TX_DESC(ctx) + 2; i++) { 3599 int pidx_prev, rem = do_prefetch ? count - i : 0; 3600 3601 mp = _ring_peek_one(r, cidx, i, rem); 3602 MPASS(mp != NULL && *mp != NULL); 3603 if (__predict_false(*mp == (struct mbuf *)txq)) { 3604 consumed++; 3605 reclaimed++; 3606 continue; 3607 } 3608 in_use_prev = txq->ift_in_use; 3609 pidx_prev = txq->ift_pidx; 3610 err = iflib_encap(txq, mp); 3611 if (__predict_false(err)) { 3612 DBG_COUNTER_INC(txq_drain_encapfail); 3613 /* no room - bail out */ 3614 if (err == ENOBUFS) 3615 break; 3616 consumed++; 3617 DBG_COUNTER_INC(txq_drain_encapfail); 3618 /* we can't send this packet - skip it */ 3619 continue; 3620 } 3621 consumed++; 3622 pkt_sent++; 3623 m = *mp; 3624 DBG_COUNTER_INC(tx_sent); 3625 bytes_sent += m->m_pkthdr.len; 3626 mcast_sent += !!(m->m_flags & M_MCAST); 3627 avail = TXQ_AVAIL(txq); 3628 3629 txq->ift_db_pending += (txq->ift_in_use - in_use_prev); 3630 desc_used += (txq->ift_in_use - in_use_prev); 3631 ETHER_BPF_MTAP(ifp, m); 3632 if (__predict_false(!(ifp->if_drv_flags & IFF_DRV_RUNNING))) 3633 break; 3634 rang = iflib_txd_db_check(ctx, txq, false, in_use_prev); 3635 } 3636 3637 /* deliberate use of bitwise or to avoid gratuitous short-circuit */ 3638 ring = rang ? false : (iflib_min_tx_latency | err) || (TXQ_AVAIL(txq) < MAX_TX_DESC(ctx)); 3639 iflib_txd_db_check(ctx, txq, ring, txq->ift_in_use); 3640 if_inc_counter(ifp, IFCOUNTER_OBYTES, bytes_sent); 3641 if_inc_counter(ifp, IFCOUNTER_OPACKETS, pkt_sent); 3642 if (mcast_sent) 3643 if_inc_counter(ifp, IFCOUNTER_OMCASTS, mcast_sent); 3644#ifdef INVARIANTS 3645 if (iflib_verbose_debug) 3646 printf("consumed=%d\n", consumed); 3647#endif 3648 return (consumed); 3649} 3650 3651static uint32_t 3652iflib_txq_drain_always(struct ifmp_ring *r) 3653{ 3654 return (1); 3655} 3656 3657static uint32_t 3658iflib_txq_drain_free(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx) 3659{ 3660 int i, avail; 3661 struct mbuf **mp; 3662 iflib_txq_t txq; 3663 3664 txq = r->cookie; 3665 3666 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3667 CALLOUT_LOCK(txq); 3668 callout_stop(&txq->ift_timer); 3669 CALLOUT_UNLOCK(txq); 3670 3671 avail = IDXDIFF(pidx, cidx, r->size); 3672 for (i = 0; i < avail; i++) { 3673 mp = _ring_peek_one(r, cidx, i, avail - i); 3674 if (__predict_false(*mp == (struct mbuf *)txq)) 3675 continue; 3676 m_freem(*mp); 3677 } 3678 MPASS(ifmp_ring_is_stalled(r) == 0); 3679 return (avail); 3680} 3681 3682static void 3683iflib_ifmp_purge(iflib_txq_t txq) 3684{ 3685 struct ifmp_ring *r; 3686 3687 r = txq->ift_br; 3688 r->drain = iflib_txq_drain_free; 3689 r->can_drain = iflib_txq_drain_always; 3690 3691 ifmp_ring_check_drainage(r, r->size); 3692 3693 r->drain = iflib_txq_drain; 3694 r->can_drain = iflib_txq_can_drain; 3695} 3696 3697static void 3698_task_fn_tx(void *context) 3699{ 3700 iflib_txq_t txq = context; 3701 if_ctx_t ctx = txq->ift_ctx; 3702 struct ifnet *ifp = ctx->ifc_ifp; 3703 int rc; 3704 3705#ifdef IFLIB_DIAGNOSTICS 3706 txq->ift_cpu_exec_count[curcpu]++; 3707#endif 3708 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) 3709 return; 3710 if (if_getcapenable(ifp) & IFCAP_NETMAP) { 3711 if (ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, false)) 3712 netmap_tx_irq(ifp, txq->ift_id); 3713 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id); 3714 return; 3715 } 3716 if (txq->ift_db_pending) 3717 ifmp_ring_enqueue(txq->ift_br, (void **)&txq, 1, TX_BATCH_SIZE); 3718 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 3719 if (ctx->ifc_flags & IFC_LEGACY) 3720 IFDI_INTR_ENABLE(ctx); 3721 else { 3722 rc = IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id); 3723 KASSERT(rc != ENOTSUP, ("MSI-X support requires queue_intr_enable, but not implemented in driver")); 3724 } 3725} 3726 3727static void 3728_task_fn_rx(void *context) 3729{ 3730 iflib_rxq_t rxq = context; 3731 if_ctx_t ctx = rxq->ifr_ctx; 3732 uint8_t more; 3733 int rc; 3734 uint16_t budget; 3735 3736#ifdef IFLIB_DIAGNOSTICS 3737 rxq->ifr_cpu_exec_count[curcpu]++; 3738#endif 3739 DBG_COUNTER_INC(task_fn_rxs); 3740 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))) 3741 return; 3742#ifdef DEV_NETMAP 3743 if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP) { 3744 u_int work = 0; 3745 if (netmap_rx_irq(ctx->ifc_ifp, rxq->ifr_id, &work)) { 3746 more = 0; 3747 goto skip_rxeof; 3748 } 3749 } 3750#endif 3751 budget = ctx->ifc_sysctl_rx_budget; 3752 if (budget == 0) 3753 budget = 16; /* XXX */ 3754 more = iflib_rxeof(rxq, budget); 3755#ifdef DEV_NETMAP 3756skip_rxeof: 3757#endif 3758 if ((more & IFLIB_RXEOF_MORE) == 0) { 3759 if (ctx->ifc_flags & IFC_LEGACY) 3760 IFDI_INTR_ENABLE(ctx); 3761 else { 3762 DBG_COUNTER_INC(rx_intr_enables); 3763 rc = IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id); 3764 KASSERT(rc != ENOTSUP, ("MSI-X support requires queue_intr_enable, but not implemented in driver")); 3765 } 3766 } 3767 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))) 3768 return; 3769 3770 if (more & IFLIB_RXEOF_MORE) 3771 GROUPTASK_ENQUEUE(&rxq->ifr_task); 3772 else if (more & IFLIB_RXEOF_EMPTY) 3773 callout_reset_curcpu(&rxq->ifr_watchdog, 1, &_task_fn_rx_watchdog, rxq); 3774} 3775 3776static void 3777_task_fn_admin(void *context) 3778{ 3779 if_ctx_t ctx = context; 3780 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 3781 iflib_txq_t txq; 3782 int i; 3783 bool oactive, running, do_reset, do_watchdog, in_detach; 3784 3785 STATE_LOCK(ctx); 3786 running = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING); 3787 oactive = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE); 3788 do_reset = (ctx->ifc_flags & IFC_DO_RESET); 3789 do_watchdog = (ctx->ifc_flags & IFC_DO_WATCHDOG); 3790 in_detach = (ctx->ifc_flags & IFC_IN_DETACH); 3791 ctx->ifc_flags &= ~(IFC_DO_RESET|IFC_DO_WATCHDOG); 3792 STATE_UNLOCK(ctx); 3793 3794 if ((!running & !oactive) && 3795 !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN)) 3796 return; 3797 if (in_detach) 3798 return; 3799 3800 CTX_LOCK(ctx); 3801 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) { 3802 CALLOUT_LOCK(txq); 3803 callout_stop(&txq->ift_timer); 3804 CALLOUT_UNLOCK(txq); 3805 } 3806 if (do_watchdog) { 3807 ctx->ifc_watchdog_events++; 3808 IFDI_WATCHDOG_RESET(ctx); 3809 } 3810 IFDI_UPDATE_ADMIN_STATUS(ctx); 3811 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) 3812 callout_reset_on(&txq->ift_timer, hz/2, iflib_timer, txq, txq->ift_timer.c_cpu); 3813 IFDI_LINK_INTR_ENABLE(ctx); 3814 if (do_reset) 3815 iflib_if_init_locked(ctx); 3816 CTX_UNLOCK(ctx); 3817 3818 if (LINK_ACTIVE(ctx) == 0) 3819 return; 3820 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) 3821 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET); 3822} 3823 3824 3825static void 3826_task_fn_iov(void *context) 3827{ 3828 if_ctx_t ctx = context; 3829 3830 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING) && 3831 !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN)) 3832 return; 3833 3834 CTX_LOCK(ctx); 3835 IFDI_VFLR_HANDLE(ctx); 3836 CTX_UNLOCK(ctx); 3837} 3838 3839static int 3840iflib_sysctl_int_delay(SYSCTL_HANDLER_ARGS) 3841{ 3842 int err; 3843 if_int_delay_info_t info; 3844 if_ctx_t ctx; 3845 3846 info = (if_int_delay_info_t)arg1; 3847 ctx = info->iidi_ctx; 3848 info->iidi_req = req; 3849 info->iidi_oidp = oidp; 3850 CTX_LOCK(ctx); 3851 err = IFDI_SYSCTL_INT_DELAY(ctx, info); 3852 CTX_UNLOCK(ctx); 3853 return (err); 3854} 3855 3856/********************************************************************* 3857 * 3858 * IFNET FUNCTIONS 3859 * 3860 **********************************************************************/ 3861 3862static void 3863iflib_if_init_locked(if_ctx_t ctx) 3864{ 3865 iflib_stop(ctx); 3866 iflib_init_locked(ctx); 3867} 3868 3869 3870static void 3871iflib_if_init(void *arg) 3872{ 3873 if_ctx_t ctx = arg; 3874 3875 CTX_LOCK(ctx); 3876 iflib_if_init_locked(ctx); 3877 CTX_UNLOCK(ctx); 3878} 3879 3880static int 3881iflib_if_transmit(if_t ifp, struct mbuf *m) 3882{ 3883 if_ctx_t ctx = if_getsoftc(ifp); 3884 3885 iflib_txq_t txq; 3886 int err, qidx; 3887 3888 if (__predict_false((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || !LINK_ACTIVE(ctx))) { 3889 DBG_COUNTER_INC(tx_frees); 3890 m_freem(m); 3891 return (ENETDOWN); 3892 } 3893 3894 MPASS(m->m_nextpkt == NULL); 3895 qidx = 0; 3896 if ((NTXQSETS(ctx) > 1) && M_HASHTYPE_GET(m)) 3897 qidx = QIDX(ctx, m); 3898 /* 3899 * XXX calculate buf_ring based on flowid (divvy up bits?) 3900 */ 3901 txq = &ctx->ifc_txqs[qidx]; 3902 3903#ifdef DRIVER_BACKPRESSURE 3904 if (txq->ift_closed) { 3905 while (m != NULL) { 3906 next = m->m_nextpkt; 3907 m->m_nextpkt = NULL; 3908 m_freem(m); 3909 m = next; 3910 } 3911 return (ENOBUFS); 3912 } 3913#endif 3914#ifdef notyet 3915 qidx = count = 0; 3916 mp = marr; 3917 next = m; 3918 do { 3919 count++; 3920 next = next->m_nextpkt; 3921 } while (next != NULL); 3922 3923 if (count > nitems(marr)) 3924 if ((mp = malloc(count*sizeof(struct mbuf *), M_IFLIB, M_NOWAIT)) == NULL) { 3925 /* XXX check nextpkt */ 3926 m_freem(m); 3927 /* XXX simplify for now */ 3928 DBG_COUNTER_INC(tx_frees); 3929 return (ENOBUFS); 3930 } 3931 for (next = m, i = 0; next != NULL; i++) { 3932 mp[i] = next; 3933 next = next->m_nextpkt; 3934 mp[i]->m_nextpkt = NULL; 3935 } 3936#endif 3937 DBG_COUNTER_INC(tx_seen); 3938 err = ifmp_ring_enqueue(txq->ift_br, (void **)&m, 1, TX_BATCH_SIZE); 3939 3940 GROUPTASK_ENQUEUE(&txq->ift_task); 3941 if (err) { 3942 /* support forthcoming later */ 3943#ifdef DRIVER_BACKPRESSURE 3944 txq->ift_closed = TRUE; 3945#endif 3946 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 3947 m_freem(m); 3948 } 3949 3950 return (err); 3951} 3952 3953static void 3954iflib_if_qflush(if_t ifp) 3955{ 3956 if_ctx_t ctx = if_getsoftc(ifp); 3957 iflib_txq_t txq = ctx->ifc_txqs; 3958 int i; 3959 3960 STATE_LOCK(ctx); 3961 ctx->ifc_flags |= IFC_QFLUSH; 3962 STATE_UNLOCK(ctx); 3963 for (i = 0; i < NTXQSETS(ctx); i++, txq++) 3964 while (!(ifmp_ring_is_idle(txq->ift_br) || ifmp_ring_is_stalled(txq->ift_br))) 3965 iflib_txq_check_drain(txq, 0); 3966 STATE_LOCK(ctx); 3967 ctx->ifc_flags &= ~IFC_QFLUSH; 3968 STATE_UNLOCK(ctx); 3969 3970 if_qflush(ifp); 3971} 3972 3973 3974#define IFCAP_FLAGS (IFCAP_TXCSUM_IPV6 | IFCAP_RXCSUM_IPV6 | IFCAP_HWCSUM | IFCAP_LRO | \ 3975 IFCAP_TSO4 | IFCAP_TSO6 | IFCAP_VLAN_HWTAGGING | IFCAP_HWSTATS | \ 3976 IFCAP_VLAN_MTU | IFCAP_VLAN_HWFILTER | IFCAP_VLAN_HWTSO) 3977 3978static int 3979iflib_if_ioctl(if_t ifp, u_long command, caddr_t data) 3980{ 3981 if_ctx_t ctx = if_getsoftc(ifp); 3982 struct ifreq *ifr = (struct ifreq *)data; 3983#if defined(INET) || defined(INET6) 3984 struct ifaddr *ifa = (struct ifaddr *)data; 3985#endif 3986 bool avoid_reset = FALSE; 3987 int err = 0, reinit = 0, bits; 3988 3989 switch (command) { 3990 case SIOCSIFADDR: 3991#ifdef INET 3992 if (ifa->ifa_addr->sa_family == AF_INET) 3993 avoid_reset = TRUE; 3994#endif 3995#ifdef INET6 3996 if (ifa->ifa_addr->sa_family == AF_INET6) 3997 avoid_reset = TRUE; 3998#endif 3999 /* 4000 ** Calling init results in link renegotiation, 4001 ** so we avoid doing it when possible. 4002 */ 4003 if (avoid_reset) { 4004 if_setflagbits(ifp, IFF_UP,0); 4005 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) 4006 reinit = 1; 4007#ifdef INET 4008 if (!(if_getflags(ifp) & IFF_NOARP)) 4009 arp_ifinit(ifp, ifa); 4010#endif 4011 } else 4012 err = ether_ioctl(ifp, command, data); 4013 break; 4014 case SIOCSIFMTU: 4015 CTX_LOCK(ctx); 4016 if (ifr->ifr_mtu == if_getmtu(ifp)) { 4017 CTX_UNLOCK(ctx); 4018 break; 4019 } 4020 bits = if_getdrvflags(ifp); 4021 /* stop the driver and free any clusters before proceeding */ 4022 iflib_stop(ctx); 4023 4024 if ((err = IFDI_MTU_SET(ctx, ifr->ifr_mtu)) == 0) { 4025 STATE_LOCK(ctx); 4026 if (ifr->ifr_mtu > ctx->ifc_max_fl_buf_size) 4027 ctx->ifc_flags |= IFC_MULTISEG; 4028 else 4029 ctx->ifc_flags &= ~IFC_MULTISEG; 4030 STATE_UNLOCK(ctx); 4031 err = if_setmtu(ifp, ifr->ifr_mtu); 4032 } 4033 iflib_init_locked(ctx); 4034 STATE_LOCK(ctx); 4035 if_setdrvflags(ifp, bits); 4036 STATE_UNLOCK(ctx); 4037 CTX_UNLOCK(ctx); 4038 break; 4039 case SIOCSIFFLAGS: 4040 CTX_LOCK(ctx); 4041 if (if_getflags(ifp) & IFF_UP) { 4042 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4043 if ((if_getflags(ifp) ^ ctx->ifc_if_flags) & 4044 (IFF_PROMISC | IFF_ALLMULTI)) { 4045 err = IFDI_PROMISC_SET(ctx, if_getflags(ifp)); 4046 } 4047 } else 4048 reinit = 1; 4049 } else if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4050 iflib_stop(ctx); 4051 } 4052 ctx->ifc_if_flags = if_getflags(ifp); 4053 CTX_UNLOCK(ctx); 4054 break; 4055 case SIOCADDMULTI: 4056 case SIOCDELMULTI: 4057 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4058 CTX_LOCK(ctx); 4059 IFDI_INTR_DISABLE(ctx); 4060 IFDI_MULTI_SET(ctx); 4061 IFDI_INTR_ENABLE(ctx); 4062 CTX_UNLOCK(ctx); 4063 } 4064 break; 4065 case SIOCSIFMEDIA: 4066 CTX_LOCK(ctx); 4067 IFDI_MEDIA_SET(ctx); 4068 CTX_UNLOCK(ctx); 4069 /* falls thru */ 4070 case SIOCGIFMEDIA: 4071 case SIOCGIFXMEDIA: 4072 err = ifmedia_ioctl(ifp, ifr, &ctx->ifc_media, command); 4073 break; 4074 case SIOCGI2C: 4075 { 4076 struct ifi2creq i2c; 4077 4078 err = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c)); 4079 if (err != 0) 4080 break; 4081 if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) { 4082 err = EINVAL; 4083 break; 4084 } 4085 if (i2c.len > sizeof(i2c.data)) { 4086 err = EINVAL; 4087 break; 4088 } 4089 4090 if ((err = IFDI_I2C_REQ(ctx, &i2c)) == 0) 4091 err = copyout(&i2c, ifr_data_get_ptr(ifr), 4092 sizeof(i2c)); 4093 break; 4094 } 4095 case SIOCSIFCAP: 4096 { 4097 int mask, setmask; 4098 4099 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp); 4100 setmask = 0; 4101#ifdef TCP_OFFLOAD 4102 setmask |= mask & (IFCAP_TOE4|IFCAP_TOE6); 4103#endif 4104 setmask |= (mask & IFCAP_FLAGS); 4105 4106 if (setmask & (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6)) 4107 setmask |= (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6); 4108 if ((mask & IFCAP_WOL) && 4109 (if_getcapabilities(ifp) & IFCAP_WOL) != 0) 4110 setmask |= (mask & (IFCAP_WOL_MCAST|IFCAP_WOL_MAGIC)); 4111 if_vlancap(ifp); 4112 /* 4113 * want to ensure that traffic has stopped before we change any of the flags 4114 */ 4115 if (setmask) { 4116 CTX_LOCK(ctx); 4117 bits = if_getdrvflags(ifp); 4118 if (bits & IFF_DRV_RUNNING) 4119 iflib_stop(ctx); 4120 STATE_LOCK(ctx); 4121 if_togglecapenable(ifp, setmask); 4122 STATE_UNLOCK(ctx); 4123 if (bits & IFF_DRV_RUNNING) 4124 iflib_init_locked(ctx); 4125 STATE_LOCK(ctx); 4126 if_setdrvflags(ifp, bits); 4127 STATE_UNLOCK(ctx); 4128 CTX_UNLOCK(ctx); 4129 } 4130 break; 4131 } 4132 case SIOCGPRIVATE_0: 4133 case SIOCSDRVSPEC: 4134 case SIOCGDRVSPEC: 4135 CTX_LOCK(ctx); 4136 err = IFDI_PRIV_IOCTL(ctx, command, data); 4137 CTX_UNLOCK(ctx); 4138 break; 4139 default: 4140 err = ether_ioctl(ifp, command, data); 4141 break; 4142 } 4143 if (reinit) 4144 iflib_if_init(ctx); 4145 return (err); 4146} 4147 4148static uint64_t 4149iflib_if_get_counter(if_t ifp, ift_counter cnt) 4150{ 4151 if_ctx_t ctx = if_getsoftc(ifp); 4152 4153 return (IFDI_GET_COUNTER(ctx, cnt)); 4154} 4155 4156/********************************************************************* 4157 * 4158 * OTHER FUNCTIONS EXPORTED TO THE STACK 4159 * 4160 **********************************************************************/ 4161 4162static void 4163iflib_vlan_register(void *arg, if_t ifp, uint16_t vtag) 4164{ 4165 if_ctx_t ctx = if_getsoftc(ifp); 4166 4167 if ((void *)ctx != arg) 4168 return; 4169 4170 if ((vtag == 0) || (vtag > 4095)) 4171 return; 4172 4173 CTX_LOCK(ctx); 4174 /* Driver may need all untagged packets to be flushed */ 4175 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG)) 4176 iflib_stop(ctx); 4177 IFDI_VLAN_REGISTER(ctx, vtag); 4178 /* Re-init to load the changes, if required */ 4179 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG)) 4180 iflib_init_locked(ctx); 4181 CTX_UNLOCK(ctx); 4182} 4183 4184static void 4185iflib_vlan_unregister(void *arg, if_t ifp, uint16_t vtag) 4186{ 4187 if_ctx_t ctx = if_getsoftc(ifp); 4188 4189 if ((void *)ctx != arg) 4190 return; 4191 4192 if ((vtag == 0) || (vtag > 4095)) 4193 return; 4194 4195 CTX_LOCK(ctx); 4196 /* Driver may need all tagged packets to be flushed */ 4197 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG)) 4198 iflib_stop(ctx); 4199 IFDI_VLAN_UNREGISTER(ctx, vtag); 4200 /* Re-init to load the changes, if required */ 4201 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG)) 4202 iflib_init_locked(ctx); 4203 CTX_UNLOCK(ctx); 4204} 4205 4206static void 4207iflib_led_func(void *arg, int onoff) 4208{ 4209 if_ctx_t ctx = arg; 4210 4211 CTX_LOCK(ctx); 4212 IFDI_LED_FUNC(ctx, onoff); 4213 CTX_UNLOCK(ctx); 4214} 4215 4216/********************************************************************* 4217 * 4218 * BUS FUNCTION DEFINITIONS 4219 * 4220 **********************************************************************/ 4221 4222int 4223iflib_device_probe(device_t dev) 4224{ 4225 pci_vendor_info_t *ent; 4226 4227 uint16_t pci_vendor_id, pci_device_id; 4228 uint16_t pci_subvendor_id, pci_subdevice_id; 4229 uint16_t pci_rev_id; 4230 if_shared_ctx_t sctx; 4231 4232 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC) 4233 return (ENOTSUP); 4234 4235 pci_vendor_id = pci_get_vendor(dev); 4236 pci_device_id = pci_get_device(dev); 4237 pci_subvendor_id = pci_get_subvendor(dev); 4238 pci_subdevice_id = pci_get_subdevice(dev); 4239 pci_rev_id = pci_get_revid(dev); 4240 if (sctx->isc_parse_devinfo != NULL) 4241 sctx->isc_parse_devinfo(&pci_device_id, &pci_subvendor_id, &pci_subdevice_id, &pci_rev_id); 4242 4243 ent = sctx->isc_vendor_info; 4244 while (ent->pvi_vendor_id != 0) { 4245 if (pci_vendor_id != ent->pvi_vendor_id) { 4246 ent++; 4247 continue; 4248 } 4249 if ((pci_device_id == ent->pvi_device_id) && 4250 ((pci_subvendor_id == ent->pvi_subvendor_id) || 4251 (ent->pvi_subvendor_id == 0)) && 4252 ((pci_subdevice_id == ent->pvi_subdevice_id) || 4253 (ent->pvi_subdevice_id == 0)) && 4254 ((pci_rev_id == ent->pvi_rev_id) || 4255 (ent->pvi_rev_id == 0))) { 4256 4257 device_set_desc_copy(dev, ent->pvi_name); 4258 /* this needs to be changed to zero if the bus probing code 4259 * ever stops re-probing on best match because the sctx 4260 * may have its values over written by register calls 4261 * in subsequent probes 4262 */ 4263 return (BUS_PROBE_DEFAULT); 4264 } 4265 ent++; 4266 } 4267 return (ENXIO); 4268} 4269 4270int 4271iflib_device_register(device_t dev, void *sc, if_shared_ctx_t sctx, if_ctx_t *ctxp) 4272{ 4273 int err, rid, msix, msix_bar; 4274 if_ctx_t ctx; 4275 if_t ifp; 4276 if_softc_ctx_t scctx; 4277 int i; 4278 uint16_t main_txq; 4279 uint16_t main_rxq; 4280 4281 4282 ctx = malloc(sizeof(* ctx), M_IFLIB, M_WAITOK|M_ZERO); 4283 4284 if (sc == NULL) { 4285 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO); 4286 device_set_softc(dev, ctx); 4287 ctx->ifc_flags |= IFC_SC_ALLOCATED; 4288 } 4289 4290 ctx->ifc_sctx = sctx; 4291 ctx->ifc_dev = dev; 4292 ctx->ifc_softc = sc; 4293 4294 if ((err = iflib_register(ctx)) != 0) { 4295 device_printf(dev, "iflib_register failed %d\n", err); 4296 return (err); 4297 } 4298 iflib_add_device_sysctl_pre(ctx); 4299 4300 scctx = &ctx->ifc_softc_ctx; 4301 ifp = ctx->ifc_ifp; 4302 ctx->ifc_nhwtxqs = sctx->isc_ntxqs; 4303 4304 /* 4305 * XXX sanity check that ntxd & nrxd are a power of 2 4306 */ 4307 if (ctx->ifc_sysctl_ntxqs != 0) 4308 scctx->isc_ntxqsets = ctx->ifc_sysctl_ntxqs; 4309 if (ctx->ifc_sysctl_nrxqs != 0) 4310 scctx->isc_nrxqsets = ctx->ifc_sysctl_nrxqs; 4311 4312 for (i = 0; i < sctx->isc_ntxqs; i++) { 4313 if (ctx->ifc_sysctl_ntxds[i] != 0) 4314 scctx->isc_ntxd[i] = ctx->ifc_sysctl_ntxds[i]; 4315 else 4316 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i]; 4317 } 4318 4319 for (i = 0; i < sctx->isc_nrxqs; i++) { 4320 if (ctx->ifc_sysctl_nrxds[i] != 0) 4321 scctx->isc_nrxd[i] = ctx->ifc_sysctl_nrxds[i]; 4322 else 4323 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i]; 4324 } 4325 4326 for (i = 0; i < sctx->isc_nrxqs; i++) { 4327 if (scctx->isc_nrxd[i] < sctx->isc_nrxd_min[i]) { 4328 device_printf(dev, "nrxd%d: %d less than nrxd_min %d - resetting to min\n", 4329 i, scctx->isc_nrxd[i], sctx->isc_nrxd_min[i]); 4330 scctx->isc_nrxd[i] = sctx->isc_nrxd_min[i]; 4331 } 4332 if (scctx->isc_nrxd[i] > sctx->isc_nrxd_max[i]) { 4333 device_printf(dev, "nrxd%d: %d greater than nrxd_max %d - resetting to max\n", 4334 i, scctx->isc_nrxd[i], sctx->isc_nrxd_max[i]); 4335 scctx->isc_nrxd[i] = sctx->isc_nrxd_max[i]; 4336 } 4337 } 4338 4339 for (i = 0; i < sctx->isc_ntxqs; i++) { 4340 if (scctx->isc_ntxd[i] < sctx->isc_ntxd_min[i]) { 4341 device_printf(dev, "ntxd%d: %d less than ntxd_min %d - resetting to min\n", 4342 i, scctx->isc_ntxd[i], sctx->isc_ntxd_min[i]); 4343 scctx->isc_ntxd[i] = sctx->isc_ntxd_min[i]; 4344 } 4345 if (scctx->isc_ntxd[i] > sctx->isc_ntxd_max[i]) { 4346 device_printf(dev, "ntxd%d: %d greater than ntxd_max %d - resetting to max\n", 4347 i, scctx->isc_ntxd[i], sctx->isc_ntxd_max[i]); 4348 scctx->isc_ntxd[i] = sctx->isc_ntxd_max[i]; 4349 } 4350 } 4351 4352 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) { 4353 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err); 4354 return (err); 4355 } 4356 _iflib_pre_assert(scctx); 4357 ctx->ifc_txrx = *scctx->isc_txrx; 4358 4359#ifdef INVARIANTS 4360 MPASS(scctx->isc_capenable); 4361 if (scctx->isc_capenable & IFCAP_TXCSUM) 4362 MPASS(scctx->isc_tx_csum_flags); 4363#endif 4364 4365 if_setcapabilities(ifp, scctx->isc_capenable | IFCAP_HWSTATS); 4366 if_setcapenable(ifp, scctx->isc_capenable | IFCAP_HWSTATS); 4367 4368 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets)) 4369 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max; 4370 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets)) 4371 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max; 4372 4373#ifdef ACPI_DMAR 4374 if (dmar_get_dma_tag(device_get_parent(dev), dev) != NULL) 4375 ctx->ifc_flags |= IFC_DMAR; 4376#elif !(defined(__i386__) || defined(__amd64__)) 4377 /* set unconditionally for !x86 */ 4378 ctx->ifc_flags |= IFC_DMAR; 4379#endif 4380 4381 msix_bar = scctx->isc_msix_bar; 4382 main_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0; 4383 main_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0; 4384 4385 /* XXX change for per-queue sizes */ 4386 device_printf(dev, "using %d tx descriptors and %d rx descriptors\n", 4387 scctx->isc_ntxd[main_txq], scctx->isc_nrxd[main_rxq]); 4388 for (i = 0; i < sctx->isc_nrxqs; i++) { 4389 if (!powerof2(scctx->isc_nrxd[i])) { 4390 /* round down instead? */ 4391 device_printf(dev, "# rx descriptors must be a power of 2\n"); 4392 err = EINVAL; 4393 goto fail; 4394 } 4395 } 4396 for (i = 0; i < sctx->isc_ntxqs; i++) { 4397 if (!powerof2(scctx->isc_ntxd[i])) { 4398 device_printf(dev, 4399 "# tx descriptors must be a power of 2"); 4400 err = EINVAL; 4401 goto fail; 4402 } 4403 } 4404 4405 if (scctx->isc_tx_nsegments > scctx->isc_ntxd[main_txq] / 4406 MAX_SINGLE_PACKET_FRACTION) 4407 scctx->isc_tx_nsegments = max(1, scctx->isc_ntxd[main_txq] / 4408 MAX_SINGLE_PACKET_FRACTION); 4409 if (scctx->isc_tx_tso_segments_max > scctx->isc_ntxd[main_txq] / 4410 MAX_SINGLE_PACKET_FRACTION) 4411 scctx->isc_tx_tso_segments_max = max(1, 4412 scctx->isc_ntxd[main_txq] / MAX_SINGLE_PACKET_FRACTION); 4413 4414 /* 4415 * Protect the stack against modern hardware 4416 */ 4417 if (scctx->isc_tx_tso_size_max > FREEBSD_TSO_SIZE_MAX) 4418 scctx->isc_tx_tso_size_max = FREEBSD_TSO_SIZE_MAX; 4419 4420 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */ 4421 ifp->if_hw_tsomaxsegcount = scctx->isc_tx_tso_segments_max; 4422 ifp->if_hw_tsomax = scctx->isc_tx_tso_size_max; 4423 ifp->if_hw_tsomaxsegsize = scctx->isc_tx_tso_segsize_max; 4424 if (scctx->isc_rss_table_size == 0) 4425 scctx->isc_rss_table_size = 64; 4426 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1; 4427 4428 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx); 4429 /* XXX format name */ 4430 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx, -1, "admin"); 4431 4432 /* Set up cpu set. If it fails, use the set of all CPUs. */ 4433 if (bus_get_cpus(dev, INTR_CPUS, sizeof(ctx->ifc_cpus), &ctx->ifc_cpus) != 0) { 4434 device_printf(dev, "Unable to fetch CPU list\n"); 4435 CPU_COPY(&all_cpus, &ctx->ifc_cpus); 4436 } 4437 MPASS(CPU_COUNT(&ctx->ifc_cpus) > 0); 4438 4439 /* 4440 ** Now setup MSI or MSI/X, should 4441 ** return us the number of supported 4442 ** vectors. (Will be 1 for MSI) 4443 */ 4444 if (sctx->isc_flags & IFLIB_SKIP_MSIX) { 4445 msix = scctx->isc_vectors; 4446 } else if (scctx->isc_msix_bar != 0) 4447 /* 4448 * The simple fact that isc_msix_bar is not 0 does not mean we 4449 * we have a good value there that is known to work. 4450 */ 4451 msix = iflib_msix_init(ctx); 4452 else { 4453 scctx->isc_vectors = 1; 4454 scctx->isc_ntxqsets = 1; 4455 scctx->isc_nrxqsets = 1; 4456 scctx->isc_intr = IFLIB_INTR_LEGACY; 4457 msix = 0; 4458 } 4459 /* Get memory for the station queues */ 4460 if ((err = iflib_queues_alloc(ctx))) { 4461 device_printf(dev, "Unable to allocate queue memory\n"); 4462 goto fail; 4463 } 4464 4465 if ((err = iflib_qset_structures_setup(ctx))) 4466 goto fail_queues; 4467 /* 4468 * Group taskqueues aren't properly set up until SMP is started, 4469 * so we disable interrupts until we can handle them post 4470 * SI_SUB_SMP. 4471 * 4472 * XXX: disabling interrupts doesn't actually work, at least for 4473 * the non-MSI case. When they occur before SI_SUB_SMP completes, 4474 * we do null handling and depend on this not causing too large an 4475 * interrupt storm. 4476 */ 4477 IFDI_INTR_DISABLE(ctx); 4478 if (msix > 1 && (err = IFDI_MSIX_INTR_ASSIGN(ctx, msix)) != 0) { 4479 device_printf(dev, "IFDI_MSIX_INTR_ASSIGN failed %d\n", err); 4480 goto fail_intr_free; 4481 } 4482 if (msix <= 1) { 4483 rid = 0; 4484 if (scctx->isc_intr == IFLIB_INTR_MSI) { 4485 MPASS(msix == 1); 4486 rid = 1; 4487 } 4488 if ((err = iflib_legacy_setup(ctx, ctx->isc_legacy_intr, ctx->ifc_softc, &rid, "irq0")) != 0) { 4489 device_printf(dev, "iflib_legacy_setup failed %d\n", err); 4490 goto fail_intr_free; 4491 } 4492 } 4493 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac); 4494 if ((err = IFDI_ATTACH_POST(ctx)) != 0) { 4495 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err); 4496 goto fail_detach; 4497 } 4498 if ((err = iflib_netmap_attach(ctx))) { 4499 device_printf(ctx->ifc_dev, "netmap attach failed: %d\n", err); 4500 goto fail_detach; 4501 } 4502 *ctxp = ctx; 4503 4504 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter); 4505 iflib_add_device_sysctl_post(ctx); 4506 return (0); 4507fail_detach: 4508 ether_ifdetach(ctx->ifc_ifp); 4509fail_intr_free: 4510 if (scctx->isc_intr == IFLIB_INTR_MSIX || scctx->isc_intr == IFLIB_INTR_MSI) 4511 pci_release_msi(ctx->ifc_dev); 4512fail_queues: 4513 iflib_tx_structures_free(ctx); 4514 iflib_rx_structures_free(ctx); 4515fail: 4516 IFDI_DETACH(ctx); 4517 return (err); 4518} 4519 4520int 4521iflib_device_attach(device_t dev) 4522{ 4523 if_ctx_t ctx; 4524 if_shared_ctx_t sctx; 4525 4526 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC) 4527 return (ENOTSUP); 4528 4529 pci_enable_busmaster(dev); 4530 4531 return (iflib_device_register(dev, NULL, sctx, &ctx)); 4532} 4533 4534int 4535iflib_device_deregister(if_ctx_t ctx) 4536{ 4537 if_t ifp = ctx->ifc_ifp; 4538 iflib_txq_t txq; 4539 iflib_rxq_t rxq; 4540 device_t dev = ctx->ifc_dev; 4541 int i, j; 4542 struct taskqgroup *tqg; 4543 iflib_fl_t fl; 4544 4545 /* Make sure VLANS are not using driver */ 4546 if (if_vlantrunkinuse(ifp)) { 4547 device_printf(dev, "Vlan in use, detach first\n"); 4548 return (EBUSY); 4549 } 4550#ifdef PCI_IOV 4551 if (!CTX_IS_VF(ctx) && pci_iov_detach(dev) != 0) { 4552 device_printf(dev, "SR-IOV in use; detach first.\n"); 4553 return (EBUSY); 4554 } 4555#endif 4556 4557 STATE_LOCK(ctx); 4558 ctx->ifc_flags |= IFC_IN_DETACH; 4559 STATE_UNLOCK(ctx); 4560 4561 /* Unregister VLAN handlers before calling iflib_stop() */ 4562 iflib_unregister_vlan_handlers(ctx); 4563 4564 iflib_netmap_detach(ifp); 4565 ether_ifdetach(ifp); 4566 4567 CTX_LOCK(ctx); 4568 iflib_stop(ctx); 4569 CTX_UNLOCK(ctx); 4570 4571 if (ctx->ifc_led_dev != NULL) 4572 led_destroy(ctx->ifc_led_dev); 4573 /* XXX drain any dependent tasks */ 4574 tqg = qgroup_if_io_tqg; 4575 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) { 4576 callout_drain(&txq->ift_timer); 4577 if (txq->ift_task.gt_uniq != NULL) 4578 taskqgroup_detach(tqg, &txq->ift_task); 4579 } 4580 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) { 4581 callout_drain(&rxq->ifr_watchdog); 4582 if (rxq->ifr_task.gt_uniq != NULL) 4583 taskqgroup_detach(tqg, &rxq->ifr_task); 4584 4585 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 4586 free(fl->ifl_rx_bitmap, M_IFLIB); 4587 4588 } 4589 tqg = qgroup_if_config_tqg; 4590 if (ctx->ifc_admin_task.gt_uniq != NULL) 4591 taskqgroup_detach(tqg, &ctx->ifc_admin_task); 4592 if (ctx->ifc_vflr_task.gt_uniq != NULL) 4593 taskqgroup_detach(tqg, &ctx->ifc_vflr_task); 4594 CTX_LOCK(ctx); 4595 IFDI_DETACH(ctx); 4596 CTX_UNLOCK(ctx); 4597 4598 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/ 4599 CTX_LOCK_DESTROY(ctx); 4600 device_set_softc(ctx->ifc_dev, NULL); 4601 iflib_free_intr_mem(ctx); 4602 4603 bus_generic_detach(dev); 4604 if_free(ifp); 4605 4606 iflib_tx_structures_free(ctx); 4607 iflib_rx_structures_free(ctx); 4608 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 4609 free(ctx->ifc_softc, M_IFLIB); 4610 STATE_LOCK_DESTROY(ctx); 4611 free(ctx, M_IFLIB); 4612 return (0); 4613} 4614 4615static void 4616iflib_free_intr_mem(if_ctx_t ctx) 4617{ 4618 4619 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_MSIX) { 4620 iflib_irq_free(ctx, &ctx->ifc_legacy_irq); 4621 } 4622 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_LEGACY) { 4623 pci_release_msi(ctx->ifc_dev); 4624 } 4625 if (ctx->ifc_msix_mem != NULL) { 4626 bus_release_resource(ctx->ifc_dev, SYS_RES_MEMORY, 4627 rman_get_rid(ctx->ifc_msix_mem), ctx->ifc_msix_mem); 4628 ctx->ifc_msix_mem = NULL; 4629 } 4630} 4631 4632int 4633iflib_device_detach(device_t dev) 4634{ 4635 if_ctx_t ctx = device_get_softc(dev); 4636 4637 return (iflib_device_deregister(ctx)); 4638} 4639 4640int 4641iflib_device_suspend(device_t dev) 4642{ 4643 if_ctx_t ctx = device_get_softc(dev); 4644 4645 CTX_LOCK(ctx); 4646 IFDI_SUSPEND(ctx); 4647 CTX_UNLOCK(ctx); 4648 4649 return bus_generic_suspend(dev); 4650} 4651int 4652iflib_device_shutdown(device_t dev) 4653{ 4654 if_ctx_t ctx = device_get_softc(dev); 4655 4656 CTX_LOCK(ctx); 4657 IFDI_SHUTDOWN(ctx); 4658 CTX_UNLOCK(ctx); 4659 4660 return bus_generic_suspend(dev); 4661} 4662 4663 4664int 4665iflib_device_resume(device_t dev) 4666{ 4667 if_ctx_t ctx = device_get_softc(dev); 4668 iflib_txq_t txq = ctx->ifc_txqs; 4669 4670 CTX_LOCK(ctx); 4671 IFDI_RESUME(ctx); 4672 iflib_if_init_locked(ctx); 4673 CTX_UNLOCK(ctx); 4674 for (int i = 0; i < NTXQSETS(ctx); i++, txq++) 4675 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET); 4676 4677 return (bus_generic_resume(dev)); 4678} 4679 4680int 4681iflib_device_iov_init(device_t dev, uint16_t num_vfs, const nvlist_t *params) 4682{ 4683 int error; 4684 if_ctx_t ctx = device_get_softc(dev); 4685 4686 CTX_LOCK(ctx); 4687 error = IFDI_IOV_INIT(ctx, num_vfs, params); 4688 CTX_UNLOCK(ctx); 4689 4690 return (error); 4691} 4692 4693void 4694iflib_device_iov_uninit(device_t dev) 4695{ 4696 if_ctx_t ctx = device_get_softc(dev); 4697 4698 CTX_LOCK(ctx); 4699 IFDI_IOV_UNINIT(ctx); 4700 CTX_UNLOCK(ctx); 4701} 4702 4703int 4704iflib_device_iov_add_vf(device_t dev, uint16_t vfnum, const nvlist_t *params) 4705{ 4706 int error; 4707 if_ctx_t ctx = device_get_softc(dev); 4708 4709 CTX_LOCK(ctx); 4710 error = IFDI_IOV_VF_ADD(ctx, vfnum, params); 4711 CTX_UNLOCK(ctx); 4712 4713 return (error); 4714} 4715 4716/********************************************************************* 4717 * 4718 * MODULE FUNCTION DEFINITIONS 4719 * 4720 **********************************************************************/ 4721 4722/* 4723 * - Start a fast taskqueue thread for each core 4724 * - Start a taskqueue for control operations 4725 */ 4726static int 4727iflib_module_init(void) 4728{ 4729 return (0); 4730} 4731 4732static int 4733iflib_module_event_handler(module_t mod, int what, void *arg) 4734{ 4735 int err; 4736 4737 switch (what) { 4738 case MOD_LOAD: 4739 if ((err = iflib_module_init()) != 0) 4740 return (err); 4741 break; 4742 case MOD_UNLOAD: 4743 return (EBUSY); 4744 default: 4745 return (EOPNOTSUPP); 4746 } 4747 4748 return (0); 4749} 4750 4751/********************************************************************* 4752 * 4753 * PUBLIC FUNCTION DEFINITIONS 4754 * ordered as in iflib.h 4755 * 4756 **********************************************************************/ 4757 4758 4759static void 4760_iflib_assert(if_shared_ctx_t sctx) 4761{ 4762 MPASS(sctx->isc_tx_maxsize); 4763 MPASS(sctx->isc_tx_maxsegsize); 4764 4765 MPASS(sctx->isc_rx_maxsize); 4766 MPASS(sctx->isc_rx_nsegments); 4767 MPASS(sctx->isc_rx_maxsegsize); 4768 4769 MPASS(sctx->isc_nrxd_min[0]); 4770 MPASS(sctx->isc_nrxd_max[0]); 4771 MPASS(sctx->isc_nrxd_default[0]); 4772 MPASS(sctx->isc_ntxd_min[0]); 4773 MPASS(sctx->isc_ntxd_max[0]); 4774 MPASS(sctx->isc_ntxd_default[0]); 4775} 4776 4777static void 4778_iflib_pre_assert(if_softc_ctx_t scctx) 4779{ 4780 4781 MPASS(scctx->isc_txrx->ift_txd_encap); 4782 MPASS(scctx->isc_txrx->ift_txd_flush); 4783 MPASS(scctx->isc_txrx->ift_txd_credits_update); 4784 MPASS(scctx->isc_txrx->ift_rxd_available); 4785 MPASS(scctx->isc_txrx->ift_rxd_pkt_get); 4786 MPASS(scctx->isc_txrx->ift_rxd_refill); 4787 MPASS(scctx->isc_txrx->ift_rxd_flush); 4788} 4789 4790static int 4791iflib_register(if_ctx_t ctx) 4792{ 4793 if_shared_ctx_t sctx = ctx->ifc_sctx; 4794 driver_t *driver = sctx->isc_driver; 4795 device_t dev = ctx->ifc_dev; 4796 if_t ifp; 4797 4798 _iflib_assert(sctx); 4799 4800 CTX_LOCK_INIT(ctx, device_get_nameunit(ctx->ifc_dev)); 4801 STATE_LOCK_INIT(ctx, device_get_nameunit(ctx->ifc_dev)); 4802 4803 ifp = ctx->ifc_ifp = if_alloc(IFT_ETHER); 4804 if (ifp == NULL) { 4805 device_printf(dev, "can not allocate ifnet structure\n"); 4806 return (ENOMEM); 4807 } 4808 4809 /* 4810 * Initialize our context's device specific methods 4811 */ 4812 kobj_init((kobj_t) ctx, (kobj_class_t) driver); 4813 kobj_class_compile((kobj_class_t) driver); 4814 driver->refs++; 4815 4816 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 4817 if_setsoftc(ifp, ctx); 4818 if_setdev(ifp, dev); 4819 if_setinitfn(ifp, iflib_if_init); 4820 if_setioctlfn(ifp, iflib_if_ioctl); 4821 if_settransmitfn(ifp, iflib_if_transmit); 4822 if_setqflushfn(ifp, iflib_if_qflush); 4823 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 4824 4825 ctx->ifc_vlan_attach_event = 4826 EVENTHANDLER_REGISTER(vlan_config, iflib_vlan_register, ctx, 4827 EVENTHANDLER_PRI_FIRST); 4828 ctx->ifc_vlan_detach_event = 4829 EVENTHANDLER_REGISTER(vlan_unconfig, iflib_vlan_unregister, ctx, 4830 EVENTHANDLER_PRI_FIRST); 4831 4832 ifmedia_init(&ctx->ifc_media, IFM_IMASK, 4833 iflib_media_change, iflib_media_status); 4834 4835 return (0); 4836} 4837 4838static void 4839iflib_unregister_vlan_handlers(if_ctx_t ctx) 4840{ 4841 /* Unregister VLAN events */ 4842 if (ctx->ifc_vlan_attach_event != NULL) { 4843 EVENTHANDLER_DEREGISTER(vlan_config, ctx->ifc_vlan_attach_event); 4844 ctx->ifc_vlan_attach_event = NULL; 4845 } 4846 if (ctx->ifc_vlan_detach_event != NULL) { 4847 EVENTHANDLER_DEREGISTER(vlan_unconfig, ctx->ifc_vlan_detach_event); 4848 ctx->ifc_vlan_detach_event = NULL; 4849 } 4850 4851} 4852 4853static int 4854iflib_queues_alloc(if_ctx_t ctx) 4855{ 4856 if_shared_ctx_t sctx = ctx->ifc_sctx; 4857 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 4858 device_t dev = ctx->ifc_dev; 4859 int nrxqsets = scctx->isc_nrxqsets; 4860 int ntxqsets = scctx->isc_ntxqsets; 4861 iflib_txq_t txq; 4862 iflib_rxq_t rxq; 4863 iflib_fl_t fl = NULL; 4864 int i, j, cpu, err, txconf, rxconf; 4865 iflib_dma_info_t ifdip; 4866 uint32_t *rxqsizes = scctx->isc_rxqsizes; 4867 uint32_t *txqsizes = scctx->isc_txqsizes; 4868 uint8_t nrxqs = sctx->isc_nrxqs; 4869 uint8_t ntxqs = sctx->isc_ntxqs; 4870 int nfree_lists = sctx->isc_nfl ? sctx->isc_nfl : 1; 4871 caddr_t *vaddrs; 4872 uint64_t *paddrs; 4873 4874 KASSERT(ntxqs > 0, ("number of queues per qset must be at least 1")); 4875 KASSERT(nrxqs > 0, ("number of queues per qset must be at least 1")); 4876 4877 /* Allocate the TX ring struct memory */ 4878 if (!(ctx->ifc_txqs = 4879 (iflib_txq_t) malloc(sizeof(struct iflib_txq) * 4880 ntxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) { 4881 device_printf(dev, "Unable to allocate TX ring memory\n"); 4882 err = ENOMEM; 4883 goto fail; 4884 } 4885 4886 /* Now allocate the RX */ 4887 if (!(ctx->ifc_rxqs = 4888 (iflib_rxq_t) malloc(sizeof(struct iflib_rxq) * 4889 nrxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) { 4890 device_printf(dev, "Unable to allocate RX ring memory\n"); 4891 err = ENOMEM; 4892 goto rx_fail; 4893 } 4894 4895 txq = ctx->ifc_txqs; 4896 rxq = ctx->ifc_rxqs; 4897 4898 /* 4899 * XXX handle allocation failure 4900 */ 4901 for (txconf = i = 0, cpu = CPU_FIRST(); i < ntxqsets; i++, txconf++, txq++, cpu = CPU_NEXT(cpu)) { 4902 /* Set up some basics */ 4903 4904 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * ntxqs, M_IFLIB, M_WAITOK|M_ZERO)) == NULL) { 4905 device_printf(dev, "failed to allocate iflib_dma_info\n"); 4906 err = ENOMEM; 4907 goto err_tx_desc; 4908 } 4909 txq->ift_ifdi = ifdip; 4910 for (j = 0; j < ntxqs; j++, ifdip++) { 4911 if (iflib_dma_alloc(ctx, txqsizes[j], ifdip, BUS_DMA_NOWAIT)) { 4912 device_printf(dev, "Unable to allocate Descriptor memory\n"); 4913 err = ENOMEM; 4914 goto err_tx_desc; 4915 } 4916 txq->ift_txd_size[j] = scctx->isc_txd_size[j]; 4917 bzero((void *)ifdip->idi_vaddr, txqsizes[j]); 4918 } 4919 txq->ift_ctx = ctx; 4920 txq->ift_id = i; 4921 if (sctx->isc_flags & IFLIB_HAS_TXCQ) { 4922 txq->ift_br_offset = 1; 4923 } else { 4924 txq->ift_br_offset = 0; 4925 } 4926 /* XXX fix this */ 4927 txq->ift_timer.c_cpu = cpu; 4928 4929 if (iflib_txsd_alloc(txq)) { 4930 device_printf(dev, "Critical Failure setting up TX buffers\n"); 4931 err = ENOMEM; 4932 goto err_tx_desc; 4933 } 4934 4935 /* Initialize the TX lock */ 4936 snprintf(txq->ift_mtx_name, MTX_NAME_LEN, "%s:tx(%d):callout", 4937 device_get_nameunit(dev), txq->ift_id); 4938 mtx_init(&txq->ift_mtx, txq->ift_mtx_name, NULL, MTX_DEF); 4939 callout_init_mtx(&txq->ift_timer, &txq->ift_mtx, 0); 4940 4941 snprintf(txq->ift_db_mtx_name, MTX_NAME_LEN, "%s:tx(%d):db", 4942 device_get_nameunit(dev), txq->ift_id); 4943 4944 err = ifmp_ring_alloc(&txq->ift_br, 2048, txq, iflib_txq_drain, 4945 iflib_txq_can_drain, M_IFLIB, M_WAITOK); 4946 if (err) { 4947 /* XXX free any allocated rings */ 4948 device_printf(dev, "Unable to allocate buf_ring\n"); 4949 goto err_tx_desc; 4950 } 4951 } 4952 4953 for (rxconf = i = 0; i < nrxqsets; i++, rxconf++, rxq++) { 4954 /* Set up some basics */ 4955 callout_init(&rxq->ifr_watchdog, 1); 4956 4957 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * nrxqs, M_IFLIB, M_WAITOK|M_ZERO)) == NULL) { 4958 device_printf(dev, "failed to allocate iflib_dma_info\n"); 4959 err = ENOMEM; 4960 goto err_tx_desc; 4961 } 4962 4963 rxq->ifr_ifdi = ifdip; 4964 /* XXX this needs to be changed if #rx queues != #tx queues */ 4965 rxq->ifr_ntxqirq = 1; 4966 rxq->ifr_txqid[0] = i; 4967 for (j = 0; j < nrxqs; j++, ifdip++) { 4968 if (iflib_dma_alloc(ctx, rxqsizes[j], ifdip, BUS_DMA_NOWAIT)) { 4969 device_printf(dev, "Unable to allocate Descriptor memory\n"); 4970 err = ENOMEM; 4971 goto err_tx_desc; 4972 } 4973 bzero((void *)ifdip->idi_vaddr, rxqsizes[j]); 4974 } 4975 rxq->ifr_ctx = ctx; 4976 rxq->ifr_id = i; 4977 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 4978 rxq->ifr_fl_offset = 1; 4979 } else { 4980 rxq->ifr_fl_offset = 0; 4981 } 4982 rxq->ifr_nfl = nfree_lists; 4983 if (!(fl = 4984 (iflib_fl_t) malloc(sizeof(struct iflib_fl) * nfree_lists, M_IFLIB, M_NOWAIT | M_ZERO))) { 4985 device_printf(dev, "Unable to allocate free list memory\n"); 4986 err = ENOMEM; 4987 goto err_tx_desc; 4988 } 4989 rxq->ifr_fl = fl; 4990 for (j = 0; j < nfree_lists; j++) { 4991 fl[j].ifl_rxq = rxq; 4992 fl[j].ifl_id = j; 4993 fl[j].ifl_ifdi = &rxq->ifr_ifdi[j + rxq->ifr_fl_offset]; 4994 fl[j].ifl_rxd_size = scctx->isc_rxd_size[j]; 4995 } 4996 /* Allocate receive buffers for the ring*/ 4997 if (iflib_rxsd_alloc(rxq)) { 4998 device_printf(dev, 4999 "Critical Failure setting up receive buffers\n"); 5000 err = ENOMEM; 5001 goto err_rx_desc; 5002 } 5003 5004 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 5005 fl->ifl_rx_bitmap = bit_alloc(fl->ifl_size, M_IFLIB, M_WAITOK|M_ZERO); 5006 } 5007 5008 /* TXQs */ 5009 vaddrs = malloc(sizeof(caddr_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK); 5010 paddrs = malloc(sizeof(uint64_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK); 5011 for (i = 0; i < ntxqsets; i++) { 5012 iflib_dma_info_t di = ctx->ifc_txqs[i].ift_ifdi; 5013 5014 for (j = 0; j < ntxqs; j++, di++) { 5015 vaddrs[i*ntxqs + j] = di->idi_vaddr; 5016 paddrs[i*ntxqs + j] = di->idi_paddr; 5017 } 5018 } 5019 if ((err = IFDI_TX_QUEUES_ALLOC(ctx, vaddrs, paddrs, ntxqs, ntxqsets)) != 0) { 5020 device_printf(ctx->ifc_dev, "device queue allocation failed\n"); 5021 iflib_tx_structures_free(ctx); 5022 free(vaddrs, M_IFLIB); 5023 free(paddrs, M_IFLIB); 5024 goto err_rx_desc; 5025 } 5026 free(vaddrs, M_IFLIB); 5027 free(paddrs, M_IFLIB); 5028 5029 /* RXQs */ 5030 vaddrs = malloc(sizeof(caddr_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK); 5031 paddrs = malloc(sizeof(uint64_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK); 5032 for (i = 0; i < nrxqsets; i++) { 5033 iflib_dma_info_t di = ctx->ifc_rxqs[i].ifr_ifdi; 5034 5035 for (j = 0; j < nrxqs; j++, di++) { 5036 vaddrs[i*nrxqs + j] = di->idi_vaddr; 5037 paddrs[i*nrxqs + j] = di->idi_paddr; 5038 } 5039 } 5040 if ((err = IFDI_RX_QUEUES_ALLOC(ctx, vaddrs, paddrs, nrxqs, nrxqsets)) != 0) { 5041 device_printf(ctx->ifc_dev, "device queue allocation failed\n"); 5042 iflib_tx_structures_free(ctx); 5043 free(vaddrs, M_IFLIB); 5044 free(paddrs, M_IFLIB); 5045 goto err_rx_desc; 5046 } 5047 free(vaddrs, M_IFLIB); 5048 free(paddrs, M_IFLIB); 5049 5050 return (0); 5051 5052/* XXX handle allocation failure changes */ 5053err_rx_desc: 5054err_tx_desc: 5055rx_fail: 5056 if (ctx->ifc_rxqs != NULL) 5057 free(ctx->ifc_rxqs, M_IFLIB); 5058 ctx->ifc_rxqs = NULL; 5059 if (ctx->ifc_txqs != NULL) 5060 free(ctx->ifc_txqs, M_IFLIB); 5061 ctx->ifc_txqs = NULL; 5062fail: 5063 return (err); 5064} 5065 5066static int 5067iflib_tx_structures_setup(if_ctx_t ctx) 5068{ 5069 iflib_txq_t txq = ctx->ifc_txqs; 5070 int i; 5071 5072 for (i = 0; i < NTXQSETS(ctx); i++, txq++) 5073 iflib_txq_setup(txq); 5074 5075 return (0); 5076} 5077 5078static void 5079iflib_tx_structures_free(if_ctx_t ctx) 5080{ 5081 iflib_txq_t txq = ctx->ifc_txqs; 5082 int i, j; 5083 5084 for (i = 0; i < NTXQSETS(ctx); i++, txq++) { 5085 for (j = 0; j < ctx->ifc_nhwtxqs; j++) 5086 iflib_dma_free(&txq->ift_ifdi[j]); 5087 iflib_txq_destroy(txq); 5088 } 5089 free(ctx->ifc_txqs, M_IFLIB); 5090 ctx->ifc_txqs = NULL; 5091 IFDI_QUEUES_FREE(ctx); 5092} 5093 5094/********************************************************************* 5095 * 5096 * Initialize all receive rings. 5097 * 5098 **********************************************************************/ 5099static int 5100iflib_rx_structures_setup(if_ctx_t ctx) 5101{ 5102 iflib_rxq_t rxq = ctx->ifc_rxqs; 5103 int q; 5104#if defined(INET6) || defined(INET) 5105 int i, err; 5106#endif 5107 5108 for (q = 0; q < ctx->ifc_softc_ctx.isc_nrxqsets; q++, rxq++) { 5109#if defined(INET6) || defined(INET) 5110 tcp_lro_free(&rxq->ifr_lc); 5111 if ((err = tcp_lro_init_args(&rxq->ifr_lc, ctx->ifc_ifp, 5112 TCP_LRO_ENTRIES, min(1024, 5113 ctx->ifc_softc_ctx.isc_nrxd[rxq->ifr_fl_offset]))) != 0) { 5114 device_printf(ctx->ifc_dev, "LRO Initialization failed!\n"); 5115 goto fail; 5116 } 5117 rxq->ifr_lro_enabled = TRUE; 5118#endif 5119 IFDI_RXQ_SETUP(ctx, rxq->ifr_id); 5120 } 5121 return (0); 5122#if defined(INET6) || defined(INET) 5123fail: 5124 /* 5125 * Free RX software descriptors allocated so far, we will only handle 5126 * the rings that completed, the failing case will have 5127 * cleaned up for itself. 'q' failed, so its the terminus. 5128 */ 5129 rxq = ctx->ifc_rxqs; 5130 for (i = 0; i < q; ++i, rxq++) { 5131 iflib_rx_sds_free(rxq); 5132 rxq->ifr_cq_gen = rxq->ifr_cq_cidx = rxq->ifr_cq_pidx = 0; 5133 } 5134 return (err); 5135#endif 5136} 5137 5138/********************************************************************* 5139 * 5140 * Free all receive rings. 5141 * 5142 **********************************************************************/ 5143static void 5144iflib_rx_structures_free(if_ctx_t ctx) 5145{ 5146 iflib_rxq_t rxq = ctx->ifc_rxqs; 5147 if_shared_ctx_t sctx = ctx->ifc_sctx; 5148 int i, j; 5149 5150 for (i = 0; i < ctx->ifc_softc_ctx.isc_nrxqsets; i++, rxq++) { 5151 for (j = 0; j < sctx->isc_nrxqs; j++) 5152 iflib_dma_free(&rxq->ifr_ifdi[j]); 5153 iflib_rx_sds_free(rxq); 5154 } 5155 free(ctx->ifc_rxqs, M_IFLIB); 5156 ctx->ifc_rxqs = NULL; 5157} 5158 5159static int 5160iflib_qset_structures_setup(if_ctx_t ctx) 5161{ 5162 int err; 5163 5164 /* 5165 * It is expected that the caller takes care of freeing queues if this 5166 * fails. 5167 */ 5168 if ((err = iflib_tx_structures_setup(ctx)) != 0) { 5169 device_printf(ctx->ifc_dev, "iflib_tx_structures_setup failed: %d\n", err); 5170 return (err); 5171 } 5172 5173 if ((err = iflib_rx_structures_setup(ctx)) != 0) 5174 device_printf(ctx->ifc_dev, "iflib_rx_structures_setup failed: %d\n", err); 5175 5176 return (err); 5177} 5178 5179int 5180iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid, 5181 driver_filter_t filter, void *filter_arg, driver_intr_t handler, void *arg, char *name) 5182{ 5183 5184 return (_iflib_irq_alloc(ctx, irq, rid, filter, handler, arg, name)); 5185} 5186 5187#ifdef SMP 5188static int 5189find_nth(if_ctx_t ctx, int qid) 5190{ 5191 cpuset_t cpus; 5192 int i, cpuid, eqid, count; 5193 5194 CPU_COPY(&ctx->ifc_cpus, &cpus); 5195 count = CPU_COUNT(&cpus); 5196 eqid = qid % count; 5197 /* clear up to the qid'th bit */ 5198 for (i = 0; i < eqid; i++) { 5199 cpuid = CPU_FFS(&cpus); 5200 MPASS(cpuid != 0); 5201 CPU_CLR(cpuid-1, &cpus); 5202 } 5203 cpuid = CPU_FFS(&cpus); 5204 MPASS(cpuid != 0); 5205 return (cpuid-1); 5206} 5207 5208#ifdef SCHED_ULE 5209extern struct cpu_group *cpu_top; /* CPU topology */ 5210 5211static int 5212find_child_with_core(int cpu, struct cpu_group *grp) 5213{ 5214 int i; 5215 5216 if (grp->cg_children == 0) 5217 return -1; 5218 5219 MPASS(grp->cg_child); 5220 for (i = 0; i < grp->cg_children; i++) { 5221 if (CPU_ISSET(cpu, &grp->cg_child[i].cg_mask)) 5222 return i; 5223 } 5224 5225 return -1; 5226} 5227 5228/* 5229 * Find the nth "close" core to the specified core 5230 * "close" is defined as the deepest level that shares 5231 * at least an L2 cache. With threads, this will be 5232 * threads on the same core. If the sahred cache is L3 5233 * or higher, simply returns the same core. 5234 */ 5235static int 5236find_close_core(int cpu, int core_offset) 5237{ 5238 struct cpu_group *grp; 5239 int i; 5240 int fcpu; 5241 cpuset_t cs; 5242 5243 grp = cpu_top; 5244 if (grp == NULL) 5245 return cpu; 5246 i = 0; 5247 while ((i = find_child_with_core(cpu, grp)) != -1) { 5248 /* If the child only has one cpu, don't descend */ 5249 if (grp->cg_child[i].cg_count <= 1) 5250 break; 5251 grp = &grp->cg_child[i]; 5252 } 5253 5254 /* If they don't share at least an L2 cache, use the same CPU */ 5255 if (grp->cg_level > CG_SHARE_L2 || grp->cg_level == CG_SHARE_NONE) 5256 return cpu; 5257 5258 /* Now pick one */ 5259 CPU_COPY(&grp->cg_mask, &cs); 5260 5261 /* Add the selected CPU offset to core offset. */ 5262 for (i = 0; (fcpu = CPU_FFS(&cs)) != 0; i++) { 5263 if (fcpu - 1 == cpu) 5264 break; 5265 CPU_CLR(fcpu - 1, &cs); 5266 } 5267 MPASS(fcpu); 5268 5269 core_offset += i; 5270 5271 CPU_COPY(&grp->cg_mask, &cs); 5272 for (i = core_offset % grp->cg_count; i > 0; i--) { 5273 MPASS(CPU_FFS(&cs)); 5274 CPU_CLR(CPU_FFS(&cs) - 1, &cs); 5275 } 5276 MPASS(CPU_FFS(&cs)); 5277 return CPU_FFS(&cs) - 1; 5278} 5279#else 5280static int 5281find_close_core(int cpu, int core_offset __unused) 5282{ 5283 return cpu; 5284} 5285#endif 5286 5287static int 5288get_core_offset(if_ctx_t ctx, iflib_intr_type_t type, int qid) 5289{ 5290 switch (type) { 5291 case IFLIB_INTR_TX: 5292 /* TX queues get cores which share at least an L2 cache with the corresponding RX queue */ 5293 /* XXX handle multiple RX threads per core and more than two core per L2 group */ 5294 return qid / CPU_COUNT(&ctx->ifc_cpus) + 1; 5295 case IFLIB_INTR_RX: 5296 case IFLIB_INTR_RXTX: 5297 /* RX queues get the specified core */ 5298 return qid / CPU_COUNT(&ctx->ifc_cpus); 5299 default: 5300 return -1; 5301 } 5302} 5303#else 5304#define get_core_offset(ctx, type, qid) CPU_FIRST() 5305#define find_close_core(cpuid, tid) CPU_FIRST() 5306#define find_nth(ctx, gid) CPU_FIRST() 5307#endif 5308 5309/* Just to avoid copy/paste */ 5310static inline int 5311iflib_irq_set_affinity(if_ctx_t ctx, int irq, iflib_intr_type_t type, int qid, 5312 struct grouptask *gtask, struct taskqgroup *tqg, void *uniq, char *name) 5313{ 5314 int cpuid; 5315 int err, tid; 5316 5317 cpuid = find_nth(ctx, qid); 5318 tid = get_core_offset(ctx, type, qid); 5319 MPASS(tid >= 0); 5320 cpuid = find_close_core(cpuid, tid); 5321 err = taskqgroup_attach_cpu(tqg, gtask, uniq, cpuid, irq, name); 5322 if (err) { 5323 device_printf(ctx->ifc_dev, "taskqgroup_attach_cpu failed %d\n", err); 5324 return (err); 5325 } 5326#ifdef notyet 5327 if (cpuid > ctx->ifc_cpuid_highest) 5328 ctx->ifc_cpuid_highest = cpuid; 5329#endif 5330 return 0; 5331} 5332 5333int 5334iflib_irq_alloc_generic(if_ctx_t ctx, if_irq_t irq, int rid, 5335 iflib_intr_type_t type, driver_filter_t *filter, 5336 void *filter_arg, int qid, char *name) 5337{ 5338 struct grouptask *gtask; 5339 struct taskqgroup *tqg; 5340 iflib_filter_info_t info; 5341 gtask_fn_t *fn; 5342 int tqrid, err; 5343 driver_filter_t *intr_fast; 5344 void *q; 5345 5346 info = &ctx->ifc_filter_info; 5347 tqrid = rid; 5348 5349 switch (type) { 5350 /* XXX merge tx/rx for netmap? */ 5351 case IFLIB_INTR_TX: 5352 q = &ctx->ifc_txqs[qid]; 5353 info = &ctx->ifc_txqs[qid].ift_filter_info; 5354 gtask = &ctx->ifc_txqs[qid].ift_task; 5355 tqg = qgroup_if_io_tqg; 5356 fn = _task_fn_tx; 5357 intr_fast = iflib_fast_intr; 5358 GROUPTASK_INIT(gtask, 0, fn, q); 5359 break; 5360 case IFLIB_INTR_RX: 5361 q = &ctx->ifc_rxqs[qid]; 5362 info = &ctx->ifc_rxqs[qid].ifr_filter_info; 5363 gtask = &ctx->ifc_rxqs[qid].ifr_task; 5364 tqg = qgroup_if_io_tqg; 5365 fn = _task_fn_rx; 5366 intr_fast = iflib_fast_intr; 5367 GROUPTASK_INIT(gtask, 0, fn, q); 5368 break; 5369 case IFLIB_INTR_RXTX: 5370 q = &ctx->ifc_rxqs[qid]; 5371 info = &ctx->ifc_rxqs[qid].ifr_filter_info; 5372 gtask = &ctx->ifc_rxqs[qid].ifr_task; 5373 tqg = qgroup_if_io_tqg; 5374 fn = _task_fn_rx; 5375 intr_fast = iflib_fast_intr_rxtx; 5376 GROUPTASK_INIT(gtask, 0, fn, q); 5377 break; 5378 case IFLIB_INTR_ADMIN: 5379 q = ctx; 5380 tqrid = -1; 5381 info = &ctx->ifc_filter_info; 5382 gtask = &ctx->ifc_admin_task; 5383 tqg = qgroup_if_config_tqg; 5384 fn = _task_fn_admin; 5385 intr_fast = iflib_fast_intr_ctx; 5386 break; 5387 default: 5388 panic("unknown net intr type"); 5389 } 5390 5391 info->ifi_filter = filter; 5392 info->ifi_filter_arg = filter_arg; 5393 info->ifi_task = gtask; 5394 info->ifi_ctx = q; 5395 5396 err = _iflib_irq_alloc(ctx, irq, rid, intr_fast, NULL, info, name); 5397 if (err != 0) { 5398 device_printf(ctx->ifc_dev, "_iflib_irq_alloc failed %d\n", err); 5399 return (err); 5400 } 5401 if (type == IFLIB_INTR_ADMIN) 5402 return (0); 5403 5404 if (tqrid != -1) { 5405 err = iflib_irq_set_affinity(ctx, rman_get_start(irq->ii_res), type, qid, gtask, tqg, q, name); 5406 if (err) 5407 return (err); 5408 } else { 5409 taskqgroup_attach(tqg, gtask, q, rman_get_start(irq->ii_res), name); 5410 } 5411 5412 return (0); 5413} 5414 5415void 5416iflib_softirq_alloc_generic(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type, void *arg, int qid, char *name) 5417{ 5418 struct grouptask *gtask; 5419 struct taskqgroup *tqg; 5420 gtask_fn_t *fn; 5421 void *q; 5422 int irq_num = -1; 5423 int err; 5424 5425 switch (type) { 5426 case IFLIB_INTR_TX: 5427 q = &ctx->ifc_txqs[qid]; 5428 gtask = &ctx->ifc_txqs[qid].ift_task; 5429 tqg = qgroup_if_io_tqg; 5430 fn = _task_fn_tx; 5431 if (irq != NULL) 5432 irq_num = rman_get_start(irq->ii_res); 5433 break; 5434 case IFLIB_INTR_RX: 5435 q = &ctx->ifc_rxqs[qid]; 5436 gtask = &ctx->ifc_rxqs[qid].ifr_task; 5437 tqg = qgroup_if_io_tqg; 5438 fn = _task_fn_rx; 5439 if (irq != NULL) 5440 irq_num = rman_get_start(irq->ii_res); 5441 break; 5442 case IFLIB_INTR_IOV: 5443 q = ctx; 5444 gtask = &ctx->ifc_vflr_task; 5445 tqg = qgroup_if_config_tqg; 5446 fn = _task_fn_iov; 5447 break; 5448 default: 5449 panic("unknown net intr type"); 5450 } 5451 GROUPTASK_INIT(gtask, 0, fn, q); 5452 if (irq_num != -1) { 5453 err = iflib_irq_set_affinity(ctx, irq_num, type, qid, gtask, tqg, q, name); 5454 if (err) 5455 taskqgroup_attach(tqg, gtask, q, irq_num, name); 5456 } 5457 else { 5458 taskqgroup_attach(tqg, gtask, q, irq_num, name); 5459 } 5460} 5461 5462void 5463iflib_irq_free(if_ctx_t ctx, if_irq_t irq) 5464{ 5465 if (irq->ii_tag) 5466 bus_teardown_intr(ctx->ifc_dev, irq->ii_res, irq->ii_tag); 5467 5468 if (irq->ii_res) 5469 bus_release_resource(ctx->ifc_dev, SYS_RES_IRQ, irq->ii_rid, irq->ii_res); 5470} 5471 5472static int 5473iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filter_arg, int *rid, char *name) 5474{ 5475 iflib_txq_t txq = ctx->ifc_txqs; 5476 iflib_rxq_t rxq = ctx->ifc_rxqs; 5477 if_irq_t irq = &ctx->ifc_legacy_irq; 5478 iflib_filter_info_t info; 5479 struct grouptask *gtask; 5480 struct taskqgroup *tqg; 5481 gtask_fn_t *fn; 5482 int tqrid; 5483 void *q; 5484 int err; 5485 5486 q = &ctx->ifc_rxqs[0]; 5487 info = &rxq[0].ifr_filter_info; 5488 gtask = &rxq[0].ifr_task; 5489 tqg = qgroup_if_io_tqg; 5490 tqrid = irq->ii_rid = *rid; 5491 fn = _task_fn_rx; 5492 5493 ctx->ifc_flags |= IFC_LEGACY; 5494 info->ifi_filter = filter; 5495 info->ifi_filter_arg = filter_arg; 5496 info->ifi_task = gtask; 5497 5498 /* We allocate a single interrupt resource */ 5499 if ((err = _iflib_irq_alloc(ctx, irq, tqrid, iflib_fast_intr_ctx, NULL, info, name)) != 0) 5500 return (err); 5501 GROUPTASK_INIT(gtask, 0, fn, q); 5502 taskqgroup_attach(tqg, gtask, q, rman_get_start(irq->ii_res), name); 5503 5504 GROUPTASK_INIT(&txq->ift_task, 0, _task_fn_tx, txq); 5505 taskqgroup_attach(qgroup_if_io_tqg, &txq->ift_task, txq, rman_get_start(irq->ii_res), "tx"); 5506 return (0); 5507} 5508 5509void 5510iflib_led_create(if_ctx_t ctx) 5511{ 5512 5513 ctx->ifc_led_dev = led_create(iflib_led_func, ctx, 5514 device_get_nameunit(ctx->ifc_dev)); 5515} 5516 5517void 5518iflib_tx_intr_deferred(if_ctx_t ctx, int txqid) 5519{ 5520 5521 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task); 5522} 5523 5524void 5525iflib_rx_intr_deferred(if_ctx_t ctx, int rxqid) 5526{ 5527 5528 GROUPTASK_ENQUEUE(&ctx->ifc_rxqs[rxqid].ifr_task); 5529} 5530 5531void 5532iflib_admin_intr_deferred(if_ctx_t ctx) 5533{ 5534#ifdef INVARIANTS 5535 struct grouptask *gtask; 5536 5537 gtask = &ctx->ifc_admin_task; 5538 MPASS(gtask != NULL && gtask->gt_taskqueue != NULL); 5539#endif 5540 5541 GROUPTASK_ENQUEUE(&ctx->ifc_admin_task); 5542} 5543 5544void 5545iflib_iov_intr_deferred(if_ctx_t ctx) 5546{ 5547 5548 GROUPTASK_ENQUEUE(&ctx->ifc_vflr_task); 5549} 5550 5551void 5552iflib_io_tqg_attach(struct grouptask *gt, void *uniq, int cpu, char *name) 5553{ 5554 5555 taskqgroup_attach_cpu(qgroup_if_io_tqg, gt, uniq, cpu, -1, name); 5556} 5557 5558void 5559iflib_config_gtask_init(if_ctx_t ctx, struct grouptask *gtask, gtask_fn_t *fn, 5560 char *name) 5561{ 5562 5563 GROUPTASK_INIT(gtask, 0, fn, ctx); 5564 taskqgroup_attach(qgroup_if_config_tqg, gtask, gtask, -1, name); 5565} 5566 5567void 5568iflib_config_gtask_deinit(struct grouptask *gtask) 5569{ 5570 5571 taskqgroup_detach(qgroup_if_config_tqg, gtask); 5572} 5573 5574void 5575iflib_link_state_change(if_ctx_t ctx, int link_state, uint64_t baudrate) 5576{ 5577 if_t ifp = ctx->ifc_ifp; 5578 iflib_txq_t txq = ctx->ifc_txqs; 5579 5580 if_setbaudrate(ifp, baudrate); 5581 if (baudrate >= IF_Gbps(10)) { 5582 STATE_LOCK(ctx); 5583 ctx->ifc_flags |= IFC_PREFETCH; 5584 STATE_UNLOCK(ctx); 5585 } 5586 /* If link down, disable watchdog */ 5587 if ((ctx->ifc_link_state == LINK_STATE_UP) && (link_state == LINK_STATE_DOWN)) { 5588 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxqsets; i++, txq++) 5589 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 5590 } 5591 ctx->ifc_link_state = link_state; 5592 if_link_state_change(ifp, link_state); 5593} 5594 5595static int 5596iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq) 5597{ 5598 int credits; 5599#ifdef INVARIANTS 5600 int credits_pre = txq->ift_cidx_processed; 5601#endif 5602 5603 if (ctx->isc_txd_credits_update == NULL) 5604 return (0); 5605 5606 if ((credits = ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, true)) == 0) 5607 return (0); 5608 5609 txq->ift_processed += credits; 5610 txq->ift_cidx_processed += credits; 5611 5612 MPASS(credits_pre + credits == txq->ift_cidx_processed); 5613 if (txq->ift_cidx_processed >= txq->ift_size) 5614 txq->ift_cidx_processed -= txq->ift_size; 5615 return (credits); 5616} 5617 5618static int 5619iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget) 5620{ 5621 5622 return (ctx->isc_rxd_available(ctx->ifc_softc, rxq->ifr_id, cidx, 5623 budget)); 5624} 5625 5626void 5627iflib_add_int_delay_sysctl(if_ctx_t ctx, const char *name, 5628 const char *description, if_int_delay_info_t info, 5629 int offset, int value) 5630{ 5631 info->iidi_ctx = ctx; 5632 info->iidi_offset = offset; 5633 info->iidi_value = value; 5634 SYSCTL_ADD_PROC(device_get_sysctl_ctx(ctx->ifc_dev), 5635 SYSCTL_CHILDREN(device_get_sysctl_tree(ctx->ifc_dev)), 5636 OID_AUTO, name, CTLTYPE_INT|CTLFLAG_RW, 5637 info, 0, iflib_sysctl_int_delay, "I", description); 5638} 5639 5640struct mtx * 5641iflib_ctx_lock_get(if_ctx_t ctx) 5642{ 5643 5644 return (&ctx->ifc_ctx_mtx); 5645} 5646 5647static int 5648iflib_msix_init(if_ctx_t ctx) 5649{ 5650 device_t dev = ctx->ifc_dev; 5651 if_shared_ctx_t sctx = ctx->ifc_sctx; 5652 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 5653 int vectors, queues, rx_queues, tx_queues, queuemsgs, msgs; 5654 int iflib_num_tx_queues, iflib_num_rx_queues; 5655 int err, admincnt, bar; 5656 5657 iflib_num_tx_queues = ctx->ifc_sysctl_ntxqs; 5658 iflib_num_rx_queues = ctx->ifc_sysctl_nrxqs; 5659 5660 device_printf(dev, "msix_init qsets capped at %d\n", imax(scctx->isc_ntxqsets, scctx->isc_nrxqsets)); 5661 5662 bar = ctx->ifc_softc_ctx.isc_msix_bar; 5663 admincnt = sctx->isc_admin_intrcnt; 5664 /* Override by global tuneable */ 5665 { 5666 int i; 5667 size_t len = sizeof(i); 5668 err = kernel_sysctlbyname(curthread, "hw.pci.enable_msix", &i, &len, NULL, 0, NULL, 0); 5669 if (err == 0) { 5670 if (i == 0) 5671 goto msi; 5672 } 5673 else { 5674 device_printf(dev, "unable to read hw.pci.enable_msix."); 5675 } 5676 } 5677 /* Override by tuneable */ 5678 if (scctx->isc_disable_msix) 5679 goto msi; 5680 5681 /* 5682 ** When used in a virtualized environment 5683 ** PCI BUSMASTER capability may not be set 5684 ** so explicity set it here and rewrite 5685 ** the ENABLE in the MSIX control register 5686 ** at this point to cause the host to 5687 ** successfully initialize us. 5688 */ 5689 { 5690 int msix_ctrl, rid; 5691 5692 pci_enable_busmaster(dev); 5693 rid = 0; 5694 if (pci_find_cap(dev, PCIY_MSIX, &rid) == 0 && rid != 0) { 5695 rid += PCIR_MSIX_CTRL; 5696 msix_ctrl = pci_read_config(dev, rid, 2); 5697 msix_ctrl |= PCIM_MSIXCTRL_MSIX_ENABLE; 5698 pci_write_config(dev, rid, msix_ctrl, 2); 5699 } else { 5700 device_printf(dev, "PCIY_MSIX capability not found; " 5701 "or rid %d == 0.\n", rid); 5702 goto msi; 5703 } 5704 } 5705 5706 /* 5707 * bar == -1 => "trust me I know what I'm doing" 5708 * Some drivers are for hardware that is so shoddily 5709 * documented that no one knows which bars are which 5710 * so the developer has to map all bars. This hack 5711 * allows shoddy garbage to use msix in this framework. 5712 */ 5713 if (bar != -1) { 5714 ctx->ifc_msix_mem = bus_alloc_resource_any(dev, 5715 SYS_RES_MEMORY, &bar, RF_ACTIVE); 5716 if (ctx->ifc_msix_mem == NULL) { 5717 /* May not be enabled */ 5718 device_printf(dev, "Unable to map MSIX table \n"); 5719 goto msi; 5720 } 5721 } 5722 /* First try MSI/X */ 5723 if ((msgs = pci_msix_count(dev)) == 0) { /* system has msix disabled */ 5724 device_printf(dev, "System has MSIX disabled \n"); 5725 bus_release_resource(dev, SYS_RES_MEMORY, 5726 bar, ctx->ifc_msix_mem); 5727 ctx->ifc_msix_mem = NULL; 5728 goto msi; 5729 } 5730#if IFLIB_DEBUG 5731 /* use only 1 qset in debug mode */ 5732 queuemsgs = min(msgs - admincnt, 1); 5733#else 5734 queuemsgs = msgs - admincnt; 5735#endif 5736#ifdef RSS 5737 queues = imin(queuemsgs, rss_getnumbuckets()); 5738#else 5739 queues = queuemsgs; 5740#endif 5741 queues = imin(CPU_COUNT(&ctx->ifc_cpus), queues); 5742 device_printf(dev, "pxm cpus: %d queue msgs: %d admincnt: %d\n", 5743 CPU_COUNT(&ctx->ifc_cpus), queuemsgs, admincnt); 5744#ifdef RSS 5745 /* If we're doing RSS, clamp at the number of RSS buckets */ 5746 if (queues > rss_getnumbuckets()) 5747 queues = rss_getnumbuckets(); 5748#endif 5749 if (iflib_num_rx_queues > 0 && iflib_num_rx_queues < queuemsgs - admincnt) 5750 rx_queues = iflib_num_rx_queues; 5751 else 5752 rx_queues = queues; 5753 5754 if (rx_queues > scctx->isc_nrxqsets) 5755 rx_queues = scctx->isc_nrxqsets; 5756 5757 /* 5758 * We want this to be all logical CPUs by default 5759 */ 5760 if (iflib_num_tx_queues > 0 && iflib_num_tx_queues < queues) 5761 tx_queues = iflib_num_tx_queues; 5762 else 5763 tx_queues = mp_ncpus; 5764 5765 if (tx_queues > scctx->isc_ntxqsets) 5766 tx_queues = scctx->isc_ntxqsets; 5767 5768 if (ctx->ifc_sysctl_qs_eq_override == 0) { 5769#ifdef INVARIANTS 5770 if (tx_queues != rx_queues) 5771 device_printf(dev, 5772 "queue equality override not set, capping rx_queues at %d and tx_queues at %d\n", 5773 min(rx_queues, tx_queues), min(rx_queues, tx_queues)); 5774#endif 5775 tx_queues = min(rx_queues, tx_queues); 5776 rx_queues = min(rx_queues, tx_queues); 5777 } 5778 5779 device_printf(dev, "using %d rx queues %d tx queues \n", rx_queues, tx_queues); 5780 5781 vectors = rx_queues + admincnt; 5782 if ((err = pci_alloc_msix(dev, &vectors)) == 0) { 5783 device_printf(dev, "Using MSI-X interrupts with %d vectors\n", 5784 vectors); 5785 scctx->isc_vectors = vectors; 5786 scctx->isc_nrxqsets = rx_queues; 5787 scctx->isc_ntxqsets = tx_queues; 5788 scctx->isc_intr = IFLIB_INTR_MSIX; 5789 5790 return (vectors); 5791 } else { 5792 device_printf(dev, 5793 "failed to allocate %d msix vectors, err: %d - using MSI\n", vectors, err); 5794 } 5795msi: 5796 vectors = pci_msi_count(dev); 5797 scctx->isc_nrxqsets = 1; 5798 scctx->isc_ntxqsets = 1; 5799 scctx->isc_vectors = vectors; 5800 if (vectors == 1 && pci_alloc_msi(dev, &vectors) == 0) { 5801 device_printf(dev,"Using an MSI interrupt\n"); 5802 scctx->isc_intr = IFLIB_INTR_MSI; 5803 } else { 5804 device_printf(dev,"Using a Legacy interrupt\n"); 5805 scctx->isc_intr = IFLIB_INTR_LEGACY; 5806 } 5807 5808 return (vectors); 5809} 5810 5811char * ring_states[] = { "IDLE", "BUSY", "STALLED", "ABDICATED" }; 5812 5813static int 5814mp_ring_state_handler(SYSCTL_HANDLER_ARGS) 5815{ 5816 int rc; 5817 uint16_t *state = ((uint16_t *)oidp->oid_arg1); 5818 struct sbuf *sb; 5819 char *ring_state = "UNKNOWN"; 5820 5821 /* XXX needed ? */ 5822 rc = sysctl_wire_old_buffer(req, 0); 5823 MPASS(rc == 0); 5824 if (rc != 0) 5825 return (rc); 5826 sb = sbuf_new_for_sysctl(NULL, NULL, 80, req); 5827 MPASS(sb != NULL); 5828 if (sb == NULL) 5829 return (ENOMEM); 5830 if (state[3] <= 3) 5831 ring_state = ring_states[state[3]]; 5832 5833 sbuf_printf(sb, "pidx_head: %04hd pidx_tail: %04hd cidx: %04hd state: %s", 5834 state[0], state[1], state[2], ring_state); 5835 rc = sbuf_finish(sb); 5836 sbuf_delete(sb); 5837 return(rc); 5838} 5839 5840enum iflib_ndesc_handler { 5841 IFLIB_NTXD_HANDLER, 5842 IFLIB_NRXD_HANDLER, 5843}; 5844 5845static int 5846mp_ndesc_handler(SYSCTL_HANDLER_ARGS) 5847{ 5848 if_ctx_t ctx = (void *)arg1; 5849 enum iflib_ndesc_handler type = arg2; 5850 char buf[256] = {0}; 5851 qidx_t *ndesc; 5852 char *p, *next; 5853 int nqs, rc, i; 5854 5855 MPASS(type == IFLIB_NTXD_HANDLER || type == IFLIB_NRXD_HANDLER); 5856 5857 nqs = 8; 5858 switch(type) { 5859 case IFLIB_NTXD_HANDLER: 5860 ndesc = ctx->ifc_sysctl_ntxds; 5861 if (ctx->ifc_sctx) 5862 nqs = ctx->ifc_sctx->isc_ntxqs; 5863 break; 5864 case IFLIB_NRXD_HANDLER: 5865 ndesc = ctx->ifc_sysctl_nrxds; 5866 if (ctx->ifc_sctx) 5867 nqs = ctx->ifc_sctx->isc_nrxqs; 5868 break; 5869 } 5870 if (nqs == 0) 5871 nqs = 8; 5872 5873 for (i=0; i<8; i++) { 5874 if (i >= nqs) 5875 break; 5876 if (i) 5877 strcat(buf, ","); 5878 sprintf(strchr(buf, 0), "%d", ndesc[i]); 5879 } 5880 5881 rc = sysctl_handle_string(oidp, buf, sizeof(buf), req); 5882 if (rc || req->newptr == NULL) 5883 return rc; 5884 5885 for (i = 0, next = buf, p = strsep(&next, " ,"); i < 8 && p; 5886 i++, p = strsep(&next, " ,")) { 5887 ndesc[i] = strtoul(p, NULL, 10); 5888 } 5889 5890 return(rc); 5891} 5892 5893#define NAME_BUFLEN 32 5894static void 5895iflib_add_device_sysctl_pre(if_ctx_t ctx) 5896{ 5897 device_t dev = iflib_get_dev(ctx); 5898 struct sysctl_oid_list *child, *oid_list; 5899 struct sysctl_ctx_list *ctx_list; 5900 struct sysctl_oid *node; 5901 5902 ctx_list = device_get_sysctl_ctx(dev); 5903 child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev)); 5904 ctx->ifc_sysctl_node = node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, "iflib", 5905 CTLFLAG_RD, NULL, "IFLIB fields"); 5906 oid_list = SYSCTL_CHILDREN(node); 5907 5908 SYSCTL_ADD_CONST_STRING(ctx_list, oid_list, OID_AUTO, "driver_version", 5909 CTLFLAG_RD, ctx->ifc_sctx->isc_driver_version, 5910 "driver version"); 5911 5912 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_ntxqs", 5913 CTLFLAG_RWTUN, &ctx->ifc_sysctl_ntxqs, 0, 5914 "# of txqs to use, 0 => use default #"); 5915 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_nrxqs", 5916 CTLFLAG_RWTUN, &ctx->ifc_sysctl_nrxqs, 0, 5917 "# of rxqs to use, 0 => use default #"); 5918 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_qs_enable", 5919 CTLFLAG_RWTUN, &ctx->ifc_sysctl_qs_eq_override, 0, 5920 "permit #txq != #rxq"); 5921 SYSCTL_ADD_INT(ctx_list, oid_list, OID_AUTO, "disable_msix", 5922 CTLFLAG_RWTUN, &ctx->ifc_softc_ctx.isc_disable_msix, 0, 5923 "disable MSIX (default 0)"); 5924 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "rx_budget", 5925 CTLFLAG_RWTUN, &ctx->ifc_sysctl_rx_budget, 0, 5926 "set the rx budget"); 5927 5928 /* XXX change for per-queue sizes */ 5929 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_ntxds", 5930 CTLTYPE_STRING|CTLFLAG_RWTUN, ctx, IFLIB_NTXD_HANDLER, 5931 mp_ndesc_handler, "A", 5932 "list of # of tx descriptors to use, 0 = use default #"); 5933 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_nrxds", 5934 CTLTYPE_STRING|CTLFLAG_RWTUN, ctx, IFLIB_NRXD_HANDLER, 5935 mp_ndesc_handler, "A", 5936 "list of # of rx descriptors to use, 0 = use default #"); 5937} 5938 5939static void 5940iflib_add_device_sysctl_post(if_ctx_t ctx) 5941{ 5942 if_shared_ctx_t sctx = ctx->ifc_sctx; 5943 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 5944 device_t dev = iflib_get_dev(ctx); 5945 struct sysctl_oid_list *child; 5946 struct sysctl_ctx_list *ctx_list; 5947 iflib_fl_t fl; 5948 iflib_txq_t txq; 5949 iflib_rxq_t rxq; 5950 int i, j; 5951 char namebuf[NAME_BUFLEN]; 5952 char *qfmt; 5953 struct sysctl_oid *queue_node, *fl_node, *node; 5954 struct sysctl_oid_list *queue_list, *fl_list; 5955 ctx_list = device_get_sysctl_ctx(dev); 5956 5957 node = ctx->ifc_sysctl_node; 5958 child = SYSCTL_CHILDREN(node); 5959 5960 if (scctx->isc_ntxqsets > 100) 5961 qfmt = "txq%03d"; 5962 else if (scctx->isc_ntxqsets > 10) 5963 qfmt = "txq%02d"; 5964 else 5965 qfmt = "txq%d"; 5966 for (i = 0, txq = ctx->ifc_txqs; i < scctx->isc_ntxqsets; i++, txq++) { 5967 snprintf(namebuf, NAME_BUFLEN, qfmt, i); 5968 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf, 5969 CTLFLAG_RD, NULL, "Queue Name"); 5970 queue_list = SYSCTL_CHILDREN(queue_node); 5971#if MEMORY_LOGGING 5972 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_dequeued", 5973 CTLFLAG_RD, 5974 &txq->ift_dequeued, "total mbufs freed"); 5975 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_enqueued", 5976 CTLFLAG_RD, 5977 &txq->ift_enqueued, "total mbufs enqueued"); 5978#endif 5979 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag", 5980 CTLFLAG_RD, 5981 &txq->ift_mbuf_defrag, "# of times m_defrag was called"); 5982 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "m_pullups", 5983 CTLFLAG_RD, 5984 &txq->ift_pullups, "# of times m_pullup was called"); 5985 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag_failed", 5986 CTLFLAG_RD, 5987 &txq->ift_mbuf_defrag_failed, "# of times m_defrag failed"); 5988 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_desc_avail", 5989 CTLFLAG_RD, 5990 &txq->ift_no_desc_avail, "# of times no descriptors were available"); 5991 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "tx_map_failed", 5992 CTLFLAG_RD, 5993 &txq->ift_map_failed, "# of times dma map failed"); 5994 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txd_encap_efbig", 5995 CTLFLAG_RD, 5996 &txq->ift_txd_encap_efbig, "# of times txd_encap returned EFBIG"); 5997 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_tx_dma_setup", 5998 CTLFLAG_RD, 5999 &txq->ift_no_tx_dma_setup, "# of times map failed for other than EFBIG"); 6000 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_pidx", 6001 CTLFLAG_RD, 6002 &txq->ift_pidx, 1, "Producer Index"); 6003 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx", 6004 CTLFLAG_RD, 6005 &txq->ift_cidx, 1, "Consumer Index"); 6006 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx_processed", 6007 CTLFLAG_RD, 6008 &txq->ift_cidx_processed, 1, "Consumer Index seen by credit update"); 6009 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_in_use", 6010 CTLFLAG_RD, 6011 &txq->ift_in_use, 1, "descriptors in use"); 6012 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_processed", 6013 CTLFLAG_RD, 6014 &txq->ift_processed, "descriptors procesed for clean"); 6015 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_cleaned", 6016 CTLFLAG_RD, 6017 &txq->ift_cleaned, "total cleaned"); 6018 SYSCTL_ADD_PROC(ctx_list, queue_list, OID_AUTO, "ring_state", 6019 CTLTYPE_STRING | CTLFLAG_RD, __DEVOLATILE(uint64_t *, &txq->ift_br->state), 6020 0, mp_ring_state_handler, "A", "soft ring state"); 6021 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_enqueues", 6022 CTLFLAG_RD, &txq->ift_br->enqueues, 6023 "# of enqueues to the mp_ring for this queue"); 6024 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_drops", 6025 CTLFLAG_RD, &txq->ift_br->drops, 6026 "# of drops in the mp_ring for this queue"); 6027 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_starts", 6028 CTLFLAG_RD, &txq->ift_br->starts, 6029 "# of normal consumer starts in the mp_ring for this queue"); 6030 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_stalls", 6031 CTLFLAG_RD, &txq->ift_br->stalls, 6032 "# of consumer stalls in the mp_ring for this queue"); 6033 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_restarts", 6034 CTLFLAG_RD, &txq->ift_br->restarts, 6035 "# of consumer restarts in the mp_ring for this queue"); 6036 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_abdications", 6037 CTLFLAG_RD, &txq->ift_br->abdications, 6038 "# of consumer abdications in the mp_ring for this queue"); 6039 } 6040 6041 if (scctx->isc_nrxqsets > 100) 6042 qfmt = "rxq%03d"; 6043 else if (scctx->isc_nrxqsets > 10) 6044 qfmt = "rxq%02d"; 6045 else 6046 qfmt = "rxq%d"; 6047 for (i = 0, rxq = ctx->ifc_rxqs; i < scctx->isc_nrxqsets; i++, rxq++) { 6048 snprintf(namebuf, NAME_BUFLEN, qfmt, i); 6049 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf, 6050 CTLFLAG_RD, NULL, "Queue Name"); 6051 queue_list = SYSCTL_CHILDREN(queue_node); 6052 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 6053 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_pidx", 6054 CTLFLAG_RD, 6055 &rxq->ifr_cq_pidx, 1, "Producer Index"); 6056 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_cidx", 6057 CTLFLAG_RD, 6058 &rxq->ifr_cq_cidx, 1, "Consumer Index"); 6059 } 6060 6061 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) { 6062 snprintf(namebuf, NAME_BUFLEN, "rxq_fl%d", j); 6063 fl_node = SYSCTL_ADD_NODE(ctx_list, queue_list, OID_AUTO, namebuf, 6064 CTLFLAG_RD, NULL, "freelist Name"); 6065 fl_list = SYSCTL_CHILDREN(fl_node); 6066 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "pidx", 6067 CTLFLAG_RD, 6068 &fl->ifl_pidx, 1, "Producer Index"); 6069 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "cidx", 6070 CTLFLAG_RD, 6071 &fl->ifl_cidx, 1, "Consumer Index"); 6072 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "credits", 6073 CTLFLAG_RD, 6074 &fl->ifl_credits, 1, "credits available"); 6075#if MEMORY_LOGGING 6076 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_enqueued", 6077 CTLFLAG_RD, 6078 &fl->ifl_m_enqueued, "mbufs allocated"); 6079 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_dequeued", 6080 CTLFLAG_RD, 6081 &fl->ifl_m_dequeued, "mbufs freed"); 6082 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_enqueued", 6083 CTLFLAG_RD, 6084 &fl->ifl_cl_enqueued, "clusters allocated"); 6085 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_dequeued", 6086 CTLFLAG_RD, 6087 &fl->ifl_cl_dequeued, "clusters freed"); 6088#endif 6089 6090 } 6091 } 6092 6093} 6094 6095void 6096iflib_request_reset(if_ctx_t ctx) 6097{ 6098 6099 STATE_LOCK(ctx); 6100 ctx->ifc_flags |= IFC_DO_RESET; 6101 STATE_UNLOCK(ctx); 6102} 6103 6104#ifndef __NO_STRICT_ALIGNMENT 6105static struct mbuf * 6106iflib_fixup_rx(struct mbuf *m) 6107{ 6108 struct mbuf *n; 6109 6110 if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN)) { 6111 bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len); 6112 m->m_data += ETHER_HDR_LEN; 6113 n = m; 6114 } else { 6115 MGETHDR(n, M_NOWAIT, MT_DATA); 6116 if (n == NULL) { 6117 m_freem(m); 6118 return (NULL); 6119 } 6120 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN); 6121 m->m_data += ETHER_HDR_LEN; 6122 m->m_len -= ETHER_HDR_LEN; 6123 n->m_len = ETHER_HDR_LEN; 6124 M_MOVE_PKTHDR(n, m); 6125 n->m_next = m; 6126 } 6127 return (n); 6128} 6129#endif 6130