sb_zbpci.c revision 203508
1/*- 2 * Copyright (c) 2009 Neelkanth Natu 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27#include <sys/param.h> 28#include <sys/types.h> 29#include <sys/kernel.h> 30#include <sys/systm.h> 31#include <sys/module.h> 32#include <sys/bus.h> 33#include <sys/pcpu.h> 34#include <sys/smp.h> 35 36#include <vm/vm.h> 37#include <vm/vm_param.h> 38#include <vm/vm_kern.h> 39#include <vm/vm_extern.h> 40#include <vm/pmap.h> 41 42#include <dev/pci/pcireg.h> 43#include <dev/pci/pcivar.h> 44#include <dev/pci/pcib_private.h> 45 46#include <machine/pmap.h> 47#include <machine/resource.h> 48 49#include "pcib_if.h" 50 51#include "sb_scd.h" 52 53__FBSDID("$FreeBSD: head/sys/mips/sibyte/sb_zbpci.c 203508 2010-02-05 02:40:42Z neel $"); 54 55static struct { 56 vm_offset_t vaddr; 57 vm_paddr_t paddr; 58} zbpci_config_space[MAXCPU]; 59 60static const vm_paddr_t CFG_PADDR_BASE = 0xFE000000; 61 62static int 63zbpci_probe(device_t dev) 64{ 65 66 device_set_desc(dev, "Broadcom/Sibyte PCI I/O Bridge"); 67 return (0); 68} 69 70static int 71zbpci_attach(device_t dev) 72{ 73 int n, rid, size; 74 vm_offset_t va; 75 struct resource *res; 76 77 /* 78 * Reserve the the physical memory that is used to read/write to the 79 * pci config space but don't activate it. We are using a page worth 80 * of KVA as a window over this region. 81 */ 82 rid = 0; 83 size = (PCI_BUSMAX + 1) * (PCI_SLOTMAX + 1) * (PCI_FUNCMAX + 1) * 256; 84 res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, CFG_PADDR_BASE, 85 CFG_PADDR_BASE + size - 1, size, 0); 86 if (res == NULL) 87 panic("Cannot allocate resource for config space accesses."); 88 89 /* 90 * Allocate KVA for accessing PCI config space. 91 */ 92 va = kmem_alloc_nofault(kernel_map, PAGE_SIZE * mp_ncpus); 93 if (va == 0) { 94 device_printf(dev, "Cannot allocate virtual addresses for " 95 "config space access.\n"); 96 return (ENOMEM); 97 } 98 99 for (n = 0; n < mp_ncpus; ++n) 100 zbpci_config_space[n].vaddr = va + n * PAGE_SIZE; 101 102 /* 103 * Sibyte has the PCI bus hierarchy rooted at bus 0 and HT-PCI 104 * hierarchy rooted at bus 1. 105 */ 106 if (device_add_child(dev, "pci", 0) == NULL) 107 panic("zbpci_attach: could not add pci bus 0.\n"); 108 109 if (device_add_child(dev, "pci", 1) == NULL) 110 panic("zbpci_attach: could not add pci bus 1.\n"); 111 112 if (bootverbose) 113 device_printf(dev, "attached.\n"); 114 115 return (bus_generic_attach(dev)); 116} 117 118static int 119zbpci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 120{ 121 122 switch (which) { 123 case PCIB_IVAR_DOMAIN: 124 *result = 0; /* single PCI domain */ 125 return (0); 126 case PCIB_IVAR_BUS: 127 *result = device_get_unit(child); /* PCI bus 0 or 1 */ 128 return (0); 129 default: 130 return (ENOENT); 131 } 132} 133 134/* 135 * We rely on the CFE to have configured the intline correctly to point to 136 * one of PCI-A/PCI-B/PCI-C/PCI-D in the interupt mapper. 137 */ 138static int 139zbpci_route_interrupt(device_t pcib, device_t dev, int pin) 140{ 141 142 return (PCI_INVALID_IRQ); 143} 144 145/* 146 * This function is expected to be called in a critical section since it 147 * changes the per-cpu pci config space va-to-pa mappings. 148 */ 149static vm_offset_t 150zbpci_config_space_va(int bus, int slot, int func, int reg, int bytes) 151{ 152 int cpu; 153 vm_offset_t va_page; 154 vm_paddr_t pa, pa_page; 155 156 if (bus <= PCI_BUSMAX && slot <= PCI_SLOTMAX && func <= PCI_FUNCMAX && 157 reg <= PCI_REGMAX && (bytes == 1 || bytes == 2 || bytes == 4) && 158 ((reg & (bytes - 1)) == 0)) { 159 cpu = PCPU_GET(cpuid); 160 va_page = zbpci_config_space[cpu].vaddr; 161 pa = CFG_PADDR_BASE | 162 (bus << 16) | (slot << 11) | (func << 8) | reg; 163 pa_page = pa & ~(PAGE_SIZE - 1); 164 if (zbpci_config_space[cpu].paddr != pa_page) { 165 pmap_kremove(va_page); 166 pmap_kenter(va_page, pa_page); 167 zbpci_config_space[cpu].paddr = pa_page; 168 } 169 return (va_page + (pa - pa_page)); 170 } else { 171 return (0); 172 } 173} 174 175static uint32_t 176zbpci_read_config(device_t dev, u_int b, u_int s, u_int f, u_int r, int w) 177{ 178 uint32_t data; 179 vm_offset_t va; 180 181 critical_enter(); 182 183 va = zbpci_config_space_va(b, s, f, r, w); 184 if (va == 0) { 185 panic("zbpci_read_config: invalid %d/%d/%d[%d] %d\n", 186 b, s, f, r, w); 187 } 188 189 switch (w) { 190 case 4: 191 data = *(uint32_t *)va; 192 break; 193 case 2: 194 data = *(uint16_t *)va; 195 break; 196 case 1: 197 data = *(uint8_t *)va; 198 break; 199 default: 200 panic("zbpci_read_config: invalid width %d\n", w); 201 } 202 203 critical_exit(); 204 205 return (data); 206} 207 208static void 209zbpci_write_config(device_t d, u_int b, u_int s, u_int f, u_int r, 210 uint32_t data, int w) 211{ 212 vm_offset_t va; 213 214 critical_enter(); 215 216 va = zbpci_config_space_va(b, s, f, r, w); 217 if (va == 0) { 218 panic("zbpci_write_config: invalid %d/%d/%d[%d] %d/%d\n", 219 b, s, f, r, data, w); 220 } 221 222 switch (w) { 223 case 4: 224 *(uint32_t *)va = data; 225 break; 226 case 2: 227 *(uint16_t *)va = data; 228 break; 229 case 1: 230 *(uint8_t *)va = data; 231 break; 232 default: 233 panic("zbpci_write_config: invalid width %d\n", w); 234 } 235 236 critical_exit(); 237} 238 239static device_method_t zbpci_methods[] ={ 240 /* Device interface */ 241 DEVMETHOD(device_probe, zbpci_probe), 242 DEVMETHOD(device_attach, zbpci_attach), 243 DEVMETHOD(device_detach, bus_generic_detach), 244 DEVMETHOD(device_shutdown, bus_generic_shutdown), 245 DEVMETHOD(device_suspend, bus_generic_suspend), 246 DEVMETHOD(device_resume, bus_generic_resume), 247 248 /* Bus interface */ 249 DEVMETHOD(bus_read_ivar, zbpci_read_ivar), 250 DEVMETHOD(bus_write_ivar, bus_generic_write_ivar), 251 DEVMETHOD(bus_alloc_resource, bus_generic_alloc_resource), 252 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 253 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 254 DEVMETHOD(bus_release_resource, bus_generic_release_resource), 255 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 256 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 257 DEVMETHOD(bus_add_child, bus_generic_add_child), 258 259 /* pcib interface */ 260 DEVMETHOD(pcib_maxslots, pcib_maxslots), 261 DEVMETHOD(pcib_read_config, zbpci_read_config), 262 DEVMETHOD(pcib_write_config, zbpci_write_config), 263 DEVMETHOD(pcib_route_interrupt, zbpci_route_interrupt), 264 265 { 0, 0 } 266}; 267 268/* 269 * The "zbpci" class inherits from the "pcib" base class. Therefore in 270 * addition to drivers that belong to the "zbpci" class we will also 271 * consider drivers belonging to the "pcib" when probing children of 272 * "zbpci". 273 */ 274DECLARE_CLASS(pcib_driver); 275DEFINE_CLASS_1(zbpci, zbpci_driver, zbpci_methods, 0, pcib_driver); 276 277static devclass_t zbpci_devclass; 278 279DRIVER_MODULE(zbpci, zbbus, zbpci_driver, zbpci_devclass, 0, 0); 280