sb_machdep.c revision 232615
1195333Simp/*- 2195333Simp * Copyright (c) 2007 Bruce M. Simpson. 3195333Simp * All rights reserved. 4195333Simp * 5195333Simp * Redistribution and use in source and binary forms, with or without 6195333Simp * modification, are permitted provided that the following conditions 7195333Simp * are met: 8195333Simp * 1. Redistributions of source code must retain the above copyright 9195333Simp * notice, this list of conditions and the following disclaimer. 10195333Simp * 2. Redistributions in binary form must reproduce the above copyright 11195333Simp * notice, this list of conditions and the following disclaimer in the 12195333Simp * documentation and/or other materials provided with the distribution. 13195333Simp * 14195333Simp * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15195333Simp * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16195333Simp * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17195333Simp * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18195333Simp * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19195333Simp * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20195333Simp * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21195333Simp * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22195333Simp * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23195333Simp * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24195333Simp * SUCH DAMAGE. 25195333Simp */ 26195333Simp 27195333Simp#include <sys/cdefs.h> 28195333Simp__FBSDID("$FreeBSD: head/sys/mips/sibyte/sb_machdep.c 232615 2012-03-06 19:01:32Z jmallett $"); 29195333Simp 30195333Simp#include "opt_ddb.h" 31195333Simp#include "opt_kdb.h" 32195333Simp 33195333Simp#include <sys/param.h> 34195333Simp#include <sys/conf.h> 35195333Simp#include <sys/kernel.h> 36195333Simp#include <sys/systm.h> 37195333Simp#include <sys/imgact.h> 38195333Simp#include <sys/bio.h> 39195333Simp#include <sys/buf.h> 40195333Simp#include <sys/bus.h> 41195333Simp#include <sys/cpu.h> 42195333Simp#include <sys/cons.h> 43195333Simp#include <sys/exec.h> 44195333Simp#include <sys/ucontext.h> 45195333Simp#include <sys/proc.h> 46195333Simp#include <sys/kdb.h> 47195333Simp#include <sys/ptrace.h> 48195333Simp#include <sys/reboot.h> 49195333Simp#include <sys/signalvar.h> 50195333Simp#include <sys/sysent.h> 51195333Simp#include <sys/sysproto.h> 52195333Simp#include <sys/user.h> 53205364Sneel#include <sys/timetc.h> 54195333Simp 55195333Simp#include <vm/vm.h> 56195333Simp#include <vm/vm_object.h> 57195333Simp#include <vm/vm_page.h> 58195333Simp#include <vm/vm_pager.h> 59195333Simp 60195333Simp#include <machine/cache.h> 61195333Simp#include <machine/clock.h> 62195333Simp#include <machine/cpu.h> 63195333Simp#include <machine/cpuinfo.h> 64195333Simp#include <machine/cpufunc.h> 65195333Simp#include <machine/cpuregs.h> 66195333Simp#include <machine/hwfunc.h> 67195333Simp#include <machine/intr_machdep.h> 68195333Simp#include <machine/locore.h> 69195333Simp#include <machine/md_var.h> 70195333Simp#include <machine/pte.h> 71195333Simp#include <machine/sigframe.h> 72195333Simp#include <machine/trap.h> 73195333Simp#include <machine/vmparam.h> 74195333Simp 75203697Sneel#ifdef SMP 76208253Sneel#include <sys/smp.h> 77203697Sneel#include <machine/smp.h> 78203697Sneel#endif 79203697Sneel 80195333Simp#ifdef CFE 81195333Simp#include <dev/cfe/cfe_api.h> 82195333Simp#endif 83195333Simp 84195333Simp#include "sb_scd.h" 85195333Simp 86195333Simp#ifdef DDB 87195333Simp#ifndef KDB 88195333Simp#error KDB must be enabled in order for DDB to work! 89195333Simp#endif 90195333Simp#endif 91195333Simp 92195333Simp#ifdef CFE_ENV 93195333Simpextern void cfe_env_init(void); 94195333Simp#endif 95195333Simp 96195333Simpextern int *edata; 97195333Simpextern int *end; 98195333Simp 99203000Sneelextern char MipsTLBMiss[], MipsTLBMissEnd[]; 100203000Sneel 101198669Srrsvoid 102198669Srrsplatform_cpu_init() 103198669Srrs{ 104198669Srrs /* Nothing special */ 105198669Srrs} 106198669Srrs 107195333Simpstatic void 108203510Sneelsb_intr_init(int cpuid) 109203510Sneel{ 110203510Sneel int intrnum, intsrc; 111203510Sneel 112203510Sneel /* 113203510Sneel * Disable all sources to the interrupt mapper and setup the mapping 114203510Sneel * between an interrupt source and the mips hard interrupt number. 115203510Sneel */ 116203510Sneel for (intsrc = 0; intsrc < NUM_INTSRC; ++intsrc) { 117203510Sneel intrnum = sb_route_intsrc(intsrc); 118203510Sneel sb_disable_intsrc(cpuid, intsrc); 119203510Sneel sb_write_intmap(cpuid, intsrc, intrnum); 120203697Sneel#ifdef SMP 121203697Sneel /* 122203697Sneel * Set up the mailbox interrupt mapping. 123203697Sneel * 124203697Sneel * The mailbox interrupt is "special" in that it is not shared 125203697Sneel * with any other interrupt source. 126203697Sneel */ 127203697Sneel if (intsrc == INTSRC_MAILBOX3) { 128203697Sneel intrnum = platform_ipi_intrnum(); 129203697Sneel sb_write_intmap(cpuid, INTSRC_MAILBOX3, intrnum); 130203697Sneel sb_enable_intsrc(cpuid, INTSRC_MAILBOX3); 131203697Sneel } 132203697Sneel#endif 133203510Sneel } 134203510Sneel} 135203510Sneel 136203510Sneelstatic void 137195333Simpmips_init(void) 138195333Simp{ 139216318Sgonzo int i, j, cfe_mem_idx, tmp; 140195333Simp uint64_t maxmem; 141195333Simp 142195333Simp#ifdef CFE_ENV 143195333Simp cfe_env_init(); 144195333Simp#endif 145195333Simp 146195333Simp TUNABLE_INT_FETCH("boothowto", &boothowto); 147195333Simp 148195333Simp if (boothowto & RB_VERBOSE) 149195333Simp bootverbose++; 150195333Simp 151195333Simp#ifdef MAXMEM 152195333Simp tmp = MAXMEM; 153195333Simp#else 154195333Simp tmp = 0; 155195333Simp#endif 156195333Simp TUNABLE_INT_FETCH("hw.physmem", &tmp); 157195333Simp maxmem = (uint64_t)tmp * 1024; 158195333Simp 159207131Sjmallett /* 160207131Sjmallett * XXX 161207131Sjmallett * If we used vm_paddr_t consistently in pmap, etc., we could 162207131Sjmallett * use 64-bit page numbers on !n64 systems, too, like i386 163207131Sjmallett * does with PAE. 164207131Sjmallett */ 165207131Sjmallett#if !defined(__mips_n64) 166207131Sjmallett if (maxmem == 0 || maxmem > 0xffffffff) 167207131Sjmallett maxmem = 0xffffffff; 168207131Sjmallett#endif 169207131Sjmallett 170195333Simp#ifdef CFE 171195333Simp /* 172195333Simp * Query DRAM memory map from CFE. 173195333Simp */ 174195333Simp physmem = 0; 175195333Simp cfe_mem_idx = 0; 176195333Simp for (i = 0; i < 10; i += 2) { 177195333Simp int result; 178195333Simp uint64_t addr, len, type; 179195333Simp 180195333Simp result = cfe_enummem(cfe_mem_idx++, 0, &addr, &len, &type); 181195333Simp if (result < 0) { 182195333Simp phys_avail[i] = phys_avail[i + 1] = 0; 183195333Simp break; 184195333Simp } 185195333Simp 186195333Simp KASSERT(type == CFE_MI_AVAILABLE, 187195333Simp ("CFE DRAM region is not available?")); 188195333Simp 189195333Simp if (bootverbose) 190210910Sneel printf("cfe_enummem: 0x%016jx/%ju.\n", addr, len); 191195333Simp 192195333Simp if (maxmem != 0) { 193195333Simp if (addr >= maxmem) { 194210910Sneel printf("Ignoring %ju bytes of memory at 0x%jx " 195195333Simp "that is above maxmem %dMB\n", 196195333Simp len, addr, 197195333Simp (int)(maxmem / (1024 * 1024))); 198195333Simp continue; 199195333Simp } 200195333Simp 201195333Simp if (addr + len > maxmem) { 202210910Sneel printf("Ignoring %ju bytes of memory " 203195333Simp "that is above maxmem %dMB\n", 204195333Simp (addr + len) - maxmem, 205195333Simp (int)(maxmem / (1024 * 1024))); 206195333Simp len = maxmem - addr; 207195333Simp } 208195333Simp } 209195333Simp 210195333Simp phys_avail[i] = addr; 211195333Simp if (i == 0 && addr == 0) { 212195333Simp /* 213195333Simp * If this is the first physical memory segment probed 214195333Simp * from CFE, omit the region at the start of physical 215195333Simp * memory where the kernel has been loaded. 216195333Simp */ 217202954Sgonzo phys_avail[i] += MIPS_KSEG0_TO_PHYS(kernel_kseg0_end); 218195333Simp } 219195333Simp phys_avail[i + 1] = addr + len; 220195333Simp physmem += len; 221195333Simp } 222195333Simp 223195333Simp realmem = btoc(physmem); 224195333Simp#endif 225195333Simp 226216320Sgonzo for (j = 0; j < i; j++) 227216318Sgonzo dump_avail[j] = phys_avail[j]; 228216318Sgonzo 229195333Simp physmem = realmem; 230195333Simp 231195333Simp init_param1(); 232195333Simp init_param2(physmem); 233195333Simp mips_cpu_init(); 234203000Sneel 235203000Sneel /* 236204689Sneel * Sibyte has a L1 data cache coherent with DMA. This includes 237204689Sneel * on-chip network interfaces as well as PCI/HyperTransport bus 238204689Sneel * masters. 239204689Sneel */ 240204689Sneel cpuinfo.cache_coherent_dma = TRUE; 241204689Sneel 242204689Sneel /* 243203000Sneel * XXX 244203000Sneel * The kernel is running in 32-bit mode but the CFE is running in 245203000Sneel * 64-bit mode. So the SR_KX bit in the status register is turned 246203000Sneel * on by the CFE every time we call into it - for e.g. CFE_CONSOLE. 247203000Sneel * 248203000Sneel * This means that if get a TLB miss for any address above 0xc0000000 249203000Sneel * and the SR_KX bit is set then we will end up in the XTLB exception 250203000Sneel * vector. 251203000Sneel * 252203000Sneel * For now work around this by copying the TLB exception handling 253203000Sneel * code to the XTLB exception vector. 254203000Sneel */ 255203000Sneel { 256232615Sjmallett bcopy(MipsTLBMiss, (void *)MIPS_XTLB_MISS_EXC_VEC, 257203000Sneel MipsTLBMissEnd - MipsTLBMiss); 258203000Sneel 259203000Sneel mips_icache_sync_all(); 260203000Sneel mips_dcache_wbinv_all(); 261203000Sneel } 262203000Sneel 263195333Simp pmap_bootstrap(); 264195333Simp mips_proc0_init(); 265195333Simp mutex_init(); 266195333Simp 267195333Simp kdb_init(); 268195333Simp#ifdef KDB 269195333Simp if (boothowto & RB_KDB) 270195333Simp kdb_enter(KDB_WHY_BOOTFLAGS, "Boot flags requested debugger"); 271195333Simp#endif 272195333Simp} 273195333Simp 274195333Simpvoid 275195333Simpplatform_halt(void) 276195333Simp{ 277195333Simp 278195333Simp} 279195333Simp 280195333Simp 281195333Simpvoid 282195333Simpplatform_identify(void) 283195333Simp{ 284195333Simp 285195333Simp} 286195333Simp 287195333Simpvoid 288195333Simpplatform_reset(void) 289195333Simp{ 290195333Simp 291195333Simp /* 292195333Simp * XXX SMP 293195333Simp * XXX flush data caches 294195333Simp */ 295195333Simp sb_system_reset(); 296195333Simp} 297195333Simp 298195333Simpvoid 299195333Simpplatform_trap_enter(void) 300195333Simp{ 301195333Simp 302195333Simp} 303195333Simp 304195333Simpvoid 305195333Simpplatform_trap_exit(void) 306195333Simp{ 307195333Simp 308195333Simp} 309195333Simp 310202864Sneelstatic void 311202864Sneelkseg0_map_coherent(void) 312202864Sneel{ 313202864Sneel uint32_t config; 314202864Sneel const int CFG_K0_COHERENT = 5; 315202864Sneel 316202864Sneel config = mips_rd_config(); 317232615Sjmallett config &= ~MIPS_CONFIG_K0_MASK; 318202864Sneel config |= CFG_K0_COHERENT; 319202864Sneel mips_wr_config(config); 320202864Sneel} 321202864Sneel 322203697Sneel#ifdef SMP 323195333Simpvoid 324203697Sneelplatform_ipi_send(int cpuid) 325203697Sneel{ 326203697Sneel KASSERT(cpuid == 0 || cpuid == 1, 327203697Sneel ("platform_ipi_send: invalid cpuid %d", cpuid)); 328203697Sneel 329203697Sneel sb_set_mailbox(cpuid, 1ULL); 330203697Sneel} 331203697Sneel 332203697Sneelvoid 333203697Sneelplatform_ipi_clear(void) 334203697Sneel{ 335203697Sneel int cpuid; 336203697Sneel 337203697Sneel cpuid = PCPU_GET(cpuid); 338203697Sneel sb_clear_mailbox(cpuid, 1ULL); 339203697Sneel} 340203697Sneel 341203697Sneelint 342203697Sneelplatform_ipi_intrnum(void) 343203697Sneel{ 344203697Sneel 345203697Sneel return (4); 346203697Sneel} 347203697Sneel 348208249Srrsstruct cpu_group * 349208249Srrsplatform_smp_topo(void) 350208249Srrs{ 351208253Sneel 352208249Srrs return (smp_topo_none()); 353208249Srrs} 354208249Srrs 355203697Sneelvoid 356203697Sneelplatform_init_ap(int cpuid) 357203697Sneel{ 358208249Srrs int ipi_int_mask, clock_int_mask; 359203697Sneel 360203697Sneel KASSERT(cpuid == 1, ("AP has an invalid cpu id %d", cpuid)); 361203697Sneel 362203697Sneel /* 363203697Sneel * Make sure that kseg0 is mapped cacheable-coherent 364203697Sneel */ 365203697Sneel kseg0_map_coherent(); 366203697Sneel 367203697Sneel sb_intr_init(cpuid); 368208249Srrs 369208249Srrs /* 370208249Srrs * Unmask the clock and ipi interrupts. 371208249Srrs */ 372208249Srrs clock_int_mask = hard_int_mask(5); 373208249Srrs ipi_int_mask = hard_int_mask(platform_ipi_intrnum()); 374212632Sneel set_intr_mask(ipi_int_mask | clock_int_mask); 375203697Sneel} 376203697Sneel 377203697Sneelint 378203697Sneelplatform_start_ap(int cpuid) 379203697Sneel{ 380203697Sneel#ifdef CFE 381203697Sneel int error; 382203697Sneel 383203697Sneel if ((error = cfe_cpu_start(cpuid, mpentry, 0, 0, 0))) { 384203697Sneel printf("cfe_cpu_start error: %d\n", error); 385203697Sneel return (-1); 386203697Sneel } else { 387203697Sneel return (0); 388203697Sneel } 389203697Sneel#else 390203697Sneel return (-1); 391203697Sneel#endif /* CFE */ 392203697Sneel} 393203697Sneel#endif /* SMP */ 394203697Sneel 395205364Sneelstatic u_int 396205364Sneelsb_get_timecount(struct timecounter *tc) 397205364Sneel{ 398205364Sneel 399205364Sneel return ((u_int)sb_zbbus_cycle_count()); 400205364Sneel} 401205364Sneel 402205364Sneelstatic void 403205364Sneelsb_timecounter_init(void) 404205364Sneel{ 405205364Sneel static struct timecounter sb_timecounter = { 406205364Sneel sb_get_timecount, 407205364Sneel NULL, 408205364Sneel ~0u, 409205364Sneel 0, 410205364Sneel "sibyte_zbbus_counter", 411205364Sneel 2000 412205364Sneel }; 413205364Sneel 414205364Sneel /* 415205364Sneel * The ZBbus cycle counter runs at half the cpu frequency. 416205364Sneel */ 417205364Sneel sb_timecounter.tc_frequency = sb_cpu_speed() / 2; 418205364Sneel platform_timecounter = &sb_timecounter; 419205364Sneel} 420205364Sneel 421203697Sneelvoid 422201631Sneelplatform_start(__register_t a0, __register_t a1, __register_t a2, 423201631Sneel __register_t a3) 424195333Simp{ 425202864Sneel /* 426202864Sneel * Make sure that kseg0 is mapped cacheable-coherent 427202864Sneel */ 428202864Sneel kseg0_map_coherent(); 429202864Sneel 430195333Simp /* clear the BSS and SBSS segments */ 431195333Simp memset(&edata, 0, (vm_offset_t)&end - (vm_offset_t)&edata); 432202954Sgonzo mips_postboot_fixup(); 433195333Simp 434203510Sneel sb_intr_init(0); 435205364Sneel sb_timecounter_init(); 436203510Sneel 437201845Simp /* Initialize pcpu stuff */ 438201881Simp mips_pcpu0_init(); 439201845Simp 440195333Simp#ifdef CFE 441195333Simp /* 442195333Simp * Initialize CFE firmware trampolines before 443195333Simp * we initialize the low-level console. 444201631Sneel * 445201631Sneel * CFE passes the following values in registers: 446201631Sneel * a0: firmware handle 447201631Sneel * a2: firmware entry point 448201631Sneel * a3: entry point seal 449195333Simp */ 450201631Sneel if (a3 == CFE_EPTSEAL) 451201631Sneel cfe_init(a0, a2); 452195333Simp#endif 453195333Simp cninit(); 454195333Simp 455195333Simp mips_init(); 456195333Simp 457195333Simp mips_timer_init_params(sb_cpu_speed(), 0); 458195333Simp} 459