sb_asm.S revision 203697 
1/*-
2 * Copyright (c) 2009 Neelkanth Natu
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 *    notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 *    notice, this list of conditions and the following disclaimer in the
12 *    documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
26 * $FreeBSD: head/sys/mips/sibyte/sb_asm.S 203697 2010-02-09 06:24:43Z neel $
27 */
28
29#include <machine/asm.h>
30#include <machine/cpuregs.h>
31
32/*
33 * We compile a 32-bit kernel to run on the SB-1 processor which is a 64-bit
34 * processor. It has some registers that must be accessed using 64-bit load
35 * and store instructions.
36 *
37 * So we have to resort to assembly because the compiler does not emit the
38 * 'ld' and 'sd' instructions since it thinks that it is compiling for a
39 * 32-bit mips processor.
40 */
41
42.set	mips64
43.set	noat
44.set	noreorder
45
46/*
47 * Parameters:		uint32_t ptr
48 * Return value: 	*(uint64_t *)ptr
49 */
50LEAF(sb_load64)
51	ld      v1, 0(a0)	/* result = *(uint64_t *)ptr */
52	move	v0, v1
53#if defined(TARGET_BIG_ENDIAN)
54	dsll32	v1, v1, 0
55	dsrl32	v1, v1, 0	/* v1 = lower_uint32(result) */
56	jr	ra
57	dsrl32	v0, v0, 0	/* v0 = upper_uint32(result) */
58#else
59	dsll32	v0, v0, 0
60	dsrl32	v0, v0, 0	/* v0 = lower_uint32(result) */
61	jr	ra
62	dsrl32	v1, v1, 0	/* v1 = upper_uint32(result) */
63#endif
64END(sb_load64)
65
66/*
67 * Parameters:		uint32_t ptr, uint64_t val
68 * Return value:	void
69 */
70LEAF(sb_store64)
71#if defined(TARGET_BIG_ENDIAN)
72	dsll32	a2, a2, 0	/* a2 = upper_uint32(val) */
73	dsll32	a3, a3, 0	/* a3 = lower_uint32(val) */
74	dsrl32	a3, a3, 0
75#else
76	dsll32	a3, a3, 0	/* a3 = upper_uint32(val) */
77	dsll32	a2, a2, 0	/* a2 = lower_uint32(val) */
78	dsrl32	a2, a2, 0
79#endif
80	or	t0, a2, a3
81	jr	ra
82	sd	t0, 0(a0)
83END(sb_store64)
84
85#ifdef SMP
86/*
87 * This function must be implemented in assembly because it is called early
88 * in AP boot without a valid stack.
89 *
90 * This cpu number is available in bits 25 to 27 of the coprocessor 0 PRID
91 * register. This is not documented in the BCM1250 user manual but can be
92 * gleaned from the CFE source code - see sb1250_altcpu.S
93 */
94LEAF(platform_processor_id)
95	mfc0	v0, MIPS_COP_0_PRID
96	srl	v0, v0, 25
97	jr	ra
98	and	v0, v0, 7
99END(platform_processor_id)
100#endif	/* SMP */
101