sb_asm.S revision 203509 
1/*-
2 * Copyright (c) 2009 Neelkanth Natu
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 *    notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 *    notice, this list of conditions and the following disclaimer in the
12 *    documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
26 * $FreeBSD: head/sys/mips/sibyte/sb_asm.S 203509 2010-02-05 03:20:47Z neel $
27 */
28
29#include <machine/asm.h>
30
31/*
32 * We compile a 32-bit kernel to run on the SB-1 processor which is a 64-bit
33 * processor. It has some registers that must be accessed using 64-bit load
34 * and store instructions.
35 *
36 * So we have to resort to assembly because the compiler does not emit the
37 * 'ld' and 'sd' instructions since it thinks that it is compiling for a
38 * 32-bit mips processor.
39 */
40
41.set	mips64
42.set	noat
43.set	noreorder
44
45/*
46 * Parameters:		uint32_t ptr
47 * Return value: 	*(uint64_t *)ptr
48 */
49LEAF(sb_load64)
50	ld      v1, 0(a0)	/* result = *(uint64_t *)ptr */
51	move	v0, v1
52#if defined(TARGET_BIG_ENDIAN)
53	dsll32	v1, v1, 0
54	dsrl32	v1, v1, 0	/* v1 = lower_uint32(result) */
55	jr	ra
56	dsrl32	v0, v0, 0	/* v0 = upper_uint32(result) */
57#else
58	dsll32	v0, v0, 0
59	dsrl32	v0, v0, 0	/* v0 = lower_uint32(result) */
60	jr	ra
61	dsrl32	v1, v1, 0	/* v1 = upper_uint32(result) */
62#endif
63END(sb_load64)
64
65/*
66 * Parameters:		uint32_t ptr, uint64_t val
67 * Return value:	void
68 */
69LEAF(sb_store64)
70#if defined(TARGET_BIG_ENDIAN)
71	dsll32	a2, a2, 0	/* a2 = upper_uint32(val) */
72	dsll32	a3, a3, 0	/* a3 = lower_uint32(val) */
73	dsrl32	a3, a3, 0
74#else
75	dsll32	a3, a3, 0	/* a3 = upper_uint32(val) */
76	dsll32	a2, a2, 0	/* a2 = lower_uint32(val) */
77	dsrl32	a2, a2, 0
78#endif
79	or	t0, a2, a3
80	jr	ra
81	sd	t0, 0(a0)
82END(sb_store64)
83