sb_asm.S revision 201905 
1/*-
2 * Copyright (c) 2009 Neelkanth Natu
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 *    notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 *    notice, this list of conditions and the following disclaimer in the
12 *    documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27#include <machine/asm.h>
28
29/*
30 * We compile a 32-bit kernel to run on the SB-1 processor which is a 64-bit
31 * processor. It has some registers that must be accessed using 64-bit load
32 * and store instructions.
33 *
34 * So we have to resort to assembly because the compiler does not emit the
35 * 'ld' and 'sd' instructions since it thinks that it is compiling for a
36 * 32-bit mips processor.
37 */
38
39.set	mips64
40.set	noat
41.set	noreorder
42
43/*
44 * return (MIPS_PHYS_TO_KSEG1(0x10020008))
45 * Parameters: none
46 */
47LEAF(sb_read_syscfg)
48	lui     v0, 0xb002
49	ori     v0, v0, 0x8
50	ld      v1, 0(v0)	/* syscfg = MIPS_PHYS_TO_KSEG1(0x10020008) */
51	move	v0, v1
52	dsll32	v0, v0, 0
53	dsrl32	v0, v0, 0	/* v0 = lower_uint32(mask) */
54	jr	ra
55	dsrl32	v1, v1, 0	/* v1 = upper_uint32(mask) */
56END(sb_read_syscfg)
57
58/*
59 * MIPS_PHYS_TO_KSEG1(0x10020008) = (uint64_t)val
60 * Parameters:
61 * - lower_uint32(val): a0
62 * - upper_uint32(val): a1
63 */
64LEAF(sb_write_syscfg)
65	lui     v0, 0xb002
66	ori     v0, v0, 0x8
67	dsll32	a1, a1, 0	/* clear lower 32 bits of a1 */
68	dsll32	a0, a0, 0
69	dsrl32	a0, a0, 0	/* clear upper 32 bits of a0 */
70	or	a1, a1, a0
71	sd	a1, 0(v0)	/* MIPS_PHYS_TO_KSEG1(0x10020008) = val */
72	jr	ra
73	nop
74	nop
75END(sb_write_syscfg)
76
77/*
78 * MIPS_PHYS_TO_KSEG1(0x10020028) |= (1 << intsrc)
79 *
80 * Parameters:
81 * - intsrc (a0)
82 */
83LEAF(sb_disable_intsrc)
84	lui     v0, 0xb002
85	ori     v0, v0, 0x28
86	ld      v1, 0(v0)	/* mask = MIPS_PHYS_TO_KSEG1(0x10020028) */
87	li      a1, 1
88	dsllv   a1, a1, a0
89	or      a1, a1, v1	/* mask |= (1 << intsrc) */
90	jr	ra
91	sd      a1, 0(v0)	/* MIPS_PHYS_TO_KSEG1(0x10020028) = mask */
92END(sb_disable_intsrc)
93
94/*
95 * MIPS_PHYS_TO_KSEG1(0x10020028) &= ~(1 << intsrc)
96 *
97 * Parameters:
98 * - intsrc (a0)
99 */
100LEAF(sb_enable_intsrc)
101	lui     v0, 0xb002
102	ori     v0, v0, 0x28
103	ld      v1, 0(v0)	/* mask = MIPS_PHYS_TO_KSEG1(0x10020028) */
104	li      a2, 1
105	dsllv   a2, a2, a0
106	nor     a2, zero, a2
107	and     a2, a2, v1	/* mask &= ~(1 << intsrc) */
108	sd      a2, 0(v0)	/* MIPS_PHYS_TO_KSEG1(0x10020028) = mask */
109	jr      ra
110	nop
111END(sb_enable_intsrc)
112
113/*
114 * return ((uint64_t)MIPS_PHYS_TO_KSEG1(0x10020028))
115 * Parameters: none
116 */
117LEAF(sb_read_intsrc_mask)
118	lui     v0, 0xb002
119	ori     v0, v0, 0x28
120	ld      v1, 0(v0)	/* mask = MIPS_PHYS_TO_KSEG1(0x10020028) */
121	move	v0, v1
122	dsll32	v0, v0, 0
123	dsrl32	v0, v0, 0	/* v0 = lower_uint32(mask) */
124	jr	ra
125	dsrl32	v1, v1, 0	/* v1 = upper_uint32(mask) */
126END(sb_read_intsrc_mask)
127
128/*
129 * return ((uint64_t *)MIPS_PHYS_TO_KSEG1(0x10020200) + intsrc)
130 * Parameters:
131 * - intsrc (a0)
132 */
133LEAF(sb_read_intmap)
134	sll	a0, a0, 3	/* compute the offset of the intmap register */
135	lui     v0, 0xb002
136	addu    a0, a0, v0
137	ld      v0, 512(a0)	/* v0 = MIPS_PHYS_TO_KSEG1(0x10020200) + off */
138	jr      ra
139	nop
140END(sb_read_intmap)
141
142/*
143 * (uint64_t *)MIPS_PHYS_TO_KSEG1(0x10020200) + intsrc = irq
144 * Parameters:
145 * - intsrc (a0)
146 * - irq    (a1)
147 */
148LEAF(sb_write_intmap)
149	sll     a0, a0, 0x3 /* compute the offset of the intmap register */
150	lui     v0, 0xb002
151	addu    a0, a0, v0
152	sd      a1, 512(a0) /* MIPS_PHYS_TO_KSEG1(0x10020200) + off = irq */
153	jr      ra
154	nop
155END(sb_write_intmap)
156