xlp_pci.c revision 238289
1331246Ssjg/*- 2246149Ssjg * Copyright (c) 2003-2012 Broadcom Corporation 3246149Ssjg * All Rights Reserved 4246149Ssjg * 5246149Ssjg * Redistribution and use in source and binary forms, with or without 6246149Ssjg * modification, are permitted provided that the following conditions 7246149Ssjg * are met: 8246149Ssjg * 9246149Ssjg * 1. Redistributions of source code must retain the above copyright 10321653Ssjg * notice, this list of conditions and the following disclaimer. 11246149Ssjg * 2. Redistributions in binary form must reproduce the above copyright 12246149Ssjg * notice, this list of conditions and the following disclaimer in 13246149Ssjg * the documentation and/or other materials provided with the 14246149Ssjg * distribution. 15246149Ssjg * 16246149Ssjg * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR 17246149Ssjg * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 18246149Ssjg * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19246149Ssjg * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE 20246149Ssjg * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21246149Ssjg * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22246149Ssjg * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 23300313Ssjg * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 24300313Ssjg * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE 25246149Ssjg * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN 26246149Ssjg * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27246149Ssjg */ 28246149Ssjg 29246149Ssjg#include <sys/cdefs.h> 30246149Ssjg__FBSDID("$FreeBSD: head/sys/mips/nlm/xlp_pci.c 238289 2012-07-09 10:17:06Z jchandra $"); 31246149Ssjg 32246149Ssjg#include <sys/param.h> 33246149Ssjg#include <sys/systm.h> 34246149Ssjg#include <sys/types.h> 35246149Ssjg#include <sys/kernel.h> 36246149Ssjg#include <sys/module.h> 37246149Ssjg#include <sys/malloc.h> 38321653Ssjg#include <sys/bus.h> 39246149Ssjg#include <sys/endian.h> 40246149Ssjg#include <sys/rman.h> 41246149Ssjg#include <sys/pciio.h> 42246149Ssjg 43246149Ssjg#include <vm/vm.h> 44246149Ssjg#include <vm/vm_param.h> 45246149Ssjg#include <vm/pmap.h> 46246149Ssjg 47246149Ssjg#include <dev/pci/pcivar.h> 48246149Ssjg#include <dev/pci/pcireg.h> 49246149Ssjg#include <dev/pci/pci_private.h> 50246149Ssjg 51246149Ssjg#include <dev/uart/uart.h> 52246149Ssjg#include <dev/uart/uart_bus.h> 53246149Ssjg#include <dev/uart/uart_cpu.h> 54246149Ssjg 55246149Ssjg#include <machine/bus.h> 56246149Ssjg#include <machine/md_var.h> 57246149Ssjg#include <machine/intr_machdep.h> 58246149Ssjg#include <machine/cpuregs.h> 59246149Ssjg 60246149Ssjg#include <mips/nlm/hal/haldefs.h> 61246149Ssjg#include <mips/nlm/interrupt.h> 62246149Ssjg#include <mips/nlm/hal/iomap.h> 63246149Ssjg#include <mips/nlm/hal/mips-extns.h> 64246149Ssjg#include <mips/nlm/hal/pic.h> 65246149Ssjg#include <mips/nlm/hal/bridge.h> 66246149Ssjg#include <mips/nlm/hal/gbu.h> 67246149Ssjg#include <mips/nlm/hal/pcibus.h> 68246149Ssjg#include <mips/nlm/hal/uart.h> 69246149Ssjg#include <mips/nlm/xlp.h> 70246149Ssjg 71246149Ssjg#include "pcib_if.h" 72246149Ssjg#include "pci_if.h" 73246149Ssjg 74246149Ssjg#define EMUL_MEM_START 0x16000000UL 75246149Ssjg#define EMUL_MEM_END 0x18ffffffUL 76246149Ssjg 77246149Ssjg/* SoC device qurik handling */ 78246149Ssjgstatic int irt_irq_map[4 * 256]; 79246149Ssjgstatic int irq_irt_map[64]; 80246149Ssjg 81246149Ssjgstatic void 82300313Ssjgxlp_add_irq(int node, int irt, int irq) 83246149Ssjg{ 84246149Ssjg int nodeirt = node * 256 + irt; 85246149Ssjg 86246149Ssjg irt_irq_map[nodeirt] = irq; 87246149Ssjg irq_irt_map[irq] = nodeirt; 88246149Ssjg} 89246149Ssjg 90246149Ssjgint 91246149Ssjgxlp_irq_to_irt(int irq) 92246149Ssjg{ 93253883Ssjg return irq_irt_map[irq]; 94331246Ssjg} 95246149Ssjg 96246149Ssjgint 97246149Ssjgxlp_irt_to_irq(int nodeirt) 98246149Ssjg{ 99246149Ssjg return irt_irq_map[nodeirt]; 100246149Ssjg} 101246149Ssjg 102246149Ssjg/* Override PCI a bit for SoC devices */ 103246149Ssjg 104246149Ssjgenum { 105246149Ssjg INTERNAL_DEV = 0x1, /* internal device, skip on enumeration */ 106246149Ssjg MEM_RES_EMUL = 0x2, /* no MEM or IO bar, custom res alloc */ 107246149Ssjg SHARED_IRQ = 0x4, 108246149Ssjg DEV_MMIO32 = 0x8, /* byte access not allowed to mmio */ 109246149Ssjg}; 110246149Ssjg 111246149Ssjgstruct soc_dev_desc { 112246149Ssjg u_int devid; /* device ID */ 113246149Ssjg int irqbase; /* start IRQ */ 114246149Ssjg u_int flags; /* flags */ 115246149Ssjg int ndevs; /* to keep track of number of devices */ 116246149Ssjg}; 117331246Ssjg 118246149Ssjgstruct soc_dev_desc xlp_dev_desc[] = { 119246149Ssjg { PCI_DEVICE_ID_NLM_ICI, 0, INTERNAL_DEV }, 120246149Ssjg { PCI_DEVICE_ID_NLM_PIC, 0, INTERNAL_DEV }, 121246149Ssjg { PCI_DEVICE_ID_NLM_FMN, 0, INTERNAL_DEV }, 122319884Ssjg { PCI_DEVICE_ID_NLM_UART, PIC_UART_0_IRQ, MEM_RES_EMUL | DEV_MMIO32}, 123246149Ssjg { PCI_DEVICE_ID_NLM_I2C, 0, MEM_RES_EMUL | DEV_MMIO32 }, 124246149Ssjg { PCI_DEVICE_ID_NLM_NOR, 0, MEM_RES_EMUL }, 125246149Ssjg { PCI_DEVICE_ID_NLM_MMC, PIC_MMC_IRQ, MEM_RES_EMUL }, 126246149Ssjg { PCI_DEVICE_ID_NLM_EHCI, PIC_EHCI_0_IRQ, 0 } 127246149Ssjg}; 128246149Ssjg 129246149Ssjgstruct xlp_devinfo { 130246149Ssjg struct pci_devinfo pcidev; 131246149Ssjg int irq; 132246149Ssjg int flags; 133246149Ssjg u_long mem_res_start; 134321653Ssjg}; 135246149Ssjg 136246149Ssjgstatic __inline struct soc_dev_desc * 137289842Ssjgxlp_find_soc_desc(int devid) 138246149Ssjg{ 139246149Ssjg struct soc_dev_desc *p; 140246149Ssjg int i, n; 141246149Ssjg 142246149Ssjg n = sizeof(xlp_dev_desc) / sizeof(xlp_dev_desc[0]); 143246149Ssjg for (i = 0, p = xlp_dev_desc; i < n; i++, p++) 144246149Ssjg if (p->devid == devid) 145246149Ssjg return (p); 146246149Ssjg return (NULL); 147246149Ssjg} 148289842Ssjg 149246149Ssjgstatic struct resource * 150319884Ssjgxlp_pci_alloc_resource(device_t bus, device_t child, int type, int *rid, 151319884Ssjg u_long start, u_long end, u_long count, u_int flags) 152319884Ssjg{ 153246149Ssjg struct resource *r; 154246149Ssjg struct xlp_devinfo *xlp_devinfo; 155246149Ssjg int busno; 156246149Ssjg 157246149Ssjg /* 158246149Ssjg * Do custom allocation for MEMORY resource for SoC device if 159246149Ssjg * MEM_RES_EMUL flag is set 160246149Ssjg */ 161246149Ssjg busno = pci_get_bus(child); 162300313Ssjg if ((type == SYS_RES_MEMORY || type == SYS_RES_IOPORT) && busno == 0) { 163246149Ssjg xlp_devinfo = (struct xlp_devinfo *)device_get_ivars(child); 164246149Ssjg if ((xlp_devinfo->flags & MEM_RES_EMUL) != 0) { 165246149Ssjg /* no emulation for IO ports */ 166246149Ssjg if (type == SYS_RES_IOPORT) 167246149Ssjg return (NULL); 168246149Ssjg 169246149Ssjg start = xlp_devinfo->mem_res_start; 170246149Ssjg count = XLP_PCIE_CFG_SIZE - XLP_IO_PCI_HDRSZ; 171246149Ssjg 172246149Ssjg /* MMC needs to 2 slots with rids 16 and 20 and a 173246149Ssjg * fixup for size */ 174246149Ssjg if (pci_get_device(child) == PCI_DEVICE_ID_NLM_MMC) { 175246149Ssjg count = 0x100; 176246149Ssjg if (*rid == 16) 177246149Ssjg ; /* first slot already setup */ 178246149Ssjg else if (*rid == 20) 179246149Ssjg start += 0x100; /* second slot */ 180246149Ssjg else 181246149Ssjg return (NULL); 182246149Ssjg } 183246149Ssjg 184246149Ssjg end = start + count - 1; 185246149Ssjg r = BUS_ALLOC_RESOURCE(device_get_parent(bus), child, 186246149Ssjg type, rid, start, end, count, flags); 187246149Ssjg if (r == NULL) 188246149Ssjg return (NULL); 189246149Ssjg if ((xlp_devinfo->flags & DEV_MMIO32) != 0) 190246149Ssjg rman_set_bustag(r, rmi_uart_bus_space); 191246149Ssjg return (r); 192319884Ssjg } 193319884Ssjg } 194319884Ssjg 195319884Ssjg /* Not custom alloc, use PCI code */ 196246149Ssjg return (pci_alloc_resource(bus, child, type, rid, start, end, count, 197246149Ssjg flags)); 198246149Ssjg} 199246149Ssjg 200246149Ssjgstatic int 201246149Ssjgxlp_pci_release_resource(device_t bus, device_t child, int type, int rid, 202246149Ssjg struct resource *r) 203246149Ssjg{ 204246149Ssjg u_long start; 205246149Ssjg 206246149Ssjg /* If custom alloc, handle that */ 207246149Ssjg start = rman_get_start(r); 208246149Ssjg if (type == SYS_RES_MEMORY && pci_get_bus(child) == 0 && 209246149Ssjg start >= EMUL_MEM_START && start <= EMUL_MEM_END) 210246149Ssjg return (BUS_RELEASE_RESOURCE(device_get_parent(bus), child, 211246149Ssjg type, rid, r)); 212246149Ssjg 213246149Ssjg /* use default PCI function */ 214246149Ssjg return (bus_generic_rl_release_resource(bus, child, type, rid, r)); 215246149Ssjg} 216246149Ssjg 217246149Ssjgstatic void 218246149Ssjgxlp_add_soc_child(device_t pcib, device_t dev, int b, int s, int f) 219246149Ssjg{ 220246149Ssjg struct pci_devinfo *dinfo; 221246149Ssjg struct xlp_devinfo *xlp_dinfo; 222246149Ssjg struct soc_dev_desc *si; 223246149Ssjg uint64_t pcibase; 224246149Ssjg int domain, node, irt, irq, flags, devoffset, num; 225246149Ssjg uint16_t devid; 226246149Ssjg 227246149Ssjg domain = pcib_get_domain(dev); 228246149Ssjg node = s / 8; 229246149Ssjg devoffset = XLP_HDR_OFFSET(node, 0, s % 8, f); 230246149Ssjg if (!nlm_dev_exists(devoffset)) 231246149Ssjg return; 232246149Ssjg 233246149Ssjg /* Find if there is a desc for the SoC device */ 234246149Ssjg devid = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_DEVICE, 2); 235246149Ssjg si = xlp_find_soc_desc(devid); 236246149Ssjg 237246149Ssjg /* update flags and irq from desc if available */ 238246149Ssjg irq = 0; 239246149Ssjg flags = 0; 240246149Ssjg if (si != NULL) { 241246149Ssjg if (si->irqbase != 0) 242246149Ssjg irq = si->irqbase + si->ndevs; 243246149Ssjg flags = si->flags; 244246149Ssjg si->ndevs++; 245246149Ssjg } 246246149Ssjg 247246149Ssjg /* skip internal devices */ 248246149Ssjg if ((flags & INTERNAL_DEV) != 0) 249246149Ssjg return; 250246149Ssjg 251246149Ssjg /* PCIe interfaces are special, bug in Ax */ 252246149Ssjg if (devid == PCI_DEVICE_ID_NLM_PCIE) { 253246149Ssjg xlp_add_irq(node, xlp_pcie_link_irt(f), PIC_PCIE_0_IRQ + f); 254246149Ssjg } else { 255246149Ssjg /* Stash intline and pin in shadow reg for devices */ 256319884Ssjg pcibase = nlm_pcicfg_base(devoffset); 257319884Ssjg irt = nlm_irtstart(pcibase); 258319884Ssjg num = nlm_irtnum(pcibase); 259319884Ssjg if (irq != 0 && num > 0) { 260319884Ssjg xlp_add_irq(node, irt, irq); 261319884Ssjg nlm_write_reg(pcibase, XLP_PCI_DEVSCRATCH_REG0, 262319884Ssjg (1 << 8) | irq); 263319884Ssjg } 264246149Ssjg } 265319884Ssjg dinfo = pci_read_device(pcib, domain, b, s, f, sizeof(*xlp_dinfo)); 266319884Ssjg if (dinfo == NULL) 267319884Ssjg return; 268319884Ssjg xlp_dinfo = (struct xlp_devinfo *)dinfo; 269319884Ssjg xlp_dinfo->irq = irq; 270319884Ssjg xlp_dinfo->flags = flags; 271319884Ssjg 272 /* memory resource from ecfg space, if MEM_RES_EMUL is set */ 273 if ((flags & MEM_RES_EMUL) != 0) 274 xlp_dinfo->mem_res_start = XLP_DEFAULT_IO_BASE + devoffset + 275 XLP_IO_PCI_HDRSZ; 276 pci_add_child(dev, dinfo); 277} 278 279static int 280xlp_pci_attach(device_t dev) 281{ 282 device_t pcib = device_get_parent(dev); 283 int maxslots, s, f, pcifunchigh; 284 int busno; 285 uint8_t hdrtype; 286 287 /* 288 * The on-chip devices are on a bus that is almost, but not 289 * quite, completely like PCI. Add those things by hand. 290 */ 291 busno = pcib_get_bus(dev); 292 maxslots = PCIB_MAXSLOTS(pcib); 293 for (s = 0; s <= maxslots; s++) { 294 pcifunchigh = 0; 295 f = 0; 296 hdrtype = PCIB_READ_CONFIG(pcib, busno, s, f, PCIR_HDRTYPE, 1); 297 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE) 298 continue; 299 if (hdrtype & PCIM_MFDEV) 300 pcifunchigh = PCI_FUNCMAX; 301 for (f = 0; f <= pcifunchigh; f++) 302 xlp_add_soc_child(pcib, dev, busno, s, f); 303 } 304 return (bus_generic_attach(dev)); 305} 306 307static int 308xlp_pci_probe(device_t dev) 309{ 310 device_t pcib; 311 312 pcib = device_get_parent(dev); 313 /* 314 * Only the top level bus has SoC devices, leave the rest to 315 * Generic PCI code 316 */ 317 if (strcmp(device_get_nameunit(pcib), "pcib0") != 0) 318 return (ENXIO); 319 device_set_desc(dev, "XLP SoCbus"); 320 return (BUS_PROBE_DEFAULT); 321} 322 323static devclass_t pci_devclass; 324static device_method_t xlp_pci_methods[] = { 325 /* Device interface */ 326 DEVMETHOD(device_probe, xlp_pci_probe), 327 DEVMETHOD(device_attach, xlp_pci_attach), 328 DEVMETHOD(bus_alloc_resource, xlp_pci_alloc_resource), 329 DEVMETHOD(bus_release_resource, xlp_pci_release_resource), 330 331 DEVMETHOD_END 332}; 333 334DEFINE_CLASS_1(pci, xlp_pci_driver, xlp_pci_methods, sizeof(struct pci_softc), 335 pci_driver); 336DRIVER_MODULE(xlp_pci, pcib, xlp_pci_driver, pci_devclass, 0, 0); 337 338static devclass_t pcib_devclass; 339static struct rman irq_rman, port_rman, mem_rman, emul_rman; 340 341static void 342xlp_pcib_init_resources(void) 343{ 344 irq_rman.rm_start = 0; 345 irq_rman.rm_end = 255; 346 irq_rman.rm_type = RMAN_ARRAY; 347 irq_rman.rm_descr = "PCI Mapped Interrupts"; 348 if (rman_init(&irq_rman) 349 || rman_manage_region(&irq_rman, 0, 255)) 350 panic("pci_init_resources irq_rman"); 351 352 port_rman.rm_start = 0; 353 port_rman.rm_end = ~0ul; 354 port_rman.rm_type = RMAN_ARRAY; 355 port_rman.rm_descr = "I/O ports"; 356 if (rman_init(&port_rman) 357 || rman_manage_region(&port_rman, PCIE_IO_BASE, PCIE_IO_LIMIT)) 358 panic("pci_init_resources port_rman"); 359 360 mem_rman.rm_start = 0; 361 mem_rman.rm_end = ~0ul; 362 mem_rman.rm_type = RMAN_ARRAY; 363 mem_rman.rm_descr = "I/O memory"; 364 if (rman_init(&mem_rman) 365 || rman_manage_region(&mem_rman, PCIE_MEM_BASE, PCIE_MEM_LIMIT)) 366 panic("pci_init_resources mem_rman"); 367 368 /* 369 * This includes the GBU (nor flash) memory range and the PCIe 370 * memory area. 371 */ 372 emul_rman.rm_start = 0; 373 emul_rman.rm_end = ~0ul; 374 emul_rman.rm_type = RMAN_ARRAY; 375 emul_rman.rm_descr = "Emulated MEMIO"; 376 if (rman_init(&emul_rman) 377 || rman_manage_region(&emul_rman, EMUL_MEM_START, EMUL_MEM_END)) 378 panic("pci_init_resources emul_rman"); 379} 380 381static int 382xlp_pcib_probe(device_t dev) 383{ 384 385 device_set_desc(dev, "XLP PCI bus"); 386 xlp_pcib_init_resources(); 387 return (0); 388} 389 390static int 391xlp_pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 392{ 393 394 switch (which) { 395 case PCIB_IVAR_DOMAIN: 396 *result = 0; 397 return (0); 398 case PCIB_IVAR_BUS: 399 *result = 0; 400 return (0); 401 } 402 return (ENOENT); 403} 404 405static int 406xlp_pcib_write_ivar(device_t dev, device_t child, int which, uintptr_t result) 407{ 408 switch (which) { 409 case PCIB_IVAR_DOMAIN: 410 return (EINVAL); 411 case PCIB_IVAR_BUS: 412 return (EINVAL); 413 } 414 return (ENOENT); 415} 416 417static int 418xlp_pcib_maxslots(device_t dev) 419{ 420 421 return (PCI_SLOTMAX); 422} 423 424static u_int32_t 425xlp_pcib_read_config(device_t dev, u_int b, u_int s, u_int f, 426 u_int reg, int width) 427{ 428 uint32_t data = 0; 429 uint64_t cfgaddr; 430 int regindex = reg/sizeof(uint32_t); 431 432 cfgaddr = nlm_pcicfg_base(XLP_HDR_OFFSET(0, b, s, f)); 433 if ((width == 2) && (reg & 1)) 434 return 0xFFFFFFFF; 435 else if ((width == 4) && (reg & 3)) 436 return 0xFFFFFFFF; 437 438 /* 439 * The intline and int pin of SoC devices are DOA, except 440 * for bridges (slot %8 == 1). 441 * use the values we stashed in a writable PCI scratch reg. 442 */ 443 if (b == 0 && regindex == 0xf && s % 8 > 1) 444 regindex = XLP_PCI_DEVSCRATCH_REG0; 445 446 data = nlm_read_pci_reg(cfgaddr, regindex); 447 if (width == 1) 448 return ((data >> ((reg & 3) << 3)) & 0xff); 449 else if (width == 2) 450 return ((data >> ((reg & 3) << 3)) & 0xffff); 451 else 452 return (data); 453} 454 455static void 456xlp_pcib_write_config(device_t dev, u_int b, u_int s, u_int f, 457 u_int reg, u_int32_t val, int width) 458{ 459 uint64_t cfgaddr; 460 uint32_t data = 0; 461 int regindex = reg / sizeof(uint32_t); 462 463 cfgaddr = nlm_pcicfg_base(XLP_HDR_OFFSET(0, b, s, f)); 464 if ((width == 2) && (reg & 1)) 465 return; 466 else if ((width == 4) && (reg & 3)) 467 return; 468 469 if (width == 1) { 470 data = nlm_read_pci_reg(cfgaddr, regindex); 471 data = (data & ~(0xff << ((reg & 3) << 3))) | 472 (val << ((reg & 3) << 3)); 473 } else if (width == 2) { 474 data = nlm_read_pci_reg(cfgaddr, regindex); 475 data = (data & ~(0xffff << ((reg & 3) << 3))) | 476 (val << ((reg & 3) << 3)); 477 } else { 478 data = val; 479 } 480 481 /* 482 * use shadow reg for intpin/intline which are dead 483 */ 484 if (b == 0 && regindex == 0xf && s % 8 > 1) 485 regindex = XLP_PCI_DEVSCRATCH_REG0; 486 nlm_write_pci_reg(cfgaddr, regindex, data); 487} 488 489/* 490 * Enable byte swap in hardware. Program a link's PCIe SWAP regions 491 * from the link's IO and MEM address ranges. 492 */ 493static void 494xlp_pcib_hardware_swap_enable(int node, int link) 495{ 496 uint64_t bbase, linkpcibase; 497 uint32_t bar; 498 int pcieoffset; 499 500 pcieoffset = XLP_IO_PCIE_OFFSET(node, link); 501 if (!nlm_dev_exists(pcieoffset)) 502 return; 503 504 bbase = nlm_get_bridge_regbase(node); 505 linkpcibase = nlm_pcicfg_base(pcieoffset); 506 bar = nlm_read_bridge_reg(bbase, BRIDGE_PCIEMEM_BASE0 + link); 507 nlm_write_pci_reg(linkpcibase, PCIE_BYTE_SWAP_MEM_BASE, bar); 508 509 bar = nlm_read_bridge_reg(bbase, BRIDGE_PCIEMEM_LIMIT0 + link); 510 nlm_write_pci_reg(linkpcibase, PCIE_BYTE_SWAP_MEM_LIM, bar | 0xFFF); 511 512 bar = nlm_read_bridge_reg(bbase, BRIDGE_PCIEIO_BASE0 + link); 513 nlm_write_pci_reg(linkpcibase, PCIE_BYTE_SWAP_IO_BASE, bar); 514 515 bar = nlm_read_bridge_reg(bbase, BRIDGE_PCIEIO_LIMIT0 + link); 516 nlm_write_pci_reg(linkpcibase, PCIE_BYTE_SWAP_IO_LIM, bar | 0xFFF); 517} 518 519static int 520xlp_pcib_attach(device_t dev) 521{ 522 int node, link; 523 524 /* enable hardware swap on all nodes/links */ 525 for (node = 0; node < XLP_MAX_NODES; node++) 526 for (link = 0; link < 4; link++) 527 xlp_pcib_hardware_swap_enable(node, link); 528 529 device_add_child(dev, "pci", 0); 530 bus_generic_attach(dev); 531 return (0); 532} 533 534static void 535xlp_pcib_identify(driver_t * driver, device_t parent) 536{ 537 538 BUS_ADD_CHILD(parent, 0, "pcib", 0); 539} 540 541/* 542 * XLS PCIe can have upto 4 links, and each link has its on IRQ 543 * Find the link on which the device is on 544 */ 545static int 546xlp_pcie_link(device_t pcib, device_t dev) 547{ 548 device_t parent, tmp; 549 550 /* find the lane on which the slot is connected to */ 551 tmp = dev; 552 while (1) { 553 parent = device_get_parent(tmp); 554 if (parent == NULL || parent == pcib) { 555 device_printf(dev, "Cannot find parent bus\n"); 556 return (-1); 557 } 558 if (strcmp(device_get_nameunit(parent), "pci0") == 0) 559 break; 560 tmp = parent; 561 } 562 return (pci_get_function(tmp)); 563} 564 565static int 566xlp_alloc_msi(device_t pcib, device_t dev, int count, int maxcount, int *irqs) 567{ 568 int i, link; 569 570 /* 571 * Each link has 32 MSIs that can be allocated, but for now 572 * we only support one device per link. 573 * msi_alloc() equivalent is needed when we start supporting 574 * bridges on the PCIe link. 575 */ 576 link = xlp_pcie_link(pcib, dev); 577 if (link == -1) 578 return (ENXIO); 579 580 /* 581 * encode the irq so that we know it is a MSI interrupt when we 582 * setup interrupts 583 */ 584 for (i = 0; i < count; i++) 585 irqs[i] = 64 + link * 32 + i; 586 587 return (0); 588} 589 590static int 591xlp_release_msi(device_t pcib, device_t dev, int count, int *irqs) 592{ 593 return (0); 594} 595 596static int 597xlp_map_msi(device_t pcib, device_t dev, int irq, uint64_t *addr, 598 uint32_t *data) 599{ 600 int msi, irt; 601 602 if (irq >= 64) { 603 msi = irq - 64; 604 *addr = MIPS_MSI_ADDR(0); 605 606 irt = xlp_pcie_link_irt(msi/32); 607 if (irt != -1) 608 *data = MIPS_MSI_DATA(xlp_irt_to_irq(irt)); 609 return (0); 610 } else { 611 device_printf(dev, "%s: map_msi for irq %d - ignored", 612 device_get_nameunit(pcib), irq); 613 return (ENXIO); 614 } 615} 616 617static void 618bridge_pcie_ack(int irq) 619{ 620 uint32_t node,reg; 621 uint64_t base; 622 623 node = nlm_nodeid(); 624 reg = PCIE_MSI_STATUS; 625 626 switch (irq) { 627 case PIC_PCIE_0_IRQ: 628 base = nlm_pcicfg_base(XLP_IO_PCIE0_OFFSET(node)); 629 break; 630 case PIC_PCIE_1_IRQ: 631 base = nlm_pcicfg_base(XLP_IO_PCIE1_OFFSET(node)); 632 break; 633 case PIC_PCIE_2_IRQ: 634 base = nlm_pcicfg_base(XLP_IO_PCIE2_OFFSET(node)); 635 break; 636 case PIC_PCIE_3_IRQ: 637 base = nlm_pcicfg_base(XLP_IO_PCIE3_OFFSET(node)); 638 break; 639 default: 640 return; 641 } 642 643 nlm_write_pci_reg(base, reg, 0xFFFFFFFF); 644 return; 645} 646 647static int 648mips_platform_pcib_setup_intr(device_t dev, device_t child, 649 struct resource *irq, int flags, driver_filter_t *filt, 650 driver_intr_t *intr, void *arg, void **cookiep) 651{ 652 int error = 0; 653 int xlpirq; 654 void *extra_ack; 655 656 error = rman_activate_resource(irq); 657 if (error) 658 return error; 659 if (rman_get_start(irq) != rman_get_end(irq)) { 660 device_printf(dev, "Interrupt allocation %lu != %lu\n", 661 rman_get_start(irq), rman_get_end(irq)); 662 return (EINVAL); 663 } 664 xlpirq = rman_get_start(irq); 665 if (xlpirq == 0) 666 return (0); 667 668 if (strcmp(device_get_name(dev), "pcib") != 0) 669 return (0); 670 671 /* 672 * temporary hack for MSI, we support just one device per 673 * link, and assign the link interrupt to the device interrupt 674 */ 675 if (xlpirq >= 64) { 676 int node, val, link; 677 uint64_t base; 678 679 xlpirq -= 64; 680 if (xlpirq % 32 != 0) 681 return (0); 682 683 node = nlm_nodeid(); 684 link = xlpirq / 32; 685 base = nlm_pcicfg_base(XLP_IO_PCIE_OFFSET(node,link)); 686 687 /* MSI Interrupt Vector enable at bridge's configuration */ 688 nlm_write_pci_reg(base, PCIE_MSI_EN, PCIE_MSI_VECTOR_INT_EN); 689 690 val = nlm_read_pci_reg(base, PCIE_INT_EN0); 691 /* MSI Interrupt enable at bridge's configuration */ 692 nlm_write_pci_reg(base, PCIE_INT_EN0, 693 (val | PCIE_MSI_INT_EN)); 694 695 /* legacy interrupt disable at bridge */ 696 val = nlm_read_pci_reg(base, PCIE_BRIDGE_CMD); 697 nlm_write_pci_reg(base, PCIE_BRIDGE_CMD, 698 (val | PCIM_CMD_INTxDIS)); 699 700 /* MSI address update at bridge */ 701 nlm_write_pci_reg(base, PCIE_BRIDGE_MSI_ADDRL, 702 MSI_MIPS_ADDR_BASE); 703 nlm_write_pci_reg(base, PCIE_BRIDGE_MSI_ADDRH, 0); 704 705 val = nlm_read_pci_reg(base, PCIE_BRIDGE_MSI_CAP); 706 /* MSI capability enable at bridge */ 707 nlm_write_pci_reg(base, PCIE_BRIDGE_MSI_CAP, 708 (val | (PCIM_MSICTRL_MSI_ENABLE << 16) | 709 (PCIM_MSICTRL_MMC_32 << 16))); 710 711 xlpirq = xlp_pcie_link_irt(xlpirq / 32); 712 if (xlpirq == -1) 713 return (EINVAL); 714 xlpirq = xlp_irt_to_irq(xlpirq); 715 } 716 /* Set all irqs to CPU 0 for now */ 717 nlm_pic_write_irt_direct(xlp_pic_base, xlp_irq_to_irt(xlpirq), 1, 0, 718 PIC_LOCAL_SCHEDULING, xlpirq, 0); 719 extra_ack = NULL; 720 if (xlpirq >= PIC_PCIE_0_IRQ && xlpirq <= PIC_PCIE_3_IRQ) 721 extra_ack = bridge_pcie_ack; 722 xlp_establish_intr(device_get_name(child), filt, 723 intr, arg, xlpirq, flags, cookiep, extra_ack); 724 725 return (0); 726} 727 728static int 729mips_platform_pcib_teardown_intr(device_t dev, device_t child, 730 struct resource *irq, void *cookie) 731{ 732 if (strcmp(device_get_name(child), "pci") == 0) { 733 /* if needed reprogram the pic to clear pcix related entry */ 734 device_printf(dev, "teardown intr\n"); 735 } 736 return (bus_generic_teardown_intr(dev, child, irq, cookie)); 737} 738 739static struct resource * 740xlp_pcib_alloc_resource(device_t bus, device_t child, int type, int *rid, 741 u_long start, u_long end, u_long count, u_int flags) 742{ 743 struct rman *rm = NULL; 744 struct resource *rv; 745 void *va; 746 int needactivate = flags & RF_ACTIVE; 747 748 switch (type) { 749 case SYS_RES_IRQ: 750 rm = &irq_rman; 751 break; 752 753 case SYS_RES_IOPORT: 754 rm = &port_rman; 755 break; 756 757 case SYS_RES_MEMORY: 758 if (start >= EMUL_MEM_START && start <= EMUL_MEM_END) 759 rm = &emul_rman; 760 else 761 rm = &mem_rman; 762 break; 763 764 default: 765 return (0); 766 } 767 768 rv = rman_reserve_resource(rm, start, end, count, flags, child); 769 if (rv == NULL) 770 return (NULL); 771 772 rman_set_rid(rv, *rid); 773 774 if (type == SYS_RES_MEMORY || type == SYS_RES_IOPORT) { 775 va = pmap_mapdev(start, count); 776 rman_set_bushandle(rv, (bus_space_handle_t)va); 777 rman_set_bustag(rv, rmi_bus_space); 778 } 779 if (needactivate) { 780 if (bus_activate_resource(child, type, *rid, rv)) { 781 rman_release_resource(rv); 782 return (NULL); 783 } 784 } 785 return (rv); 786} 787 788static int 789xlp_pcib_release_resource(device_t bus, device_t child, int type, int rid, 790 struct resource *r) 791{ 792 793 return (rman_release_resource(r)); 794} 795 796static int 797xlp_pcib_activate_resource(device_t bus, device_t child, int type, int rid, 798 struct resource *r) 799{ 800 801 return (rman_activate_resource(r)); 802} 803 804static int 805xlp_pcib_deactivate_resource(device_t bus, device_t child, int type, int rid, 806 struct resource *r) 807{ 808 809 return (rman_deactivate_resource(r)); 810} 811 812static int 813mips_pcib_route_interrupt(device_t bus, device_t dev, int pin) 814{ 815 int irt, link; 816 817 /* 818 * Validate requested pin number. 819 */ 820 if ((pin < 1) || (pin > 4)) 821 return (255); 822 823 if (pci_get_bus(dev) == 0 && 824 pci_get_vendor(dev) == PCI_VENDOR_NETLOGIC) { 825 /* SoC devices */ 826 uint64_t pcibase; 827 int f, n, d, num; 828 829 f = pci_get_function(dev); 830 n = pci_get_slot(dev) / 8; 831 d = pci_get_slot(dev) % 8; 832 833 /* 834 * For PCIe links, return link IRT, for other SoC devices 835 * get the IRT from its PCIe header 836 */ 837 if (d == 1) { 838 irt = xlp_pcie_link_irt(f); 839 } else { 840 pcibase = nlm_pcicfg_base(XLP_HDR_OFFSET(n, 0, d, f)); 841 irt = nlm_irtstart(pcibase); 842 num = nlm_irtnum(pcibase); 843 if (num != 1) 844 device_printf(bus, "[%d:%d:%d] Error %d IRQs\n", 845 n, d, f, num); 846 } 847 } else { 848 /* Regular PCI devices */ 849 link = xlp_pcie_link(bus, dev); 850 irt = xlp_pcie_link_irt(link); 851 } 852 853 if (irt != -1) 854 return (xlp_irt_to_irq(irt)); 855 856 return (255); 857} 858 859static device_method_t xlp_pcib_methods[] = { 860 /* Device interface */ 861 DEVMETHOD(device_identify, xlp_pcib_identify), 862 DEVMETHOD(device_probe, xlp_pcib_probe), 863 DEVMETHOD(device_attach, xlp_pcib_attach), 864 865 /* Bus interface */ 866 DEVMETHOD(bus_read_ivar, xlp_pcib_read_ivar), 867 DEVMETHOD(bus_write_ivar, xlp_pcib_write_ivar), 868 DEVMETHOD(bus_alloc_resource, xlp_pcib_alloc_resource), 869 DEVMETHOD(bus_release_resource, xlp_pcib_release_resource), 870 DEVMETHOD(bus_activate_resource, xlp_pcib_activate_resource), 871 DEVMETHOD(bus_deactivate_resource, xlp_pcib_deactivate_resource), 872 DEVMETHOD(bus_setup_intr, mips_platform_pcib_setup_intr), 873 DEVMETHOD(bus_teardown_intr, mips_platform_pcib_teardown_intr), 874 875 /* pcib interface */ 876 DEVMETHOD(pcib_maxslots, xlp_pcib_maxslots), 877 DEVMETHOD(pcib_read_config, xlp_pcib_read_config), 878 DEVMETHOD(pcib_write_config, xlp_pcib_write_config), 879 DEVMETHOD(pcib_route_interrupt, mips_pcib_route_interrupt), 880 881 DEVMETHOD(pcib_alloc_msi, xlp_alloc_msi), 882 DEVMETHOD(pcib_release_msi, xlp_release_msi), 883 DEVMETHOD(pcib_map_msi, xlp_map_msi), 884 885 DEVMETHOD_END 886}; 887 888static driver_t xlp_pcib_driver = { 889 "pcib", 890 xlp_pcib_methods, 891 1, /* no softc */ 892}; 893 894DRIVER_MODULE(pcib, nexus, xlp_pcib_driver, pcib_devclass, 0, 0); 895