xlp_pci.c revision 233564
1130561Sobrien/*- 2130561Sobrien * Copyright (c) 2003-2012 Broadcom Corporation 3130561Sobrien * All Rights Reserved 4130561Sobrien * 5130561Sobrien * Redistribution and use in source and binary forms, with or without 6130561Sobrien * modification, are permitted provided that the following conditions 7130561Sobrien * are met: 8130561Sobrien * 9130561Sobrien * 1. Redistributions of source code must retain the above copyright 10130561Sobrien * notice, this list of conditions and the following disclaimer. 11130561Sobrien * 2. Redistributions in binary form must reproduce the above copyright 12130561Sobrien * notice, this list of conditions and the following disclaimer in 13130561Sobrien * the documentation and/or other materials provided with the 14130561Sobrien * distribution. 15130561Sobrien * 16130561Sobrien * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR 17130561Sobrien * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 18130561Sobrien * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19130561Sobrien * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE 20218822Sdim * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21218822Sdim * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22130561Sobrien * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 23130561Sobrien * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 24130561Sobrien * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE 25130561Sobrien * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN 26130561Sobrien * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27130561Sobrien */ 28130561Sobrien 29130561Sobrien#include <sys/cdefs.h> 30130561Sobrien__FBSDID("$FreeBSD: head/sys/mips/nlm/xlp_pci.c 233564 2012-03-27 15:43:32Z jchandra $"); 31130561Sobrien 32130561Sobrien#include <sys/param.h> 33130561Sobrien#include <sys/systm.h> 34130561Sobrien#include <sys/types.h> 35130561Sobrien#include <sys/kernel.h> 36130561Sobrien#include <sys/module.h> 37130561Sobrien#include <sys/malloc.h> 38130561Sobrien#include <sys/bus.h> 39130561Sobrien#include <sys/endian.h> 40130561Sobrien#include <sys/rman.h> 41130561Sobrien#include <sys/pciio.h> 42130561Sobrien 43130561Sobrien#include <vm/vm.h> 44130561Sobrien#include <vm/vm_param.h> 45130561Sobrien#include <vm/pmap.h> 46130561Sobrien 47130561Sobrien#include <dev/pci/pcivar.h> 48130561Sobrien#include <dev/pci/pcireg.h> 49130561Sobrien#include <dev/pci/pci_private.h> 50130561Sobrien 51130561Sobrien#include <dev/uart/uart.h> 52130561Sobrien#include <dev/uart/uart_bus.h> 53130561Sobrien#include <dev/uart/uart_cpu.h> 54130561Sobrien 55130561Sobrien#include <machine/bus.h> 56130561Sobrien#include <machine/md_var.h> 57130561Sobrien#include <machine/intr_machdep.h> 58130561Sobrien#include <machine/cpuregs.h> 59130561Sobrien 60130561Sobrien#include <mips/nlm/hal/haldefs.h> 61130561Sobrien#include <mips/nlm/interrupt.h> 62130561Sobrien#include <mips/nlm/hal/iomap.h> 63130561Sobrien#include <mips/nlm/hal/mips-extns.h> 64130561Sobrien#include <mips/nlm/hal/pic.h> 65130561Sobrien#include <mips/nlm/hal/bridge.h> 66130561Sobrien#include <mips/nlm/hal/gbu.h> 67218822Sdim#include <mips/nlm/hal/pcibus.h> 68218822Sdim#include <mips/nlm/hal/uart.h> 69218822Sdim#include <mips/nlm/xlp.h> 70218822Sdim 71218822Sdim#include "pcib_if.h" 72218822Sdim#include "pci_if.h" 73130561Sobrien 74130561Sobrien#define EMUL_MEM_START 0x16000000UL 75130561Sobrien#define EMUL_MEM_END 0x18ffffffUL 76218822Sdim 77130561Sobrien/* SoC device qurik handling */ 78130561Sobrienstatic int irt_irq_map[4 * 256]; 79130561Sobrienstatic int irq_irt_map[64]; 80130561Sobrien 81130561Sobrienstatic void 82130561Sobrienxlp_add_irq(int node, int irt, int irq) 83130561Sobrien{ 84130561Sobrien int nodeirt = node * 256 + irt; 85130561Sobrien 86130561Sobrien irt_irq_map[nodeirt] = irq; 87130561Sobrien irq_irt_map[irq] = nodeirt; 88130561Sobrien} 89130561Sobrien 90130561Sobrienint 91130561Sobrienxlp_irq_to_irt(int irq) 92130561Sobrien{ 93130561Sobrien return irq_irt_map[irq]; 94130561Sobrien} 95130561Sobrien 96130561Sobrienint 97130561Sobrienxlp_irt_to_irq(int nodeirt) 98130561Sobrien{ 99130561Sobrien return irt_irq_map[nodeirt]; 100130561Sobrien} 101130561Sobrien 102130561Sobrien/* Override PCI a bit for SoC devices */ 103130561Sobrien 104130561Sobrienenum { 105130561Sobrien INTERNAL_DEV = 0x1, /* internal device, skip on enumeration */ 106130561Sobrien MEM_RES_EMUL = 0x2, /* no MEM or IO bar, custom res alloc */ 107130561Sobrien SHARED_IRQ = 0x4, 108130561Sobrien DEV_MMIO32 = 0x8, /* byte access not allowed to mmio */ 109130561Sobrien}; 110130561Sobrien 111130561Sobrienstruct soc_dev_desc { 112130561Sobrien u_int devid; /* device ID */ 113130561Sobrien int irqbase; /* start IRQ */ 114130561Sobrien u_int flags; /* flags */ 115130561Sobrien int ndevs; /* to keep track of number of devices */ 116130561Sobrien}; 117130561Sobrien 118130561Sobrienstruct soc_dev_desc xlp_dev_desc[] = { 119130561Sobrien { PCI_DEVICE_ID_NLM_ICI, 0, INTERNAL_DEV }, 120218822Sdim { PCI_DEVICE_ID_NLM_PIC, 0, INTERNAL_DEV }, 121130561Sobrien { PCI_DEVICE_ID_NLM_FMN, 0, INTERNAL_DEV }, 122130561Sobrien { PCI_DEVICE_ID_NLM_UART, PIC_UART_0_IRQ, MEM_RES_EMUL | DEV_MMIO32}, 123130561Sobrien { PCI_DEVICE_ID_NLM_I2C, 0, MEM_RES_EMUL | DEV_MMIO32 }, 124130561Sobrien { PCI_DEVICE_ID_NLM_NOR, 0, MEM_RES_EMUL }, 125130561Sobrien { PCI_DEVICE_ID_NLM_MMC, PIC_MMC_IRQ, MEM_RES_EMUL }, 126130561Sobrien { PCI_DEVICE_ID_NLM_EHCI, PIC_EHCI_0_IRQ, 0 } 127130561Sobrien}; 128130561Sobrien 129130561Sobrienstruct xlp_devinfo { 130130561Sobrien struct pci_devinfo pcidev; 131218822Sdim int irq; 132218822Sdim int flags; 133218822Sdim u_long mem_res_start; 134218822Sdim}; 135218822Sdim 136218822Sdimstatic __inline struct soc_dev_desc * 137218822Sdimxlp_find_soc_desc(int devid) 138218822Sdim{ 139218822Sdim struct soc_dev_desc *p; 140218822Sdim int i, n; 141218822Sdim 142218822Sdim n = sizeof(xlp_dev_desc) / sizeof(xlp_dev_desc[0]); 143218822Sdim for (i = 0, p = xlp_dev_desc; i < n; i++, p++) 144218822Sdim if (p->devid == devid) 145218822Sdim return (p); 146218822Sdim return (NULL); 147218822Sdim} 148218822Sdim 149218822Sdimstatic struct resource * 150218822Sdimxlp_pci_alloc_resource(device_t bus, device_t child, int type, int *rid, 151218822Sdim u_long start, u_long end, u_long count, u_int flags) 152218822Sdim{ 153218822Sdim struct resource *r; 154218822Sdim struct xlp_devinfo *xlp_devinfo; 155130561Sobrien int busno; 156130561Sobrien 157130561Sobrien /* 158 * Do custom allocation for MEMORY resource for SoC device if 159 * MEM_RES_EMUL flag is set 160 */ 161 busno = pci_get_bus(child); 162 if ((type == SYS_RES_MEMORY || type == SYS_RES_IOPORT) && busno == 0) { 163 xlp_devinfo = (struct xlp_devinfo *)device_get_ivars(child); 164 if ((xlp_devinfo->flags & MEM_RES_EMUL) != 0) { 165 /* no emulation for IO ports */ 166 if (type == SYS_RES_IOPORT) 167 return (NULL); 168 169 start = xlp_devinfo->mem_res_start; 170 count = XLP_PCIE_CFG_SIZE - XLP_IO_PCI_HDRSZ; 171 172 /* MMC needs to 2 slots with rids 16 and 20 and a 173 * fixup for size */ 174 if (pci_get_device(child) == PCI_DEVICE_ID_NLM_MMC) { 175 count = 0x100; 176 if (*rid == 16) 177 ; /* first slot already setup */ 178 else if (*rid == 20) 179 start += 0x100; /* second slot */ 180 else 181 return (NULL); 182 } 183 184 end = start + count - 1; 185 r = BUS_ALLOC_RESOURCE(device_get_parent(bus), child, 186 type, rid, start, end, count, flags); 187 if (r == NULL) 188 return (NULL); 189 if ((xlp_devinfo->flags & DEV_MMIO32) != 0) 190 rman_set_bustag(r, rmi_uart_bus_space); 191 return (r); 192 } 193 } 194 195 /* Not custom alloc, use PCI code */ 196 return (pci_alloc_resource(bus, child, type, rid, start, end, count, 197 flags)); 198} 199 200static int 201xlp_pci_release_resource(device_t bus, device_t child, int type, int rid, 202 struct resource *r) 203{ 204 u_long start; 205 206 /* If custom alloc, handle that */ 207 start = rman_get_start(r); 208 if (type == SYS_RES_MEMORY && pci_get_bus(child) == 0 && 209 start >= EMUL_MEM_START && start <= EMUL_MEM_END) 210 return (BUS_RELEASE_RESOURCE(device_get_parent(bus), child, 211 type, rid, r)); 212 213 /* use default PCI function */ 214 return (bus_generic_rl_release_resource(bus, child, type, rid, r)); 215} 216 217static void 218xlp_add_soc_child(device_t pcib, device_t dev, int b, int s, int f) 219{ 220 struct pci_devinfo *dinfo; 221 struct xlp_devinfo *xlp_dinfo; 222 struct soc_dev_desc *si; 223 uint64_t pcibase; 224 int domain, node, irt, irq, flags, devoffset, num; 225 uint16_t devid; 226 227 domain = pcib_get_domain(dev); 228 node = s / 8; 229 devoffset = XLP_HDR_OFFSET(node, 0, s % 8, f); 230 if (!nlm_dev_exists(devoffset)) 231 return; 232 233 /* Find if there is a desc for the SoC device */ 234 devid = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_DEVICE, 2); 235 si = xlp_find_soc_desc(devid); 236 237 /* update flags and irq from desc if available */ 238 irq = 0; 239 flags = 0; 240 if (si != NULL) { 241 if (si->irqbase != 0) 242 irq = si->irqbase + si->ndevs; 243 flags = si->flags; 244 si->ndevs++; 245 } 246 247 /* skip internal devices */ 248 if ((flags & INTERNAL_DEV) != 0) 249 return; 250 251 /* PCIe interfaces are special, bug in Ax */ 252 if (devid == PCI_DEVICE_ID_NLM_PCIE) { 253 xlp_add_irq(node, xlp_pcie_link_irt(f), PIC_PCIE_0_IRQ + f); 254 } else { 255 /* Stash intline and pin in shadow reg for devices */ 256 pcibase = nlm_pcicfg_base(devoffset); 257 irt = nlm_irtstart(pcibase); 258 num = nlm_irtnum(pcibase); 259 if (irq != 0 && num > 0) { 260 xlp_add_irq(node, irt, irq); 261 nlm_write_reg(pcibase, XLP_PCI_DEVSCRATCH_REG0, 262 (1 << 8) | irq); 263 } 264 } 265 dinfo = pci_read_device(pcib, domain, b, s, f, sizeof(*xlp_dinfo)); 266 if (dinfo == NULL) 267 return; 268 xlp_dinfo = (struct xlp_devinfo *)dinfo; 269 xlp_dinfo->irq = irq; 270 xlp_dinfo->flags = flags; 271 272 /* memory resource from ecfg space, if MEM_RES_EMUL is set */ 273 if ((flags & MEM_RES_EMUL) != 0) 274 xlp_dinfo->mem_res_start = XLP_DEFAULT_IO_BASE + devoffset + 275 XLP_IO_PCI_HDRSZ; 276 pci_add_child(dev, dinfo); 277} 278 279static int 280xlp_pci_attach(device_t dev) 281{ 282 device_t pcib = device_get_parent(dev); 283 int maxslots, s, f, pcifunchigh; 284 int busno; 285 uint8_t hdrtype; 286 287 /* 288 * The on-chip devices are on a bus that is almost, but not 289 * quite, completely like PCI. Add those things by hand. 290 */ 291 busno = pcib_get_bus(dev); 292 maxslots = PCIB_MAXSLOTS(pcib); 293 for (s = 0; s <= maxslots; s++) { 294 pcifunchigh = 0; 295 f = 0; 296 hdrtype = PCIB_READ_CONFIG(pcib, busno, s, f, PCIR_HDRTYPE, 1); 297 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE) 298 continue; 299 if (hdrtype & PCIM_MFDEV) 300 pcifunchigh = PCI_FUNCMAX; 301 for (f = 0; f <= pcifunchigh; f++) 302 xlp_add_soc_child(pcib, dev, busno, s, f); 303 } 304 return (bus_generic_attach(dev)); 305} 306 307static int 308xlp_pci_probe(device_t dev) 309{ 310 device_t pcib; 311 312 pcib = device_get_parent(dev); 313 /* 314 * Only the top level bus has SoC devices, leave the rest to 315 * Generic PCI code 316 */ 317 if (strcmp(device_get_nameunit(pcib), "pcib0") != 0) 318 return (ENXIO); 319 device_set_desc(dev, "XLP SoCbus"); 320 return (BUS_PROBE_DEFAULT); 321} 322 323static devclass_t pci_devclass; 324static device_method_t xlp_pci_methods[] = { 325 /* Device interface */ 326 DEVMETHOD(device_probe, xlp_pci_probe), 327 DEVMETHOD(device_attach, xlp_pci_attach), 328 DEVMETHOD(bus_alloc_resource, xlp_pci_alloc_resource), 329 DEVMETHOD(bus_release_resource, xlp_pci_release_resource), 330 331 DEVMETHOD_END 332}; 333 334DEFINE_CLASS_1(pci, xlp_pci_driver, xlp_pci_methods, 0, pci_driver); 335DRIVER_MODULE(xlp_pci, pcib, xlp_pci_driver, pci_devclass, 0, 0); 336 337static devclass_t pcib_devclass; 338static struct rman irq_rman, port_rman, mem_rman, emul_rman; 339 340static void 341xlp_pcib_init_resources(void) 342{ 343 irq_rman.rm_start = 0; 344 irq_rman.rm_end = 255; 345 irq_rman.rm_type = RMAN_ARRAY; 346 irq_rman.rm_descr = "PCI Mapped Interrupts"; 347 if (rman_init(&irq_rman) 348 || rman_manage_region(&irq_rman, 0, 255)) 349 panic("pci_init_resources irq_rman"); 350 351 port_rman.rm_start = 0; 352 port_rman.rm_end = ~0ul; 353 port_rman.rm_type = RMAN_ARRAY; 354 port_rman.rm_descr = "I/O ports"; 355 if (rman_init(&port_rman) 356 || rman_manage_region(&port_rman, PCIE_IO_BASE, PCIE_IO_LIMIT)) 357 panic("pci_init_resources port_rman"); 358 359 mem_rman.rm_start = 0; 360 mem_rman.rm_end = ~0ul; 361 mem_rman.rm_type = RMAN_ARRAY; 362 mem_rman.rm_descr = "I/O memory"; 363 if (rman_init(&mem_rman) 364 || rman_manage_region(&mem_rman, PCIE_MEM_BASE, PCIE_MEM_LIMIT)) 365 panic("pci_init_resources mem_rman"); 366 367 /* 368 * This includes the GBU (nor flash) memory range and the PCIe 369 * memory area. 370 */ 371 emul_rman.rm_start = 0; 372 emul_rman.rm_end = ~0ul; 373 emul_rman.rm_type = RMAN_ARRAY; 374 emul_rman.rm_descr = "Emulated MEMIO"; 375 if (rman_init(&emul_rman) 376 || rman_manage_region(&emul_rman, EMUL_MEM_START, EMUL_MEM_END)) 377 panic("pci_init_resources emul_rman"); 378} 379 380static int 381xlp_pcib_probe(device_t dev) 382{ 383 384 device_set_desc(dev, "XLP PCI bus"); 385 xlp_pcib_init_resources(); 386 return (0); 387} 388 389static int 390xlp_pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 391{ 392 393 switch (which) { 394 case PCIB_IVAR_DOMAIN: 395 *result = 0; 396 return (0); 397 case PCIB_IVAR_BUS: 398 *result = 0; 399 return (0); 400 } 401 return (ENOENT); 402} 403 404static int 405xlp_pcib_write_ivar(device_t dev, device_t child, int which, uintptr_t result) 406{ 407 switch (which) { 408 case PCIB_IVAR_DOMAIN: 409 return (EINVAL); 410 case PCIB_IVAR_BUS: 411 return (EINVAL); 412 } 413 return (ENOENT); 414} 415 416static int 417xlp_pcib_maxslots(device_t dev) 418{ 419 420 return (PCI_SLOTMAX); 421} 422 423static u_int32_t 424xlp_pcib_read_config(device_t dev, u_int b, u_int s, u_int f, 425 u_int reg, int width) 426{ 427 uint32_t data = 0; 428 uint64_t cfgaddr; 429 int regindex = reg/sizeof(uint32_t); 430 431 cfgaddr = nlm_pcicfg_base(XLP_HDR_OFFSET(0, b, s, f)); 432 if ((width == 2) && (reg & 1)) 433 return 0xFFFFFFFF; 434 else if ((width == 4) && (reg & 3)) 435 return 0xFFFFFFFF; 436 437 /* 438 * The intline and int pin of SoC devices are DOA, except 439 * for bridges (slot %8 == 1). 440 * use the values we stashed in a writable PCI scratch reg. 441 */ 442 if (b == 0 && regindex == 0xf && s % 8 > 1) 443 regindex = XLP_PCI_DEVSCRATCH_REG0; 444 445 data = nlm_read_pci_reg(cfgaddr, regindex); 446 if (width == 1) 447 return ((data >> ((reg & 3) << 3)) & 0xff); 448 else if (width == 2) 449 return ((data >> ((reg & 3) << 3)) & 0xffff); 450 else 451 return (data); 452} 453 454static void 455xlp_pcib_write_config(device_t dev, u_int b, u_int s, u_int f, 456 u_int reg, u_int32_t val, int width) 457{ 458 uint64_t cfgaddr; 459 uint32_t data = 0; 460 int regindex = reg / sizeof(uint32_t); 461 462 cfgaddr = nlm_pcicfg_base(XLP_HDR_OFFSET(0, b, s, f)); 463 if ((width == 2) && (reg & 1)) 464 return; 465 else if ((width == 4) && (reg & 3)) 466 return; 467 468 if (width == 1) { 469 data = nlm_read_pci_reg(cfgaddr, regindex); 470 data = (data & ~(0xff << ((reg & 3) << 3))) | 471 (val << ((reg & 3) << 3)); 472 } else if (width == 2) { 473 data = nlm_read_pci_reg(cfgaddr, regindex); 474 data = (data & ~(0xffff << ((reg & 3) << 3))) | 475 (val << ((reg & 3) << 3)); 476 } else { 477 data = val; 478 } 479 480 /* 481 * use shadow reg for intpin/intline which are dead 482 */ 483 if (b == 0 && regindex == 0xf && s % 8 > 1) 484 regindex = XLP_PCI_DEVSCRATCH_REG0; 485 nlm_write_pci_reg(cfgaddr, regindex, data); 486} 487 488/* 489 * Enable byte swap in hardware. Program a link's PCIe SWAP regions 490 * from the link's IO and MEM address ranges. 491 */ 492static void 493xlp_pcib_hardware_swap_enable(int node, int link) 494{ 495 uint64_t bbase, linkpcibase; 496 uint32_t bar; 497 int pcieoffset; 498 499 pcieoffset = XLP_IO_PCIE_OFFSET(node, link); 500 if (!nlm_dev_exists(pcieoffset)) 501 return; 502 503 bbase = nlm_get_bridge_regbase(node); 504 linkpcibase = nlm_pcicfg_base(pcieoffset); 505 bar = nlm_read_bridge_reg(bbase, BRIDGE_PCIEMEM_BASE0 + link); 506 nlm_write_pci_reg(linkpcibase, PCIE_BYTE_SWAP_MEM_BASE, bar); 507 508 bar = nlm_read_bridge_reg(bbase, BRIDGE_PCIEMEM_LIMIT0 + link); 509 nlm_write_pci_reg(linkpcibase, PCIE_BYTE_SWAP_MEM_LIM, bar); 510 511 bar = nlm_read_bridge_reg(bbase, BRIDGE_PCIEIO_BASE0 + link); 512 nlm_write_pci_reg(linkpcibase, PCIE_BYTE_SWAP_IO_BASE, bar); 513 514 bar = nlm_read_bridge_reg(bbase, BRIDGE_PCIEIO_LIMIT0 + link); 515 nlm_write_pci_reg(linkpcibase, PCIE_BYTE_SWAP_IO_LIM, bar); 516} 517 518static int 519xlp_pcib_attach(device_t dev) 520{ 521 int node, link; 522 523 /* enable hardware swap on all nodes/links */ 524 for (node = 0; node < XLP_MAX_NODES; node++) 525 for (link = 0; link < 4; link++) 526 xlp_pcib_hardware_swap_enable(node, link); 527 528 device_add_child(dev, "pci", 0); 529 bus_generic_attach(dev); 530 return (0); 531} 532 533static void 534xlp_pcib_identify(driver_t * driver, device_t parent) 535{ 536 537 BUS_ADD_CHILD(parent, 0, "pcib", 0); 538} 539 540/* 541 * XLS PCIe can have upto 4 links, and each link has its on IRQ 542 * Find the link on which the device is on 543 */ 544static int 545xlp_pcie_link(device_t pcib, device_t dev) 546{ 547 device_t parent, tmp; 548 549 /* find the lane on which the slot is connected to */ 550 tmp = dev; 551 while (1) { 552 parent = device_get_parent(tmp); 553 if (parent == NULL || parent == pcib) { 554 device_printf(dev, "Cannot find parent bus\n"); 555 return (-1); 556 } 557 if (strcmp(device_get_nameunit(parent), "pci0") == 0) 558 break; 559 tmp = parent; 560 } 561 return (pci_get_function(tmp)); 562} 563 564static int 565xlp_alloc_msi(device_t pcib, device_t dev, int count, int maxcount, int *irqs) 566{ 567 int i, link; 568 569 /* 570 * Each link has 32 MSIs that can be allocated, but for now 571 * we only support one device per link. 572 * msi_alloc() equivalent is needed when we start supporting 573 * bridges on the PCIe link. 574 */ 575 link = xlp_pcie_link(pcib, dev); 576 if (link == -1) 577 return (ENXIO); 578 579 /* 580 * encode the irq so that we know it is a MSI interrupt when we 581 * setup interrupts 582 */ 583 for (i = 0; i < count; i++) 584 irqs[i] = 64 + link * 32 + i; 585 586 return (0); 587} 588 589static int 590xlp_release_msi(device_t pcib, device_t dev, int count, int *irqs) 591{ 592 return (0); 593} 594 595static int 596xlp_map_msi(device_t pcib, device_t dev, int irq, uint64_t *addr, 597 uint32_t *data) 598{ 599 int msi, irt; 600 601 if (irq >= 64) { 602 msi = irq - 64; 603 *addr = MIPS_MSI_ADDR(0); 604 605 irt = xlp_pcie_link_irt(msi/32); 606 if (irt != -1) 607 *data = MIPS_MSI_DATA(xlp_irt_to_irq(irt)); 608 return (0); 609 } else { 610 device_printf(dev, "%s: map_msi for irq %d - ignored", 611 device_get_nameunit(pcib), irq); 612 return (ENXIO); 613 } 614} 615 616static void 617bridge_pcie_ack(int irq) 618{ 619 uint32_t node,reg; 620 uint64_t base; 621 622 node = nlm_nodeid(); 623 reg = PCIE_MSI_STATUS; 624 625 switch (irq) { 626 case PIC_PCIE_0_IRQ: 627 base = nlm_pcicfg_base(XLP_IO_PCIE0_OFFSET(node)); 628 break; 629 case PIC_PCIE_1_IRQ: 630 base = nlm_pcicfg_base(XLP_IO_PCIE1_OFFSET(node)); 631 break; 632 case PIC_PCIE_2_IRQ: 633 base = nlm_pcicfg_base(XLP_IO_PCIE2_OFFSET(node)); 634 break; 635 case PIC_PCIE_3_IRQ: 636 base = nlm_pcicfg_base(XLP_IO_PCIE3_OFFSET(node)); 637 break; 638 default: 639 return; 640 } 641 642 nlm_write_pci_reg(base, reg, 0xFFFFFFFF); 643 return; 644} 645 646static int 647mips_platform_pcib_setup_intr(device_t dev, device_t child, 648 struct resource *irq, int flags, driver_filter_t *filt, 649 driver_intr_t *intr, void *arg, void **cookiep) 650{ 651 int error = 0; 652 int xlpirq; 653 void *extra_ack; 654 655 error = rman_activate_resource(irq); 656 if (error) 657 return error; 658 if (rman_get_start(irq) != rman_get_end(irq)) { 659 device_printf(dev, "Interrupt allocation %lu != %lu\n", 660 rman_get_start(irq), rman_get_end(irq)); 661 return (EINVAL); 662 } 663 xlpirq = rman_get_start(irq); 664 if (xlpirq == 0) 665 return (0); 666 667 if (strcmp(device_get_name(dev), "pcib") != 0) 668 return (0); 669 670 /* 671 * temporary hack for MSI, we support just one device per 672 * link, and assign the link interrupt to the device interrupt 673 */ 674 if (xlpirq >= 64) { 675 int node, val, link; 676 uint64_t base; 677 678 xlpirq -= 64; 679 if (xlpirq % 32 != 0) 680 return (0); 681 682 node = nlm_nodeid(); 683 link = xlpirq / 32; 684 base = nlm_pcicfg_base(XLP_IO_PCIE_OFFSET(node,link)); 685 686 /* MSI Interrupt Vector enable at bridge's configuration */ 687 nlm_write_pci_reg(base, PCIE_MSI_EN, PCIE_MSI_VECTOR_INT_EN); 688 689 val = nlm_read_pci_reg(base, PCIE_INT_EN0); 690 /* MSI Interrupt enable at bridge's configuration */ 691 nlm_write_pci_reg(base, PCIE_INT_EN0, 692 (val | PCIE_MSI_INT_EN)); 693 694 /* legacy interrupt disable at bridge */ 695 val = nlm_read_pci_reg(base, PCIE_BRIDGE_CMD); 696 nlm_write_pci_reg(base, PCIE_BRIDGE_CMD, 697 (val | PCIM_CMD_INTxDIS)); 698 699 /* MSI address update at bridge */ 700 nlm_write_pci_reg(base, PCIE_BRIDGE_MSI_ADDRL, 701 MSI_MIPS_ADDR_BASE); 702 nlm_write_pci_reg(base, PCIE_BRIDGE_MSI_ADDRH, 0); 703 704 val = nlm_read_pci_reg(base, PCIE_BRIDGE_MSI_CAP); 705 /* MSI capability enable at bridge */ 706 nlm_write_pci_reg(base, PCIE_BRIDGE_MSI_CAP, 707 (val | (PCIM_MSICTRL_MSI_ENABLE << 16) | 708 (PCIM_MSICTRL_MMC_32 << 16))); 709 710 xlpirq = xlp_pcie_link_irt(xlpirq / 32); 711 if (xlpirq == -1) 712 return (EINVAL); 713 xlpirq = xlp_irt_to_irq(xlpirq); 714 } 715 /* Set all irqs to CPU 0 for now */ 716 nlm_pic_write_irt_direct(xlp_pic_base, xlp_irq_to_irt(xlpirq), 1, 0, 717 PIC_LOCAL_SCHEDULING, xlpirq, 0); 718 extra_ack = NULL; 719 if (xlpirq >= PIC_PCIE_0_IRQ && xlpirq <= PIC_PCIE_3_IRQ) 720 extra_ack = bridge_pcie_ack; 721 xlp_establish_intr(device_get_name(child), filt, 722 intr, arg, xlpirq, flags, cookiep, extra_ack); 723 724 return (0); 725} 726 727static int 728mips_platform_pcib_teardown_intr(device_t dev, device_t child, 729 struct resource *irq, void *cookie) 730{ 731 if (strcmp(device_get_name(child), "pci") == 0) { 732 /* if needed reprogram the pic to clear pcix related entry */ 733 device_printf(dev, "teardown intr\n"); 734 } 735 return (bus_generic_teardown_intr(dev, child, irq, cookie)); 736} 737 738static struct resource * 739xlp_pcib_alloc_resource(device_t bus, device_t child, int type, int *rid, 740 u_long start, u_long end, u_long count, u_int flags) 741{ 742 struct rman *rm = NULL; 743 struct resource *rv; 744 void *va; 745 int needactivate = flags & RF_ACTIVE; 746 747 switch (type) { 748 case SYS_RES_IRQ: 749 rm = &irq_rman; 750 break; 751 752 case SYS_RES_IOPORT: 753 rm = &port_rman; 754 break; 755 756 case SYS_RES_MEMORY: 757 if (start >= EMUL_MEM_START && start <= EMUL_MEM_END) 758 rm = &emul_rman; 759 else 760 rm = &mem_rman; 761 break; 762 763 default: 764 return (0); 765 } 766 767 rv = rman_reserve_resource(rm, start, end, count, flags, child); 768 if (rv == NULL) 769 return (NULL); 770 771 rman_set_rid(rv, *rid); 772 773 if (type == SYS_RES_MEMORY || type == SYS_RES_IOPORT) { 774 va = pmap_mapdev(start, count); 775 rman_set_bushandle(rv, (bus_space_handle_t)va); 776 rman_set_bustag(rv, rmi_bus_space); 777 } 778 if (needactivate) { 779 if (bus_activate_resource(child, type, *rid, rv)) { 780 rman_release_resource(rv); 781 return (NULL); 782 } 783 } 784 return (rv); 785} 786 787static int 788xlp_pcib_release_resource(device_t bus, device_t child, int type, int rid, 789 struct resource *r) 790{ 791 792 return (rman_release_resource(r)); 793} 794 795static int 796xlp_pcib_activate_resource(device_t bus, device_t child, int type, int rid, 797 struct resource *r) 798{ 799 800 return (rman_activate_resource(r)); 801} 802 803static int 804xlp_pcib_deactivate_resource(device_t bus, device_t child, int type, int rid, 805 struct resource *r) 806{ 807 808 return (rman_deactivate_resource(r)); 809} 810 811static int 812mips_pcib_route_interrupt(device_t bus, device_t dev, int pin) 813{ 814 int irt, link; 815 816 /* 817 * Validate requested pin number. 818 */ 819 if ((pin < 1) || (pin > 4)) 820 return (255); 821 822 if (pci_get_bus(dev) == 0 && 823 pci_get_vendor(dev) == PCI_VENDOR_NETLOGIC) { 824 /* SoC devices */ 825 uint64_t pcibase; 826 int f, n, d, num; 827 828 f = pci_get_function(dev); 829 n = pci_get_slot(dev) / 8; 830 d = pci_get_slot(dev) % 8; 831 832 /* 833 * For PCIe links, return link IRT, for other SoC devices 834 * get the IRT from its PCIe header 835 */ 836 if (d == 1) { 837 irt = xlp_pcie_link_irt(f); 838 } else { 839 pcibase = nlm_pcicfg_base(XLP_HDR_OFFSET(n, 0, d, f)); 840 irt = nlm_irtstart(pcibase); 841 num = nlm_irtnum(pcibase); 842 if (num != 1) 843 device_printf(bus, "[%d:%d:%d] Error %d IRQs\n", 844 n, d, f, num); 845 } 846 } else { 847 /* Regular PCI devices */ 848 link = xlp_pcie_link(bus, dev); 849 irt = xlp_pcie_link_irt(link); 850 } 851 852 if (irt != -1) 853 return (xlp_irt_to_irq(irt)); 854 855 return (255); 856} 857 858static device_method_t xlp_pcib_methods[] = { 859 /* Device interface */ 860 DEVMETHOD(device_identify, xlp_pcib_identify), 861 DEVMETHOD(device_probe, xlp_pcib_probe), 862 DEVMETHOD(device_attach, xlp_pcib_attach), 863 864 /* Bus interface */ 865 DEVMETHOD(bus_read_ivar, xlp_pcib_read_ivar), 866 DEVMETHOD(bus_write_ivar, xlp_pcib_write_ivar), 867 DEVMETHOD(bus_alloc_resource, xlp_pcib_alloc_resource), 868 DEVMETHOD(bus_release_resource, xlp_pcib_release_resource), 869 DEVMETHOD(bus_activate_resource, xlp_pcib_activate_resource), 870 DEVMETHOD(bus_deactivate_resource, xlp_pcib_deactivate_resource), 871 DEVMETHOD(bus_setup_intr, mips_platform_pcib_setup_intr), 872 DEVMETHOD(bus_teardown_intr, mips_platform_pcib_teardown_intr), 873 874 /* pcib interface */ 875 DEVMETHOD(pcib_maxslots, xlp_pcib_maxslots), 876 DEVMETHOD(pcib_read_config, xlp_pcib_read_config), 877 DEVMETHOD(pcib_write_config, xlp_pcib_write_config), 878 DEVMETHOD(pcib_route_interrupt, mips_pcib_route_interrupt), 879 880 DEVMETHOD(pcib_alloc_msi, xlp_alloc_msi), 881 DEVMETHOD(pcib_release_msi, xlp_release_msi), 882 DEVMETHOD(pcib_map_msi, xlp_map_msi), 883 884 DEVMETHOD_END 885}; 886 887static driver_t xlp_pcib_driver = { 888 "pcib", 889 xlp_pcib_methods, 890 1, /* no softc */ 891}; 892 893DRIVER_MODULE(pcib, nexus, xlp_pcib_driver, pcib_devclass, 0, 0); 894