xlp_pci.c revision 233540
1/*- 2 * Copyright (c) 2003-2009 RMI Corporation 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. Neither the name of RMI Corporation, nor the names of its contributors, 14 * may be used to endorse or promote products derived from this software 15 * without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * NETLOGIC_BSD */ 30#include <sys/cdefs.h> 31__FBSDID("$FreeBSD: head/sys/mips/nlm/xlp_pci.c 233540 2012-03-27 11:17:04Z jchandra $"); 32 33#include <sys/param.h> 34#include <sys/systm.h> 35#include <sys/types.h> 36#include <sys/kernel.h> 37#include <sys/module.h> 38#include <sys/malloc.h> 39#include <sys/bus.h> 40#include <sys/endian.h> 41#include <sys/rman.h> 42 43#include <vm/vm.h> 44#include <vm/vm_param.h> 45#include <vm/pmap.h> 46 47#include <sys/pciio.h> 48#include <dev/pci/pcivar.h> 49#include <dev/pci/pcireg.h> 50#include <dev/uart/uart.h> 51#include <dev/uart/uart_bus.h> 52#include <dev/uart/uart_cpu.h> 53 54#include <machine/bus.h> 55#include <machine/md_var.h> 56#include <machine/intr_machdep.h> 57#include <machine/cpuregs.h> 58 59#include <mips/nlm/hal/haldefs.h> 60#include <mips/nlm/interrupt.h> 61#include <mips/nlm/hal/iomap.h> 62#include <mips/nlm/hal/mips-extns.h> 63#include <mips/nlm/hal/pic.h> 64#include <mips/nlm/hal/bridge.h> 65#include <mips/nlm/hal/pcibus.h> 66#include <mips/nlm/hal/uart.h> 67#include <mips/nlm/xlp.h> 68 69#include "pcib_if.h" 70 71struct xlp_pcib_softc { 72 bus_dma_tag_t sc_pci_dmat; /* PCI DMA tag pointer */ 73}; 74 75static devclass_t pcib_devclass; 76static struct rman irq_rman, port_rman, mem_rman, emul_rman; 77 78static void 79xlp_pci_init_resources(void) 80{ 81 irq_rman.rm_start = 0; 82 irq_rman.rm_end = 255; 83 irq_rman.rm_type = RMAN_ARRAY; 84 irq_rman.rm_descr = "PCI Mapped Interrupts"; 85 if (rman_init(&irq_rman) 86 || rman_manage_region(&irq_rman, 0, 255)) 87 panic("pci_init_resources irq_rman"); 88 89 port_rman.rm_start = 0; 90 port_rman.rm_end = ~0ul; 91 port_rman.rm_type = RMAN_ARRAY; 92 port_rman.rm_descr = "I/O ports"; 93 if (rman_init(&port_rman) 94 || rman_manage_region(&port_rman, PCIE_IO_BASE, PCIE_IO_LIMIT)) 95 panic("pci_init_resources port_rman"); 96 97 mem_rman.rm_start = 0; 98 mem_rman.rm_end = ~0ul; 99 mem_rman.rm_type = RMAN_ARRAY; 100 mem_rman.rm_descr = "I/O memory"; 101 if (rman_init(&mem_rman) 102 || rman_manage_region(&mem_rman, PCIE_MEM_BASE, PCIE_MEM_LIMIT)) 103 panic("pci_init_resources mem_rman"); 104 105 /* 106 * This includes the GBU (nor flash) memory range and the PCIe 107 * memory area. 108 */ 109 emul_rman.rm_start = 0; 110 emul_rman.rm_end = ~0ul; 111 emul_rman.rm_type = RMAN_ARRAY; 112 emul_rman.rm_descr = "Emulated MEMIO"; 113 if (rman_init(&emul_rman) 114 || rman_manage_region(&emul_rman, 0x16000000UL, 0x18ffffffUL)) 115 panic("pci_init_resources emul_rman"); 116} 117 118static int 119xlp_pcib_probe(device_t dev) 120{ 121 122 device_set_desc(dev, "XLP PCI bus"); 123 xlp_pci_init_resources(); 124 return (0); 125} 126 127static int 128xlp_pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 129{ 130 131 switch (which) { 132 case PCIB_IVAR_DOMAIN: 133 *result = 0; 134 return (0); 135 case PCIB_IVAR_BUS: 136 *result = 0; 137 return (0); 138 } 139 return (ENOENT); 140} 141 142static int 143xlp_pcib_write_ivar(device_t dev, device_t child, int which, uintptr_t result) 144{ 145 switch (which) { 146 case PCIB_IVAR_DOMAIN: 147 return (EINVAL); 148 case PCIB_IVAR_BUS: 149 return (EINVAL); 150 } 151 return (ENOENT); 152} 153 154static int 155xlp_pcib_maxslots(device_t dev) 156{ 157 158 return (PCI_SLOTMAX); 159} 160 161static u_int32_t 162xlp_pcib_read_config(device_t dev, u_int b, u_int s, u_int f, 163 u_int reg, int width) 164{ 165 uint32_t data = 0; 166 uint64_t cfgaddr; 167 int regindex = reg/sizeof(uint32_t); 168 169 cfgaddr = nlm_pcicfg_base(XLP_HDR_OFFSET(0, b, s, f)); 170 if ((width == 2) && (reg & 1)) 171 return 0xFFFFFFFF; 172 else if ((width == 4) && (reg & 3)) 173 return 0xFFFFFFFF; 174 175 data = nlm_read_pci_reg(cfgaddr, regindex); 176 177 /* 178 * Fix up read data in some SoC devices 179 * to emulate complete PCIe header 180 */ 181 if (b == 0) { 182 int dev = s % 8; 183 184 /* Fake intpin on config read for UART/I2C, USB, SD/Flash */ 185 if (regindex == 0xf && 186 (dev == 6 || dev == 2 || dev == 7)) 187 data |= 0x1 << 8; /* Fake int pin */ 188 } 189 if (width == 1) 190 return ((data >> ((reg & 3) << 3)) & 0xff); 191 else if (width == 2) 192 return ((data >> ((reg & 3) << 3)) & 0xffff); 193 else 194 return (data); 195} 196 197static void 198xlp_pcib_write_config(device_t dev, u_int b, u_int s, u_int f, 199 u_int reg, u_int32_t val, int width) 200{ 201 uint64_t cfgaddr; 202 uint32_t data = 0; 203 int regindex = reg / sizeof(uint32_t); 204 205 cfgaddr = nlm_pcicfg_base(XLP_HDR_OFFSET(0, b, s, f)); 206 if ((width == 2) && (reg & 1)) 207 return; 208 else if ((width == 4) && (reg & 3)) 209 return; 210 211 if (width == 1) { 212 data = nlm_read_pci_reg(cfgaddr, regindex); 213 data = (data & ~(0xff << ((reg & 3) << 3))) | 214 (val << ((reg & 3) << 3)); 215 } else if (width == 2) { 216 data = nlm_read_pci_reg(cfgaddr, regindex); 217 data = (data & ~(0xffff << ((reg & 3) << 3))) | 218 (val << ((reg & 3) << 3)); 219 } else { 220 data = val; 221 } 222 223 nlm_write_pci_reg(cfgaddr, regindex, data); 224 return; 225} 226 227/* 228 * Enable byte swap in hardware. Program a link's PCIe SWAP regions 229 * from the link's IO and MEM address ranges. 230 */ 231static void 232xlp_pci_hardware_swap_enable(int node, int link) 233{ 234 uint64_t bbase, linkpcibase; 235 uint32_t bar; 236 int pcieoffset; 237 238 pcieoffset = XLP_IO_PCIE_OFFSET(node, link); 239 if (!nlm_dev_exists(pcieoffset)) 240 return; 241 242 bbase = nlm_get_bridge_regbase(node); 243 linkpcibase = nlm_pcicfg_base(pcieoffset); 244 bar = nlm_read_bridge_reg(bbase, BRIDGE_PCIEMEM_BASE0 + link); 245 nlm_write_pci_reg(linkpcibase, PCIE_BYTE_SWAP_MEM_BASE, bar); 246 247 bar = nlm_read_bridge_reg(bbase, BRIDGE_PCIEMEM_LIMIT0 + link); 248 nlm_write_pci_reg(linkpcibase, PCIE_BYTE_SWAP_MEM_LIM, bar); 249 250 bar = nlm_read_bridge_reg(bbase, BRIDGE_PCIEIO_BASE0 + link); 251 nlm_write_pci_reg(linkpcibase, PCIE_BYTE_SWAP_IO_BASE, bar); 252 253 bar = nlm_read_bridge_reg(bbase, BRIDGE_PCIEIO_LIMIT0 + link); 254 nlm_write_pci_reg(linkpcibase, PCIE_BYTE_SWAP_IO_LIM, bar); 255} 256 257static int 258xlp_pcib_attach(device_t dev) 259{ 260 int node, link; 261 262 /* enable hardware swap on all nodes/links */ 263 for (node = 0; node < XLP_MAX_NODES; node++) 264 for (link = 0; link < 4; link++) 265 xlp_pci_hardware_swap_enable(node, link); 266 267 device_add_child(dev, "pci", 0); 268 bus_generic_attach(dev); 269 return (0); 270} 271 272static void 273xlp_pcib_identify(driver_t * driver, device_t parent) 274{ 275 276 BUS_ADD_CHILD(parent, 0, "pcib", 0); 277} 278 279/* 280 * XLS PCIe can have upto 4 links, and each link has its on IRQ 281 * Find the link on which the device is on 282 */ 283static int 284xlp_pcie_link(device_t pcib, device_t dev) 285{ 286 device_t parent, tmp; 287 288 /* find the lane on which the slot is connected to */ 289 tmp = dev; 290 while (1) { 291 parent = device_get_parent(tmp); 292 if (parent == NULL || parent == pcib) { 293 device_printf(dev, "Cannot find parent bus\n"); 294 return (-1); 295 } 296 if (strcmp(device_get_nameunit(parent), "pci0") == 0) 297 break; 298 tmp = parent; 299 } 300 return (pci_get_function(tmp)); 301} 302 303static int 304xlp_alloc_msi(device_t pcib, device_t dev, int count, int maxcount, int *irqs) 305{ 306 int i, link; 307 308 /* 309 * Each link has 32 MSIs that can be allocated, but for now 310 * we only support one device per link. 311 * msi_alloc() equivalent is needed when we start supporting 312 * bridges on the PCIe link. 313 */ 314 link = xlp_pcie_link(pcib, dev); 315 if (link == -1) 316 return (ENXIO); 317 318 /* 319 * encode the irq so that we know it is a MSI interrupt when we 320 * setup interrupts 321 */ 322 for (i = 0; i < count; i++) 323 irqs[i] = 64 + link * 32 + i; 324 325 return (0); 326} 327 328static int 329xlp_release_msi(device_t pcib, device_t dev, int count, int *irqs) 330{ 331 return (0); 332} 333 334static int 335xlp_map_msi(device_t pcib, device_t dev, int irq, uint64_t *addr, 336 uint32_t *data) 337{ 338 int msi, irt; 339 340 if (irq >= 64) { 341 msi = irq - 64; 342 *addr = MIPS_MSI_ADDR(0); 343 344 irt = xlp_pcie_link_irt(msi/32); 345 if (irt != -1) 346 *data = MIPS_MSI_DATA(xlp_irt_to_irq(irt)); 347 return (0); 348 } else { 349 device_printf(dev, "%s: map_msi for irq %d - ignored", 350 device_get_nameunit(pcib), irq); 351 return (ENXIO); 352 } 353} 354 355static void 356bridge_pcie_ack(int irq) 357{ 358 uint32_t node,reg; 359 uint64_t base; 360 361 node = nlm_nodeid(); 362 reg = PCIE_MSI_STATUS; 363 364 switch (irq) { 365 case PIC_PCIE_0_IRQ: 366 base = nlm_pcicfg_base(XLP_IO_PCIE0_OFFSET(node)); 367 break; 368 case PIC_PCIE_1_IRQ: 369 base = nlm_pcicfg_base(XLP_IO_PCIE1_OFFSET(node)); 370 break; 371 case PIC_PCIE_2_IRQ: 372 base = nlm_pcicfg_base(XLP_IO_PCIE2_OFFSET(node)); 373 break; 374 case PIC_PCIE_3_IRQ: 375 base = nlm_pcicfg_base(XLP_IO_PCIE3_OFFSET(node)); 376 break; 377 default: 378 return; 379 } 380 381 nlm_write_pci_reg(base, reg, 0xFFFFFFFF); 382 return; 383} 384 385static int 386mips_platform_pci_setup_intr(device_t dev, device_t child, 387 struct resource *irq, int flags, driver_filter_t *filt, 388 driver_intr_t *intr, void *arg, void **cookiep) 389{ 390 int error = 0; 391 int xlpirq; 392 void *extra_ack; 393 394 error = rman_activate_resource(irq); 395 if (error) 396 return error; 397 if (rman_get_start(irq) != rman_get_end(irq)) { 398 device_printf(dev, "Interrupt allocation %lu != %lu\n", 399 rman_get_start(irq), rman_get_end(irq)); 400 return (EINVAL); 401 } 402 xlpirq = rman_get_start(irq); 403 404 if (strcmp(device_get_name(dev), "pcib") != 0) { 405 device_printf(dev, "ret 0 on dev\n"); 406 return (0); 407 } 408 409 /* 410 * temporary hack for MSI, we support just one device per 411 * link, and assign the link interrupt to the device interrupt 412 */ 413 if (xlpirq >= 64) { 414 int node, val, link; 415 uint64_t base; 416 417 xlpirq -= 64; 418 if (xlpirq % 32 != 0) 419 return (0); 420 421 node = nlm_nodeid(); 422 link = xlpirq / 32; 423 base = nlm_pcicfg_base(XLP_IO_PCIE_OFFSET(node,link)); 424 425 /* MSI Interrupt Vector enable at bridge's configuration */ 426 nlm_write_pci_reg(base, PCIE_MSI_EN, PCIE_MSI_VECTOR_INT_EN); 427 428 val = nlm_read_pci_reg(base, PCIE_INT_EN0); 429 /* MSI Interrupt enable at bridge's configuration */ 430 nlm_write_pci_reg(base, PCIE_INT_EN0, 431 (val | PCIE_MSI_INT_EN)); 432 433 /* legacy interrupt disable at bridge */ 434 val = nlm_read_pci_reg(base, PCIE_BRIDGE_CMD); 435 nlm_write_pci_reg(base, PCIE_BRIDGE_CMD, 436 (val | PCIM_CMD_INTxDIS)); 437 438 /* MSI address update at bridge */ 439 nlm_write_pci_reg(base, PCIE_BRIDGE_MSI_ADDRL, 440 MSI_MIPS_ADDR_BASE); 441 nlm_write_pci_reg(base, PCIE_BRIDGE_MSI_ADDRH, 0); 442 443 val = nlm_read_pci_reg(base, PCIE_BRIDGE_MSI_CAP); 444 /* MSI capability enable at bridge */ 445 nlm_write_pci_reg(base, PCIE_BRIDGE_MSI_CAP, 446 (val | (PCIM_MSICTRL_MSI_ENABLE << 16) | 447 (PCIM_MSICTRL_MMC_32 << 16))); 448 449 xlpirq = xlp_pcie_link_irt(xlpirq / 32); 450 if (xlpirq == -1) 451 return (EINVAL); 452 xlpirq = xlp_irt_to_irq(xlpirq); 453 } 454 /* Set all irqs to CPU 0 for now */ 455 nlm_pic_write_irt_direct(xlp_pic_base, xlp_irq_to_irt(xlpirq), 1, 0, 456 PIC_LOCAL_SCHEDULING, xlpirq, 0); 457 extra_ack = NULL; 458 if (xlpirq >= PIC_PCIE_0_IRQ && xlpirq <= PIC_PCIE_3_IRQ) 459 extra_ack = bridge_pcie_ack; 460 xlp_establish_intr(device_get_name(child), filt, 461 intr, arg, xlpirq, flags, cookiep, extra_ack); 462 463 return (0); 464} 465 466static int 467mips_platform_pci_teardown_intr(device_t dev, device_t child, 468 struct resource *irq, void *cookie) 469{ 470 if (strcmp(device_get_name(child), "pci") == 0) { 471 /* if needed reprogram the pic to clear pcix related entry */ 472 device_printf(dev, "teardown intr\n"); 473 } 474 return (bus_generic_teardown_intr(dev, child, irq, cookie)); 475} 476 477static void 478assign_soc_resource(device_t child, int type, u_long *startp, u_long *endp, 479 u_long *countp, struct rman **rm, bus_space_tag_t *bst, vm_offset_t *va) 480{ 481 int devid, inst, node, unit; 482 483 devid = pci_get_device(child); 484 inst = pci_get_function(child); 485 node = pci_get_slot(child) / 8; 486 unit = device_get_unit(child); 487 488 *rm = NULL; 489 *va = 0; 490 *bst = 0; 491 if (type == SYS_RES_MEMORY) { 492 switch (devid) { 493 case PCI_DEVICE_ID_NLM_UART: 494 *va = nlm_get_uart_regbase(node, inst); 495 *startp = MIPS_KSEG1_TO_PHYS(*va); 496 *countp = 0x100; 497 *rm = &emul_rman; 498 *bst = uart_bus_space_mem; 499 break; 500 501 case PCI_DEVICE_ID_NLM_I2C: 502 *va = nlm_pcicfg_base(XLP_IO_I2C_OFFSET(node, unit)) + 503 XLP_IO_PCI_HDRSZ; 504 *startp = MIPS_KSEG1_TO_PHYS(*va); 505 *countp = 0x100; 506 *rm = &emul_rman; 507 *bst = uart_bus_space_mem; 508 break; 509 } 510 /* calculate end if allocated */ 511 if (*rm) 512 *endp = *startp + *countp - 1; 513 } else if (type != SYS_RES_IRQ) { 514 /* 515 * IRQ allocation is done by route_interrupt, 516 * for any other request print warning. 517 */ 518 printf("Unknown type %d in req for [%x%x]\n", 519 type, devid, inst); 520 } 521} 522 523static struct resource * 524xlp_pci_alloc_resource(device_t bus, device_t child, int type, int *rid, 525 u_long start, u_long end, u_long count, u_int flags) 526{ 527 struct rman *rm = NULL; 528 struct resource *rv; 529 vm_offset_t va = 0; 530 int needactivate = flags & RF_ACTIVE; 531 bus_space_tag_t bst = 0; 532 533 /* 534 * For SoC PCI devices, we have to assign resources correctly 535 * since the IRQ and MEM resources depend on the block. 536 * If the address is not from BAR0, then we use emul_rman 537 */ 538 if (pci_get_bus(child) == 0 && 539 pci_get_vendor(child) == PCI_VENDOR_NETLOGIC) 540 assign_soc_resource(child, type, &start, &end, 541 &count, &rm, &bst, &va); 542 if (rm == NULL) { 543 switch (type) { 544 case SYS_RES_IRQ: 545 rm = &irq_rman; 546 break; 547 548 case SYS_RES_IOPORT: 549 rm = &port_rman; 550 break; 551 552 case SYS_RES_MEMORY: 553 rm = &mem_rman; 554 break; 555 556 default: 557 return (0); 558 } 559 } 560 561 rv = rman_reserve_resource(rm, start, end, count, flags, child); 562 if (rv == 0) 563 return (0); 564 565 rman_set_rid(rv, *rid); 566 567 if (type == SYS_RES_MEMORY || type == SYS_RES_IOPORT) { 568 if (va == 0) 569 va = (vm_offset_t)pmap_mapdev(start, count); 570 if (bst == 0) 571 bst = rmi_bus_space; 572 573 rman_set_bushandle(rv, va); 574 rman_set_virtual(rv, (void *)va); 575 rman_set_bustag(rv, bst); 576 } 577 578 if (needactivate) { 579 if (bus_activate_resource(child, type, *rid, rv)) { 580 rman_release_resource(rv); 581 return (NULL); 582 } 583 } 584 585 return (rv); 586} 587 588static int 589xlp_pci_release_resource(device_t bus, device_t child, int type, int rid, 590 struct resource *r) 591{ 592 593 return (rman_release_resource(r)); 594} 595 596static bus_dma_tag_t 597xlp_pci_get_dma_tag(device_t bus, device_t child) 598{ 599 struct xlp_pcib_softc *sc; 600 601 sc = device_get_softc(bus); 602 return (sc->sc_pci_dmat); 603} 604 605static int 606xlp_pci_activate_resource(device_t bus, device_t child, int type, int rid, 607 struct resource *r) 608{ 609 610 return (rman_activate_resource(r)); 611} 612 613static int 614xlp_pci_deactivate_resource(device_t bus, device_t child, int type, int rid, 615 struct resource *r) 616{ 617 618 return (rman_deactivate_resource(r)); 619} 620 621static int 622mips_pci_route_interrupt(device_t bus, device_t dev, int pin) 623{ 624 int irt, link; 625 626 /* 627 * Validate requested pin number. 628 */ 629 if ((pin < 1) || (pin > 4)) 630 return (255); 631 632 if (pci_get_bus(dev) == 0 && 633 pci_get_vendor(dev) == PCI_VENDOR_NETLOGIC) { 634 /* SoC devices */ 635 uint64_t pcibase; 636 int f, n, d, num; 637 638 f = pci_get_function(dev); 639 n = pci_get_slot(dev) / 8; 640 d = pci_get_slot(dev) % 8; 641 642 /* 643 * For PCIe links, return link IRT, for other SoC devices 644 * get the IRT from its PCIe header 645 */ 646 if (d == 1) { 647 irt = xlp_pcie_link_irt(f); 648 } else { 649 pcibase = nlm_pcicfg_base(XLP_HDR_OFFSET(n, 0, d, f)); 650 irt = nlm_irtstart(pcibase); 651 num = nlm_irtnum(pcibase); 652 if (num != 1) 653 device_printf(bus, "[%d:%d:%d] Error %d IRQs\n", 654 n, d, f, num); 655 } 656 } else { 657 /* Regular PCI devices */ 658 link = xlp_pcie_link(bus, dev); 659 irt = xlp_pcie_link_irt(link); 660 } 661 662 if (irt != -1) 663 return (xlp_irt_to_irq(irt)); 664 665 return (255); 666} 667 668static device_method_t xlp_pcib_methods[] = { 669 /* Device interface */ 670 DEVMETHOD(device_identify, xlp_pcib_identify), 671 DEVMETHOD(device_probe, xlp_pcib_probe), 672 DEVMETHOD(device_attach, xlp_pcib_attach), 673 674 /* Bus interface */ 675 DEVMETHOD(bus_read_ivar, xlp_pcib_read_ivar), 676 DEVMETHOD(bus_write_ivar, xlp_pcib_write_ivar), 677 DEVMETHOD(bus_alloc_resource, xlp_pci_alloc_resource), 678 DEVMETHOD(bus_release_resource, xlp_pci_release_resource), 679 DEVMETHOD(bus_get_dma_tag, xlp_pci_get_dma_tag), 680 DEVMETHOD(bus_activate_resource, xlp_pci_activate_resource), 681 DEVMETHOD(bus_deactivate_resource, xlp_pci_deactivate_resource), 682 DEVMETHOD(bus_setup_intr, mips_platform_pci_setup_intr), 683 DEVMETHOD(bus_teardown_intr, mips_platform_pci_teardown_intr), 684 685 /* pcib interface */ 686 DEVMETHOD(pcib_maxslots, xlp_pcib_maxslots), 687 DEVMETHOD(pcib_read_config, xlp_pcib_read_config), 688 DEVMETHOD(pcib_write_config, xlp_pcib_write_config), 689 DEVMETHOD(pcib_route_interrupt, mips_pci_route_interrupt), 690 691 DEVMETHOD(pcib_alloc_msi, xlp_alloc_msi), 692 DEVMETHOD(pcib_release_msi, xlp_release_msi), 693 DEVMETHOD(pcib_map_msi, xlp_map_msi), 694 695 DEVMETHOD_END 696}; 697 698static driver_t xlp_pcib_driver = { 699 "pcib", 700 xlp_pcib_methods, 701 sizeof(struct xlp_pcib_softc), 702}; 703 704DRIVER_MODULE(pcib, nexus, xlp_pcib_driver, pcib_devclass, 0, 0); 705