xlp_pci.c revision 233556
1/*- 2 * Copyright (c) 2003-2009 RMI Corporation 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. Neither the name of RMI Corporation, nor the names of its contributors, 14 * may be used to endorse or promote products derived from this software 15 * without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * NETLOGIC_BSD */ 30#include <sys/cdefs.h> 31__FBSDID("$FreeBSD: head/sys/mips/nlm/xlp_pci.c 233556 2012-03-27 15:16:38Z jchandra $"); 32 33#include <sys/param.h> 34#include <sys/systm.h> 35#include <sys/types.h> 36#include <sys/kernel.h> 37#include <sys/module.h> 38#include <sys/malloc.h> 39#include <sys/bus.h> 40#include <sys/endian.h> 41#include <sys/rman.h> 42 43#include <vm/vm.h> 44#include <vm/vm_param.h> 45#include <vm/pmap.h> 46 47#include <sys/pciio.h> 48#include <dev/pci/pcivar.h> 49#include <dev/pci/pcireg.h> 50#include <dev/uart/uart.h> 51#include <dev/uart/uart_bus.h> 52#include <dev/uart/uart_cpu.h> 53 54#include <machine/bus.h> 55#include <machine/md_var.h> 56#include <machine/intr_machdep.h> 57#include <machine/cpuregs.h> 58 59#include <mips/nlm/hal/haldefs.h> 60#include <mips/nlm/interrupt.h> 61#include <mips/nlm/hal/iomap.h> 62#include <mips/nlm/hal/mips-extns.h> 63#include <mips/nlm/hal/pic.h> 64#include <mips/nlm/hal/bridge.h> 65#include <mips/nlm/hal/gbu.h> 66#include <mips/nlm/hal/pcibus.h> 67#include <mips/nlm/hal/uart.h> 68#include <mips/nlm/xlp.h> 69 70#include "pcib_if.h" 71 72struct xlp_pcib_softc { 73 bus_dma_tag_t sc_pci_dmat; /* PCI DMA tag pointer */ 74}; 75 76static devclass_t pcib_devclass; 77static struct rman irq_rman, port_rman, mem_rman, emul_rman; 78 79static void 80xlp_pci_init_resources(void) 81{ 82 irq_rman.rm_start = 0; 83 irq_rman.rm_end = 255; 84 irq_rman.rm_type = RMAN_ARRAY; 85 irq_rman.rm_descr = "PCI Mapped Interrupts"; 86 if (rman_init(&irq_rman) 87 || rman_manage_region(&irq_rman, 0, 255)) 88 panic("pci_init_resources irq_rman"); 89 90 port_rman.rm_start = 0; 91 port_rman.rm_end = ~0ul; 92 port_rman.rm_type = RMAN_ARRAY; 93 port_rman.rm_descr = "I/O ports"; 94 if (rman_init(&port_rman) 95 || rman_manage_region(&port_rman, PCIE_IO_BASE, PCIE_IO_LIMIT)) 96 panic("pci_init_resources port_rman"); 97 98 mem_rman.rm_start = 0; 99 mem_rman.rm_end = ~0ul; 100 mem_rman.rm_type = RMAN_ARRAY; 101 mem_rman.rm_descr = "I/O memory"; 102 if (rman_init(&mem_rman) 103 || rman_manage_region(&mem_rman, PCIE_MEM_BASE, PCIE_MEM_LIMIT)) 104 panic("pci_init_resources mem_rman"); 105 106 /* 107 * This includes the GBU (nor flash) memory range and the PCIe 108 * memory area. 109 */ 110 emul_rman.rm_start = 0; 111 emul_rman.rm_end = ~0ul; 112 emul_rman.rm_type = RMAN_ARRAY; 113 emul_rman.rm_descr = "Emulated MEMIO"; 114 if (rman_init(&emul_rman) 115 || rman_manage_region(&emul_rman, 0x16000000UL, 0x18ffffffUL)) 116 panic("pci_init_resources emul_rman"); 117} 118 119static int 120xlp_pcib_probe(device_t dev) 121{ 122 123 device_set_desc(dev, "XLP PCI bus"); 124 xlp_pci_init_resources(); 125 return (0); 126} 127 128static int 129xlp_pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 130{ 131 132 switch (which) { 133 case PCIB_IVAR_DOMAIN: 134 *result = 0; 135 return (0); 136 case PCIB_IVAR_BUS: 137 *result = 0; 138 return (0); 139 } 140 return (ENOENT); 141} 142 143static int 144xlp_pcib_write_ivar(device_t dev, device_t child, int which, uintptr_t result) 145{ 146 switch (which) { 147 case PCIB_IVAR_DOMAIN: 148 return (EINVAL); 149 case PCIB_IVAR_BUS: 150 return (EINVAL); 151 } 152 return (ENOENT); 153} 154 155static int 156xlp_pcib_maxslots(device_t dev) 157{ 158 159 return (PCI_SLOTMAX); 160} 161 162static u_int32_t 163xlp_pcib_read_config(device_t dev, u_int b, u_int s, u_int f, 164 u_int reg, int width) 165{ 166 uint32_t data = 0; 167 uint64_t cfgaddr; 168 int regindex = reg/sizeof(uint32_t); 169 170 cfgaddr = nlm_pcicfg_base(XLP_HDR_OFFSET(0, b, s, f)); 171 if ((width == 2) && (reg & 1)) 172 return 0xFFFFFFFF; 173 else if ((width == 4) && (reg & 3)) 174 return 0xFFFFFFFF; 175 176 data = nlm_read_pci_reg(cfgaddr, regindex); 177 178 /* 179 * Fix up read data in some SoC devices 180 * to emulate complete PCIe header 181 */ 182 if (b == 0) { 183 int dev = s % 8; 184 185 /* Fake intpin on config read for UART/I2C, USB, SD/Flash */ 186 if (regindex == 0xf && 187 (dev == 6 || dev == 2 || dev == 7)) 188 data |= 0x1 << 8; /* Fake int pin */ 189 } 190 if (width == 1) 191 return ((data >> ((reg & 3) << 3)) & 0xff); 192 else if (width == 2) 193 return ((data >> ((reg & 3) << 3)) & 0xffff); 194 else 195 return (data); 196} 197 198static void 199xlp_pcib_write_config(device_t dev, u_int b, u_int s, u_int f, 200 u_int reg, u_int32_t val, int width) 201{ 202 uint64_t cfgaddr; 203 uint32_t data = 0; 204 int regindex = reg / sizeof(uint32_t); 205 206 cfgaddr = nlm_pcicfg_base(XLP_HDR_OFFSET(0, b, s, f)); 207 if ((width == 2) && (reg & 1)) 208 return; 209 else if ((width == 4) && (reg & 3)) 210 return; 211 212 if (width == 1) { 213 data = nlm_read_pci_reg(cfgaddr, regindex); 214 data = (data & ~(0xff << ((reg & 3) << 3))) | 215 (val << ((reg & 3) << 3)); 216 } else if (width == 2) { 217 data = nlm_read_pci_reg(cfgaddr, regindex); 218 data = (data & ~(0xffff << ((reg & 3) << 3))) | 219 (val << ((reg & 3) << 3)); 220 } else { 221 data = val; 222 } 223 224 nlm_write_pci_reg(cfgaddr, regindex, data); 225 return; 226} 227 228/* 229 * Enable byte swap in hardware. Program a link's PCIe SWAP regions 230 * from the link's IO and MEM address ranges. 231 */ 232static void 233xlp_pci_hardware_swap_enable(int node, int link) 234{ 235 uint64_t bbase, linkpcibase; 236 uint32_t bar; 237 int pcieoffset; 238 239 pcieoffset = XLP_IO_PCIE_OFFSET(node, link); 240 if (!nlm_dev_exists(pcieoffset)) 241 return; 242 243 bbase = nlm_get_bridge_regbase(node); 244 linkpcibase = nlm_pcicfg_base(pcieoffset); 245 bar = nlm_read_bridge_reg(bbase, BRIDGE_PCIEMEM_BASE0 + link); 246 nlm_write_pci_reg(linkpcibase, PCIE_BYTE_SWAP_MEM_BASE, bar); 247 248 bar = nlm_read_bridge_reg(bbase, BRIDGE_PCIEMEM_LIMIT0 + link); 249 nlm_write_pci_reg(linkpcibase, PCIE_BYTE_SWAP_MEM_LIM, bar); 250 251 bar = nlm_read_bridge_reg(bbase, BRIDGE_PCIEIO_BASE0 + link); 252 nlm_write_pci_reg(linkpcibase, PCIE_BYTE_SWAP_IO_BASE, bar); 253 254 bar = nlm_read_bridge_reg(bbase, BRIDGE_PCIEIO_LIMIT0 + link); 255 nlm_write_pci_reg(linkpcibase, PCIE_BYTE_SWAP_IO_LIM, bar); 256} 257 258static int 259xlp_pcib_attach(device_t dev) 260{ 261 int node, link; 262 263 /* enable hardware swap on all nodes/links */ 264 for (node = 0; node < XLP_MAX_NODES; node++) 265 for (link = 0; link < 4; link++) 266 xlp_pci_hardware_swap_enable(node, link); 267 268 device_add_child(dev, "pci", 0); 269 bus_generic_attach(dev); 270 return (0); 271} 272 273static void 274xlp_pcib_identify(driver_t * driver, device_t parent) 275{ 276 277 BUS_ADD_CHILD(parent, 0, "pcib", 0); 278} 279 280/* 281 * XLS PCIe can have upto 4 links, and each link has its on IRQ 282 * Find the link on which the device is on 283 */ 284static int 285xlp_pcie_link(device_t pcib, device_t dev) 286{ 287 device_t parent, tmp; 288 289 /* find the lane on which the slot is connected to */ 290 tmp = dev; 291 while (1) { 292 parent = device_get_parent(tmp); 293 if (parent == NULL || parent == pcib) { 294 device_printf(dev, "Cannot find parent bus\n"); 295 return (-1); 296 } 297 if (strcmp(device_get_nameunit(parent), "pci0") == 0) 298 break; 299 tmp = parent; 300 } 301 return (pci_get_function(tmp)); 302} 303 304static int 305xlp_alloc_msi(device_t pcib, device_t dev, int count, int maxcount, int *irqs) 306{ 307 int i, link; 308 309 /* 310 * Each link has 32 MSIs that can be allocated, but for now 311 * we only support one device per link. 312 * msi_alloc() equivalent is needed when we start supporting 313 * bridges on the PCIe link. 314 */ 315 link = xlp_pcie_link(pcib, dev); 316 if (link == -1) 317 return (ENXIO); 318 319 /* 320 * encode the irq so that we know it is a MSI interrupt when we 321 * setup interrupts 322 */ 323 for (i = 0; i < count; i++) 324 irqs[i] = 64 + link * 32 + i; 325 326 return (0); 327} 328 329static int 330xlp_release_msi(device_t pcib, device_t dev, int count, int *irqs) 331{ 332 return (0); 333} 334 335static int 336xlp_map_msi(device_t pcib, device_t dev, int irq, uint64_t *addr, 337 uint32_t *data) 338{ 339 int msi, irt; 340 341 if (irq >= 64) { 342 msi = irq - 64; 343 *addr = MIPS_MSI_ADDR(0); 344 345 irt = xlp_pcie_link_irt(msi/32); 346 if (irt != -1) 347 *data = MIPS_MSI_DATA(xlp_irt_to_irq(irt)); 348 return (0); 349 } else { 350 device_printf(dev, "%s: map_msi for irq %d - ignored", 351 device_get_nameunit(pcib), irq); 352 return (ENXIO); 353 } 354} 355 356static void 357bridge_pcie_ack(int irq) 358{ 359 uint32_t node,reg; 360 uint64_t base; 361 362 node = nlm_nodeid(); 363 reg = PCIE_MSI_STATUS; 364 365 switch (irq) { 366 case PIC_PCIE_0_IRQ: 367 base = nlm_pcicfg_base(XLP_IO_PCIE0_OFFSET(node)); 368 break; 369 case PIC_PCIE_1_IRQ: 370 base = nlm_pcicfg_base(XLP_IO_PCIE1_OFFSET(node)); 371 break; 372 case PIC_PCIE_2_IRQ: 373 base = nlm_pcicfg_base(XLP_IO_PCIE2_OFFSET(node)); 374 break; 375 case PIC_PCIE_3_IRQ: 376 base = nlm_pcicfg_base(XLP_IO_PCIE3_OFFSET(node)); 377 break; 378 default: 379 return; 380 } 381 382 nlm_write_pci_reg(base, reg, 0xFFFFFFFF); 383 return; 384} 385 386static int 387mips_platform_pci_setup_intr(device_t dev, device_t child, 388 struct resource *irq, int flags, driver_filter_t *filt, 389 driver_intr_t *intr, void *arg, void **cookiep) 390{ 391 int error = 0; 392 int xlpirq; 393 void *extra_ack; 394 395 error = rman_activate_resource(irq); 396 if (error) 397 return error; 398 if (rman_get_start(irq) != rman_get_end(irq)) { 399 device_printf(dev, "Interrupt allocation %lu != %lu\n", 400 rman_get_start(irq), rman_get_end(irq)); 401 return (EINVAL); 402 } 403 xlpirq = rman_get_start(irq); 404 405 if (strcmp(device_get_name(dev), "pcib") != 0) { 406 device_printf(dev, "ret 0 on dev\n"); 407 return (0); 408 } 409 410 /* 411 * temporary hack for MSI, we support just one device per 412 * link, and assign the link interrupt to the device interrupt 413 */ 414 if (xlpirq >= 64) { 415 int node, val, link; 416 uint64_t base; 417 418 xlpirq -= 64; 419 if (xlpirq % 32 != 0) 420 return (0); 421 422 node = nlm_nodeid(); 423 link = xlpirq / 32; 424 base = nlm_pcicfg_base(XLP_IO_PCIE_OFFSET(node,link)); 425 426 /* MSI Interrupt Vector enable at bridge's configuration */ 427 nlm_write_pci_reg(base, PCIE_MSI_EN, PCIE_MSI_VECTOR_INT_EN); 428 429 val = nlm_read_pci_reg(base, PCIE_INT_EN0); 430 /* MSI Interrupt enable at bridge's configuration */ 431 nlm_write_pci_reg(base, PCIE_INT_EN0, 432 (val | PCIE_MSI_INT_EN)); 433 434 /* legacy interrupt disable at bridge */ 435 val = nlm_read_pci_reg(base, PCIE_BRIDGE_CMD); 436 nlm_write_pci_reg(base, PCIE_BRIDGE_CMD, 437 (val | PCIM_CMD_INTxDIS)); 438 439 /* MSI address update at bridge */ 440 nlm_write_pci_reg(base, PCIE_BRIDGE_MSI_ADDRL, 441 MSI_MIPS_ADDR_BASE); 442 nlm_write_pci_reg(base, PCIE_BRIDGE_MSI_ADDRH, 0); 443 444 val = nlm_read_pci_reg(base, PCIE_BRIDGE_MSI_CAP); 445 /* MSI capability enable at bridge */ 446 nlm_write_pci_reg(base, PCIE_BRIDGE_MSI_CAP, 447 (val | (PCIM_MSICTRL_MSI_ENABLE << 16) | 448 (PCIM_MSICTRL_MMC_32 << 16))); 449 450 xlpirq = xlp_pcie_link_irt(xlpirq / 32); 451 if (xlpirq == -1) 452 return (EINVAL); 453 xlpirq = xlp_irt_to_irq(xlpirq); 454 } 455 /* Set all irqs to CPU 0 for now */ 456 nlm_pic_write_irt_direct(xlp_pic_base, xlp_irq_to_irt(xlpirq), 1, 0, 457 PIC_LOCAL_SCHEDULING, xlpirq, 0); 458 extra_ack = NULL; 459 if (xlpirq >= PIC_PCIE_0_IRQ && xlpirq <= PIC_PCIE_3_IRQ) 460 extra_ack = bridge_pcie_ack; 461 xlp_establish_intr(device_get_name(child), filt, 462 intr, arg, xlpirq, flags, cookiep, extra_ack); 463 464 return (0); 465} 466 467static int 468mips_platform_pci_teardown_intr(device_t dev, device_t child, 469 struct resource *irq, void *cookie) 470{ 471 if (strcmp(device_get_name(child), "pci") == 0) { 472 /* if needed reprogram the pic to clear pcix related entry */ 473 device_printf(dev, "teardown intr\n"); 474 } 475 return (bus_generic_teardown_intr(dev, child, irq, cookie)); 476} 477 478static void 479assign_soc_resource(device_t child, int type, u_long *startp, u_long *endp, 480 u_long *countp, struct rman **rm, bus_space_tag_t *bst, vm_offset_t *va) 481{ 482 int devid, inst, node, unit; 483 uint32_t val; 484 485 devid = pci_get_device(child); 486 inst = pci_get_function(child); 487 node = pci_get_slot(child) / 8; 488 unit = device_get_unit(child); 489 490 *rm = NULL; 491 *va = 0; 492 *bst = 0; 493 if (type == SYS_RES_MEMORY) { 494 switch (devid) { 495 case PCI_DEVICE_ID_NLM_UART: 496 *va = nlm_get_uart_regbase(node, inst); 497 *startp = MIPS_KSEG1_TO_PHYS(*va); 498 *countp = 0x100; 499 *rm = &emul_rman; 500 *bst = uart_bus_space_mem; 501 break; 502 503 case PCI_DEVICE_ID_NLM_I2C: 504 *va = nlm_pcicfg_base(XLP_IO_I2C_OFFSET(node, unit)) + 505 XLP_IO_PCI_HDRSZ; 506 *startp = MIPS_KSEG1_TO_PHYS(*va); 507 *countp = 0x100; 508 *rm = &emul_rman; 509 *bst = uart_bus_space_mem; 510 break; 511 case PCI_DEVICE_ID_NLM_NOR: 512 /* XXXJC: support multiple chip selects */ 513 val = nlm_read_pci_reg(nlm_get_gbu_regbase(node), 0); 514 *startp = val << 8; 515 *va = MIPS_PHYS_TO_KSEG1(*startp); 516 /* XXXJC: count is not correct */ 517 *countp = 0x100; 518 *rm = &emul_rman; 519 break; 520 } 521 /* calculate end if allocated */ 522 if (*rm) 523 *endp = *startp + *countp - 1; 524 } else if (type != SYS_RES_IRQ) { 525 /* 526 * IRQ allocation is done by route_interrupt, 527 * for any other request print warning. 528 */ 529 printf("Unknown type %d in req for [%x%x]\n", 530 type, devid, inst); 531 } 532} 533 534static struct resource * 535xlp_pci_alloc_resource(device_t bus, device_t child, int type, int *rid, 536 u_long start, u_long end, u_long count, u_int flags) 537{ 538 struct rman *rm = NULL; 539 struct resource *rv; 540 vm_offset_t va = 0; 541 int needactivate = flags & RF_ACTIVE; 542 bus_space_tag_t bst = 0; 543 544 /* 545 * For SoC PCI devices, we have to assign resources correctly 546 * since the IRQ and MEM resources depend on the block. 547 * If the address is not from BAR0, then we use emul_rman 548 */ 549 if (pci_get_bus(child) == 0 && 550 pci_get_vendor(child) == PCI_VENDOR_NETLOGIC) 551 assign_soc_resource(child, type, &start, &end, 552 &count, &rm, &bst, &va); 553 if (rm == NULL) { 554 switch (type) { 555 case SYS_RES_IRQ: 556 rm = &irq_rman; 557 break; 558 559 case SYS_RES_IOPORT: 560 rm = &port_rman; 561 break; 562 563 case SYS_RES_MEMORY: 564 rm = &mem_rman; 565 break; 566 567 default: 568 return (0); 569 } 570 } 571 572 rv = rman_reserve_resource(rm, start, end, count, flags, child); 573 if (rv == 0) 574 return (0); 575 576 rman_set_rid(rv, *rid); 577 578 if (type == SYS_RES_MEMORY || type == SYS_RES_IOPORT) { 579 if (va == 0) 580 va = (vm_offset_t)pmap_mapdev(start, count); 581 if (bst == 0) 582 bst = rmi_bus_space; 583 584 rman_set_bushandle(rv, va); 585 rman_set_virtual(rv, (void *)va); 586 rman_set_bustag(rv, bst); 587 } 588 589 if (needactivate) { 590 if (bus_activate_resource(child, type, *rid, rv)) { 591 rman_release_resource(rv); 592 return (NULL); 593 } 594 } 595 596 return (rv); 597} 598 599static int 600xlp_pci_release_resource(device_t bus, device_t child, int type, int rid, 601 struct resource *r) 602{ 603 604 return (rman_release_resource(r)); 605} 606 607static bus_dma_tag_t 608xlp_pci_get_dma_tag(device_t bus, device_t child) 609{ 610 struct xlp_pcib_softc *sc; 611 612 sc = device_get_softc(bus); 613 return (sc->sc_pci_dmat); 614} 615 616static int 617xlp_pci_activate_resource(device_t bus, device_t child, int type, int rid, 618 struct resource *r) 619{ 620 621 return (rman_activate_resource(r)); 622} 623 624static int 625xlp_pci_deactivate_resource(device_t bus, device_t child, int type, int rid, 626 struct resource *r) 627{ 628 629 return (rman_deactivate_resource(r)); 630} 631 632static int 633mips_pci_route_interrupt(device_t bus, device_t dev, int pin) 634{ 635 int irt, link; 636 637 /* 638 * Validate requested pin number. 639 */ 640 if ((pin < 1) || (pin > 4)) 641 return (255); 642 643 if (pci_get_bus(dev) == 0 && 644 pci_get_vendor(dev) == PCI_VENDOR_NETLOGIC) { 645 /* SoC devices */ 646 uint64_t pcibase; 647 int f, n, d, num; 648 649 f = pci_get_function(dev); 650 n = pci_get_slot(dev) / 8; 651 d = pci_get_slot(dev) % 8; 652 653 /* 654 * For PCIe links, return link IRT, for other SoC devices 655 * get the IRT from its PCIe header 656 */ 657 if (d == 1) { 658 irt = xlp_pcie_link_irt(f); 659 } else { 660 pcibase = nlm_pcicfg_base(XLP_HDR_OFFSET(n, 0, d, f)); 661 irt = nlm_irtstart(pcibase); 662 num = nlm_irtnum(pcibase); 663 if (num != 1) 664 device_printf(bus, "[%d:%d:%d] Error %d IRQs\n", 665 n, d, f, num); 666 } 667 } else { 668 /* Regular PCI devices */ 669 link = xlp_pcie_link(bus, dev); 670 irt = xlp_pcie_link_irt(link); 671 } 672 673 if (irt != -1) 674 return (xlp_irt_to_irq(irt)); 675 676 return (255); 677} 678 679static device_method_t xlp_pcib_methods[] = { 680 /* Device interface */ 681 DEVMETHOD(device_identify, xlp_pcib_identify), 682 DEVMETHOD(device_probe, xlp_pcib_probe), 683 DEVMETHOD(device_attach, xlp_pcib_attach), 684 685 /* Bus interface */ 686 DEVMETHOD(bus_read_ivar, xlp_pcib_read_ivar), 687 DEVMETHOD(bus_write_ivar, xlp_pcib_write_ivar), 688 DEVMETHOD(bus_alloc_resource, xlp_pci_alloc_resource), 689 DEVMETHOD(bus_release_resource, xlp_pci_release_resource), 690 DEVMETHOD(bus_get_dma_tag, xlp_pci_get_dma_tag), 691 DEVMETHOD(bus_activate_resource, xlp_pci_activate_resource), 692 DEVMETHOD(bus_deactivate_resource, xlp_pci_deactivate_resource), 693 DEVMETHOD(bus_setup_intr, mips_platform_pci_setup_intr), 694 DEVMETHOD(bus_teardown_intr, mips_platform_pci_teardown_intr), 695 696 /* pcib interface */ 697 DEVMETHOD(pcib_maxslots, xlp_pcib_maxslots), 698 DEVMETHOD(pcib_read_config, xlp_pcib_read_config), 699 DEVMETHOD(pcib_write_config, xlp_pcib_write_config), 700 DEVMETHOD(pcib_route_interrupt, mips_pci_route_interrupt), 701 702 DEVMETHOD(pcib_alloc_msi, xlp_alloc_msi), 703 DEVMETHOD(pcib_release_msi, xlp_release_msi), 704 DEVMETHOD(pcib_map_msi, xlp_map_msi), 705 706 DEVMETHOD_END 707}; 708 709static driver_t xlp_pcib_driver = { 710 "pcib", 711 xlp_pcib_methods, 712 sizeof(struct xlp_pcib_softc), 713}; 714 715DRIVER_MODULE(pcib, nexus, xlp_pcib_driver, pcib_devclass, 0, 0); 716