1225394Sjchandra/*- 2233563Sjchandra * Copyright (c) 2003-2012 Broadcom Corporation 3233563Sjchandra * All Rights Reserved 4225394Sjchandra * 5225394Sjchandra * Redistribution and use in source and binary forms, with or without 6225394Sjchandra * modification, are permitted provided that the following conditions 7225394Sjchandra * are met: 8233563Sjchandra * 9225394Sjchandra * 1. Redistributions of source code must retain the above copyright 10225394Sjchandra * notice, this list of conditions and the following disclaimer. 11225394Sjchandra * 2. Redistributions in binary form must reproduce the above copyright 12233563Sjchandra * notice, this list of conditions and the following disclaimer in 13233563Sjchandra * the documentation and/or other materials provided with the 14233563Sjchandra * distribution. 15279387Sjchandra * 16233563Sjchandra * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR 17233563Sjchandra * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 18233563Sjchandra * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19233563Sjchandra * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE 20233563Sjchandra * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21233563Sjchandra * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22233563Sjchandra * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 23233563Sjchandra * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 24233563Sjchandra * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE 25233563Sjchandra * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN 26233563Sjchandra * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27233563Sjchandra */ 28233563Sjchandra 29225394Sjchandra#include <sys/cdefs.h> 30225394Sjchandra__FBSDID("$FreeBSD$"); 31225394Sjchandra 32225394Sjchandra#include <sys/param.h> 33225394Sjchandra#include <sys/systm.h> 34225394Sjchandra#include <sys/types.h> 35225394Sjchandra#include <sys/kernel.h> 36225394Sjchandra#include <sys/module.h> 37225394Sjchandra#include <sys/malloc.h> 38225394Sjchandra#include <sys/bus.h> 39225394Sjchandra#include <sys/endian.h> 40225394Sjchandra#include <sys/rman.h> 41233563Sjchandra#include <sys/pciio.h> 42225394Sjchandra 43225394Sjchandra#include <vm/vm.h> 44225394Sjchandra#include <vm/vm_param.h> 45225394Sjchandra#include <vm/pmap.h> 46225394Sjchandra 47225394Sjchandra#include <dev/pci/pcivar.h> 48225394Sjchandra#include <dev/pci/pcireg.h> 49233563Sjchandra#include <dev/pci/pci_private.h> 50233563Sjchandra 51225394Sjchandra#include <dev/uart/uart.h> 52225394Sjchandra#include <dev/uart/uart_bus.h> 53225394Sjchandra#include <dev/uart/uart_cpu.h> 54225394Sjchandra 55279384Sjchandra#include <dev/ofw/openfirm.h> 56279345Sjchandra#include <dev/ofw/ofw_bus.h> 57279345Sjchandra#include <dev/ofw/ofw_bus_subr.h> 58279345Sjchandra 59225394Sjchandra#include <machine/bus.h> 60225394Sjchandra#include <machine/md_var.h> 61225394Sjchandra#include <machine/intr_machdep.h> 62225394Sjchandra#include <machine/cpuregs.h> 63225394Sjchandra 64225394Sjchandra#include <mips/nlm/hal/haldefs.h> 65225394Sjchandra#include <mips/nlm/interrupt.h> 66225394Sjchandra#include <mips/nlm/hal/iomap.h> 67225394Sjchandra#include <mips/nlm/hal/mips-extns.h> 68225394Sjchandra#include <mips/nlm/hal/pic.h> 69233536Sjchandra#include <mips/nlm/hal/bridge.h> 70233556Sjchandra#include <mips/nlm/hal/gbu.h> 71225394Sjchandra#include <mips/nlm/hal/pcibus.h> 72225394Sjchandra#include <mips/nlm/hal/uart.h> 73225394Sjchandra#include <mips/nlm/xlp.h> 74225394Sjchandra 75225394Sjchandra#include "pcib_if.h" 76233563Sjchandra#include "pci_if.h" 77225394Sjchandra 78233563Sjchandrastatic int 79279384Sjchandraxlp_pci_attach(device_t dev) 80233563Sjchandra{ 81233563Sjchandra struct pci_devinfo *dinfo; 82279384Sjchandra device_t pcib; 83279384Sjchandra int maxslots, s, f, pcifunchigh, irq; 84279384Sjchandra int busno, node, devoffset; 85233563Sjchandra uint16_t devid; 86233563Sjchandra uint8_t hdrtype; 87233563Sjchandra 88233563Sjchandra /* 89233563Sjchandra * The on-chip devices are on a bus that is almost, but not 90233563Sjchandra * quite, completely like PCI. Add those things by hand. 91233563Sjchandra */ 92279384Sjchandra pcib = device_get_parent(dev); 93233563Sjchandra busno = pcib_get_bus(dev); 94233563Sjchandra maxslots = PCIB_MAXSLOTS(pcib); 95233563Sjchandra for (s = 0; s <= maxslots; s++) { 96233563Sjchandra pcifunchigh = 0; 97233563Sjchandra f = 0; 98233563Sjchandra hdrtype = PCIB_READ_CONFIG(pcib, busno, s, f, PCIR_HDRTYPE, 1); 99233563Sjchandra if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE) 100233563Sjchandra continue; 101233563Sjchandra if (hdrtype & PCIM_MFDEV) 102233563Sjchandra pcifunchigh = PCI_FUNCMAX; 103279384Sjchandra node = s / 8; 104279384Sjchandra for (f = 0; f <= pcifunchigh; f++) { 105279384Sjchandra devoffset = XLP_HDR_OFFSET(node, 0, s % 8, f); 106279384Sjchandra if (!nlm_dev_exists(devoffset)) 107279384Sjchandra continue; 108279384Sjchandra 109279384Sjchandra /* Find if there is a desc for the SoC device */ 110279384Sjchandra devid = PCIB_READ_CONFIG(pcib, busno, s, f, PCIR_DEVICE, 2); 111279384Sjchandra 112279384Sjchandra /* Skip devices that don't have a proper PCI header */ 113279384Sjchandra switch (devid) { 114279384Sjchandra case PCI_DEVICE_ID_NLM_ICI: 115279384Sjchandra case PCI_DEVICE_ID_NLM_PIC: 116279384Sjchandra case PCI_DEVICE_ID_NLM_FMN: 117279384Sjchandra case PCI_DEVICE_ID_NLM_UART: 118279384Sjchandra case PCI_DEVICE_ID_NLM_I2C: 119279384Sjchandra case PCI_DEVICE_ID_NLM_NOR: 120279384Sjchandra case PCI_DEVICE_ID_NLM_MMC: 121279384Sjchandra continue; 122279384Sjchandra case PCI_DEVICE_ID_NLM_EHCI: 123279384Sjchandra irq = PIC_USB_IRQ(f); 124279384Sjchandra PCIB_WRITE_CONFIG(pcib, busno, s, f, 125279384Sjchandra XLP_PCI_DEVSCRATCH_REG0 << 2, 126279384Sjchandra (1 << 8) | irq, 4); 127279384Sjchandra } 128298029Sjhb dinfo = pci_read_device(pcib, dev, pcib_get_domain(dev), 129298029Sjhb busno, s, f); 130279384Sjchandra pci_add_child(dev, dinfo); 131279384Sjchandra } 132233563Sjchandra } 133233563Sjchandra return (bus_generic_attach(dev)); 134233563Sjchandra} 135233563Sjchandra 136233563Sjchandrastatic int 137233563Sjchandraxlp_pci_probe(device_t dev) 138233563Sjchandra{ 139233563Sjchandra device_t pcib; 140233563Sjchandra 141233563Sjchandra pcib = device_get_parent(dev); 142233563Sjchandra /* 143233563Sjchandra * Only the top level bus has SoC devices, leave the rest to 144233563Sjchandra * Generic PCI code 145233563Sjchandra */ 146233563Sjchandra if (strcmp(device_get_nameunit(pcib), "pcib0") != 0) 147233563Sjchandra return (ENXIO); 148233563Sjchandra device_set_desc(dev, "XLP SoCbus"); 149233563Sjchandra return (BUS_PROBE_DEFAULT); 150233563Sjchandra} 151233563Sjchandra 152233563Sjchandrastatic devclass_t pci_devclass; 153233563Sjchandrastatic device_method_t xlp_pci_methods[] = { 154233563Sjchandra /* Device interface */ 155233563Sjchandra DEVMETHOD(device_probe, xlp_pci_probe), 156233563Sjchandra DEVMETHOD(device_attach, xlp_pci_attach), 157298712Sjhb DEVMETHOD(bus_rescan, bus_null_rescan), 158233563Sjchandra DEVMETHOD_END 159233563Sjchandra}; 160233563Sjchandra 161233570SjchandraDEFINE_CLASS_1(pci, xlp_pci_driver, xlp_pci_methods, sizeof(struct pci_softc), 162233570Sjchandra pci_driver); 163233563SjchandraDRIVER_MODULE(xlp_pci, pcib, xlp_pci_driver, pci_devclass, 0, 0); 164233563Sjchandra 165225394Sjchandrastatic int 166225394Sjchandraxlp_pcib_probe(device_t dev) 167225394Sjchandra{ 168225394Sjchandra 169279345Sjchandra if (ofw_bus_is_compatible(dev, "netlogic,xlp-pci")) { 170279345Sjchandra device_set_desc(dev, "XLP PCI bus"); 171279345Sjchandra return (BUS_PROBE_DEFAULT); 172279345Sjchandra } 173279345Sjchandra return (ENXIO); 174225394Sjchandra} 175225394Sjchandra 176225394Sjchandrastatic int 177225394Sjchandraxlp_pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 178225394Sjchandra{ 179225394Sjchandra 180225394Sjchandra switch (which) { 181225394Sjchandra case PCIB_IVAR_DOMAIN: 182225394Sjchandra *result = 0; 183225394Sjchandra return (0); 184225394Sjchandra case PCIB_IVAR_BUS: 185225394Sjchandra *result = 0; 186225394Sjchandra return (0); 187225394Sjchandra } 188225394Sjchandra return (ENOENT); 189225394Sjchandra} 190225394Sjchandra 191225394Sjchandrastatic int 192225394Sjchandraxlp_pcib_write_ivar(device_t dev, device_t child, int which, uintptr_t result) 193225394Sjchandra{ 194225394Sjchandra switch (which) { 195225394Sjchandra case PCIB_IVAR_DOMAIN: 196225394Sjchandra return (EINVAL); 197225394Sjchandra case PCIB_IVAR_BUS: 198225394Sjchandra return (EINVAL); 199225394Sjchandra } 200225394Sjchandra return (ENOENT); 201225394Sjchandra} 202225394Sjchandra 203225394Sjchandrastatic int 204225394Sjchandraxlp_pcib_maxslots(device_t dev) 205225394Sjchandra{ 206225394Sjchandra 207225394Sjchandra return (PCI_SLOTMAX); 208225394Sjchandra} 209225394Sjchandra 210225394Sjchandrastatic u_int32_t 211225394Sjchandraxlp_pcib_read_config(device_t dev, u_int b, u_int s, u_int f, 212225394Sjchandra u_int reg, int width) 213225394Sjchandra{ 214225394Sjchandra uint32_t data = 0; 215225394Sjchandra uint64_t cfgaddr; 216225394Sjchandra int regindex = reg/sizeof(uint32_t); 217225394Sjchandra 218225394Sjchandra cfgaddr = nlm_pcicfg_base(XLP_HDR_OFFSET(0, b, s, f)); 219225394Sjchandra if ((width == 2) && (reg & 1)) 220225394Sjchandra return 0xFFFFFFFF; 221225394Sjchandra else if ((width == 4) && (reg & 3)) 222225394Sjchandra return 0xFFFFFFFF; 223225394Sjchandra 224279387Sjchandra /* 225233563Sjchandra * The intline and int pin of SoC devices are DOA, except 226233563Sjchandra * for bridges (slot %8 == 1). 227233563Sjchandra * use the values we stashed in a writable PCI scratch reg. 228225394Sjchandra */ 229233563Sjchandra if (b == 0 && regindex == 0xf && s % 8 > 1) 230233563Sjchandra regindex = XLP_PCI_DEVSCRATCH_REG0; 231225394Sjchandra 232233563Sjchandra data = nlm_read_pci_reg(cfgaddr, regindex); 233225394Sjchandra if (width == 1) 234225394Sjchandra return ((data >> ((reg & 3) << 3)) & 0xff); 235225394Sjchandra else if (width == 2) 236225394Sjchandra return ((data >> ((reg & 3) << 3)) & 0xffff); 237225394Sjchandra else 238225394Sjchandra return (data); 239225394Sjchandra} 240225394Sjchandra 241225394Sjchandrastatic void 242225394Sjchandraxlp_pcib_write_config(device_t dev, u_int b, u_int s, u_int f, 243225394Sjchandra u_int reg, u_int32_t val, int width) 244225394Sjchandra{ 245225394Sjchandra uint64_t cfgaddr; 246225394Sjchandra uint32_t data = 0; 247225394Sjchandra int regindex = reg / sizeof(uint32_t); 248225394Sjchandra 249225394Sjchandra cfgaddr = nlm_pcicfg_base(XLP_HDR_OFFSET(0, b, s, f)); 250225394Sjchandra if ((width == 2) && (reg & 1)) 251225394Sjchandra return; 252225394Sjchandra else if ((width == 4) && (reg & 3)) 253225394Sjchandra return; 254225394Sjchandra 255225394Sjchandra if (width == 1) { 256225394Sjchandra data = nlm_read_pci_reg(cfgaddr, regindex); 257225394Sjchandra data = (data & ~(0xff << ((reg & 3) << 3))) | 258225394Sjchandra (val << ((reg & 3) << 3)); 259225394Sjchandra } else if (width == 2) { 260225394Sjchandra data = nlm_read_pci_reg(cfgaddr, regindex); 261225394Sjchandra data = (data & ~(0xffff << ((reg & 3) << 3))) | 262225394Sjchandra (val << ((reg & 3) << 3)); 263225394Sjchandra } else { 264225394Sjchandra data = val; 265225394Sjchandra } 266225394Sjchandra 267233563Sjchandra /* 268233563Sjchandra * use shadow reg for intpin/intline which are dead 269233563Sjchandra */ 270233563Sjchandra if (b == 0 && regindex == 0xf && s % 8 > 1) 271233563Sjchandra regindex = XLP_PCI_DEVSCRATCH_REG0; 272225394Sjchandra nlm_write_pci_reg(cfgaddr, regindex, data); 273225394Sjchandra} 274225394Sjchandra 275233536Sjchandra/* 276245877Sjchandra * Enable byte swap in hardware when compiled big-endian. 277245877Sjchandra * Programs a link's PCIe SWAP regions from the link's IO and MEM address 278245877Sjchandra * ranges. 279233536Sjchandra */ 280233536Sjchandrastatic void 281233563Sjchandraxlp_pcib_hardware_swap_enable(int node, int link) 282233536Sjchandra{ 283245877Sjchandra#if BYTE_ORDER == BIG_ENDIAN 284233536Sjchandra uint64_t bbase, linkpcibase; 285233536Sjchandra uint32_t bar; 286233536Sjchandra int pcieoffset; 287233536Sjchandra 288233536Sjchandra pcieoffset = XLP_IO_PCIE_OFFSET(node, link); 289233536Sjchandra if (!nlm_dev_exists(pcieoffset)) 290233536Sjchandra return; 291233536Sjchandra 292233536Sjchandra bbase = nlm_get_bridge_regbase(node); 293233536Sjchandra linkpcibase = nlm_pcicfg_base(pcieoffset); 294233536Sjchandra bar = nlm_read_bridge_reg(bbase, BRIDGE_PCIEMEM_BASE0 + link); 295233536Sjchandra nlm_write_pci_reg(linkpcibase, PCIE_BYTE_SWAP_MEM_BASE, bar); 296233536Sjchandra 297233536Sjchandra bar = nlm_read_bridge_reg(bbase, BRIDGE_PCIEMEM_LIMIT0 + link); 298238289Sjchandra nlm_write_pci_reg(linkpcibase, PCIE_BYTE_SWAP_MEM_LIM, bar | 0xFFF); 299233536Sjchandra 300233536Sjchandra bar = nlm_read_bridge_reg(bbase, BRIDGE_PCIEIO_BASE0 + link); 301233536Sjchandra nlm_write_pci_reg(linkpcibase, PCIE_BYTE_SWAP_IO_BASE, bar); 302233536Sjchandra 303233536Sjchandra bar = nlm_read_bridge_reg(bbase, BRIDGE_PCIEIO_LIMIT0 + link); 304238289Sjchandra nlm_write_pci_reg(linkpcibase, PCIE_BYTE_SWAP_IO_LIM, bar | 0xFFF); 305245877Sjchandra#endif 306233536Sjchandra} 307233536Sjchandra 308279387Sjchandrastatic int 309225394Sjchandraxlp_pcib_attach(device_t dev) 310225394Sjchandra{ 311233536Sjchandra int node, link; 312225394Sjchandra 313233536Sjchandra /* enable hardware swap on all nodes/links */ 314233536Sjchandra for (node = 0; node < XLP_MAX_NODES; node++) 315233536Sjchandra for (link = 0; link < 4; link++) 316233563Sjchandra xlp_pcib_hardware_swap_enable(node, link); 317233536Sjchandra 318287882Szbb device_add_child(dev, "pci", -1); 319225394Sjchandra bus_generic_attach(dev); 320225394Sjchandra return (0); 321225394Sjchandra} 322225394Sjchandra 323225394Sjchandra/* 324225394Sjchandra * XLS PCIe can have upto 4 links, and each link has its on IRQ 325279387Sjchandra * Find the link on which the device is on 326225394Sjchandra */ 327225394Sjchandrastatic int 328225394Sjchandraxlp_pcie_link(device_t pcib, device_t dev) 329225394Sjchandra{ 330225394Sjchandra device_t parent, tmp; 331225394Sjchandra 332225394Sjchandra /* find the lane on which the slot is connected to */ 333225394Sjchandra tmp = dev; 334225394Sjchandra while (1) { 335225394Sjchandra parent = device_get_parent(tmp); 336225394Sjchandra if (parent == NULL || parent == pcib) { 337225394Sjchandra device_printf(dev, "Cannot find parent bus\n"); 338225394Sjchandra return (-1); 339225394Sjchandra } 340225394Sjchandra if (strcmp(device_get_nameunit(parent), "pci0") == 0) 341225394Sjchandra break; 342225394Sjchandra tmp = parent; 343225394Sjchandra } 344225394Sjchandra return (pci_get_function(tmp)); 345225394Sjchandra} 346225394Sjchandra 347225394Sjchandrastatic int 348225394Sjchandraxlp_alloc_msi(device_t pcib, device_t dev, int count, int maxcount, int *irqs) 349225394Sjchandra{ 350225394Sjchandra int i, link; 351225394Sjchandra 352225394Sjchandra /* 353225394Sjchandra * Each link has 32 MSIs that can be allocated, but for now 354225394Sjchandra * we only support one device per link. 355279387Sjchandra * msi_alloc() equivalent is needed when we start supporting 356225394Sjchandra * bridges on the PCIe link. 357225394Sjchandra */ 358225394Sjchandra link = xlp_pcie_link(pcib, dev); 359225394Sjchandra if (link == -1) 360225394Sjchandra return (ENXIO); 361225394Sjchandra 362225394Sjchandra /* 363225394Sjchandra * encode the irq so that we know it is a MSI interrupt when we 364225394Sjchandra * setup interrupts 365225394Sjchandra */ 366225394Sjchandra for (i = 0; i < count; i++) 367225394Sjchandra irqs[i] = 64 + link * 32 + i; 368225394Sjchandra 369225394Sjchandra return (0); 370225394Sjchandra} 371225394Sjchandra 372225394Sjchandrastatic int 373225394Sjchandraxlp_release_msi(device_t pcib, device_t dev, int count, int *irqs) 374225394Sjchandra{ 375225394Sjchandra return (0); 376225394Sjchandra} 377225394Sjchandra 378225394Sjchandrastatic int 379225394Sjchandraxlp_map_msi(device_t pcib, device_t dev, int irq, uint64_t *addr, 380225394Sjchandra uint32_t *data) 381225394Sjchandra{ 382279306Sjchandra int link; 383225394Sjchandra 384279306Sjchandra if (irq < 64) { 385279387Sjchandra device_printf(dev, "%s: map_msi for irq %d - ignored", 386225394Sjchandra device_get_nameunit(pcib), irq); 387225394Sjchandra return (ENXIO); 388225394Sjchandra } 389279306Sjchandra link = (irq - 64) / 32; 390279306Sjchandra *addr = MIPS_MSI_ADDR(0); 391279306Sjchandra *data = MIPS_MSI_DATA(PIC_PCIE_IRQ(link)); 392279306Sjchandra return (0); 393225394Sjchandra} 394225394Sjchandra 395225394Sjchandrastatic void 396279341Sjchandrabridge_pcie_ack(int irq, void *arg) 397225394Sjchandra{ 398225394Sjchandra uint32_t node,reg; 399225394Sjchandra uint64_t base; 400225394Sjchandra 401225394Sjchandra node = nlm_nodeid(); 402225394Sjchandra reg = PCIE_MSI_STATUS; 403225394Sjchandra 404227783Sjchandra switch (irq) { 405225394Sjchandra case PIC_PCIE_0_IRQ: 406225394Sjchandra base = nlm_pcicfg_base(XLP_IO_PCIE0_OFFSET(node)); 407225394Sjchandra break; 408225394Sjchandra case PIC_PCIE_1_IRQ: 409225394Sjchandra base = nlm_pcicfg_base(XLP_IO_PCIE1_OFFSET(node)); 410225394Sjchandra break; 411225394Sjchandra case PIC_PCIE_2_IRQ: 412225394Sjchandra base = nlm_pcicfg_base(XLP_IO_PCIE2_OFFSET(node)); 413225394Sjchandra break; 414225394Sjchandra case PIC_PCIE_3_IRQ: 415225394Sjchandra base = nlm_pcicfg_base(XLP_IO_PCIE3_OFFSET(node)); 416225394Sjchandra break; 417225394Sjchandra default: 418225394Sjchandra return; 419225394Sjchandra } 420225394Sjchandra 421225394Sjchandra nlm_write_pci_reg(base, reg, 0xFFFFFFFF); 422225394Sjchandra return; 423225394Sjchandra} 424225394Sjchandra 425225394Sjchandrastatic int 426233563Sjchandramips_platform_pcib_setup_intr(device_t dev, device_t child, 427225394Sjchandra struct resource *irq, int flags, driver_filter_t *filt, 428225394Sjchandra driver_intr_t *intr, void *arg, void **cookiep) 429225394Sjchandra{ 430225394Sjchandra int error = 0; 431225394Sjchandra int xlpirq; 432225394Sjchandra 433225394Sjchandra error = rman_activate_resource(irq); 434225394Sjchandra if (error) 435225394Sjchandra return error; 436225394Sjchandra if (rman_get_start(irq) != rman_get_end(irq)) { 437297000Sjhibbits device_printf(dev, "Interrupt allocation %ju != %ju\n", 438225394Sjchandra rman_get_start(irq), rman_get_end(irq)); 439225394Sjchandra return (EINVAL); 440225394Sjchandra } 441225394Sjchandra xlpirq = rman_get_start(irq); 442233563Sjchandra if (xlpirq == 0) 443233563Sjchandra return (0); 444225394Sjchandra 445233563Sjchandra if (strcmp(device_get_name(dev), "pcib") != 0) 446225394Sjchandra return (0); 447225394Sjchandra 448279387Sjchandra /* 449225394Sjchandra * temporary hack for MSI, we support just one device per 450225394Sjchandra * link, and assign the link interrupt to the device interrupt 451225394Sjchandra */ 452225394Sjchandra if (xlpirq >= 64) { 453227783Sjchandra int node, val, link; 454227783Sjchandra uint64_t base; 455227783Sjchandra 456225394Sjchandra xlpirq -= 64; 457225394Sjchandra if (xlpirq % 32 != 0) 458225394Sjchandra return (0); 459225394Sjchandra 460225394Sjchandra node = nlm_nodeid(); 461233536Sjchandra link = xlpirq / 32; 462225394Sjchandra base = nlm_pcicfg_base(XLP_IO_PCIE_OFFSET(node,link)); 463225394Sjchandra 464225394Sjchandra /* MSI Interrupt Vector enable at bridge's configuration */ 465225394Sjchandra nlm_write_pci_reg(base, PCIE_MSI_EN, PCIE_MSI_VECTOR_INT_EN); 466225394Sjchandra 467225394Sjchandra val = nlm_read_pci_reg(base, PCIE_INT_EN0); 468225394Sjchandra /* MSI Interrupt enable at bridge's configuration */ 469225394Sjchandra nlm_write_pci_reg(base, PCIE_INT_EN0, 470233536Sjchandra (val | PCIE_MSI_INT_EN)); 471225394Sjchandra 472225394Sjchandra /* legacy interrupt disable at bridge */ 473225394Sjchandra val = nlm_read_pci_reg(base, PCIE_BRIDGE_CMD); 474225394Sjchandra nlm_write_pci_reg(base, PCIE_BRIDGE_CMD, 475233536Sjchandra (val | PCIM_CMD_INTxDIS)); 476225394Sjchandra 477225394Sjchandra /* MSI address update at bridge */ 478225394Sjchandra nlm_write_pci_reg(base, PCIE_BRIDGE_MSI_ADDRL, 479233536Sjchandra MSI_MIPS_ADDR_BASE); 480233536Sjchandra nlm_write_pci_reg(base, PCIE_BRIDGE_MSI_ADDRH, 0); 481225394Sjchandra 482225394Sjchandra val = nlm_read_pci_reg(base, PCIE_BRIDGE_MSI_CAP); 483225394Sjchandra /* MSI capability enable at bridge */ 484279387Sjchandra nlm_write_pci_reg(base, PCIE_BRIDGE_MSI_CAP, 485233536Sjchandra (val | (PCIM_MSICTRL_MSI_ENABLE << 16) | 486233536Sjchandra (PCIM_MSICTRL_MMC_32 << 16))); 487279306Sjchandra xlpirq = PIC_PCIE_IRQ(link); 488279306Sjchandra } 489225394Sjchandra 490279341Sjchandra /* if it is for real PCIe, we need to ack at bridge too */ 491279341Sjchandra if (xlpirq >= PIC_PCIE_IRQ(0) && xlpirq <= PIC_PCIE_IRQ(3)) 492279341Sjchandra xlp_set_bus_ack(xlpirq, bridge_pcie_ack, NULL); 493279341Sjchandra cpu_establish_hardintr(device_get_name(child), filt, intr, arg, 494279341Sjchandra xlpirq, flags, cookiep); 495225394Sjchandra 496225394Sjchandra return (0); 497225394Sjchandra} 498225394Sjchandra 499225394Sjchandrastatic int 500233563Sjchandramips_platform_pcib_teardown_intr(device_t dev, device_t child, 501225394Sjchandra struct resource *irq, void *cookie) 502225394Sjchandra{ 503225394Sjchandra if (strcmp(device_get_name(child), "pci") == 0) { 504225394Sjchandra /* if needed reprogram the pic to clear pcix related entry */ 505225394Sjchandra device_printf(dev, "teardown intr\n"); 506225394Sjchandra } 507225394Sjchandra return (bus_generic_teardown_intr(dev, child, irq, cookie)); 508225394Sjchandra} 509225394Sjchandra 510225394Sjchandrastatic int 511233563Sjchandramips_pcib_route_interrupt(device_t bus, device_t dev, int pin) 512225394Sjchandra{ 513279306Sjchandra int f, d; 514225394Sjchandra 515225394Sjchandra /* 516225394Sjchandra * Validate requested pin number. 517225394Sjchandra */ 518225394Sjchandra if ((pin < 1) || (pin > 4)) 519225394Sjchandra return (255); 520225394Sjchandra 521227783Sjchandra if (pci_get_bus(dev) == 0 && 522227783Sjchandra pci_get_vendor(dev) == PCI_VENDOR_NETLOGIC) { 523227783Sjchandra f = pci_get_function(dev); 524227783Sjchandra d = pci_get_slot(dev) % 8; 525227783Sjchandra 526227783Sjchandra /* 527227783Sjchandra * For PCIe links, return link IRT, for other SoC devices 528227783Sjchandra * get the IRT from its PCIe header 529227783Sjchandra */ 530279306Sjchandra if (d == 1) 531279306Sjchandra return (PIC_PCIE_IRQ(f)); 532279306Sjchandra else 533279306Sjchandra return (255); /* use intline, don't reroute */ 534227783Sjchandra } else { 535227783Sjchandra /* Regular PCI devices */ 536279306Sjchandra return (PIC_PCIE_IRQ(xlp_pcie_link(bus, dev))); 537227783Sjchandra } 538225394Sjchandra} 539225394Sjchandra 540225394Sjchandrastatic device_method_t xlp_pcib_methods[] = { 541225394Sjchandra /* Device interface */ 542225394Sjchandra DEVMETHOD(device_probe, xlp_pcib_probe), 543225394Sjchandra DEVMETHOD(device_attach, xlp_pcib_attach), 544225394Sjchandra 545225394Sjchandra /* Bus interface */ 546225394Sjchandra DEVMETHOD(bus_read_ivar, xlp_pcib_read_ivar), 547225394Sjchandra DEVMETHOD(bus_write_ivar, xlp_pcib_write_ivar), 548279384Sjchandra DEVMETHOD(bus_alloc_resource, bus_generic_alloc_resource), 549279384Sjchandra DEVMETHOD(bus_release_resource, bus_generic_release_resource), 550279384Sjchandra DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 551279384Sjchandra DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 552233563Sjchandra DEVMETHOD(bus_setup_intr, mips_platform_pcib_setup_intr), 553233563Sjchandra DEVMETHOD(bus_teardown_intr, mips_platform_pcib_teardown_intr), 554225394Sjchandra 555225394Sjchandra /* pcib interface */ 556225394Sjchandra DEVMETHOD(pcib_maxslots, xlp_pcib_maxslots), 557225394Sjchandra DEVMETHOD(pcib_read_config, xlp_pcib_read_config), 558225394Sjchandra DEVMETHOD(pcib_write_config, xlp_pcib_write_config), 559233563Sjchandra DEVMETHOD(pcib_route_interrupt, mips_pcib_route_interrupt), 560225394Sjchandra 561225394Sjchandra DEVMETHOD(pcib_alloc_msi, xlp_alloc_msi), 562225394Sjchandra DEVMETHOD(pcib_release_msi, xlp_release_msi), 563225394Sjchandra DEVMETHOD(pcib_map_msi, xlp_map_msi), 564225394Sjchandra 565227843Smarius DEVMETHOD_END 566225394Sjchandra}; 567225394Sjchandra 568225394Sjchandrastatic driver_t xlp_pcib_driver = { 569225394Sjchandra "pcib", 570225394Sjchandra xlp_pcib_methods, 571233563Sjchandra 1, /* no softc */ 572225394Sjchandra}; 573225394Sjchandra 574279345Sjchandrastatic devclass_t pcib_devclass; 575279345SjchandraDRIVER_MODULE(xlp_pcib, simplebus, xlp_pcib_driver, pcib_devclass, 0, 0); 576