1224110Sjchandra/*- 2224110Sjchandra * Copyright 2003-2011 Netlogic Microsystems (Netlogic). All rights 3224110Sjchandra * reserved. 4224110Sjchandra * 5224110Sjchandra * Redistribution and use in source and binary forms, with or without 6224110Sjchandra * modification, are permitted provided that the following conditions are 7224110Sjchandra * met: 8224110Sjchandra * 9224110Sjchandra * 1. Redistributions of source code must retain the above copyright 10224110Sjchandra * notice, this list of conditions and the following disclaimer. 11224110Sjchandra * 2. Redistributions in binary form must reproduce the above copyright 12224110Sjchandra * notice, this list of conditions and the following disclaimer in 13224110Sjchandra * the documentation and/or other materials provided with the 14224110Sjchandra * distribution. 15224110Sjchandra * 16224110Sjchandra * THIS SOFTWARE IS PROVIDED BY Netlogic Microsystems ``AS IS'' AND 17224110Sjchandra * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18224110Sjchandra * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19224110Sjchandra * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE 20224110Sjchandra * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21224110Sjchandra * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22224110Sjchandra * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23224110Sjchandra * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24224110Sjchandra * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25224110Sjchandra * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 26224110Sjchandra * THE POSSIBILITY OF SUCH DAMAGE. 27224110Sjchandra * 28225394Sjchandra * NETLOGIC_BSD 29224110Sjchandra * $FreeBSD$ 30225394Sjchandra */ 31224110Sjchandra 32224110Sjchandra#ifndef __NLM_MIPS_EXTNS_H__ 33227722Sjchandra#define __NLM_MIPS_EXTNS_H__ 34224110Sjchandra 35224110Sjchandra#if !defined(LOCORE) && !defined(__ASSEMBLY__) 36224110Sjchandrastatic __inline__ int32_t nlm_swapw(int32_t *loc, int32_t val) 37224110Sjchandra{ 38224110Sjchandra int32_t oldval = 0; 39224110Sjchandra 40224110Sjchandra __asm__ __volatile__ ( 41224110Sjchandra ".set push\n" 42224110Sjchandra ".set noreorder\n" 43224110Sjchandra "move $9, %2\n" 44224110Sjchandra "move $8, %3\n" 45224110Sjchandra ".word 0x71280014\n" /* "swapw $8, $9\n" */ 46224110Sjchandra "move %1, $8\n" 47224110Sjchandra ".set pop\n" 48224110Sjchandra : "+m" (*loc), "=r" (oldval) 49224110Sjchandra : "r" (loc), "r" (val) 50224110Sjchandra : "$8", "$9" ); 51224110Sjchandra 52224110Sjchandra return oldval; 53224110Sjchandra} 54224110Sjchandra 55224110Sjchandrastatic __inline__ uint32_t nlm_swapwu(int32_t *loc, uint32_t val) 56224110Sjchandra{ 57224110Sjchandra uint32_t oldval; 58224110Sjchandra 59224110Sjchandra __asm__ __volatile__ ( 60224110Sjchandra ".set push\n" 61224110Sjchandra ".set noreorder\n" 62224110Sjchandra "move $9, %2\n" 63224110Sjchandra "move $8, %3\n" 64224110Sjchandra ".word 0x71280015\n" /* "swapwu $8, $9\n" */ 65224110Sjchandra "move %1, $8\n" 66224110Sjchandra ".set pop\n" 67224110Sjchandra : "+m" (*loc), "=r" (oldval) 68224110Sjchandra : "r" (loc), "r" (val) 69224110Sjchandra : "$8", "$9" ); 70224110Sjchandra 71224110Sjchandra return oldval; 72224110Sjchandra} 73224110Sjchandra 74224110Sjchandra#if (__mips == 64) 75224110Sjchandrastatic __inline__ uint64_t nlm_swapd(int32_t *loc, uint64_t val) 76224110Sjchandra{ 77224110Sjchandra uint64_t oldval; 78224110Sjchandra 79224110Sjchandra __asm__ __volatile__ ( 80224110Sjchandra ".set push\n" 81224110Sjchandra ".set noreorder\n" 82224110Sjchandra "move $9, %2\n" 83224110Sjchandra "move $8, %3\n" 84224110Sjchandra ".word 0x71280014\n" /* "swapw $8, $9\n" */ 85224110Sjchandra "move %1, $8\n" 86224110Sjchandra ".set pop\n" 87224110Sjchandra : "+m" (*loc), "=r" (oldval) 88224110Sjchandra : "r" (loc), "r" (val) 89224110Sjchandra : "$8", "$9" ); 90224110Sjchandra 91224110Sjchandra return oldval; 92224110Sjchandra} 93224110Sjchandra#endif 94224110Sjchandra 95225394Sjchandra/* 96225394Sjchandra * Atomic increment a unsigned int 97225394Sjchandra */ 98225394Sjchandrastatic __inline unsigned int 99225394Sjchandranlm_ldaddwu(unsigned int value, unsigned int *addr) 100225394Sjchandra{ 101225394Sjchandra __asm__ __volatile__( 102225394Sjchandra ".set push\n" 103225394Sjchandra ".set noreorder\n" 104225394Sjchandra "move $8, %2\n" 105225394Sjchandra "move $9, %3\n" 106225394Sjchandra ".word 0x71280011\n" /* ldaddwu $8, $9 */ 107225394Sjchandra "move %0, $8\n" 108225394Sjchandra ".set pop\n" 109225394Sjchandra : "=&r"(value), "+m"(*addr) 110225394Sjchandra : "0"(value), "r" ((unsigned long)addr) 111225394Sjchandra : "$8", "$9"); 112225394Sjchandra 113225394Sjchandra return (value); 114225394Sjchandra} 115225394Sjchandra/* 116225394Sjchandra * 32 bit read write for c0 117225394Sjchandra */ 118227722Sjchandra#define read_c0_register32(reg, sel) \ 119225394Sjchandra({ \ 120225394Sjchandra uint32_t __rv; \ 121225394Sjchandra __asm__ __volatile__( \ 122225394Sjchandra ".set push\n\t" \ 123225394Sjchandra ".set mips32\n\t" \ 124225394Sjchandra "mfc0 %0, $%1, %2\n\t" \ 125225394Sjchandra ".set pop\n" \ 126225394Sjchandra : "=r" (__rv) : "i" (reg), "i" (sel) ); \ 127225394Sjchandra __rv; \ 128225394Sjchandra }) 129225394Sjchandra 130227722Sjchandra#define write_c0_register32(reg, sel, value) \ 131225394Sjchandra __asm__ __volatile__( \ 132225394Sjchandra ".set push\n\t" \ 133225394Sjchandra ".set mips32\n\t" \ 134225394Sjchandra "mtc0 %0, $%1, %2\n\t" \ 135225394Sjchandra ".set pop\n" \ 136225394Sjchandra : : "r" (value), "i" (reg), "i" (sel) ); 137225394Sjchandra 138224110Sjchandra#if defined(__mips_n64) || defined(__mips_n32) 139225394Sjchandra/* 140225394Sjchandra * On 64 bit compilation, the operations are simple 141225394Sjchandra */ 142227722Sjchandra#define read_c0_register64(reg, sel) \ 143225394Sjchandra({ \ 144225394Sjchandra uint64_t __rv; \ 145225394Sjchandra __asm__ __volatile__( \ 146225394Sjchandra ".set push\n\t" \ 147225394Sjchandra ".set mips64\n\t" \ 148225394Sjchandra "dmfc0 %0, $%1, %2\n\t" \ 149225394Sjchandra ".set pop\n" \ 150225394Sjchandra : "=r" (__rv) : "i" (reg), "i" (sel) ); \ 151225394Sjchandra __rv; \ 152225394Sjchandra }) 153225394Sjchandra 154227722Sjchandra#define write_c0_register64(reg, sel, value) \ 155225394Sjchandra __asm__ __volatile__( \ 156225394Sjchandra ".set push\n\t" \ 157225394Sjchandra ".set mips64\n\t" \ 158225394Sjchandra "dmtc0 %0, $%1, %2\n\t" \ 159225394Sjchandra ".set pop\n" \ 160225394Sjchandra : : "r" (value), "i" (reg), "i" (sel) ); 161225394Sjchandra#else /* ! (defined(__mips_n64) || defined(__mips_n32)) */ 162225394Sjchandra 163225394Sjchandra/* 164279387Sjchandra * 32 bit compilation, 64 bit values has to split 165225394Sjchandra */ 166227722Sjchandra#define read_c0_register64(reg, sel) \ 167225394Sjchandra({ \ 168225394Sjchandra uint32_t __high, __low; \ 169225394Sjchandra __asm__ __volatile__( \ 170225394Sjchandra ".set push\n\t" \ 171225394Sjchandra ".set noreorder\n\t" \ 172225394Sjchandra ".set mips64\n\t" \ 173225394Sjchandra "dmfc0 $8, $%2, %3\n\t" \ 174225394Sjchandra "dsra32 %0, $8, 0\n\t" \ 175225394Sjchandra "sll %1, $8, 0\n\t" \ 176225394Sjchandra ".set pop\n" \ 177225394Sjchandra : "=r"(__high), "=r"(__low): "i"(reg), "i"(sel) \ 178225394Sjchandra : "$8"); \ 179225394Sjchandra ((uint64_t)__high << 32) | __low; \ 180225394Sjchandra}) 181225394Sjchandra 182227722Sjchandra#define write_c0_register64(reg, sel, value) \ 183225394Sjchandrado { \ 184225394Sjchandra uint32_t __high = value >> 32; \ 185225394Sjchandra uint32_t __low = value & 0xffffffff; \ 186225394Sjchandra __asm__ __volatile__( \ 187225394Sjchandra ".set push\n\t" \ 188225394Sjchandra ".set noreorder\n\t" \ 189225394Sjchandra ".set mips64\n\t" \ 190225394Sjchandra "dsll32 $8, %1, 0\n\t" \ 191225394Sjchandra "dsll32 $9, %0, 0\n\t" \ 192225394Sjchandra "dsrl32 $8, $8, 0\n\t" \ 193225394Sjchandra "or $8, $8, $9\n\t" \ 194225394Sjchandra "dmtc0 $8, $%2, %3\n\t" \ 195225394Sjchandra ".set pop" \ 196225394Sjchandra :: "r"(__high), "r"(__low), "i"(reg), "i"(sel) \ 197225394Sjchandra :"$8", "$9"); \ 198225394Sjchandra} while(0) 199225394Sjchandra 200225394Sjchandra#endif 201225394Sjchandra/* functions to write to and read from the extended 202225394Sjchandra * cp0 registers. 203225394Sjchandra * EIRR : Extended Interrupt Request Register 204225394Sjchandra * cp0 register 9 sel 6 205225394Sjchandra * bits 0...7 are same as cause register 8...15 206225394Sjchandra * EIMR : Extended Interrupt Mask Register 207225394Sjchandra * cp0 register 9 sel 7 208225394Sjchandra * bits 0...7 are same as status register 8...15 209225394Sjchandra */ 210279387Sjchandrastatic __inline uint64_t 211225394Sjchandranlm_read_c0_eirr(void) 212224110Sjchandra{ 213224110Sjchandra 214225394Sjchandra return (read_c0_register64(9, 6)); 215224110Sjchandra} 216224110Sjchandra 217224110Sjchandrastatic __inline void 218225394Sjchandranlm_write_c0_eirr(uint64_t val) 219224110Sjchandra{ 220225394Sjchandra 221225394Sjchandra write_c0_register64(9, 6, val); 222224110Sjchandra} 223224110Sjchandra 224279387Sjchandrastatic __inline uint64_t 225225394Sjchandranlm_read_c0_eimr(void) 226225394Sjchandra{ 227224110Sjchandra 228225394Sjchandra return (read_c0_register64(9, 7)); 229225394Sjchandra} 230225394Sjchandra 231225394Sjchandrastatic __inline void 232225394Sjchandranlm_write_c0_eimr(uint64_t val) 233224110Sjchandra{ 234224110Sjchandra 235225394Sjchandra write_c0_register64(9, 7, val); 236224110Sjchandra} 237224110Sjchandra 238225394Sjchandrastatic __inline__ uint32_t 239225394Sjchandranlm_read_c0_ebase(void) 240224110Sjchandra{ 241224110Sjchandra 242225394Sjchandra return (read_c0_register32(15, 1)); 243224110Sjchandra} 244224110Sjchandra 245225394Sjchandrastatic __inline__ int 246225394Sjchandranlm_nodeid(void) 247225394Sjchandra{ 248225394Sjchandra return (nlm_read_c0_ebase() >> 5) & 0x3; 249225394Sjchandra} 250224110Sjchandra 251225394Sjchandrastatic __inline__ int 252225394Sjchandranlm_cpuid(void) 253224110Sjchandra{ 254225394Sjchandra return nlm_read_c0_ebase() & 0x1f; 255225394Sjchandra} 256224110Sjchandra 257225394Sjchandrastatic __inline__ int 258225394Sjchandranlm_threadid(void) 259225394Sjchandra{ 260225394Sjchandra return nlm_read_c0_ebase() & 0x3; 261224110Sjchandra} 262225394Sjchandra 263225394Sjchandrastatic __inline__ int 264225394Sjchandranlm_coreid(void) 265225394Sjchandra{ 266225394Sjchandra return (nlm_read_c0_ebase() >> 2) & 0x7; 267225394Sjchandra} 268224110Sjchandra#endif 269225394Sjchandra 270227722Sjchandra#define XLP_MAX_NODES 4 271227722Sjchandra#define XLP_MAX_CORES 8 272227722Sjchandra#define XLP_MAX_THREADS 4 273225394Sjchandra 274224110Sjchandra#endif 275