pmap.c revision 241156
1/* 2 * Copyright (c) 1991 Regents of the University of California. 3 * All rights reserved. 4 * Copyright (c) 1994 John S. Dyson 5 * All rights reserved. 6 * Copyright (c) 1994 David Greenman 7 * All rights reserved. 8 * 9 * This code is derived from software contributed to Berkeley by 10 * the Systems Programming Group of the University of Utah Computer 11 * Science Department and William Jolitz of UUNET Technologies Inc. 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 1. Redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution. 21 * 4. Neither the name of the University nor the names of its contributors 22 * may be used to endorse or promote products derived from this software 23 * without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 28 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 31 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35 * SUCH DAMAGE. 36 * 37 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91 38 * from: src/sys/i386/i386/pmap.c,v 1.250.2.8 2000/11/21 00:09:14 ps 39 * JNPR: pmap.c,v 1.11.2.1 2007/08/16 11:51:06 girish 40 */ 41 42/* 43 * Manages physical address maps. 44 * 45 * Since the information managed by this module is 46 * also stored by the logical address mapping module, 47 * this module may throw away valid virtual-to-physical 48 * mappings at almost any time. However, invalidations 49 * of virtual-to-physical mappings must be done as 50 * requested. 51 * 52 * In order to cope with hardware architectures which 53 * make virtual-to-physical map invalidates expensive, 54 * this module may delay invalidate or reduced protection 55 * operations until such time as they are actually 56 * necessary. This module is given full information as 57 * to which processors are currently using which maps, 58 * and to when physical maps must be made correct. 59 */ 60 61#include <sys/cdefs.h> 62__FBSDID("$FreeBSD: head/sys/mips/mips/pmap.c 241156 2012-10-03 05:42:15Z alc $"); 63 64#include "opt_ddb.h" 65#include "opt_pmap.h" 66 67#include <sys/param.h> 68#include <sys/systm.h> 69#include <sys/lock.h> 70#include <sys/mman.h> 71#include <sys/msgbuf.h> 72#include <sys/mutex.h> 73#include <sys/pcpu.h> 74#include <sys/proc.h> 75#include <sys/rwlock.h> 76#include <sys/sched.h> 77#ifdef SMP 78#include <sys/smp.h> 79#else 80#include <sys/cpuset.h> 81#endif 82#include <sys/sysctl.h> 83#include <sys/vmmeter.h> 84 85#ifdef DDB 86#include <ddb/ddb.h> 87#endif 88 89#include <vm/vm.h> 90#include <vm/vm_param.h> 91#include <vm/vm_kern.h> 92#include <vm/vm_page.h> 93#include <vm/vm_map.h> 94#include <vm/vm_object.h> 95#include <vm/vm_extern.h> 96#include <vm/vm_pageout.h> 97#include <vm/vm_pager.h> 98#include <vm/uma.h> 99 100#include <machine/cache.h> 101#include <machine/md_var.h> 102#include <machine/tlb.h> 103 104#undef PMAP_DEBUG 105 106#if !defined(DIAGNOSTIC) 107#define PMAP_INLINE __inline 108#else 109#define PMAP_INLINE 110#endif 111 112#ifdef PV_STATS 113#define PV_STAT(x) do { x ; } while (0) 114#else 115#define PV_STAT(x) do { } while (0) 116#endif 117 118/* 119 * Get PDEs and PTEs for user/kernel address space 120 */ 121#define pmap_seg_index(v) (((v) >> SEGSHIFT) & (NPDEPG - 1)) 122#define pmap_pde_index(v) (((v) >> PDRSHIFT) & (NPDEPG - 1)) 123#define pmap_pte_index(v) (((v) >> PAGE_SHIFT) & (NPTEPG - 1)) 124#define pmap_pde_pindex(v) ((v) >> PDRSHIFT) 125 126#ifdef __mips_n64 127#define NUPDE (NPDEPG * NPDEPG) 128#define NUSERPGTBLS (NUPDE + NPDEPG) 129#else 130#define NUPDE (NPDEPG) 131#define NUSERPGTBLS (NUPDE) 132#endif 133 134#define is_kernel_pmap(x) ((x) == kernel_pmap) 135 136struct pmap kernel_pmap_store; 137pd_entry_t *kernel_segmap; 138 139vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */ 140vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */ 141 142static int nkpt; 143unsigned pmap_max_asid; /* max ASID supported by the system */ 144 145#define PMAP_ASID_RESERVED 0 146 147vm_offset_t kernel_vm_end = VM_MIN_KERNEL_ADDRESS; 148 149static void pmap_asid_alloc(pmap_t pmap); 150 151/* 152 * Isolate the global pv list lock from data and other locks to prevent false 153 * sharing within the cache. 154 */ 155static struct { 156 struct rwlock lock; 157 char padding[CACHE_LINE_SIZE - sizeof(struct rwlock)]; 158} pvh_global __aligned(CACHE_LINE_SIZE); 159 160#define pvh_global_lock pvh_global.lock 161 162/* 163 * Data for the pv entry allocation mechanism 164 */ 165static TAILQ_HEAD(pch, pv_chunk) pv_chunks = TAILQ_HEAD_INITIALIZER(pv_chunks); 166static int pv_entry_count; 167 168static void free_pv_chunk(struct pv_chunk *pc); 169static void free_pv_entry(pmap_t pmap, pv_entry_t pv); 170static pv_entry_t get_pv_entry(pmap_t pmap, boolean_t try); 171static vm_page_t pmap_pv_reclaim(pmap_t locked_pmap); 172static void pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va); 173static pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, 174 vm_offset_t va); 175static vm_page_t pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, 176 vm_page_t m, vm_prot_t prot, vm_page_t mpte); 177static int pmap_remove_pte(struct pmap *pmap, pt_entry_t *ptq, vm_offset_t va, 178 pd_entry_t pde); 179static void pmap_remove_page(struct pmap *pmap, vm_offset_t va); 180static void pmap_remove_entry(struct pmap *pmap, vm_page_t m, vm_offset_t va); 181static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_page_t mpte, 182 vm_offset_t va, vm_page_t m); 183static void pmap_update_page(pmap_t pmap, vm_offset_t va, pt_entry_t pte); 184static void pmap_invalidate_all(pmap_t pmap); 185static void pmap_invalidate_page(pmap_t pmap, vm_offset_t va); 186static void _pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m); 187 188static vm_page_t pmap_allocpte(pmap_t pmap, vm_offset_t va, int flags); 189static vm_page_t _pmap_allocpte(pmap_t pmap, unsigned ptepindex, int flags); 190static int pmap_unuse_pt(pmap_t, vm_offset_t, pd_entry_t); 191static pt_entry_t init_pte_prot(vm_page_t m, vm_prot_t access, vm_prot_t prot); 192 193static void pmap_invalidate_page_action(void *arg); 194static void pmap_invalidate_range_action(void *arg); 195static void pmap_update_page_action(void *arg); 196 197#ifndef __mips_n64 198/* 199 * This structure is for high memory (memory above 512Meg in 32 bit) support. 200 * The highmem area does not have a KSEG0 mapping, and we need a mechanism to 201 * do temporary per-CPU mappings for pmap_zero_page, pmap_copy_page etc. 202 * 203 * At bootup, we reserve 2 virtual pages per CPU for mapping highmem pages. To 204 * access a highmem physical address on a CPU, we map the physical address to 205 * the reserved virtual address for the CPU in the kernel pagetable. This is 206 * done with interrupts disabled(although a spinlock and sched_pin would be 207 * sufficient). 208 */ 209struct local_sysmaps { 210 vm_offset_t base; 211 uint32_t saved_intr; 212 uint16_t valid1, valid2; 213}; 214static struct local_sysmaps sysmap_lmem[MAXCPU]; 215 216static __inline void 217pmap_alloc_lmem_map(void) 218{ 219 int i; 220 221 for (i = 0; i < MAXCPU; i++) { 222 sysmap_lmem[i].base = virtual_avail; 223 virtual_avail += PAGE_SIZE * 2; 224 sysmap_lmem[i].valid1 = sysmap_lmem[i].valid2 = 0; 225 } 226} 227 228static __inline vm_offset_t 229pmap_lmem_map1(vm_paddr_t phys) 230{ 231 struct local_sysmaps *sysm; 232 pt_entry_t *pte, npte; 233 vm_offset_t va; 234 uint32_t intr; 235 int cpu; 236 237 intr = intr_disable(); 238 cpu = PCPU_GET(cpuid); 239 sysm = &sysmap_lmem[cpu]; 240 sysm->saved_intr = intr; 241 va = sysm->base; 242 npte = TLBLO_PA_TO_PFN(phys) | 243 PTE_D | PTE_V | PTE_G | PTE_W | PTE_C_CACHE; 244 pte = pmap_pte(kernel_pmap, va); 245 *pte = npte; 246 sysm->valid1 = 1; 247 return (va); 248} 249 250static __inline vm_offset_t 251pmap_lmem_map2(vm_paddr_t phys1, vm_paddr_t phys2) 252{ 253 struct local_sysmaps *sysm; 254 pt_entry_t *pte, npte; 255 vm_offset_t va1, va2; 256 uint32_t intr; 257 int cpu; 258 259 intr = intr_disable(); 260 cpu = PCPU_GET(cpuid); 261 sysm = &sysmap_lmem[cpu]; 262 sysm->saved_intr = intr; 263 va1 = sysm->base; 264 va2 = sysm->base + PAGE_SIZE; 265 npte = TLBLO_PA_TO_PFN(phys1) | 266 PTE_D | PTE_V | PTE_G | PTE_W | PTE_C_CACHE; 267 pte = pmap_pte(kernel_pmap, va1); 268 *pte = npte; 269 npte = TLBLO_PA_TO_PFN(phys2) | 270 PTE_D | PTE_V | PTE_G | PTE_W | PTE_C_CACHE; 271 pte = pmap_pte(kernel_pmap, va2); 272 *pte = npte; 273 sysm->valid1 = 1; 274 sysm->valid2 = 1; 275 return (va1); 276} 277 278static __inline void 279pmap_lmem_unmap(void) 280{ 281 struct local_sysmaps *sysm; 282 pt_entry_t *pte; 283 int cpu; 284 285 cpu = PCPU_GET(cpuid); 286 sysm = &sysmap_lmem[cpu]; 287 pte = pmap_pte(kernel_pmap, sysm->base); 288 *pte = PTE_G; 289 tlb_invalidate_address(kernel_pmap, sysm->base); 290 sysm->valid1 = 0; 291 if (sysm->valid2) { 292 pte = pmap_pte(kernel_pmap, sysm->base + PAGE_SIZE); 293 *pte = PTE_G; 294 tlb_invalidate_address(kernel_pmap, sysm->base + PAGE_SIZE); 295 sysm->valid2 = 0; 296 } 297 intr_restore(sysm->saved_intr); 298} 299#else /* __mips_n64 */ 300 301static __inline void 302pmap_alloc_lmem_map(void) 303{ 304} 305 306static __inline vm_offset_t 307pmap_lmem_map1(vm_paddr_t phys) 308{ 309 310 return (0); 311} 312 313static __inline vm_offset_t 314pmap_lmem_map2(vm_paddr_t phys1, vm_paddr_t phys2) 315{ 316 317 return (0); 318} 319 320static __inline vm_offset_t 321pmap_lmem_unmap(void) 322{ 323 324 return (0); 325} 326#endif /* !__mips_n64 */ 327 328/* 329 * Page table entry lookup routines. 330 */ 331static __inline pd_entry_t * 332pmap_segmap(pmap_t pmap, vm_offset_t va) 333{ 334 335 return (&pmap->pm_segtab[pmap_seg_index(va)]); 336} 337 338#ifdef __mips_n64 339static __inline pd_entry_t * 340pmap_pdpe_to_pde(pd_entry_t *pdpe, vm_offset_t va) 341{ 342 pd_entry_t *pde; 343 344 pde = (pd_entry_t *)*pdpe; 345 return (&pde[pmap_pde_index(va)]); 346} 347 348static __inline pd_entry_t * 349pmap_pde(pmap_t pmap, vm_offset_t va) 350{ 351 pd_entry_t *pdpe; 352 353 pdpe = pmap_segmap(pmap, va); 354 if (*pdpe == NULL) 355 return (NULL); 356 357 return (pmap_pdpe_to_pde(pdpe, va)); 358} 359#else 360static __inline pd_entry_t * 361pmap_pdpe_to_pde(pd_entry_t *pdpe, vm_offset_t va) 362{ 363 364 return (pdpe); 365} 366 367static __inline 368pd_entry_t *pmap_pde(pmap_t pmap, vm_offset_t va) 369{ 370 371 return (pmap_segmap(pmap, va)); 372} 373#endif 374 375static __inline pt_entry_t * 376pmap_pde_to_pte(pd_entry_t *pde, vm_offset_t va) 377{ 378 pt_entry_t *pte; 379 380 pte = (pt_entry_t *)*pde; 381 return (&pte[pmap_pte_index(va)]); 382} 383 384pt_entry_t * 385pmap_pte(pmap_t pmap, vm_offset_t va) 386{ 387 pd_entry_t *pde; 388 389 pde = pmap_pde(pmap, va); 390 if (pde == NULL || *pde == NULL) 391 return (NULL); 392 393 return (pmap_pde_to_pte(pde, va)); 394} 395 396vm_offset_t 397pmap_steal_memory(vm_size_t size) 398{ 399 vm_paddr_t bank_size, pa; 400 vm_offset_t va; 401 402 size = round_page(size); 403 bank_size = phys_avail[1] - phys_avail[0]; 404 while (size > bank_size) { 405 int i; 406 407 for (i = 0; phys_avail[i + 2]; i += 2) { 408 phys_avail[i] = phys_avail[i + 2]; 409 phys_avail[i + 1] = phys_avail[i + 3]; 410 } 411 phys_avail[i] = 0; 412 phys_avail[i + 1] = 0; 413 if (!phys_avail[0]) 414 panic("pmap_steal_memory: out of memory"); 415 bank_size = phys_avail[1] - phys_avail[0]; 416 } 417 418 pa = phys_avail[0]; 419 phys_avail[0] += size; 420 if (MIPS_DIRECT_MAPPABLE(pa) == 0) 421 panic("Out of memory below 512Meg?"); 422 va = MIPS_PHYS_TO_DIRECT(pa); 423 bzero((caddr_t)va, size); 424 return (va); 425} 426 427/* 428 * Bootstrap the system enough to run with virtual memory. This 429 * assumes that the phys_avail array has been initialized. 430 */ 431static void 432pmap_create_kernel_pagetable(void) 433{ 434 int i, j; 435 vm_offset_t ptaddr; 436 pt_entry_t *pte; 437#ifdef __mips_n64 438 pd_entry_t *pde; 439 vm_offset_t pdaddr; 440 int npt, npde; 441#endif 442 443 /* 444 * Allocate segment table for the kernel 445 */ 446 kernel_segmap = (pd_entry_t *)pmap_steal_memory(PAGE_SIZE); 447 448 /* 449 * Allocate second level page tables for the kernel 450 */ 451#ifdef __mips_n64 452 npde = howmany(NKPT, NPDEPG); 453 pdaddr = pmap_steal_memory(PAGE_SIZE * npde); 454#endif 455 nkpt = NKPT; 456 ptaddr = pmap_steal_memory(PAGE_SIZE * nkpt); 457 458 /* 459 * The R[4-7]?00 stores only one copy of the Global bit in the 460 * translation lookaside buffer for each 2 page entry. Thus invalid 461 * entrys must have the Global bit set so when Entry LO and Entry HI 462 * G bits are anded together they will produce a global bit to store 463 * in the tlb. 464 */ 465 for (i = 0, pte = (pt_entry_t *)ptaddr; i < (nkpt * NPTEPG); i++, pte++) 466 *pte = PTE_G; 467 468#ifdef __mips_n64 469 for (i = 0, npt = nkpt; npt > 0; i++) { 470 kernel_segmap[i] = (pd_entry_t)(pdaddr + i * PAGE_SIZE); 471 pde = (pd_entry_t *)kernel_segmap[i]; 472 473 for (j = 0; j < NPDEPG && npt > 0; j++, npt--) 474 pde[j] = (pd_entry_t)(ptaddr + (i * NPDEPG + j) * PAGE_SIZE); 475 } 476#else 477 for (i = 0, j = pmap_seg_index(VM_MIN_KERNEL_ADDRESS); i < nkpt; i++, j++) 478 kernel_segmap[j] = (pd_entry_t)(ptaddr + (i * PAGE_SIZE)); 479#endif 480 481 PMAP_LOCK_INIT(kernel_pmap); 482 kernel_pmap->pm_segtab = kernel_segmap; 483 CPU_FILL(&kernel_pmap->pm_active); 484 TAILQ_INIT(&kernel_pmap->pm_pvchunk); 485 kernel_pmap->pm_asid[0].asid = PMAP_ASID_RESERVED; 486 kernel_pmap->pm_asid[0].gen = 0; 487 kernel_vm_end += nkpt * NPTEPG * PAGE_SIZE; 488} 489 490void 491pmap_bootstrap(void) 492{ 493 int i; 494 int need_local_mappings = 0; 495 496 /* Sort. */ 497again: 498 for (i = 0; phys_avail[i + 1] != 0; i += 2) { 499 /* 500 * Keep the memory aligned on page boundary. 501 */ 502 phys_avail[i] = round_page(phys_avail[i]); 503 phys_avail[i + 1] = trunc_page(phys_avail[i + 1]); 504 505 if (i < 2) 506 continue; 507 if (phys_avail[i - 2] > phys_avail[i]) { 508 vm_paddr_t ptemp[2]; 509 510 ptemp[0] = phys_avail[i + 0]; 511 ptemp[1] = phys_avail[i + 1]; 512 513 phys_avail[i + 0] = phys_avail[i - 2]; 514 phys_avail[i + 1] = phys_avail[i - 1]; 515 516 phys_avail[i - 2] = ptemp[0]; 517 phys_avail[i - 1] = ptemp[1]; 518 goto again; 519 } 520 } 521 522 /* 523 * In 32 bit, we may have memory which cannot be mapped directly. 524 * This memory will need temporary mapping before it can be 525 * accessed. 526 */ 527 if (!MIPS_DIRECT_MAPPABLE(phys_avail[i - 1] - 1)) 528 need_local_mappings = 1; 529 530 /* 531 * Copy the phys_avail[] array before we start stealing memory from it. 532 */ 533 for (i = 0; phys_avail[i + 1] != 0; i += 2) { 534 physmem_desc[i] = phys_avail[i]; 535 physmem_desc[i + 1] = phys_avail[i + 1]; 536 } 537 538 Maxmem = atop(phys_avail[i - 1]); 539 540 if (bootverbose) { 541 printf("Physical memory chunk(s):\n"); 542 for (i = 0; phys_avail[i + 1] != 0; i += 2) { 543 vm_paddr_t size; 544 545 size = phys_avail[i + 1] - phys_avail[i]; 546 printf("%#08jx - %#08jx, %ju bytes (%ju pages)\n", 547 (uintmax_t) phys_avail[i], 548 (uintmax_t) phys_avail[i + 1] - 1, 549 (uintmax_t) size, (uintmax_t) size / PAGE_SIZE); 550 } 551 printf("Maxmem is 0x%0jx\n", ptoa((uintmax_t)Maxmem)); 552 } 553 /* 554 * Steal the message buffer from the beginning of memory. 555 */ 556 msgbufp = (struct msgbuf *)pmap_steal_memory(msgbufsize); 557 msgbufinit(msgbufp, msgbufsize); 558 559 /* 560 * Steal thread0 kstack. 561 */ 562 kstack0 = pmap_steal_memory(KSTACK_PAGES << PAGE_SHIFT); 563 564 virtual_avail = VM_MIN_KERNEL_ADDRESS; 565 virtual_end = VM_MAX_KERNEL_ADDRESS; 566 567#ifdef SMP 568 /* 569 * Steal some virtual address space to map the pcpu area. 570 */ 571 virtual_avail = roundup2(virtual_avail, PAGE_SIZE * 2); 572 pcpup = (struct pcpu *)virtual_avail; 573 virtual_avail += PAGE_SIZE * 2; 574 575 /* 576 * Initialize the wired TLB entry mapping the pcpu region for 577 * the BSP at 'pcpup'. Up until this point we were operating 578 * with the 'pcpup' for the BSP pointing to a virtual address 579 * in KSEG0 so there was no need for a TLB mapping. 580 */ 581 mips_pcpu_tlb_init(PCPU_ADDR(0)); 582 583 if (bootverbose) 584 printf("pcpu is available at virtual address %p.\n", pcpup); 585#endif 586 587 if (need_local_mappings) 588 pmap_alloc_lmem_map(); 589 pmap_create_kernel_pagetable(); 590 pmap_max_asid = VMNUM_PIDS; 591 mips_wr_entryhi(0); 592 mips_wr_pagemask(0); 593 594 /* 595 * Initialize the global pv list lock. 596 */ 597 rw_init(&pvh_global_lock, "pmap pv global"); 598} 599 600/* 601 * Initialize a vm_page's machine-dependent fields. 602 */ 603void 604pmap_page_init(vm_page_t m) 605{ 606 607 TAILQ_INIT(&m->md.pv_list); 608 m->md.pv_flags = 0; 609} 610 611/* 612 * Initialize the pmap module. 613 * Called by vm_init, to initialize any structures that the pmap 614 * system needs to map virtual memory. 615 */ 616void 617pmap_init(void) 618{ 619} 620 621/*************************************************** 622 * Low level helper routines..... 623 ***************************************************/ 624 625#ifdef SMP 626static __inline void 627pmap_call_on_active_cpus(pmap_t pmap, void (*fn)(void *), void *arg) 628{ 629 int cpuid, cpu, self; 630 cpuset_t active_cpus; 631 632 sched_pin(); 633 if (is_kernel_pmap(pmap)) { 634 smp_rendezvous(NULL, fn, NULL, arg); 635 goto out; 636 } 637 /* Force ASID update on inactive CPUs */ 638 CPU_FOREACH(cpu) { 639 if (!CPU_ISSET(cpu, &pmap->pm_active)) 640 pmap->pm_asid[cpu].gen = 0; 641 } 642 cpuid = PCPU_GET(cpuid); 643 /* 644 * XXX: barrier/locking for active? 645 * 646 * Take a snapshot of active here, any further changes are ignored. 647 * tlb update/invalidate should be harmless on inactive CPUs 648 */ 649 active_cpus = pmap->pm_active; 650 self = CPU_ISSET(cpuid, &active_cpus); 651 CPU_CLR(cpuid, &active_cpus); 652 /* Optimize for the case where this cpu is the only active one */ 653 if (CPU_EMPTY(&active_cpus)) { 654 if (self) 655 fn(arg); 656 } else { 657 if (self) 658 CPU_SET(cpuid, &active_cpus); 659 smp_rendezvous_cpus(active_cpus, NULL, fn, NULL, arg); 660 } 661out: 662 sched_unpin(); 663} 664#else /* !SMP */ 665static __inline void 666pmap_call_on_active_cpus(pmap_t pmap, void (*fn)(void *), void *arg) 667{ 668 int cpuid; 669 670 if (is_kernel_pmap(pmap)) { 671 fn(arg); 672 return; 673 } 674 cpuid = PCPU_GET(cpuid); 675 if (!CPU_ISSET(cpuid, &pmap->pm_active)) 676 pmap->pm_asid[cpuid].gen = 0; 677 else 678 fn(arg); 679} 680#endif /* SMP */ 681 682static void 683pmap_invalidate_all(pmap_t pmap) 684{ 685 686 pmap_call_on_active_cpus(pmap, 687 (void (*)(void *))tlb_invalidate_all_user, pmap); 688} 689 690struct pmap_invalidate_page_arg { 691 pmap_t pmap; 692 vm_offset_t va; 693}; 694 695static void 696pmap_invalidate_page_action(void *arg) 697{ 698 struct pmap_invalidate_page_arg *p = arg; 699 700 tlb_invalidate_address(p->pmap, p->va); 701} 702 703static void 704pmap_invalidate_page(pmap_t pmap, vm_offset_t va) 705{ 706 struct pmap_invalidate_page_arg arg; 707 708 arg.pmap = pmap; 709 arg.va = va; 710 pmap_call_on_active_cpus(pmap, pmap_invalidate_page_action, &arg); 711} 712 713struct pmap_invalidate_range_arg { 714 pmap_t pmap; 715 vm_offset_t sva; 716 vm_offset_t eva; 717}; 718 719static void 720pmap_invalidate_range_action(void *arg) 721{ 722 struct pmap_invalidate_range_arg *p = arg; 723 724 tlb_invalidate_range(p->pmap, p->sva, p->eva); 725} 726 727static void 728pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva) 729{ 730 struct pmap_invalidate_range_arg arg; 731 732 arg.pmap = pmap; 733 arg.sva = sva; 734 arg.eva = eva; 735 pmap_call_on_active_cpus(pmap, pmap_invalidate_range_action, &arg); 736} 737 738struct pmap_update_page_arg { 739 pmap_t pmap; 740 vm_offset_t va; 741 pt_entry_t pte; 742}; 743 744static void 745pmap_update_page_action(void *arg) 746{ 747 struct pmap_update_page_arg *p = arg; 748 749 tlb_update(p->pmap, p->va, p->pte); 750} 751 752static void 753pmap_update_page(pmap_t pmap, vm_offset_t va, pt_entry_t pte) 754{ 755 struct pmap_update_page_arg arg; 756 757 arg.pmap = pmap; 758 arg.va = va; 759 arg.pte = pte; 760 pmap_call_on_active_cpus(pmap, pmap_update_page_action, &arg); 761} 762 763/* 764 * Routine: pmap_extract 765 * Function: 766 * Extract the physical page address associated 767 * with the given map/virtual_address pair. 768 */ 769vm_paddr_t 770pmap_extract(pmap_t pmap, vm_offset_t va) 771{ 772 pt_entry_t *pte; 773 vm_offset_t retval = 0; 774 775 PMAP_LOCK(pmap); 776 pte = pmap_pte(pmap, va); 777 if (pte) { 778 retval = TLBLO_PTE_TO_PA(*pte) | (va & PAGE_MASK); 779 } 780 PMAP_UNLOCK(pmap); 781 return (retval); 782} 783 784/* 785 * Routine: pmap_extract_and_hold 786 * Function: 787 * Atomically extract and hold the physical page 788 * with the given pmap and virtual address pair 789 * if that mapping permits the given protection. 790 */ 791vm_page_t 792pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot) 793{ 794 pt_entry_t *ptep; 795 pt_entry_t pte; 796 vm_page_t m; 797 vm_paddr_t pa; 798 799 m = NULL; 800 pa = 0; 801 PMAP_LOCK(pmap); 802retry: 803 ptep = pmap_pte(pmap, va); 804 if ((ptep != NULL) && ((pte = *ptep) != 0) && 805 pte_test(&pte, PTE_V) && 806 (pte_test(&pte, PTE_D) || (prot & VM_PROT_WRITE) == 0)) { 807 if (vm_page_pa_tryrelock(pmap, TLBLO_PTE_TO_PA(pte), &pa)) 808 goto retry; 809 810 m = PHYS_TO_VM_PAGE(TLBLO_PTE_TO_PA(pte)); 811 vm_page_hold(m); 812 } 813 PA_UNLOCK_COND(pa); 814 PMAP_UNLOCK(pmap); 815 return (m); 816} 817 818/*************************************************** 819 * Low level mapping routines..... 820 ***************************************************/ 821 822/* 823 * add a wired page to the kva 824 */ 825void 826pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int attr) 827{ 828 pt_entry_t *pte; 829 pt_entry_t opte, npte; 830 831#ifdef PMAP_DEBUG 832 printf("pmap_kenter: va: %p -> pa: %p\n", (void *)va, (void *)pa); 833#endif 834 835 pte = pmap_pte(kernel_pmap, va); 836 opte = *pte; 837 npte = TLBLO_PA_TO_PFN(pa) | attr | PTE_D | PTE_V | PTE_G; 838 *pte = npte; 839 if (pte_test(&opte, PTE_V) && opte != npte) 840 pmap_update_page(kernel_pmap, va, npte); 841} 842 843void 844pmap_kenter(vm_offset_t va, vm_paddr_t pa) 845{ 846 847 KASSERT(is_cacheable_mem(pa), 848 ("pmap_kenter: memory at 0x%lx is not cacheable", (u_long)pa)); 849 850 pmap_kenter_attr(va, pa, PTE_C_CACHE); 851} 852 853/* 854 * remove a page from the kernel pagetables 855 */ 856 /* PMAP_INLINE */ void 857pmap_kremove(vm_offset_t va) 858{ 859 pt_entry_t *pte; 860 861 /* 862 * Write back all caches from the page being destroyed 863 */ 864 mips_dcache_wbinv_range_index(va, PAGE_SIZE); 865 866 pte = pmap_pte(kernel_pmap, va); 867 *pte = PTE_G; 868 pmap_invalidate_page(kernel_pmap, va); 869} 870 871/* 872 * Used to map a range of physical addresses into kernel 873 * virtual address space. 874 * 875 * The value passed in '*virt' is a suggested virtual address for 876 * the mapping. Architectures which can support a direct-mapped 877 * physical to virtual region can return the appropriate address 878 * within that region, leaving '*virt' unchanged. Other 879 * architectures should map the pages starting at '*virt' and 880 * update '*virt' with the first usable address after the mapped 881 * region. 882 * 883 * Use XKPHYS for 64 bit, and KSEG0 where possible for 32 bit. 884 */ 885vm_offset_t 886pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot) 887{ 888 vm_offset_t va, sva; 889 890 if (MIPS_DIRECT_MAPPABLE(end - 1)) 891 return (MIPS_PHYS_TO_DIRECT(start)); 892 893 va = sva = *virt; 894 while (start < end) { 895 pmap_kenter(va, start); 896 va += PAGE_SIZE; 897 start += PAGE_SIZE; 898 } 899 *virt = va; 900 return (sva); 901} 902 903/* 904 * Add a list of wired pages to the kva 905 * this routine is only used for temporary 906 * kernel mappings that do not need to have 907 * page modification or references recorded. 908 * Note that old mappings are simply written 909 * over. The page *must* be wired. 910 */ 911void 912pmap_qenter(vm_offset_t va, vm_page_t *m, int count) 913{ 914 int i; 915 vm_offset_t origva = va; 916 917 for (i = 0; i < count; i++) { 918 pmap_flush_pvcache(m[i]); 919 pmap_kenter(va, VM_PAGE_TO_PHYS(m[i])); 920 va += PAGE_SIZE; 921 } 922 923 mips_dcache_wbinv_range_index(origva, PAGE_SIZE*count); 924} 925 926/* 927 * this routine jerks page mappings from the 928 * kernel -- it is meant only for temporary mappings. 929 */ 930void 931pmap_qremove(vm_offset_t va, int count) 932{ 933 pt_entry_t *pte; 934 vm_offset_t origva; 935 936 if (count < 1) 937 return; 938 mips_dcache_wbinv_range_index(va, PAGE_SIZE * count); 939 origva = va; 940 do { 941 pte = pmap_pte(kernel_pmap, va); 942 *pte = PTE_G; 943 va += PAGE_SIZE; 944 } while (--count > 0); 945 pmap_invalidate_range(kernel_pmap, origva, va); 946} 947 948/*************************************************** 949 * Page table page management routines..... 950 ***************************************************/ 951 952/* 953 * Decrements a page table page's wire count, which is used to record the 954 * number of valid page table entries within the page. If the wire count 955 * drops to zero, then the page table page is unmapped. Returns TRUE if the 956 * page table page was unmapped and FALSE otherwise. 957 */ 958static PMAP_INLINE boolean_t 959pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m) 960{ 961 962 --m->wire_count; 963 if (m->wire_count == 0) { 964 _pmap_unwire_ptp(pmap, va, m); 965 return (TRUE); 966 } else 967 return (FALSE); 968} 969 970static void 971_pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m) 972{ 973 pd_entry_t *pde; 974 975 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 976 /* 977 * unmap the page table page 978 */ 979#ifdef __mips_n64 980 if (m->pindex < NUPDE) 981 pde = pmap_pde(pmap, va); 982 else 983 pde = pmap_segmap(pmap, va); 984#else 985 pde = pmap_pde(pmap, va); 986#endif 987 *pde = 0; 988 pmap->pm_stats.resident_count--; 989 990#ifdef __mips_n64 991 if (m->pindex < NUPDE) { 992 pd_entry_t *pdp; 993 vm_page_t pdpg; 994 995 /* 996 * Recursively decrement next level pagetable refcount 997 */ 998 pdp = (pd_entry_t *)*pmap_segmap(pmap, va); 999 pdpg = PHYS_TO_VM_PAGE(MIPS_DIRECT_TO_PHYS(pdp)); 1000 pmap_unwire_ptp(pmap, va, pdpg); 1001 } 1002#endif 1003 1004 /* 1005 * If the page is finally unwired, simply free it. 1006 */ 1007 vm_page_free_zero(m); 1008 atomic_subtract_int(&cnt.v_wire_count, 1); 1009} 1010 1011/* 1012 * After removing a page table entry, this routine is used to 1013 * conditionally free the page, and manage the hold/wire counts. 1014 */ 1015static int 1016pmap_unuse_pt(pmap_t pmap, vm_offset_t va, pd_entry_t pde) 1017{ 1018 vm_page_t mpte; 1019 1020 if (va >= VM_MAXUSER_ADDRESS) 1021 return (0); 1022 KASSERT(pde != 0, ("pmap_unuse_pt: pde != 0")); 1023 mpte = PHYS_TO_VM_PAGE(MIPS_DIRECT_TO_PHYS(pde)); 1024 return (pmap_unwire_ptp(pmap, va, mpte)); 1025} 1026 1027void 1028pmap_pinit0(pmap_t pmap) 1029{ 1030 int i; 1031 1032 PMAP_LOCK_INIT(pmap); 1033 pmap->pm_segtab = kernel_segmap; 1034 CPU_ZERO(&pmap->pm_active); 1035 for (i = 0; i < MAXCPU; i++) { 1036 pmap->pm_asid[i].asid = PMAP_ASID_RESERVED; 1037 pmap->pm_asid[i].gen = 0; 1038 } 1039 PCPU_SET(curpmap, pmap); 1040 TAILQ_INIT(&pmap->pm_pvchunk); 1041 bzero(&pmap->pm_stats, sizeof pmap->pm_stats); 1042} 1043 1044void 1045pmap_grow_direct_page_cache() 1046{ 1047 1048#ifdef __mips_n64 1049 vm_pageout_grow_cache(3, 0, MIPS_XKPHYS_LARGEST_PHYS); 1050#else 1051 vm_pageout_grow_cache(3, 0, MIPS_KSEG0_LARGEST_PHYS); 1052#endif 1053} 1054 1055vm_page_t 1056pmap_alloc_direct_page(unsigned int index, int req) 1057{ 1058 vm_page_t m; 1059 1060 m = vm_page_alloc_freelist(VM_FREELIST_DIRECT, req | VM_ALLOC_WIRED | 1061 VM_ALLOC_ZERO); 1062 if (m == NULL) 1063 return (NULL); 1064 1065 if ((m->flags & PG_ZERO) == 0) 1066 pmap_zero_page(m); 1067 1068 m->pindex = index; 1069 return (m); 1070} 1071 1072/* 1073 * Initialize a preallocated and zeroed pmap structure, 1074 * such as one in a vmspace structure. 1075 */ 1076int 1077pmap_pinit(pmap_t pmap) 1078{ 1079 vm_offset_t ptdva; 1080 vm_page_t ptdpg; 1081 int i; 1082 1083 PMAP_LOCK_INIT(pmap); 1084 1085 /* 1086 * allocate the page directory page 1087 */ 1088 while ((ptdpg = pmap_alloc_direct_page(NUSERPGTBLS, VM_ALLOC_NORMAL)) == NULL) 1089 pmap_grow_direct_page_cache(); 1090 1091 ptdva = MIPS_PHYS_TO_DIRECT(VM_PAGE_TO_PHYS(ptdpg)); 1092 pmap->pm_segtab = (pd_entry_t *)ptdva; 1093 CPU_ZERO(&pmap->pm_active); 1094 for (i = 0; i < MAXCPU; i++) { 1095 pmap->pm_asid[i].asid = PMAP_ASID_RESERVED; 1096 pmap->pm_asid[i].gen = 0; 1097 } 1098 TAILQ_INIT(&pmap->pm_pvchunk); 1099 bzero(&pmap->pm_stats, sizeof pmap->pm_stats); 1100 1101 return (1); 1102} 1103 1104/* 1105 * this routine is called if the page table page is not 1106 * mapped correctly. 1107 */ 1108static vm_page_t 1109_pmap_allocpte(pmap_t pmap, unsigned ptepindex, int flags) 1110{ 1111 vm_offset_t pageva; 1112 vm_page_t m; 1113 1114 KASSERT((flags & (M_NOWAIT | M_WAITOK)) == M_NOWAIT || 1115 (flags & (M_NOWAIT | M_WAITOK)) == M_WAITOK, 1116 ("_pmap_allocpte: flags is neither M_NOWAIT nor M_WAITOK")); 1117 1118 /* 1119 * Find or fabricate a new pagetable page 1120 */ 1121 if ((m = pmap_alloc_direct_page(ptepindex, VM_ALLOC_NORMAL)) == NULL) { 1122 if (flags & M_WAITOK) { 1123 PMAP_UNLOCK(pmap); 1124 rw_wunlock(&pvh_global_lock); 1125 pmap_grow_direct_page_cache(); 1126 rw_wlock(&pvh_global_lock); 1127 PMAP_LOCK(pmap); 1128 } 1129 1130 /* 1131 * Indicate the need to retry. While waiting, the page 1132 * table page may have been allocated. 1133 */ 1134 return (NULL); 1135 } 1136 1137 /* 1138 * Map the pagetable page into the process address space, if it 1139 * isn't already there. 1140 */ 1141 pageva = MIPS_PHYS_TO_DIRECT(VM_PAGE_TO_PHYS(m)); 1142 1143#ifdef __mips_n64 1144 if (ptepindex >= NUPDE) { 1145 pmap->pm_segtab[ptepindex - NUPDE] = (pd_entry_t)pageva; 1146 } else { 1147 pd_entry_t *pdep, *pde; 1148 int segindex = ptepindex >> (SEGSHIFT - PDRSHIFT); 1149 int pdeindex = ptepindex & (NPDEPG - 1); 1150 vm_page_t pg; 1151 1152 pdep = &pmap->pm_segtab[segindex]; 1153 if (*pdep == NULL) { 1154 /* recurse for allocating page dir */ 1155 if (_pmap_allocpte(pmap, NUPDE + segindex, 1156 flags) == NULL) { 1157 /* alloc failed, release current */ 1158 --m->wire_count; 1159 atomic_subtract_int(&cnt.v_wire_count, 1); 1160 vm_page_free_zero(m); 1161 return (NULL); 1162 } 1163 } else { 1164 pg = PHYS_TO_VM_PAGE(MIPS_DIRECT_TO_PHYS(*pdep)); 1165 pg->wire_count++; 1166 } 1167 /* Next level entry */ 1168 pde = (pd_entry_t *)*pdep; 1169 pde[pdeindex] = (pd_entry_t)pageva; 1170 } 1171#else 1172 pmap->pm_segtab[ptepindex] = (pd_entry_t)pageva; 1173#endif 1174 pmap->pm_stats.resident_count++; 1175 return (m); 1176} 1177 1178static vm_page_t 1179pmap_allocpte(pmap_t pmap, vm_offset_t va, int flags) 1180{ 1181 unsigned ptepindex; 1182 pd_entry_t *pde; 1183 vm_page_t m; 1184 1185 KASSERT((flags & (M_NOWAIT | M_WAITOK)) == M_NOWAIT || 1186 (flags & (M_NOWAIT | M_WAITOK)) == M_WAITOK, 1187 ("pmap_allocpte: flags is neither M_NOWAIT nor M_WAITOK")); 1188 1189 /* 1190 * Calculate pagetable page index 1191 */ 1192 ptepindex = pmap_pde_pindex(va); 1193retry: 1194 /* 1195 * Get the page directory entry 1196 */ 1197 pde = pmap_pde(pmap, va); 1198 1199 /* 1200 * If the page table page is mapped, we just increment the hold 1201 * count, and activate it. 1202 */ 1203 if (pde != NULL && *pde != NULL) { 1204 m = PHYS_TO_VM_PAGE(MIPS_DIRECT_TO_PHYS(*pde)); 1205 m->wire_count++; 1206 } else { 1207 /* 1208 * Here if the pte page isn't mapped, or if it has been 1209 * deallocated. 1210 */ 1211 m = _pmap_allocpte(pmap, ptepindex, flags); 1212 if (m == NULL && (flags & M_WAITOK)) 1213 goto retry; 1214 } 1215 return (m); 1216} 1217 1218 1219/*************************************************** 1220 * Pmap allocation/deallocation routines. 1221 ***************************************************/ 1222 1223/* 1224 * Release any resources held by the given physical map. 1225 * Called when a pmap initialized by pmap_pinit is being released. 1226 * Should only be called if the map contains no valid mappings. 1227 */ 1228void 1229pmap_release(pmap_t pmap) 1230{ 1231 vm_offset_t ptdva; 1232 vm_page_t ptdpg; 1233 1234 KASSERT(pmap->pm_stats.resident_count == 0, 1235 ("pmap_release: pmap resident count %ld != 0", 1236 pmap->pm_stats.resident_count)); 1237 1238 ptdva = (vm_offset_t)pmap->pm_segtab; 1239 ptdpg = PHYS_TO_VM_PAGE(MIPS_DIRECT_TO_PHYS(ptdva)); 1240 1241 ptdpg->wire_count--; 1242 atomic_subtract_int(&cnt.v_wire_count, 1); 1243 vm_page_free_zero(ptdpg); 1244 PMAP_LOCK_DESTROY(pmap); 1245} 1246 1247/* 1248 * grow the number of kernel page table entries, if needed 1249 */ 1250void 1251pmap_growkernel(vm_offset_t addr) 1252{ 1253 vm_page_t nkpg; 1254 pd_entry_t *pde, *pdpe; 1255 pt_entry_t *pte; 1256 int i; 1257 1258 mtx_assert(&kernel_map->system_mtx, MA_OWNED); 1259 addr = roundup2(addr, NBSEG); 1260 if (addr - 1 >= kernel_map->max_offset) 1261 addr = kernel_map->max_offset; 1262 while (kernel_vm_end < addr) { 1263 pdpe = pmap_segmap(kernel_pmap, kernel_vm_end); 1264#ifdef __mips_n64 1265 if (*pdpe == 0) { 1266 /* new intermediate page table entry */ 1267 nkpg = pmap_alloc_direct_page(nkpt, VM_ALLOC_INTERRUPT); 1268 if (nkpg == NULL) 1269 panic("pmap_growkernel: no memory to grow kernel"); 1270 *pdpe = (pd_entry_t)MIPS_PHYS_TO_DIRECT(VM_PAGE_TO_PHYS(nkpg)); 1271 continue; /* try again */ 1272 } 1273#endif 1274 pde = pmap_pdpe_to_pde(pdpe, kernel_vm_end); 1275 if (*pde != 0) { 1276 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK; 1277 if (kernel_vm_end - 1 >= kernel_map->max_offset) { 1278 kernel_vm_end = kernel_map->max_offset; 1279 break; 1280 } 1281 continue; 1282 } 1283 1284 /* 1285 * This index is bogus, but out of the way 1286 */ 1287 nkpg = pmap_alloc_direct_page(nkpt, VM_ALLOC_INTERRUPT); 1288 if (!nkpg) 1289 panic("pmap_growkernel: no memory to grow kernel"); 1290 nkpt++; 1291 *pde = (pd_entry_t)MIPS_PHYS_TO_DIRECT(VM_PAGE_TO_PHYS(nkpg)); 1292 1293 /* 1294 * The R[4-7]?00 stores only one copy of the Global bit in 1295 * the translation lookaside buffer for each 2 page entry. 1296 * Thus invalid entrys must have the Global bit set so when 1297 * Entry LO and Entry HI G bits are anded together they will 1298 * produce a global bit to store in the tlb. 1299 */ 1300 pte = (pt_entry_t *)*pde; 1301 for (i = 0; i < NPTEPG; i++) 1302 pte[i] = PTE_G; 1303 1304 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK; 1305 if (kernel_vm_end - 1 >= kernel_map->max_offset) { 1306 kernel_vm_end = kernel_map->max_offset; 1307 break; 1308 } 1309 } 1310} 1311 1312/*************************************************** 1313 * page management routines. 1314 ***************************************************/ 1315 1316CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE); 1317#ifdef __mips_n64 1318CTASSERT(_NPCM == 3); 1319CTASSERT(_NPCPV == 168); 1320#else 1321CTASSERT(_NPCM == 11); 1322CTASSERT(_NPCPV == 336); 1323#endif 1324 1325static __inline struct pv_chunk * 1326pv_to_chunk(pv_entry_t pv) 1327{ 1328 1329 return ((struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK)); 1330} 1331 1332#define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap) 1333 1334#ifdef __mips_n64 1335#define PC_FREE0_1 0xfffffffffffffffful 1336#define PC_FREE2 0x000000fffffffffful 1337#else 1338#define PC_FREE0_9 0xfffffffful /* Free values for index 0 through 9 */ 1339#define PC_FREE10 0x0000fffful /* Free values for index 10 */ 1340#endif 1341 1342static const u_long pc_freemask[_NPCM] = { 1343#ifdef __mips_n64 1344 PC_FREE0_1, PC_FREE0_1, PC_FREE2 1345#else 1346 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9, 1347 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9, 1348 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9, 1349 PC_FREE0_9, PC_FREE10 1350#endif 1351}; 1352 1353static SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD, 0, "VM/pmap parameters"); 1354 1355SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0, 1356 "Current number of pv entries"); 1357 1358#ifdef PV_STATS 1359static int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail; 1360 1361SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0, 1362 "Current number of pv entry chunks"); 1363SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0, 1364 "Current number of pv entry chunks allocated"); 1365SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0, 1366 "Current number of pv entry chunks frees"); 1367SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail, 0, 1368 "Number of times tried to get a chunk page but failed."); 1369 1370static long pv_entry_frees, pv_entry_allocs; 1371static int pv_entry_spare; 1372 1373SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0, 1374 "Current number of pv entry frees"); 1375SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs, 0, 1376 "Current number of pv entry allocs"); 1377SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0, 1378 "Current number of spare pv entries"); 1379#endif 1380 1381/* 1382 * We are in a serious low memory condition. Resort to 1383 * drastic measures to free some pages so we can allocate 1384 * another pv entry chunk. 1385 */ 1386static vm_page_t 1387pmap_pv_reclaim(pmap_t locked_pmap) 1388{ 1389 struct pch newtail; 1390 struct pv_chunk *pc; 1391 pd_entry_t *pde; 1392 pmap_t pmap; 1393 pt_entry_t *pte, oldpte; 1394 pv_entry_t pv; 1395 vm_offset_t va; 1396 vm_page_t m, m_pc; 1397 u_long inuse; 1398 int bit, field, freed, idx; 1399 1400 PMAP_LOCK_ASSERT(locked_pmap, MA_OWNED); 1401 pmap = NULL; 1402 m_pc = NULL; 1403 TAILQ_INIT(&newtail); 1404 while ((pc = TAILQ_FIRST(&pv_chunks)) != NULL) { 1405 TAILQ_REMOVE(&pv_chunks, pc, pc_lru); 1406 if (pmap != pc->pc_pmap) { 1407 if (pmap != NULL) { 1408 pmap_invalidate_all(pmap); 1409 if (pmap != locked_pmap) 1410 PMAP_UNLOCK(pmap); 1411 } 1412 pmap = pc->pc_pmap; 1413 /* Avoid deadlock and lock recursion. */ 1414 if (pmap > locked_pmap) 1415 PMAP_LOCK(pmap); 1416 else if (pmap != locked_pmap && !PMAP_TRYLOCK(pmap)) { 1417 pmap = NULL; 1418 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru); 1419 continue; 1420 } 1421 } 1422 1423 /* 1424 * Destroy every non-wired, 4 KB page mapping in the chunk. 1425 */ 1426 freed = 0; 1427 for (field = 0; field < _NPCM; field++) { 1428 for (inuse = ~pc->pc_map[field] & pc_freemask[field]; 1429 inuse != 0; inuse &= ~(1UL << bit)) { 1430 bit = ffsl(inuse) - 1; 1431 idx = field * sizeof(inuse) * NBBY + bit; 1432 pv = &pc->pc_pventry[idx]; 1433 va = pv->pv_va; 1434 pde = pmap_pde(pmap, va); 1435 KASSERT(pde != NULL && *pde != 0, 1436 ("pmap_pv_reclaim: pde")); 1437 pte = pmap_pde_to_pte(pde, va); 1438 oldpte = *pte; 1439 KASSERT(!pte_test(&oldpte, PTE_W), 1440 ("wired pte for unwired page")); 1441 if (is_kernel_pmap(pmap)) 1442 *pte = PTE_G; 1443 else 1444 *pte = 0; 1445 pmap_invalidate_page(pmap, va); 1446 m = PHYS_TO_VM_PAGE(TLBLO_PTE_TO_PA(oldpte)); 1447 if (pte_test(&oldpte, PTE_D)) 1448 vm_page_dirty(m); 1449 if (m->md.pv_flags & PV_TABLE_REF) 1450 vm_page_aflag_set(m, PGA_REFERENCED); 1451 m->md.pv_flags &= ~PV_TABLE_REF; 1452 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list); 1453 if (TAILQ_EMPTY(&m->md.pv_list)) 1454 vm_page_aflag_clear(m, PGA_WRITEABLE); 1455 pc->pc_map[field] |= 1UL << bit; 1456 pmap_unuse_pt(pmap, va, *pde); 1457 freed++; 1458 } 1459 } 1460 if (freed == 0) { 1461 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru); 1462 continue; 1463 } 1464 /* Every freed mapping is for a 4 KB page. */ 1465 pmap->pm_stats.resident_count -= freed; 1466 PV_STAT(pv_entry_frees += freed); 1467 PV_STAT(pv_entry_spare += freed); 1468 pv_entry_count -= freed; 1469 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 1470 for (field = 0; field < _NPCM; field++) 1471 if (pc->pc_map[field] != pc_freemask[field]) { 1472 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, 1473 pc_list); 1474 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru); 1475 1476 /* 1477 * One freed pv entry in locked_pmap is 1478 * sufficient. 1479 */ 1480 if (pmap == locked_pmap) 1481 goto out; 1482 break; 1483 } 1484 if (field == _NPCM) { 1485 PV_STAT(pv_entry_spare -= _NPCPV); 1486 PV_STAT(pc_chunk_count--); 1487 PV_STAT(pc_chunk_frees++); 1488 /* Entire chunk is free; return it. */ 1489 m_pc = PHYS_TO_VM_PAGE(MIPS_DIRECT_TO_PHYS( 1490 (vm_offset_t)pc)); 1491 break; 1492 } 1493 } 1494out: 1495 TAILQ_CONCAT(&pv_chunks, &newtail, pc_lru); 1496 if (pmap != NULL) { 1497 pmap_invalidate_all(pmap); 1498 if (pmap != locked_pmap) 1499 PMAP_UNLOCK(pmap); 1500 } 1501 return (m_pc); 1502} 1503 1504/* 1505 * free the pv_entry back to the free list 1506 */ 1507static void 1508free_pv_entry(pmap_t pmap, pv_entry_t pv) 1509{ 1510 struct pv_chunk *pc; 1511 int bit, field, idx; 1512 1513 rw_assert(&pvh_global_lock, RA_WLOCKED); 1514 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1515 PV_STAT(pv_entry_frees++); 1516 PV_STAT(pv_entry_spare++); 1517 pv_entry_count--; 1518 pc = pv_to_chunk(pv); 1519 idx = pv - &pc->pc_pventry[0]; 1520 field = idx / (sizeof(u_long) * NBBY); 1521 bit = idx % (sizeof(u_long) * NBBY); 1522 pc->pc_map[field] |= 1ul << bit; 1523 for (idx = 0; idx < _NPCM; idx++) 1524 if (pc->pc_map[idx] != pc_freemask[idx]) { 1525 /* 1526 * 98% of the time, pc is already at the head of the 1527 * list. If it isn't already, move it to the head. 1528 */ 1529 if (__predict_false(TAILQ_FIRST(&pmap->pm_pvchunk) != 1530 pc)) { 1531 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 1532 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, 1533 pc_list); 1534 } 1535 return; 1536 } 1537 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 1538 free_pv_chunk(pc); 1539} 1540 1541static void 1542free_pv_chunk(struct pv_chunk *pc) 1543{ 1544 vm_page_t m; 1545 1546 TAILQ_REMOVE(&pv_chunks, pc, pc_lru); 1547 PV_STAT(pv_entry_spare -= _NPCPV); 1548 PV_STAT(pc_chunk_count--); 1549 PV_STAT(pc_chunk_frees++); 1550 /* entire chunk is free, return it */ 1551 m = PHYS_TO_VM_PAGE(MIPS_DIRECT_TO_PHYS((vm_offset_t)pc)); 1552 vm_page_unwire(m, 0); 1553 vm_page_free(m); 1554} 1555 1556/* 1557 * get a new pv_entry, allocating a block from the system 1558 * when needed. 1559 */ 1560static pv_entry_t 1561get_pv_entry(pmap_t pmap, boolean_t try) 1562{ 1563 struct pv_chunk *pc; 1564 pv_entry_t pv; 1565 vm_page_t m; 1566 int bit, field, idx; 1567 1568 rw_assert(&pvh_global_lock, RA_WLOCKED); 1569 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1570 PV_STAT(pv_entry_allocs++); 1571 pv_entry_count++; 1572retry: 1573 pc = TAILQ_FIRST(&pmap->pm_pvchunk); 1574 if (pc != NULL) { 1575 for (field = 0; field < _NPCM; field++) { 1576 if (pc->pc_map[field]) { 1577 bit = ffsl(pc->pc_map[field]) - 1; 1578 break; 1579 } 1580 } 1581 if (field < _NPCM) { 1582 idx = field * sizeof(pc->pc_map[field]) * NBBY + bit; 1583 pv = &pc->pc_pventry[idx]; 1584 pc->pc_map[field] &= ~(1ul << bit); 1585 /* If this was the last item, move it to tail */ 1586 for (field = 0; field < _NPCM; field++) 1587 if (pc->pc_map[field] != 0) { 1588 PV_STAT(pv_entry_spare--); 1589 return (pv); /* not full, return */ 1590 } 1591 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 1592 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list); 1593 PV_STAT(pv_entry_spare--); 1594 return (pv); 1595 } 1596 } 1597 /* No free items, allocate another chunk */ 1598 m = vm_page_alloc_freelist(VM_FREELIST_DIRECT, VM_ALLOC_NORMAL | 1599 VM_ALLOC_WIRED); 1600 if (m == NULL) { 1601 if (try) { 1602 pv_entry_count--; 1603 PV_STAT(pc_chunk_tryfail++); 1604 return (NULL); 1605 } 1606 m = pmap_pv_reclaim(pmap); 1607 if (m == NULL) 1608 goto retry; 1609 } 1610 PV_STAT(pc_chunk_count++); 1611 PV_STAT(pc_chunk_allocs++); 1612 pc = (struct pv_chunk *)MIPS_PHYS_TO_DIRECT(VM_PAGE_TO_PHYS(m)); 1613 pc->pc_pmap = pmap; 1614 pc->pc_map[0] = pc_freemask[0] & ~1ul; /* preallocated bit 0 */ 1615 for (field = 1; field < _NPCM; field++) 1616 pc->pc_map[field] = pc_freemask[field]; 1617 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru); 1618 pv = &pc->pc_pventry[0]; 1619 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list); 1620 PV_STAT(pv_entry_spare += _NPCPV - 1); 1621 return (pv); 1622} 1623 1624/* 1625 * If it is the first entry on the list, it is actually 1626 * in the header and we must copy the following entry up 1627 * to the header. Otherwise we must search the list for 1628 * the entry. In either case we free the now unused entry. 1629 */ 1630 1631static pv_entry_t 1632pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va) 1633{ 1634 pv_entry_t pv; 1635 1636 rw_assert(&pvh_global_lock, RA_WLOCKED); 1637 TAILQ_FOREACH(pv, &pvh->pv_list, pv_list) { 1638 if (pmap == PV_PMAP(pv) && va == pv->pv_va) { 1639 TAILQ_REMOVE(&pvh->pv_list, pv, pv_list); 1640 break; 1641 } 1642 } 1643 return (pv); 1644} 1645 1646static void 1647pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va) 1648{ 1649 pv_entry_t pv; 1650 1651 pv = pmap_pvh_remove(pvh, pmap, va); 1652 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found, pa %lx va %lx", 1653 (u_long)VM_PAGE_TO_PHYS(__containerof(pvh, struct vm_page, md)), 1654 (u_long)va)); 1655 free_pv_entry(pmap, pv); 1656} 1657 1658static void 1659pmap_remove_entry(pmap_t pmap, vm_page_t m, vm_offset_t va) 1660{ 1661 1662 rw_assert(&pvh_global_lock, RA_WLOCKED); 1663 pmap_pvh_free(&m->md, pmap, va); 1664 if (TAILQ_EMPTY(&m->md.pv_list)) 1665 vm_page_aflag_clear(m, PGA_WRITEABLE); 1666} 1667 1668/* 1669 * Conditionally create a pv entry. 1670 */ 1671static boolean_t 1672pmap_try_insert_pv_entry(pmap_t pmap, vm_page_t mpte, vm_offset_t va, 1673 vm_page_t m) 1674{ 1675 pv_entry_t pv; 1676 1677 rw_assert(&pvh_global_lock, RA_WLOCKED); 1678 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1679 if ((pv = get_pv_entry(pmap, TRUE)) != NULL) { 1680 pv->pv_va = va; 1681 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_list); 1682 return (TRUE); 1683 } else 1684 return (FALSE); 1685} 1686 1687/* 1688 * pmap_remove_pte: do the things to unmap a page in a process 1689 */ 1690static int 1691pmap_remove_pte(struct pmap *pmap, pt_entry_t *ptq, vm_offset_t va, 1692 pd_entry_t pde) 1693{ 1694 pt_entry_t oldpte; 1695 vm_page_t m; 1696 vm_paddr_t pa; 1697 1698 rw_assert(&pvh_global_lock, RA_WLOCKED); 1699 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1700 1701 /* 1702 * Write back all cache lines from the page being unmapped. 1703 */ 1704 mips_dcache_wbinv_range_index(va, PAGE_SIZE); 1705 1706 oldpte = *ptq; 1707 if (is_kernel_pmap(pmap)) 1708 *ptq = PTE_G; 1709 else 1710 *ptq = 0; 1711 1712 if (pte_test(&oldpte, PTE_W)) 1713 pmap->pm_stats.wired_count -= 1; 1714 1715 pmap->pm_stats.resident_count -= 1; 1716 1717 if (pte_test(&oldpte, PTE_MANAGED)) { 1718 pa = TLBLO_PTE_TO_PA(oldpte); 1719 m = PHYS_TO_VM_PAGE(pa); 1720 if (pte_test(&oldpte, PTE_D)) { 1721 KASSERT(!pte_test(&oldpte, PTE_RO), 1722 ("%s: modified page not writable: va: %p, pte: %#jx", 1723 __func__, (void *)va, (uintmax_t)oldpte)); 1724 vm_page_dirty(m); 1725 } 1726 if (m->md.pv_flags & PV_TABLE_REF) 1727 vm_page_aflag_set(m, PGA_REFERENCED); 1728 m->md.pv_flags &= ~PV_TABLE_REF; 1729 1730 pmap_remove_entry(pmap, m, va); 1731 } 1732 return (pmap_unuse_pt(pmap, va, pde)); 1733} 1734 1735/* 1736 * Remove a single page from a process address space 1737 */ 1738static void 1739pmap_remove_page(struct pmap *pmap, vm_offset_t va) 1740{ 1741 pd_entry_t *pde; 1742 pt_entry_t *ptq; 1743 1744 rw_assert(&pvh_global_lock, RA_WLOCKED); 1745 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1746 pde = pmap_pde(pmap, va); 1747 if (pde == NULL || *pde == 0) 1748 return; 1749 ptq = pmap_pde_to_pte(pde, va); 1750 1751 /* 1752 * If there is no pte for this address, just skip it! 1753 */ 1754 if (!pte_test(ptq, PTE_V)) 1755 return; 1756 1757 (void)pmap_remove_pte(pmap, ptq, va, *pde); 1758 pmap_invalidate_page(pmap, va); 1759} 1760 1761/* 1762 * Remove the given range of addresses from the specified map. 1763 * 1764 * It is assumed that the start and end are properly 1765 * rounded to the page size. 1766 */ 1767void 1768pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva) 1769{ 1770 pd_entry_t *pde, *pdpe; 1771 pt_entry_t *pte; 1772 vm_offset_t va, va_next; 1773 1774 /* 1775 * Perform an unsynchronized read. This is, however, safe. 1776 */ 1777 if (pmap->pm_stats.resident_count == 0) 1778 return; 1779 1780 rw_wlock(&pvh_global_lock); 1781 PMAP_LOCK(pmap); 1782 1783 /* 1784 * special handling of removing one page. a very common operation 1785 * and easy to short circuit some code. 1786 */ 1787 if ((sva + PAGE_SIZE) == eva) { 1788 pmap_remove_page(pmap, sva); 1789 goto out; 1790 } 1791 for (; sva < eva; sva = va_next) { 1792 pdpe = pmap_segmap(pmap, sva); 1793#ifdef __mips_n64 1794 if (*pdpe == 0) { 1795 va_next = (sva + NBSEG) & ~SEGMASK; 1796 if (va_next < sva) 1797 va_next = eva; 1798 continue; 1799 } 1800#endif 1801 va_next = (sva + NBPDR) & ~PDRMASK; 1802 if (va_next < sva) 1803 va_next = eva; 1804 1805 pde = pmap_pdpe_to_pde(pdpe, sva); 1806 if (*pde == NULL) 1807 continue; 1808 1809 /* 1810 * Limit our scan to either the end of the va represented 1811 * by the current page table page, or to the end of the 1812 * range being removed. 1813 */ 1814 if (va_next > eva) 1815 va_next = eva; 1816 1817 va = va_next; 1818 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++, 1819 sva += PAGE_SIZE) { 1820 if (!pte_test(pte, PTE_V)) { 1821 if (va != va_next) { 1822 pmap_invalidate_range(pmap, va, sva); 1823 va = va_next; 1824 } 1825 continue; 1826 } 1827 if (va == va_next) 1828 va = sva; 1829 if (pmap_remove_pte(pmap, pte, sva, *pde)) { 1830 sva += PAGE_SIZE; 1831 break; 1832 } 1833 } 1834 if (va != va_next) 1835 pmap_invalidate_range(pmap, va, sva); 1836 } 1837out: 1838 rw_wunlock(&pvh_global_lock); 1839 PMAP_UNLOCK(pmap); 1840} 1841 1842/* 1843 * Routine: pmap_remove_all 1844 * Function: 1845 * Removes this physical page from 1846 * all physical maps in which it resides. 1847 * Reflects back modify bits to the pager. 1848 * 1849 * Notes: 1850 * Original versions of this routine were very 1851 * inefficient because they iteratively called 1852 * pmap_remove (slow...) 1853 */ 1854 1855void 1856pmap_remove_all(vm_page_t m) 1857{ 1858 pv_entry_t pv; 1859 pmap_t pmap; 1860 pd_entry_t *pde; 1861 pt_entry_t *pte, tpte; 1862 1863 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1864 ("pmap_remove_all: page %p is not managed", m)); 1865 rw_wlock(&pvh_global_lock); 1866 1867 if (m->md.pv_flags & PV_TABLE_REF) 1868 vm_page_aflag_set(m, PGA_REFERENCED); 1869 1870 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) { 1871 pmap = PV_PMAP(pv); 1872 PMAP_LOCK(pmap); 1873 1874 /* 1875 * If it's last mapping writeback all caches from 1876 * the page being destroyed 1877 */ 1878 if (TAILQ_NEXT(pv, pv_list) == NULL) 1879 mips_dcache_wbinv_range_index(pv->pv_va, PAGE_SIZE); 1880 1881 pmap->pm_stats.resident_count--; 1882 1883 pde = pmap_pde(pmap, pv->pv_va); 1884 KASSERT(pde != NULL && *pde != 0, ("pmap_remove_all: pde")); 1885 pte = pmap_pde_to_pte(pde, pv->pv_va); 1886 1887 tpte = *pte; 1888 if (is_kernel_pmap(pmap)) 1889 *pte = PTE_G; 1890 else 1891 *pte = 0; 1892 1893 if (pte_test(&tpte, PTE_W)) 1894 pmap->pm_stats.wired_count--; 1895 1896 /* 1897 * Update the vm_page_t clean and reference bits. 1898 */ 1899 if (pte_test(&tpte, PTE_D)) { 1900 KASSERT(!pte_test(&tpte, PTE_RO), 1901 ("%s: modified page not writable: va: %p, pte: %#jx", 1902 __func__, (void *)pv->pv_va, (uintmax_t)tpte)); 1903 vm_page_dirty(m); 1904 } 1905 pmap_invalidate_page(pmap, pv->pv_va); 1906 1907 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list); 1908 pmap_unuse_pt(pmap, pv->pv_va, *pde); 1909 free_pv_entry(pmap, pv); 1910 PMAP_UNLOCK(pmap); 1911 } 1912 1913 vm_page_aflag_clear(m, PGA_WRITEABLE); 1914 m->md.pv_flags &= ~PV_TABLE_REF; 1915 rw_wunlock(&pvh_global_lock); 1916} 1917 1918/* 1919 * Set the physical protection on the 1920 * specified range of this map as requested. 1921 */ 1922void 1923pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot) 1924{ 1925 pt_entry_t *pte; 1926 pd_entry_t *pde, *pdpe; 1927 vm_offset_t va_next; 1928 1929 if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 1930 pmap_remove(pmap, sva, eva); 1931 return; 1932 } 1933 if (prot & VM_PROT_WRITE) 1934 return; 1935 1936 rw_wlock(&pvh_global_lock); 1937 PMAP_LOCK(pmap); 1938 for (; sva < eva; sva = va_next) { 1939 pt_entry_t pbits; 1940 vm_page_t m; 1941 vm_paddr_t pa; 1942 1943 pdpe = pmap_segmap(pmap, sva); 1944#ifdef __mips_n64 1945 if (*pdpe == 0) { 1946 va_next = (sva + NBSEG) & ~SEGMASK; 1947 if (va_next < sva) 1948 va_next = eva; 1949 continue; 1950 } 1951#endif 1952 va_next = (sva + NBPDR) & ~PDRMASK; 1953 if (va_next < sva) 1954 va_next = eva; 1955 1956 pde = pmap_pdpe_to_pde(pdpe, sva); 1957 if (*pde == NULL) 1958 continue; 1959 if (va_next > eva) 1960 va_next = eva; 1961 1962 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++, 1963 sva += PAGE_SIZE) { 1964 1965 /* Skip invalid PTEs */ 1966 if (!pte_test(pte, PTE_V)) 1967 continue; 1968 pbits = *pte; 1969 if (pte_test(&pbits, PTE_MANAGED | PTE_D)) { 1970 pa = TLBLO_PTE_TO_PA(pbits); 1971 m = PHYS_TO_VM_PAGE(pa); 1972 vm_page_dirty(m); 1973 } 1974 pte_clear(&pbits, PTE_D); 1975 pte_set(&pbits, PTE_RO); 1976 1977 if (pbits != *pte) { 1978 *pte = pbits; 1979 pmap_update_page(pmap, sva, pbits); 1980 } 1981 } 1982 } 1983 rw_wunlock(&pvh_global_lock); 1984 PMAP_UNLOCK(pmap); 1985} 1986 1987/* 1988 * Insert the given physical page (p) at 1989 * the specified virtual address (v) in the 1990 * target physical map with the protection requested. 1991 * 1992 * If specified, the page will be wired down, meaning 1993 * that the related pte can not be reclaimed. 1994 * 1995 * NB: This is the only routine which MAY NOT lazy-evaluate 1996 * or lose information. That is, this routine must actually 1997 * insert this page into the given map NOW. 1998 */ 1999void 2000pmap_enter(pmap_t pmap, vm_offset_t va, vm_prot_t access, vm_page_t m, 2001 vm_prot_t prot, boolean_t wired) 2002{ 2003 vm_paddr_t pa, opa; 2004 pt_entry_t *pte; 2005 pt_entry_t origpte, newpte; 2006 pv_entry_t pv; 2007 vm_page_t mpte, om; 2008 2009 va &= ~PAGE_MASK; 2010 KASSERT(va <= VM_MAX_KERNEL_ADDRESS, ("pmap_enter: toobig")); 2011 KASSERT((m->oflags & VPO_UNMANAGED) != 0 || va < kmi.clean_sva || 2012 va >= kmi.clean_eva, 2013 ("pmap_enter: managed mapping within the clean submap")); 2014 KASSERT((m->oflags & (VPO_UNMANAGED | VPO_BUSY)) != 0, 2015 ("pmap_enter: page %p is not busy", m)); 2016 pa = VM_PAGE_TO_PHYS(m); 2017 newpte = TLBLO_PA_TO_PFN(pa) | init_pte_prot(m, access, prot); 2018 if (wired) 2019 newpte |= PTE_W; 2020 if (is_kernel_pmap(pmap)) 2021 newpte |= PTE_G; 2022 if (is_cacheable_mem(pa)) 2023 newpte |= PTE_C_CACHE; 2024 else 2025 newpte |= PTE_C_UNCACHED; 2026 2027 mpte = NULL; 2028 2029 rw_wlock(&pvh_global_lock); 2030 PMAP_LOCK(pmap); 2031 2032 /* 2033 * In the case that a page table page is not resident, we are 2034 * creating it here. 2035 */ 2036 if (va < VM_MAXUSER_ADDRESS) { 2037 mpte = pmap_allocpte(pmap, va, M_WAITOK); 2038 } 2039 pte = pmap_pte(pmap, va); 2040 2041 /* 2042 * Page Directory table entry not valid, we need a new PT page 2043 */ 2044 if (pte == NULL) { 2045 panic("pmap_enter: invalid page directory, pdir=%p, va=%p", 2046 (void *)pmap->pm_segtab, (void *)va); 2047 } 2048 om = NULL; 2049 origpte = *pte; 2050 opa = TLBLO_PTE_TO_PA(origpte); 2051 2052 /* 2053 * Mapping has not changed, must be protection or wiring change. 2054 */ 2055 if (pte_test(&origpte, PTE_V) && opa == pa) { 2056 /* 2057 * Wiring change, just update stats. We don't worry about 2058 * wiring PT pages as they remain resident as long as there 2059 * are valid mappings in them. Hence, if a user page is 2060 * wired, the PT page will be also. 2061 */ 2062 if (wired && !pte_test(&origpte, PTE_W)) 2063 pmap->pm_stats.wired_count++; 2064 else if (!wired && pte_test(&origpte, PTE_W)) 2065 pmap->pm_stats.wired_count--; 2066 2067 KASSERT(!pte_test(&origpte, PTE_D | PTE_RO), 2068 ("%s: modified page not writable: va: %p, pte: %#jx", 2069 __func__, (void *)va, (uintmax_t)origpte)); 2070 2071 /* 2072 * Remove extra pte reference 2073 */ 2074 if (mpte) 2075 mpte->wire_count--; 2076 2077 if (pte_test(&origpte, PTE_MANAGED)) { 2078 m->md.pv_flags |= PV_TABLE_REF; 2079 om = m; 2080 newpte |= PTE_MANAGED; 2081 if (!pte_test(&newpte, PTE_RO)) 2082 vm_page_aflag_set(m, PGA_WRITEABLE); 2083 } 2084 goto validate; 2085 } 2086 2087 pv = NULL; 2088 2089 /* 2090 * Mapping has changed, invalidate old range and fall through to 2091 * handle validating new mapping. 2092 */ 2093 if (opa) { 2094 if (pte_test(&origpte, PTE_W)) 2095 pmap->pm_stats.wired_count--; 2096 2097 if (pte_test(&origpte, PTE_MANAGED)) { 2098 om = PHYS_TO_VM_PAGE(opa); 2099 pv = pmap_pvh_remove(&om->md, pmap, va); 2100 } 2101 if (mpte != NULL) { 2102 mpte->wire_count--; 2103 KASSERT(mpte->wire_count > 0, 2104 ("pmap_enter: missing reference to page table page," 2105 " va: %p", (void *)va)); 2106 } 2107 } else 2108 pmap->pm_stats.resident_count++; 2109 2110 /* 2111 * Enter on the PV list if part of our managed memory. 2112 */ 2113 if ((m->oflags & VPO_UNMANAGED) == 0) { 2114 m->md.pv_flags |= PV_TABLE_REF; 2115 if (pv == NULL) 2116 pv = get_pv_entry(pmap, FALSE); 2117 pv->pv_va = va; 2118 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_list); 2119 newpte |= PTE_MANAGED; 2120 if (!pte_test(&newpte, PTE_RO)) 2121 vm_page_aflag_set(m, PGA_WRITEABLE); 2122 } else if (pv != NULL) 2123 free_pv_entry(pmap, pv); 2124 2125 /* 2126 * Increment counters 2127 */ 2128 if (wired) 2129 pmap->pm_stats.wired_count++; 2130 2131validate: 2132 2133#ifdef PMAP_DEBUG 2134 printf("pmap_enter: va: %p -> pa: %p\n", (void *)va, (void *)pa); 2135#endif 2136 2137 /* 2138 * if the mapping or permission bits are different, we need to 2139 * update the pte. 2140 */ 2141 if (origpte != newpte) { 2142 *pte = newpte; 2143 if (pte_test(&origpte, PTE_V)) { 2144 if (pte_test(&origpte, PTE_MANAGED) && opa != pa) { 2145 if (om->md.pv_flags & PV_TABLE_REF) 2146 vm_page_aflag_set(om, PGA_REFERENCED); 2147 om->md.pv_flags &= ~PV_TABLE_REF; 2148 } 2149 if (pte_test(&origpte, PTE_D)) { 2150 KASSERT(!pte_test(&origpte, PTE_RO), 2151 ("pmap_enter: modified page not writable:" 2152 " va: %p, pte: %#jx", (void *)va, (uintmax_t)origpte)); 2153 if (pte_test(&origpte, PTE_MANAGED)) 2154 vm_page_dirty(om); 2155 } 2156 if (pte_test(&origpte, PTE_MANAGED) && 2157 TAILQ_EMPTY(&om->md.pv_list)) 2158 vm_page_aflag_clear(om, PGA_WRITEABLE); 2159 pmap_update_page(pmap, va, newpte); 2160 } 2161 } 2162 2163 /* 2164 * Sync I & D caches for executable pages. Do this only if the 2165 * target pmap belongs to the current process. Otherwise, an 2166 * unresolvable TLB miss may occur. 2167 */ 2168 if (!is_kernel_pmap(pmap) && (pmap == &curproc->p_vmspace->vm_pmap) && 2169 (prot & VM_PROT_EXECUTE)) { 2170 mips_icache_sync_range(va, PAGE_SIZE); 2171 mips_dcache_wbinv_range(va, PAGE_SIZE); 2172 } 2173 rw_wunlock(&pvh_global_lock); 2174 PMAP_UNLOCK(pmap); 2175} 2176 2177/* 2178 * this code makes some *MAJOR* assumptions: 2179 * 1. Current pmap & pmap exists. 2180 * 2. Not wired. 2181 * 3. Read access. 2182 * 4. No page table pages. 2183 * but is *MUCH* faster than pmap_enter... 2184 */ 2185 2186void 2187pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot) 2188{ 2189 2190 rw_wlock(&pvh_global_lock); 2191 PMAP_LOCK(pmap); 2192 (void)pmap_enter_quick_locked(pmap, va, m, prot, NULL); 2193 rw_wunlock(&pvh_global_lock); 2194 PMAP_UNLOCK(pmap); 2195} 2196 2197static vm_page_t 2198pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m, 2199 vm_prot_t prot, vm_page_t mpte) 2200{ 2201 pt_entry_t *pte; 2202 vm_paddr_t pa; 2203 2204 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva || 2205 (m->oflags & VPO_UNMANAGED) != 0, 2206 ("pmap_enter_quick_locked: managed mapping within the clean submap")); 2207 rw_assert(&pvh_global_lock, RA_WLOCKED); 2208 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2209 2210 /* 2211 * In the case that a page table page is not resident, we are 2212 * creating it here. 2213 */ 2214 if (va < VM_MAXUSER_ADDRESS) { 2215 pd_entry_t *pde; 2216 unsigned ptepindex; 2217 2218 /* 2219 * Calculate pagetable page index 2220 */ 2221 ptepindex = pmap_pde_pindex(va); 2222 if (mpte && (mpte->pindex == ptepindex)) { 2223 mpte->wire_count++; 2224 } else { 2225 /* 2226 * Get the page directory entry 2227 */ 2228 pde = pmap_pde(pmap, va); 2229 2230 /* 2231 * If the page table page is mapped, we just 2232 * increment the hold count, and activate it. 2233 */ 2234 if (pde && *pde != 0) { 2235 mpte = PHYS_TO_VM_PAGE( 2236 MIPS_DIRECT_TO_PHYS(*pde)); 2237 mpte->wire_count++; 2238 } else { 2239 mpte = _pmap_allocpte(pmap, ptepindex, 2240 M_NOWAIT); 2241 if (mpte == NULL) 2242 return (mpte); 2243 } 2244 } 2245 } else { 2246 mpte = NULL; 2247 } 2248 2249 pte = pmap_pte(pmap, va); 2250 if (pte_test(pte, PTE_V)) { 2251 if (mpte != NULL) { 2252 mpte->wire_count--; 2253 mpte = NULL; 2254 } 2255 return (mpte); 2256 } 2257 2258 /* 2259 * Enter on the PV list if part of our managed memory. 2260 */ 2261 if ((m->oflags & VPO_UNMANAGED) == 0 && 2262 !pmap_try_insert_pv_entry(pmap, mpte, va, m)) { 2263 if (mpte != NULL) { 2264 pmap_unwire_ptp(pmap, va, mpte); 2265 mpte = NULL; 2266 } 2267 return (mpte); 2268 } 2269 2270 /* 2271 * Increment counters 2272 */ 2273 pmap->pm_stats.resident_count++; 2274 2275 pa = VM_PAGE_TO_PHYS(m); 2276 2277 /* 2278 * Now validate mapping with RO protection 2279 */ 2280 *pte = PTE_RO | TLBLO_PA_TO_PFN(pa) | PTE_V; 2281 if ((m->oflags & VPO_UNMANAGED) == 0) 2282 *pte |= PTE_MANAGED; 2283 2284 if (is_cacheable_mem(pa)) 2285 *pte |= PTE_C_CACHE; 2286 else 2287 *pte |= PTE_C_UNCACHED; 2288 2289 if (is_kernel_pmap(pmap)) 2290 *pte |= PTE_G; 2291 else { 2292 /* 2293 * Sync I & D caches. Do this only if the target pmap 2294 * belongs to the current process. Otherwise, an 2295 * unresolvable TLB miss may occur. */ 2296 if (pmap == &curproc->p_vmspace->vm_pmap) { 2297 va &= ~PAGE_MASK; 2298 mips_icache_sync_range(va, PAGE_SIZE); 2299 mips_dcache_wbinv_range(va, PAGE_SIZE); 2300 } 2301 } 2302 return (mpte); 2303} 2304 2305/* 2306 * Make a temporary mapping for a physical address. This is only intended 2307 * to be used for panic dumps. 2308 * 2309 * Use XKPHYS for 64 bit, and KSEG0 where possible for 32 bit. 2310 */ 2311void * 2312pmap_kenter_temporary(vm_paddr_t pa, int i) 2313{ 2314 vm_offset_t va; 2315 2316 if (i != 0) 2317 printf("%s: ERROR!!! More than one page of virtual address mapping not supported\n", 2318 __func__); 2319 2320 if (MIPS_DIRECT_MAPPABLE(pa)) { 2321 va = MIPS_PHYS_TO_DIRECT(pa); 2322 } else { 2323#ifndef __mips_n64 /* XXX : to be converted to new style */ 2324 int cpu; 2325 register_t intr; 2326 struct local_sysmaps *sysm; 2327 pt_entry_t *pte, npte; 2328 2329 /* If this is used other than for dumps, we may need to leave 2330 * interrupts disasbled on return. If crash dumps don't work when 2331 * we get to this point, we might want to consider this (leaving things 2332 * disabled as a starting point ;-) 2333 */ 2334 intr = intr_disable(); 2335 cpu = PCPU_GET(cpuid); 2336 sysm = &sysmap_lmem[cpu]; 2337 /* Since this is for the debugger, no locks or any other fun */ 2338 npte = TLBLO_PA_TO_PFN(pa) | PTE_D | PTE_V | PTE_G | PTE_W | PTE_C_CACHE; 2339 pte = pmap_pte(kernel_pmap, sysm->base); 2340 *pte = npte; 2341 sysm->valid1 = 1; 2342 pmap_update_page(kernel_pmap, sysm->base, npte); 2343 va = sysm->base; 2344 intr_restore(intr); 2345#endif 2346 } 2347 return ((void *)va); 2348} 2349 2350void 2351pmap_kenter_temporary_free(vm_paddr_t pa) 2352{ 2353#ifndef __mips_n64 /* XXX : to be converted to new style */ 2354 int cpu; 2355 register_t intr; 2356 struct local_sysmaps *sysm; 2357#endif 2358 2359 if (MIPS_DIRECT_MAPPABLE(pa)) { 2360 /* nothing to do for this case */ 2361 return; 2362 } 2363#ifndef __mips_n64 /* XXX : to be converted to new style */ 2364 cpu = PCPU_GET(cpuid); 2365 sysm = &sysmap_lmem[cpu]; 2366 if (sysm->valid1) { 2367 pt_entry_t *pte; 2368 2369 intr = intr_disable(); 2370 pte = pmap_pte(kernel_pmap, sysm->base); 2371 *pte = PTE_G; 2372 pmap_invalidate_page(kernel_pmap, sysm->base); 2373 intr_restore(intr); 2374 sysm->valid1 = 0; 2375 } 2376#endif 2377} 2378 2379/* 2380 * Maps a sequence of resident pages belonging to the same object. 2381 * The sequence begins with the given page m_start. This page is 2382 * mapped at the given virtual address start. Each subsequent page is 2383 * mapped at a virtual address that is offset from start by the same 2384 * amount as the page is offset from m_start within the object. The 2385 * last page in the sequence is the page with the largest offset from 2386 * m_start that can be mapped at a virtual address less than the given 2387 * virtual address end. Not every virtual page between start and end 2388 * is mapped; only those for which a resident page exists with the 2389 * corresponding offset from m_start are mapped. 2390 */ 2391void 2392pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end, 2393 vm_page_t m_start, vm_prot_t prot) 2394{ 2395 vm_page_t m, mpte; 2396 vm_pindex_t diff, psize; 2397 2398 VM_OBJECT_LOCK_ASSERT(m_start->object, MA_OWNED); 2399 psize = atop(end - start); 2400 mpte = NULL; 2401 m = m_start; 2402 rw_wlock(&pvh_global_lock); 2403 PMAP_LOCK(pmap); 2404 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 2405 mpte = pmap_enter_quick_locked(pmap, start + ptoa(diff), m, 2406 prot, mpte); 2407 m = TAILQ_NEXT(m, listq); 2408 } 2409 rw_wunlock(&pvh_global_lock); 2410 PMAP_UNLOCK(pmap); 2411} 2412 2413/* 2414 * pmap_object_init_pt preloads the ptes for a given object 2415 * into the specified pmap. This eliminates the blast of soft 2416 * faults on process startup and immediately after an mmap. 2417 */ 2418void 2419pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, 2420 vm_object_t object, vm_pindex_t pindex, vm_size_t size) 2421{ 2422 VM_OBJECT_LOCK_ASSERT(object, MA_OWNED); 2423 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG, 2424 ("pmap_object_init_pt: non-device object")); 2425} 2426 2427/* 2428 * Routine: pmap_change_wiring 2429 * Function: Change the wiring attribute for a map/virtual-address 2430 * pair. 2431 * In/out conditions: 2432 * The mapping must already exist in the pmap. 2433 */ 2434void 2435pmap_change_wiring(pmap_t pmap, vm_offset_t va, boolean_t wired) 2436{ 2437 pt_entry_t *pte; 2438 2439 PMAP_LOCK(pmap); 2440 pte = pmap_pte(pmap, va); 2441 2442 if (wired && !pte_test(pte, PTE_W)) 2443 pmap->pm_stats.wired_count++; 2444 else if (!wired && pte_test(pte, PTE_W)) 2445 pmap->pm_stats.wired_count--; 2446 2447 /* 2448 * Wiring is not a hardware characteristic so there is no need to 2449 * invalidate TLB. 2450 */ 2451 if (wired) 2452 pte_set(pte, PTE_W); 2453 else 2454 pte_clear(pte, PTE_W); 2455 PMAP_UNLOCK(pmap); 2456} 2457 2458/* 2459 * Copy the range specified by src_addr/len 2460 * from the source map to the range dst_addr/len 2461 * in the destination map. 2462 * 2463 * This routine is only advisory and need not do anything. 2464 */ 2465 2466void 2467pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, 2468 vm_size_t len, vm_offset_t src_addr) 2469{ 2470} 2471 2472/* 2473 * pmap_zero_page zeros the specified hardware page by mapping 2474 * the page into KVM and using bzero to clear its contents. 2475 * 2476 * Use XKPHYS for 64 bit, and KSEG0 where possible for 32 bit. 2477 */ 2478void 2479pmap_zero_page(vm_page_t m) 2480{ 2481 vm_offset_t va; 2482 vm_paddr_t phys = VM_PAGE_TO_PHYS(m); 2483 2484 if (MIPS_DIRECT_MAPPABLE(phys)) { 2485 va = MIPS_PHYS_TO_DIRECT(phys); 2486 bzero((caddr_t)va, PAGE_SIZE); 2487 mips_dcache_wbinv_range(va, PAGE_SIZE); 2488 } else { 2489 va = pmap_lmem_map1(phys); 2490 bzero((caddr_t)va, PAGE_SIZE); 2491 mips_dcache_wbinv_range(va, PAGE_SIZE); 2492 pmap_lmem_unmap(); 2493 } 2494} 2495 2496/* 2497 * pmap_zero_page_area zeros the specified hardware page by mapping 2498 * the page into KVM and using bzero to clear its contents. 2499 * 2500 * off and size may not cover an area beyond a single hardware page. 2501 */ 2502void 2503pmap_zero_page_area(vm_page_t m, int off, int size) 2504{ 2505 vm_offset_t va; 2506 vm_paddr_t phys = VM_PAGE_TO_PHYS(m); 2507 2508 if (MIPS_DIRECT_MAPPABLE(phys)) { 2509 va = MIPS_PHYS_TO_DIRECT(phys); 2510 bzero((char *)(caddr_t)va + off, size); 2511 mips_dcache_wbinv_range(va + off, size); 2512 } else { 2513 va = pmap_lmem_map1(phys); 2514 bzero((char *)va + off, size); 2515 mips_dcache_wbinv_range(va + off, size); 2516 pmap_lmem_unmap(); 2517 } 2518} 2519 2520void 2521pmap_zero_page_idle(vm_page_t m) 2522{ 2523 vm_offset_t va; 2524 vm_paddr_t phys = VM_PAGE_TO_PHYS(m); 2525 2526 if (MIPS_DIRECT_MAPPABLE(phys)) { 2527 va = MIPS_PHYS_TO_DIRECT(phys); 2528 bzero((caddr_t)va, PAGE_SIZE); 2529 mips_dcache_wbinv_range(va, PAGE_SIZE); 2530 } else { 2531 va = pmap_lmem_map1(phys); 2532 bzero((caddr_t)va, PAGE_SIZE); 2533 mips_dcache_wbinv_range(va, PAGE_SIZE); 2534 pmap_lmem_unmap(); 2535 } 2536} 2537 2538/* 2539 * pmap_copy_page copies the specified (machine independent) 2540 * page by mapping the page into virtual memory and using 2541 * bcopy to copy the page, one machine dependent page at a 2542 * time. 2543 * 2544 * Use XKPHYS for 64 bit, and KSEG0 where possible for 32 bit. 2545 */ 2546void 2547pmap_copy_page(vm_page_t src, vm_page_t dst) 2548{ 2549 vm_offset_t va_src, va_dst; 2550 vm_paddr_t phys_src = VM_PAGE_TO_PHYS(src); 2551 vm_paddr_t phys_dst = VM_PAGE_TO_PHYS(dst); 2552 2553 if (MIPS_DIRECT_MAPPABLE(phys_src) && MIPS_DIRECT_MAPPABLE(phys_dst)) { 2554 /* easy case, all can be accessed via KSEG0 */ 2555 /* 2556 * Flush all caches for VA that are mapped to this page 2557 * to make sure that data in SDRAM is up to date 2558 */ 2559 pmap_flush_pvcache(src); 2560 mips_dcache_wbinv_range_index( 2561 MIPS_PHYS_TO_DIRECT(phys_dst), PAGE_SIZE); 2562 va_src = MIPS_PHYS_TO_DIRECT(phys_src); 2563 va_dst = MIPS_PHYS_TO_DIRECT(phys_dst); 2564 bcopy((caddr_t)va_src, (caddr_t)va_dst, PAGE_SIZE); 2565 mips_dcache_wbinv_range(va_dst, PAGE_SIZE); 2566 } else { 2567 va_src = pmap_lmem_map2(phys_src, phys_dst); 2568 va_dst = va_src + PAGE_SIZE; 2569 bcopy((void *)va_src, (void *)va_dst, PAGE_SIZE); 2570 mips_dcache_wbinv_range(va_dst, PAGE_SIZE); 2571 pmap_lmem_unmap(); 2572 } 2573} 2574 2575/* 2576 * Returns true if the pmap's pv is one of the first 2577 * 16 pvs linked to from this page. This count may 2578 * be changed upwards or downwards in the future; it 2579 * is only necessary that true be returned for a small 2580 * subset of pmaps for proper page aging. 2581 */ 2582boolean_t 2583pmap_page_exists_quick(pmap_t pmap, vm_page_t m) 2584{ 2585 pv_entry_t pv; 2586 int loops = 0; 2587 boolean_t rv; 2588 2589 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2590 ("pmap_page_exists_quick: page %p is not managed", m)); 2591 rv = FALSE; 2592 rw_wlock(&pvh_global_lock); 2593 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 2594 if (PV_PMAP(pv) == pmap) { 2595 rv = TRUE; 2596 break; 2597 } 2598 loops++; 2599 if (loops >= 16) 2600 break; 2601 } 2602 rw_wunlock(&pvh_global_lock); 2603 return (rv); 2604} 2605 2606/* 2607 * Remove all pages from specified address space 2608 * this aids process exit speeds. Also, this code 2609 * is special cased for current process only, but 2610 * can have the more generic (and slightly slower) 2611 * mode enabled. This is much faster than pmap_remove 2612 * in the case of running down an entire address space. 2613 */ 2614void 2615pmap_remove_pages(pmap_t pmap) 2616{ 2617 pd_entry_t *pde; 2618 pt_entry_t *pte, tpte; 2619 pv_entry_t pv; 2620 vm_page_t m; 2621 struct pv_chunk *pc, *npc; 2622 u_long inuse, bitmask; 2623 int allfree, bit, field, idx; 2624 2625 if (pmap != vmspace_pmap(curthread->td_proc->p_vmspace)) { 2626 printf("warning: pmap_remove_pages called with non-current pmap\n"); 2627 return; 2628 } 2629 rw_wlock(&pvh_global_lock); 2630 PMAP_LOCK(pmap); 2631 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) { 2632 allfree = 1; 2633 for (field = 0; field < _NPCM; field++) { 2634 inuse = ~pc->pc_map[field] & pc_freemask[field]; 2635 while (inuse != 0) { 2636 bit = ffsl(inuse) - 1; 2637 bitmask = 1UL << bit; 2638 idx = field * sizeof(inuse) * NBBY + bit; 2639 pv = &pc->pc_pventry[idx]; 2640 inuse &= ~bitmask; 2641 2642 pde = pmap_pde(pmap, pv->pv_va); 2643 KASSERT(pde != NULL && *pde != 0, 2644 ("pmap_remove_pages: pde")); 2645 pte = pmap_pde_to_pte(pde, pv->pv_va); 2646 if (!pte_test(pte, PTE_V)) 2647 panic("pmap_remove_pages: bad pte"); 2648 tpte = *pte; 2649 2650/* 2651 * We cannot remove wired pages from a process' mapping at this time 2652 */ 2653 if (pte_test(&tpte, PTE_W)) { 2654 allfree = 0; 2655 continue; 2656 } 2657 *pte = is_kernel_pmap(pmap) ? PTE_G : 0; 2658 2659 m = PHYS_TO_VM_PAGE(TLBLO_PTE_TO_PA(tpte)); 2660 KASSERT(m != NULL, 2661 ("pmap_remove_pages: bad tpte %#jx", 2662 (uintmax_t)tpte)); 2663 2664 /* 2665 * Update the vm_page_t clean and reference bits. 2666 */ 2667 if (pte_test(&tpte, PTE_D)) 2668 vm_page_dirty(m); 2669 2670 /* Mark free */ 2671 PV_STAT(pv_entry_frees++); 2672 PV_STAT(pv_entry_spare++); 2673 pv_entry_count--; 2674 pc->pc_map[field] |= bitmask; 2675 pmap->pm_stats.resident_count--; 2676 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list); 2677 if (TAILQ_EMPTY(&m->md.pv_list)) 2678 vm_page_aflag_clear(m, PGA_WRITEABLE); 2679 pmap_unuse_pt(pmap, pv->pv_va, *pde); 2680 } 2681 } 2682 if (allfree) { 2683 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 2684 free_pv_chunk(pc); 2685 } 2686 } 2687 pmap_invalidate_all(pmap); 2688 PMAP_UNLOCK(pmap); 2689 rw_wunlock(&pvh_global_lock); 2690} 2691 2692/* 2693 * pmap_testbit tests bits in pte's 2694 */ 2695static boolean_t 2696pmap_testbit(vm_page_t m, int bit) 2697{ 2698 pv_entry_t pv; 2699 pmap_t pmap; 2700 pt_entry_t *pte; 2701 boolean_t rv = FALSE; 2702 2703 if (m->oflags & VPO_UNMANAGED) 2704 return (rv); 2705 2706 rw_assert(&pvh_global_lock, RA_WLOCKED); 2707 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 2708 pmap = PV_PMAP(pv); 2709 PMAP_LOCK(pmap); 2710 pte = pmap_pte(pmap, pv->pv_va); 2711 rv = pte_test(pte, bit); 2712 PMAP_UNLOCK(pmap); 2713 if (rv) 2714 break; 2715 } 2716 return (rv); 2717} 2718 2719/* 2720 * pmap_page_wired_mappings: 2721 * 2722 * Return the number of managed mappings to the given physical page 2723 * that are wired. 2724 */ 2725int 2726pmap_page_wired_mappings(vm_page_t m) 2727{ 2728 pv_entry_t pv; 2729 pmap_t pmap; 2730 pt_entry_t *pte; 2731 int count; 2732 2733 count = 0; 2734 if ((m->oflags & VPO_UNMANAGED) != 0) 2735 return (count); 2736 rw_wlock(&pvh_global_lock); 2737 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 2738 pmap = PV_PMAP(pv); 2739 PMAP_LOCK(pmap); 2740 pte = pmap_pte(pmap, pv->pv_va); 2741 if (pte_test(pte, PTE_W)) 2742 count++; 2743 PMAP_UNLOCK(pmap); 2744 } 2745 rw_wunlock(&pvh_global_lock); 2746 return (count); 2747} 2748 2749/* 2750 * Clear the write and modified bits in each of the given page's mappings. 2751 */ 2752void 2753pmap_remove_write(vm_page_t m) 2754{ 2755 pmap_t pmap; 2756 pt_entry_t pbits, *pte; 2757 pv_entry_t pv; 2758 2759 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2760 ("pmap_remove_write: page %p is not managed", m)); 2761 2762 /* 2763 * If the page is not VPO_BUSY, then PGA_WRITEABLE cannot be set by 2764 * another thread while the object is locked. Thus, if PGA_WRITEABLE 2765 * is clear, no page table entries need updating. 2766 */ 2767 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED); 2768 if ((m->oflags & VPO_BUSY) == 0 && 2769 (m->aflags & PGA_WRITEABLE) == 0) 2770 return; 2771 rw_wlock(&pvh_global_lock); 2772 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 2773 pmap = PV_PMAP(pv); 2774 PMAP_LOCK(pmap); 2775 pte = pmap_pte(pmap, pv->pv_va); 2776 KASSERT(pte != NULL && pte_test(pte, PTE_V), 2777 ("page on pv_list has no pte")); 2778 pbits = *pte; 2779 if (pte_test(&pbits, PTE_D)) { 2780 pte_clear(&pbits, PTE_D); 2781 vm_page_dirty(m); 2782 } 2783 pte_set(&pbits, PTE_RO); 2784 if (pbits != *pte) { 2785 *pte = pbits; 2786 pmap_update_page(pmap, pv->pv_va, pbits); 2787 } 2788 PMAP_UNLOCK(pmap); 2789 } 2790 vm_page_aflag_clear(m, PGA_WRITEABLE); 2791 rw_wunlock(&pvh_global_lock); 2792} 2793 2794/* 2795 * pmap_ts_referenced: 2796 * 2797 * Return the count of reference bits for a page, clearing all of them. 2798 */ 2799int 2800pmap_ts_referenced(vm_page_t m) 2801{ 2802 2803 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2804 ("pmap_ts_referenced: page %p is not managed", m)); 2805 if (m->md.pv_flags & PV_TABLE_REF) { 2806 rw_wlock(&pvh_global_lock); 2807 m->md.pv_flags &= ~PV_TABLE_REF; 2808 rw_wunlock(&pvh_global_lock); 2809 return (1); 2810 } 2811 return (0); 2812} 2813 2814/* 2815 * pmap_is_modified: 2816 * 2817 * Return whether or not the specified physical page was modified 2818 * in any physical maps. 2819 */ 2820boolean_t 2821pmap_is_modified(vm_page_t m) 2822{ 2823 boolean_t rv; 2824 2825 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2826 ("pmap_is_modified: page %p is not managed", m)); 2827 2828 /* 2829 * If the page is not VPO_BUSY, then PGA_WRITEABLE cannot be 2830 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE 2831 * is clear, no PTEs can have PTE_D set. 2832 */ 2833 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED); 2834 if ((m->oflags & VPO_BUSY) == 0 && 2835 (m->aflags & PGA_WRITEABLE) == 0) 2836 return (FALSE); 2837 rw_wlock(&pvh_global_lock); 2838 rv = pmap_testbit(m, PTE_D); 2839 rw_wunlock(&pvh_global_lock); 2840 return (rv); 2841} 2842 2843/* N/C */ 2844 2845/* 2846 * pmap_is_prefaultable: 2847 * 2848 * Return whether or not the specified virtual address is elgible 2849 * for prefault. 2850 */ 2851boolean_t 2852pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr) 2853{ 2854 pd_entry_t *pde; 2855 pt_entry_t *pte; 2856 boolean_t rv; 2857 2858 rv = FALSE; 2859 PMAP_LOCK(pmap); 2860 pde = pmap_pde(pmap, addr); 2861 if (pde != NULL && *pde != 0) { 2862 pte = pmap_pde_to_pte(pde, addr); 2863 rv = (*pte == 0); 2864 } 2865 PMAP_UNLOCK(pmap); 2866 return (rv); 2867} 2868 2869/* 2870 * Clear the modify bits on the specified physical page. 2871 */ 2872void 2873pmap_clear_modify(vm_page_t m) 2874{ 2875 pmap_t pmap; 2876 pt_entry_t *pte; 2877 pv_entry_t pv; 2878 2879 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2880 ("pmap_clear_modify: page %p is not managed", m)); 2881 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED); 2882 KASSERT((m->oflags & VPO_BUSY) == 0, 2883 ("pmap_clear_modify: page %p is busy", m)); 2884 2885 /* 2886 * If the page is not PGA_WRITEABLE, then no PTEs can have PTE_D set. 2887 * If the object containing the page is locked and the page is not 2888 * VPO_BUSY, then PGA_WRITEABLE cannot be concurrently set. 2889 */ 2890 if ((m->aflags & PGA_WRITEABLE) == 0) 2891 return; 2892 rw_wlock(&pvh_global_lock); 2893 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 2894 pmap = PV_PMAP(pv); 2895 PMAP_LOCK(pmap); 2896 pte = pmap_pte(pmap, pv->pv_va); 2897 if (pte_test(pte, PTE_D)) { 2898 pte_clear(pte, PTE_D); 2899 pmap_update_page(pmap, pv->pv_va, *pte); 2900 } 2901 PMAP_UNLOCK(pmap); 2902 } 2903 rw_wunlock(&pvh_global_lock); 2904} 2905 2906/* 2907 * pmap_is_referenced: 2908 * 2909 * Return whether or not the specified physical page was referenced 2910 * in any physical maps. 2911 */ 2912boolean_t 2913pmap_is_referenced(vm_page_t m) 2914{ 2915 2916 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2917 ("pmap_is_referenced: page %p is not managed", m)); 2918 return ((m->md.pv_flags & PV_TABLE_REF) != 0); 2919} 2920 2921/* 2922 * pmap_clear_reference: 2923 * 2924 * Clear the reference bit on the specified physical page. 2925 */ 2926void 2927pmap_clear_reference(vm_page_t m) 2928{ 2929 2930 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2931 ("pmap_clear_reference: page %p is not managed", m)); 2932 rw_wlock(&pvh_global_lock); 2933 if (m->md.pv_flags & PV_TABLE_REF) { 2934 m->md.pv_flags &= ~PV_TABLE_REF; 2935 } 2936 rw_wunlock(&pvh_global_lock); 2937} 2938 2939/* 2940 * Miscellaneous support routines follow 2941 */ 2942 2943/* 2944 * Map a set of physical memory pages into the kernel virtual 2945 * address space. Return a pointer to where it is mapped. This 2946 * routine is intended to be used for mapping device memory, 2947 * NOT real memory. 2948 */ 2949 2950/* 2951 * Map a set of physical memory pages into the kernel virtual 2952 * address space. Return a pointer to where it is mapped. This 2953 * routine is intended to be used for mapping device memory, 2954 * NOT real memory. 2955 * 2956 * Use XKPHYS uncached for 64 bit, and KSEG1 where possible for 32 bit. 2957 */ 2958void * 2959pmap_mapdev(vm_paddr_t pa, vm_size_t size) 2960{ 2961 vm_offset_t va, tmpva, offset; 2962 2963 /* 2964 * KSEG1 maps only first 512M of phys address space. For 2965 * pa > 0x20000000 we should make proper mapping * using pmap_kenter. 2966 */ 2967 if (MIPS_DIRECT_MAPPABLE(pa + size - 1)) 2968 return ((void *)MIPS_PHYS_TO_DIRECT_UNCACHED(pa)); 2969 else { 2970 offset = pa & PAGE_MASK; 2971 size = roundup(size + offset, PAGE_SIZE); 2972 2973 va = kmem_alloc_nofault(kernel_map, size); 2974 if (!va) 2975 panic("pmap_mapdev: Couldn't alloc kernel virtual memory"); 2976 pa = trunc_page(pa); 2977 for (tmpva = va; size > 0;) { 2978 pmap_kenter_attr(tmpva, pa, PTE_C_UNCACHED); 2979 size -= PAGE_SIZE; 2980 tmpva += PAGE_SIZE; 2981 pa += PAGE_SIZE; 2982 } 2983 } 2984 2985 return ((void *)(va + offset)); 2986} 2987 2988void 2989pmap_unmapdev(vm_offset_t va, vm_size_t size) 2990{ 2991#ifndef __mips_n64 2992 vm_offset_t base, offset; 2993 2994 /* If the address is within KSEG1 then there is nothing to do */ 2995 if (va >= MIPS_KSEG1_START && va <= MIPS_KSEG1_END) 2996 return; 2997 2998 base = trunc_page(va); 2999 offset = va & PAGE_MASK; 3000 size = roundup(size + offset, PAGE_SIZE); 3001 kmem_free(kernel_map, base, size); 3002#endif 3003} 3004 3005/* 3006 * perform the pmap work for mincore 3007 */ 3008int 3009pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *locked_pa) 3010{ 3011 pt_entry_t *ptep, pte; 3012 vm_paddr_t pa; 3013 vm_page_t m; 3014 int val; 3015 3016 PMAP_LOCK(pmap); 3017retry: 3018 ptep = pmap_pte(pmap, addr); 3019 pte = (ptep != NULL) ? *ptep : 0; 3020 if (!pte_test(&pte, PTE_V)) { 3021 val = 0; 3022 goto out; 3023 } 3024 val = MINCORE_INCORE; 3025 if (pte_test(&pte, PTE_D)) 3026 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER; 3027 pa = TLBLO_PTE_TO_PA(pte); 3028 if (pte_test(&pte, PTE_MANAGED)) { 3029 /* 3030 * This may falsely report the given address as 3031 * MINCORE_REFERENCED. Unfortunately, due to the lack of 3032 * per-PTE reference information, it is impossible to 3033 * determine if the address is MINCORE_REFERENCED. 3034 */ 3035 m = PHYS_TO_VM_PAGE(pa); 3036 if ((m->aflags & PGA_REFERENCED) != 0) 3037 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER; 3038 } 3039 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) != 3040 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) && 3041 pte_test(&pte, PTE_MANAGED)) { 3042 /* Ensure that "PHYS_TO_VM_PAGE(pa)->object" doesn't change. */ 3043 if (vm_page_pa_tryrelock(pmap, pa, locked_pa)) 3044 goto retry; 3045 } else 3046out: 3047 PA_UNLOCK_COND(*locked_pa); 3048 PMAP_UNLOCK(pmap); 3049 return (val); 3050} 3051 3052void 3053pmap_activate(struct thread *td) 3054{ 3055 pmap_t pmap, oldpmap; 3056 struct proc *p = td->td_proc; 3057 u_int cpuid; 3058 3059 critical_enter(); 3060 3061 pmap = vmspace_pmap(p->p_vmspace); 3062 oldpmap = PCPU_GET(curpmap); 3063 cpuid = PCPU_GET(cpuid); 3064 3065 if (oldpmap) 3066 CPU_CLR_ATOMIC(cpuid, &oldpmap->pm_active); 3067 CPU_SET_ATOMIC(cpuid, &pmap->pm_active); 3068 pmap_asid_alloc(pmap); 3069 if (td == curthread) { 3070 PCPU_SET(segbase, pmap->pm_segtab); 3071 mips_wr_entryhi(pmap->pm_asid[cpuid].asid); 3072 } 3073 3074 PCPU_SET(curpmap, pmap); 3075 critical_exit(); 3076} 3077 3078void 3079pmap_sync_icache(pmap_t pm, vm_offset_t va, vm_size_t sz) 3080{ 3081} 3082 3083/* 3084 * Increase the starting virtual address of the given mapping if a 3085 * different alignment might result in more superpage mappings. 3086 */ 3087void 3088pmap_align_superpage(vm_object_t object, vm_ooffset_t offset, 3089 vm_offset_t *addr, vm_size_t size) 3090{ 3091 vm_offset_t superpage_offset; 3092 3093 if (size < NBSEG) 3094 return; 3095 if (object != NULL && (object->flags & OBJ_COLORED) != 0) 3096 offset += ptoa(object->pg_color); 3097 superpage_offset = offset & SEGMASK; 3098 if (size - ((NBSEG - superpage_offset) & SEGMASK) < NBSEG || 3099 (*addr & SEGMASK) == superpage_offset) 3100 return; 3101 if ((*addr & SEGMASK) < superpage_offset) 3102 *addr = (*addr & ~SEGMASK) + superpage_offset; 3103 else 3104 *addr = ((*addr + SEGMASK) & ~SEGMASK) + superpage_offset; 3105} 3106 3107/* 3108 * Increase the starting virtual address of the given mapping so 3109 * that it is aligned to not be the second page in a TLB entry. 3110 * This routine assumes that the length is appropriately-sized so 3111 * that the allocation does not share a TLB entry at all if required. 3112 */ 3113void 3114pmap_align_tlb(vm_offset_t *addr) 3115{ 3116 if ((*addr & PAGE_SIZE) == 0) 3117 return; 3118 *addr += PAGE_SIZE; 3119 return; 3120} 3121 3122#ifdef DDB 3123DB_SHOW_COMMAND(ptable, ddb_pid_dump) 3124{ 3125 pmap_t pmap; 3126 struct thread *td = NULL; 3127 struct proc *p; 3128 int i, j, k; 3129 vm_paddr_t pa; 3130 vm_offset_t va; 3131 3132 if (have_addr) { 3133 td = db_lookup_thread(addr, TRUE); 3134 if (td == NULL) { 3135 db_printf("Invalid pid or tid"); 3136 return; 3137 } 3138 p = td->td_proc; 3139 if (p->p_vmspace == NULL) { 3140 db_printf("No vmspace for process"); 3141 return; 3142 } 3143 pmap = vmspace_pmap(p->p_vmspace); 3144 } else 3145 pmap = kernel_pmap; 3146 3147 db_printf("pmap:%p segtab:%p asid:%x generation:%x\n", 3148 pmap, pmap->pm_segtab, pmap->pm_asid[0].asid, 3149 pmap->pm_asid[0].gen); 3150 for (i = 0; i < NPDEPG; i++) { 3151 pd_entry_t *pdpe; 3152 pt_entry_t *pde; 3153 pt_entry_t pte; 3154 3155 pdpe = (pd_entry_t *)pmap->pm_segtab[i]; 3156 if (pdpe == NULL) 3157 continue; 3158 db_printf("[%4d] %p\n", i, pdpe); 3159#ifdef __mips_n64 3160 for (j = 0; j < NPDEPG; j++) { 3161 pde = (pt_entry_t *)pdpe[j]; 3162 if (pde == NULL) 3163 continue; 3164 db_printf("\t[%4d] %p\n", j, pde); 3165#else 3166 { 3167 j = 0; 3168 pde = (pt_entry_t *)pdpe; 3169#endif 3170 for (k = 0; k < NPTEPG; k++) { 3171 pte = pde[k]; 3172 if (pte == 0 || !pte_test(&pte, PTE_V)) 3173 continue; 3174 pa = TLBLO_PTE_TO_PA(pte); 3175 va = ((u_long)i << SEGSHIFT) | (j << PDRSHIFT) | (k << PAGE_SHIFT); 3176 db_printf("\t\t[%04d] va: %p pte: %8jx pa:%jx\n", 3177 k, (void *)va, (uintmax_t)pte, (uintmax_t)pa); 3178 } 3179 } 3180 } 3181} 3182#endif 3183 3184#if defined(DEBUG) 3185 3186static void pads(pmap_t pm); 3187void pmap_pvdump(vm_offset_t pa); 3188 3189/* print address space of pmap*/ 3190static void 3191pads(pmap_t pm) 3192{ 3193 unsigned va, i, j; 3194 pt_entry_t *ptep; 3195 3196 if (pm == kernel_pmap) 3197 return; 3198 for (i = 0; i < NPTEPG; i++) 3199 if (pm->pm_segtab[i]) 3200 for (j = 0; j < NPTEPG; j++) { 3201 va = (i << SEGSHIFT) + (j << PAGE_SHIFT); 3202 if (pm == kernel_pmap && va < KERNBASE) 3203 continue; 3204 if (pm != kernel_pmap && 3205 va >= VM_MAXUSER_ADDRESS) 3206 continue; 3207 ptep = pmap_pte(pm, va); 3208 if (pte_test(ptep, PTE_V)) 3209 printf("%x:%x ", va, *(int *)ptep); 3210 } 3211 3212} 3213 3214void 3215pmap_pvdump(vm_offset_t pa) 3216{ 3217 register pv_entry_t pv; 3218 vm_page_t m; 3219 3220 printf("pa %x", pa); 3221 m = PHYS_TO_VM_PAGE(pa); 3222 for (pv = TAILQ_FIRST(&m->md.pv_list); pv; 3223 pv = TAILQ_NEXT(pv, pv_list)) { 3224 printf(" -> pmap %p, va %x", (void *)pv->pv_pmap, pv->pv_va); 3225 pads(pv->pv_pmap); 3226 } 3227 printf(" "); 3228} 3229 3230/* N/C */ 3231#endif 3232 3233 3234/* 3235 * Allocate TLB address space tag (called ASID or TLBPID) and return it. 3236 * It takes almost as much or more time to search the TLB for a 3237 * specific ASID and flush those entries as it does to flush the entire TLB. 3238 * Therefore, when we allocate a new ASID, we just take the next number. When 3239 * we run out of numbers, we flush the TLB, increment the generation count 3240 * and start over. ASID zero is reserved for kernel use. 3241 */ 3242static void 3243pmap_asid_alloc(pmap) 3244 pmap_t pmap; 3245{ 3246 if (pmap->pm_asid[PCPU_GET(cpuid)].asid != PMAP_ASID_RESERVED && 3247 pmap->pm_asid[PCPU_GET(cpuid)].gen == PCPU_GET(asid_generation)); 3248 else { 3249 if (PCPU_GET(next_asid) == pmap_max_asid) { 3250 tlb_invalidate_all_user(NULL); 3251 PCPU_SET(asid_generation, 3252 (PCPU_GET(asid_generation) + 1) & ASIDGEN_MASK); 3253 if (PCPU_GET(asid_generation) == 0) { 3254 PCPU_SET(asid_generation, 1); 3255 } 3256 PCPU_SET(next_asid, 1); /* 0 means invalid */ 3257 } 3258 pmap->pm_asid[PCPU_GET(cpuid)].asid = PCPU_GET(next_asid); 3259 pmap->pm_asid[PCPU_GET(cpuid)].gen = PCPU_GET(asid_generation); 3260 PCPU_SET(next_asid, PCPU_GET(next_asid) + 1); 3261 } 3262} 3263 3264static pt_entry_t 3265init_pte_prot(vm_page_t m, vm_prot_t access, vm_prot_t prot) 3266{ 3267 pt_entry_t rw; 3268 3269 if (!(prot & VM_PROT_WRITE)) 3270 rw = PTE_V | PTE_RO; 3271 else if ((m->oflags & VPO_UNMANAGED) == 0) { 3272 if ((access & VM_PROT_WRITE) != 0) 3273 rw = PTE_V | PTE_D; 3274 else 3275 rw = PTE_V; 3276 } else 3277 /* Needn't emulate a modified bit for unmanaged pages. */ 3278 rw = PTE_V | PTE_D; 3279 return (rw); 3280} 3281 3282/* 3283 * pmap_emulate_modified : do dirty bit emulation 3284 * 3285 * On SMP, update just the local TLB, other CPUs will update their 3286 * TLBs from PTE lazily, if they get the exception. 3287 * Returns 0 in case of sucess, 1 if the page is read only and we 3288 * need to fault. 3289 */ 3290int 3291pmap_emulate_modified(pmap_t pmap, vm_offset_t va) 3292{ 3293 pt_entry_t *pte; 3294 3295 PMAP_LOCK(pmap); 3296 pte = pmap_pte(pmap, va); 3297 if (pte == NULL) 3298 panic("pmap_emulate_modified: can't find PTE"); 3299#ifdef SMP 3300 /* It is possible that some other CPU changed m-bit */ 3301 if (!pte_test(pte, PTE_V) || pte_test(pte, PTE_D)) { 3302 tlb_update(pmap, va, *pte); 3303 PMAP_UNLOCK(pmap); 3304 return (0); 3305 } 3306#else 3307 if (!pte_test(pte, PTE_V) || pte_test(pte, PTE_D)) 3308 panic("pmap_emulate_modified: invalid pte"); 3309#endif 3310 if (pte_test(pte, PTE_RO)) { 3311 PMAP_UNLOCK(pmap); 3312 return (1); 3313 } 3314 pte_set(pte, PTE_D); 3315 tlb_update(pmap, va, *pte); 3316 if (!pte_test(pte, PTE_MANAGED)) 3317 panic("pmap_emulate_modified: unmanaged page"); 3318 PMAP_UNLOCK(pmap); 3319 return (0); 3320} 3321 3322/* 3323 * Routine: pmap_kextract 3324 * Function: 3325 * Extract the physical page address associated 3326 * virtual address. 3327 */ 3328vm_paddr_t 3329pmap_kextract(vm_offset_t va) 3330{ 3331 int mapped; 3332 3333 /* 3334 * First, the direct-mapped regions. 3335 */ 3336#if defined(__mips_n64) 3337 if (va >= MIPS_XKPHYS_START && va < MIPS_XKPHYS_END) 3338 return (MIPS_XKPHYS_TO_PHYS(va)); 3339#endif 3340 if (va >= MIPS_KSEG0_START && va < MIPS_KSEG0_END) 3341 return (MIPS_KSEG0_TO_PHYS(va)); 3342 3343 if (va >= MIPS_KSEG1_START && va < MIPS_KSEG1_END) 3344 return (MIPS_KSEG1_TO_PHYS(va)); 3345 3346 /* 3347 * User virtual addresses. 3348 */ 3349 if (va < VM_MAXUSER_ADDRESS) { 3350 pt_entry_t *ptep; 3351 3352 if (curproc && curproc->p_vmspace) { 3353 ptep = pmap_pte(&curproc->p_vmspace->vm_pmap, va); 3354 if (ptep) { 3355 return (TLBLO_PTE_TO_PA(*ptep) | 3356 (va & PAGE_MASK)); 3357 } 3358 return (0); 3359 } 3360 } 3361 3362 /* 3363 * Should be kernel virtual here, otherwise fail 3364 */ 3365 mapped = (va >= MIPS_KSEG2_START || va < MIPS_KSEG2_END); 3366#if defined(__mips_n64) 3367 mapped = mapped || (va >= MIPS_XKSEG_START || va < MIPS_XKSEG_END); 3368#endif 3369 /* 3370 * Kernel virtual. 3371 */ 3372 3373 if (mapped) { 3374 pt_entry_t *ptep; 3375 3376 /* Is the kernel pmap initialized? */ 3377 if (!CPU_EMPTY(&kernel_pmap->pm_active)) { 3378 /* It's inside the virtual address range */ 3379 ptep = pmap_pte(kernel_pmap, va); 3380 if (ptep) { 3381 return (TLBLO_PTE_TO_PA(*ptep) | 3382 (va & PAGE_MASK)); 3383 } 3384 } 3385 return (0); 3386 } 3387 3388 panic("%s for unknown address space %p.", __func__, (void *)va); 3389} 3390 3391 3392void 3393pmap_flush_pvcache(vm_page_t m) 3394{ 3395 pv_entry_t pv; 3396 3397 if (m != NULL) { 3398 for (pv = TAILQ_FIRST(&m->md.pv_list); pv; 3399 pv = TAILQ_NEXT(pv, pv_list)) { 3400 mips_dcache_wbinv_range_index(pv->pv_va, PAGE_SIZE); 3401 } 3402 } 3403} 3404