pmap.c revision 207441
1/* 2 * Copyright (c) 1991 Regents of the University of California. 3 * All rights reserved. 4 * Copyright (c) 1994 John S. Dyson 5 * All rights reserved. 6 * Copyright (c) 1994 David Greenman 7 * All rights reserved. 8 * 9 * This code is derived from software contributed to Berkeley by 10 * the Systems Programming Group of the University of Utah Computer 11 * Science Department and William Jolitz of UUNET Technologies Inc. 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 1. Redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution. 21 * 4. Neither the name of the University nor the names of its contributors 22 * may be used to endorse or promote products derived from this software 23 * without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 28 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 31 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35 * SUCH DAMAGE. 36 * 37 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91 38 * from: src/sys/i386/i386/pmap.c,v 1.250.2.8 2000/11/21 00:09:14 ps 39 * JNPR: pmap.c,v 1.11.2.1 2007/08/16 11:51:06 girish 40 */ 41 42/* 43 * Manages physical address maps. 44 * 45 * In addition to hardware address maps, this 46 * module is called upon to provide software-use-only 47 * maps which may or may not be stored in the same 48 * form as hardware maps. These pseudo-maps are 49 * used to store intermediate results from copy 50 * operations to and from address spaces. 51 * 52 * Since the information managed by this module is 53 * also stored by the logical address mapping module, 54 * this module may throw away valid virtual-to-physical 55 * mappings at almost any time. However, invalidations 56 * of virtual-to-physical mappings must be done as 57 * requested. 58 * 59 * In order to cope with hardware architectures which 60 * make virtual-to-physical map invalidates expensive, 61 * this module may delay invalidate or reduced protection 62 * operations until such time as they are actually 63 * necessary. This module is given full information as 64 * to which processors are currently using which maps, 65 * and to when physical maps must be made correct. 66 */ 67 68#include <sys/cdefs.h> 69__FBSDID("$FreeBSD: head/sys/mips/mips/pmap.c 207441 2010-04-30 17:12:20Z rrs $"); 70 71#include "opt_ddb.h" 72#include "opt_msgbuf.h" 73#include <sys/param.h> 74#include <sys/systm.h> 75#include <sys/proc.h> 76#include <sys/msgbuf.h> 77#include <sys/vmmeter.h> 78#include <sys/mman.h> 79#include <sys/smp.h> 80 81#include <vm/vm.h> 82#include <vm/vm_param.h> 83#include <sys/lock.h> 84#include <sys/mutex.h> 85#include <vm/vm_kern.h> 86#include <vm/vm_page.h> 87#include <vm/vm_map.h> 88#include <vm/vm_object.h> 89#include <vm/vm_extern.h> 90#include <vm/vm_pageout.h> 91#include <vm/vm_pager.h> 92#include <vm/uma.h> 93#include <sys/pcpu.h> 94#include <sys/sched.h> 95#ifdef SMP 96#include <sys/smp.h> 97#endif 98 99#include <machine/cache.h> 100#include <machine/md_var.h> 101 102#if defined(DIAGNOSTIC) 103#define PMAP_DIAGNOSTIC 104#endif 105 106#undef PMAP_DEBUG 107 108#ifndef PMAP_SHPGPERPROC 109#define PMAP_SHPGPERPROC 200 110#endif 111 112#if !defined(PMAP_DIAGNOSTIC) 113#define PMAP_INLINE __inline 114#else 115#define PMAP_INLINE 116#endif 117 118/* 119 * Get PDEs and PTEs for user/kernel address space 120 */ 121#define pmap_pde(m, v) (&((m)->pm_segtab[(vm_offset_t)(v) >> SEGSHIFT])) 122#define segtab_pde(m, v) (m[(vm_offset_t)(v) >> SEGSHIFT]) 123 124#define pmap_pte_w(pte) ((*(int *)pte & PTE_W) != 0) 125#define pmap_pde_v(pte) ((*(int *)pte) != 0) 126#define pmap_pte_m(pte) ((*(int *)pte & PTE_M) != 0) 127#define pmap_pte_v(pte) ((*(int *)pte & PTE_V) != 0) 128 129#define pmap_pte_set_w(pte, v) ((v)?(*(int *)pte |= PTE_W):(*(int *)pte &= ~PTE_W)) 130#define pmap_pte_set_prot(pte, v) ((*(int *)pte &= ~PG_PROT), (*(int *)pte |= (v))) 131 132#define MIPS_SEGSIZE (1L << SEGSHIFT) 133#define mips_segtrunc(va) ((va) & ~(MIPS_SEGSIZE-1)) 134#define pmap_TLB_invalidate_all() MIPS_TBIAP() 135#define pmap_va_asid(pmap, va) ((va) | ((pmap)->pm_asid[PCPU_GET(cpuid)].asid << VMTLB_PID_SHIFT)) 136#define is_kernel_pmap(x) ((x) == kernel_pmap) 137 138struct pmap kernel_pmap_store; 139pd_entry_t *kernel_segmap; 140 141vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */ 142vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */ 143 144static int nkpt; 145unsigned pmap_max_asid; /* max ASID supported by the system */ 146 147 148#define PMAP_ASID_RESERVED 0 149 150vm_offset_t kernel_vm_end; 151 152static struct tlb tlbstash[MAXCPU][MIPS_MAX_TLB_ENTRIES]; 153 154static void pmap_asid_alloc(pmap_t pmap); 155 156/* 157 * Data for the pv entry allocation mechanism 158 */ 159static uma_zone_t pvzone; 160static struct vm_object pvzone_obj; 161static int pv_entry_count = 0, pv_entry_max = 0, pv_entry_high_water = 0; 162 163static PMAP_INLINE void free_pv_entry(pv_entry_t pv); 164static pv_entry_t get_pv_entry(pmap_t locked_pmap); 165static __inline void pmap_changebit(vm_page_t m, int bit, boolean_t setem); 166 167static vm_page_t pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, 168 vm_page_t m, vm_prot_t prot, vm_page_t mpte); 169static int pmap_remove_pte(struct pmap *pmap, pt_entry_t *ptq, vm_offset_t va); 170static void pmap_remove_page(struct pmap *pmap, vm_offset_t va); 171static void pmap_remove_entry(struct pmap *pmap, vm_page_t m, vm_offset_t va); 172static boolean_t pmap_testbit(vm_page_t m, int bit); 173static void 174pmap_insert_entry(pmap_t pmap, vm_offset_t va, vm_page_t mpte, 175 vm_page_t m, boolean_t wired); 176static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_page_t mpte, 177 vm_offset_t va, vm_page_t m); 178 179static vm_page_t pmap_allocpte(pmap_t pmap, vm_offset_t va, int flags); 180 181static vm_page_t _pmap_allocpte(pmap_t pmap, unsigned ptepindex, int flags); 182static int pmap_unuse_pt(pmap_t, vm_offset_t, vm_page_t); 183static int init_pte_prot(vm_offset_t va, vm_page_t m, vm_prot_t prot); 184static void pmap_TLB_invalidate_kernel(vm_offset_t); 185static void pmap_TLB_update_kernel(vm_offset_t, pt_entry_t); 186 187#ifdef SMP 188static void pmap_invalidate_page_action(void *arg); 189static void pmap_invalidate_all_action(void *arg); 190static void pmap_update_page_action(void *arg); 191 192#endif 193 194struct local_sysmaps { 195 struct mtx lock; 196 vm_offset_t base; 197 uint16_t valid1, valid2; 198}; 199 200/* This structure is for large memory 201 * above 512Meg. We can't (in 32 bit mode) 202 * just use the direct mapped MIPS_KSEG0_TO_PHYS() 203 * macros since we can't see the memory and must 204 * map it in when we need to access it. In 64 205 * bit mode this goes away. 206 */ 207static struct local_sysmaps sysmap_lmem[MAXCPU]; 208caddr_t virtual_sys_start = (caddr_t)0; 209 210#define PMAP_LMEM_MAP1(va, phys) \ 211 int cpu; \ 212 struct local_sysmaps *sysm; \ 213 pt_entry_t *pte, npte; \ 214 \ 215 cpu = PCPU_GET(cpuid); \ 216 sysm = &sysmap_lmem[cpu]; \ 217 PMAP_LGMEM_LOCK(sysm); \ 218 intr = intr_disable(); \ 219 sched_pin(); \ 220 va = sysm->base; \ 221 npte = mips_paddr_to_tlbpfn(phys) | \ 222 PTE_RW | PTE_V | PTE_G | PTE_W | PTE_CACHE; \ 223 pte = pmap_pte(kernel_pmap, va); \ 224 *pte = npte; \ 225 sysm->valid1 = 1; 226 227#define PMAP_LMEM_MAP2(va1, phys1, va2, phys2) \ 228 int cpu; \ 229 struct local_sysmaps *sysm; \ 230 pt_entry_t *pte, npte; \ 231 \ 232 cpu = PCPU_GET(cpuid); \ 233 sysm = &sysmap_lmem[cpu]; \ 234 PMAP_LGMEM_LOCK(sysm); \ 235 intr = intr_disable(); \ 236 sched_pin(); \ 237 va1 = sysm->base; \ 238 va2 = sysm->base + PAGE_SIZE; \ 239 npte = mips_paddr_to_tlbpfn(phys1) | \ 240 PTE_RW | PTE_V | PTE_G | PTE_W | PTE_CACHE; \ 241 pte = pmap_pte(kernel_pmap, va1); \ 242 *pte = npte; \ 243 npte = mips_paddr_to_tlbpfn(phys2) | \ 244 PTE_RW | PTE_V | PTE_G | PTE_W | PTE_CACHE; \ 245 pte = pmap_pte(kernel_pmap, va2); \ 246 *pte = npte; \ 247 sysm->valid1 = 1; \ 248 sysm->valid2 = 1; 249 250#define PMAP_LMEM_UNMAP() \ 251 pte = pmap_pte(kernel_pmap, sysm->base); \ 252 *pte = PTE_G; \ 253 pmap_TLB_invalidate_kernel(sysm->base); \ 254 sysm->valid1 = 0; \ 255 pte = pmap_pte(kernel_pmap, sysm->base + PAGE_SIZE); \ 256 *pte = PTE_G; \ 257 pmap_TLB_invalidate_kernel(sysm->base + PAGE_SIZE); \ 258 sysm->valid2 = 0; \ 259 sched_unpin(); \ 260 intr_restore(intr); \ 261 PMAP_LGMEM_UNLOCK(sysm); 262 263pd_entry_t 264pmap_segmap(pmap_t pmap, vm_offset_t va) 265{ 266 if (pmap->pm_segtab) 267 return (pmap->pm_segtab[((vm_offset_t)(va) >> SEGSHIFT)]); 268 else 269 return ((pd_entry_t)0); 270} 271 272/* 273 * Routine: pmap_pte 274 * Function: 275 * Extract the page table entry associated 276 * with the given map/virtual_address pair. 277 */ 278pt_entry_t * 279pmap_pte(pmap_t pmap, vm_offset_t va) 280{ 281 pt_entry_t *pdeaddr; 282 283 if (pmap) { 284 pdeaddr = (pt_entry_t *)pmap_segmap(pmap, va); 285 if (pdeaddr) { 286 return pdeaddr + vad_to_pte_offset(va); 287 } 288 } 289 return ((pt_entry_t *)0); 290} 291 292 293vm_offset_t 294pmap_steal_memory(vm_size_t size) 295{ 296 vm_size_t bank_size; 297 vm_offset_t pa, va; 298 299 size = round_page(size); 300 301 bank_size = phys_avail[1] - phys_avail[0]; 302 while (size > bank_size) { 303 int i; 304 305 for (i = 0; phys_avail[i + 2]; i += 2) { 306 phys_avail[i] = phys_avail[i + 2]; 307 phys_avail[i + 1] = phys_avail[i + 3]; 308 } 309 phys_avail[i] = 0; 310 phys_avail[i + 1] = 0; 311 if (!phys_avail[0]) 312 panic("pmap_steal_memory: out of memory"); 313 bank_size = phys_avail[1] - phys_avail[0]; 314 } 315 316 pa = phys_avail[0]; 317 phys_avail[0] += size; 318 if (pa >= MIPS_KSEG0_LARGEST_PHYS) { 319 panic("Out of memory below 512Meg?"); 320 } 321 va = MIPS_PHYS_TO_KSEG0(pa); 322 bzero((caddr_t)va, size); 323 return va; 324} 325 326/* 327 * Bootstrap the system enough to run with virtual memory. This 328 * assumes that the phys_avail array has been initialized. 329 */ 330void 331pmap_bootstrap(void) 332{ 333 pt_entry_t *pgtab; 334 pt_entry_t *pte; 335 int i, j; 336 int memory_larger_than_512meg = 0; 337 338 /* Sort. */ 339again: 340 for (i = 0; phys_avail[i + 1] != 0; i += 2) { 341 /* 342 * Keep the memory aligned on page boundary. 343 */ 344 phys_avail[i] = round_page(phys_avail[i]); 345 phys_avail[i + 1] = trunc_page(phys_avail[i + 1]); 346 347 if (phys_avail[i + 1] >= MIPS_KSEG0_LARGEST_PHYS) 348 memory_larger_than_512meg++; 349 if (i < 2) 350 continue; 351 if (phys_avail[i - 2] > phys_avail[i]) { 352 vm_paddr_t ptemp[2]; 353 354 355 ptemp[0] = phys_avail[i + 0]; 356 ptemp[1] = phys_avail[i + 1]; 357 358 phys_avail[i + 0] = phys_avail[i - 2]; 359 phys_avail[i + 1] = phys_avail[i - 1]; 360 361 phys_avail[i - 2] = ptemp[0]; 362 phys_avail[i - 1] = ptemp[1]; 363 goto again; 364 } 365 } 366 367 /* 368 * Copy the phys_avail[] array before we start stealing memory from it. 369 */ 370 for (i = 0; phys_avail[i + 1] != 0; i += 2) { 371 physmem_desc[i] = phys_avail[i]; 372 physmem_desc[i + 1] = phys_avail[i + 1]; 373 } 374 375 Maxmem = atop(phys_avail[i - 1]); 376 377 if (bootverbose) { 378 printf("Physical memory chunk(s):\n"); 379 for (i = 0; phys_avail[i + 1] != 0; i += 2) { 380 vm_paddr_t size; 381 382 size = phys_avail[i + 1] - phys_avail[i]; 383 printf("%#08jx - %#08jx, %ju bytes (%ju pages)\n", 384 (uintmax_t) phys_avail[i], 385 (uintmax_t) phys_avail[i + 1] - 1, 386 (uintmax_t) size, (uintmax_t) size / PAGE_SIZE); 387 } 388 printf("Maxmem is 0x%0lx\n", ptoa(Maxmem)); 389 } 390 /* 391 * Steal the message buffer from the beginning of memory. 392 */ 393 msgbufp = (struct msgbuf *)pmap_steal_memory(MSGBUF_SIZE); 394 msgbufinit(msgbufp, MSGBUF_SIZE); 395 396 /* 397 * Steal thread0 kstack. 398 */ 399 kstack0 = pmap_steal_memory(KSTACK_PAGES << PAGE_SHIFT); 400 401 402 virtual_avail = VM_MIN_KERNEL_ADDRESS; 403 virtual_end = VM_MAX_KERNEL_ADDRESS; 404 405#ifdef SMP 406 /* 407 * Steal some virtual address space to map the pcpu area. 408 */ 409 virtual_avail = roundup2(virtual_avail, PAGE_SIZE * 2); 410 pcpup = (struct pcpu *)virtual_avail; 411 virtual_avail += PAGE_SIZE * 2; 412 413 /* 414 * Initialize the wired TLB entry mapping the pcpu region for 415 * the BSP at 'pcpup'. Up until this point we were operating 416 * with the 'pcpup' for the BSP pointing to a virtual address 417 * in KSEG0 so there was no need for a TLB mapping. 418 */ 419 mips_pcpu_tlb_init(PCPU_ADDR(0)); 420 421 if (bootverbose) 422 printf("pcpu is available at virtual address %p.\n", pcpup); 423#endif 424 425 /* 426 * Steal some virtual space that will not be in kernel_segmap. This 427 * va memory space will be used to map in kernel pages that are 428 * outside the 512Meg region. Note that we only do this steal when 429 * we do have memory in this region, that way for systems with 430 * smaller memory we don't "steal" any va ranges :-) 431 */ 432 if (memory_larger_than_512meg) { 433 for (i = 0; i < MAXCPU; i++) { 434 sysmap_lmem[i].base = virtual_avail; 435 virtual_avail += PAGE_SIZE * 2; 436 sysmap_lmem[i].valid1 = sysmap_lmem[i].valid2 = 0; 437 PMAP_LGMEM_LOCK_INIT(&sysmap_lmem[i]); 438 } 439 } 440 virtual_sys_start = (caddr_t)virtual_avail; 441 /* 442 * Allocate segment table for the kernel 443 */ 444 kernel_segmap = (pd_entry_t *)pmap_steal_memory(PAGE_SIZE); 445 446 /* 447 * Allocate second level page tables for the kernel 448 */ 449 nkpt = NKPT; 450 if (memory_larger_than_512meg) { 451 /* 452 * If we have a large memory system we CANNOT afford to hit 453 * pmap_growkernel() and allocate memory. Since we MAY end 454 * up with a page that is NOT mappable. For that reason we 455 * up front grab more. Normall NKPT is 120 (YMMV see pmap.h) 456 * this gives us 480meg of kernel virtual addresses at the 457 * cost of 120 pages (each page gets us 4 Meg). Since the 458 * kernel starts at virtual_avail, we can use this to 459 * calculate how many entris are left from there to the end 460 * of the segmap, we want to allocate all of it, which would 461 * be somewhere above 0xC0000000 - 0xFFFFFFFF which results 462 * in about 256 entries or so instead of the 120. 463 */ 464 nkpt = (PAGE_SIZE / sizeof(pd_entry_t)) - (virtual_avail >> SEGSHIFT); 465 } 466 pgtab = (pt_entry_t *)pmap_steal_memory(PAGE_SIZE * nkpt); 467 468 /* 469 * The R[4-7]?00 stores only one copy of the Global bit in the 470 * translation lookaside buffer for each 2 page entry. Thus invalid 471 * entrys must have the Global bit set so when Entry LO and Entry HI 472 * G bits are anded together they will produce a global bit to store 473 * in the tlb. 474 */ 475 for (i = 0, pte = pgtab; i < (nkpt * NPTEPG); i++, pte++) 476 *pte = PTE_G; 477 478 /* 479 * The segment table contains the KVA of the pages in the second 480 * level page table. 481 */ 482 for (i = 0, j = (virtual_avail >> SEGSHIFT); i < nkpt; i++, j++) 483 kernel_segmap[j] = (pd_entry_t)(pgtab + (i * NPTEPG)); 484 485 /* 486 * The kernel's pmap is statically allocated so we don't have to use 487 * pmap_create, which is unlikely to work correctly at this part of 488 * the boot sequence (XXX and which no longer exists). 489 */ 490 PMAP_LOCK_INIT(kernel_pmap); 491 kernel_pmap->pm_segtab = kernel_segmap; 492 kernel_pmap->pm_active = ~0; 493 TAILQ_INIT(&kernel_pmap->pm_pvlist); 494 kernel_pmap->pm_asid[0].asid = PMAP_ASID_RESERVED; 495 kernel_pmap->pm_asid[0].gen = 0; 496 pmap_max_asid = VMNUM_PIDS; 497 MachSetPID(0); 498} 499 500/* 501 * Initialize a vm_page's machine-dependent fields. 502 */ 503void 504pmap_page_init(vm_page_t m) 505{ 506 507 TAILQ_INIT(&m->md.pv_list); 508 m->md.pv_list_count = 0; 509 m->md.pv_flags = 0; 510} 511 512/* 513 * Initialize the pmap module. 514 * Called by vm_init, to initialize any structures that the pmap 515 * system needs to map virtual memory. 516 * pmap_init has been enhanced to support in a fairly consistant 517 * way, discontiguous physical memory. 518 */ 519void 520pmap_init(void) 521{ 522 523 /* 524 * Initialize the address space (zone) for the pv entries. Set a 525 * high water mark so that the system can recover from excessive 526 * numbers of pv entries. 527 */ 528 pvzone = uma_zcreate("PV ENTRY", sizeof(struct pv_entry), NULL, NULL, 529 NULL, NULL, UMA_ALIGN_PTR, UMA_ZONE_VM | UMA_ZONE_NOFREE); 530 pv_entry_max = PMAP_SHPGPERPROC * maxproc + cnt.v_page_count; 531 pv_entry_high_water = 9 * (pv_entry_max / 10); 532 uma_zone_set_obj(pvzone, &pvzone_obj, pv_entry_max); 533} 534 535/*************************************************** 536 * Low level helper routines..... 537 ***************************************************/ 538 539#if defined(PMAP_DIAGNOSTIC) 540 541/* 542 * This code checks for non-writeable/modified pages. 543 * This should be an invalid condition. 544 */ 545static int 546pmap_nw_modified(pt_entry_t pte) 547{ 548 if ((pte & (PTE_M | PTE_RO)) == (PTE_M | PTE_RO)) 549 return (1); 550 else 551 return (0); 552} 553 554#endif 555 556static void 557pmap_invalidate_all(pmap_t pmap) 558{ 559#ifdef SMP 560 smp_rendezvous(0, pmap_invalidate_all_action, 0, (void *)pmap); 561} 562 563static void 564pmap_invalidate_all_action(void *arg) 565{ 566 pmap_t pmap = (pmap_t)arg; 567 568#endif 569 570 if (pmap->pm_active & PCPU_GET(cpumask)) { 571 pmap_TLB_invalidate_all(); 572 } else 573 pmap->pm_asid[PCPU_GET(cpuid)].gen = 0; 574} 575 576struct pmap_invalidate_page_arg { 577 pmap_t pmap; 578 vm_offset_t va; 579}; 580 581static __inline void 582pmap_invalidate_page(pmap_t pmap, vm_offset_t va) 583{ 584#ifdef SMP 585 struct pmap_invalidate_page_arg arg; 586 587 arg.pmap = pmap; 588 arg.va = va; 589 590 smp_rendezvous(0, pmap_invalidate_page_action, 0, (void *)&arg); 591} 592 593static void 594pmap_invalidate_page_action(void *arg) 595{ 596 pmap_t pmap = ((struct pmap_invalidate_page_arg *)arg)->pmap; 597 vm_offset_t va = ((struct pmap_invalidate_page_arg *)arg)->va; 598 599#endif 600 601 if (is_kernel_pmap(pmap)) { 602 pmap_TLB_invalidate_kernel(va); 603 return; 604 } 605 if (pmap->pm_asid[PCPU_GET(cpuid)].gen != PCPU_GET(asid_generation)) 606 return; 607 else if (!(pmap->pm_active & PCPU_GET(cpumask))) { 608 pmap->pm_asid[PCPU_GET(cpuid)].gen = 0; 609 return; 610 } 611 va = pmap_va_asid(pmap, (va & ~PAGE_MASK)); 612 mips_TBIS(va); 613} 614 615static void 616pmap_TLB_invalidate_kernel(vm_offset_t va) 617{ 618 u_int32_t pid; 619 620 MachTLBGetPID(pid); 621 va = va | (pid << VMTLB_PID_SHIFT); 622 mips_TBIS(va); 623} 624 625struct pmap_update_page_arg { 626 pmap_t pmap; 627 vm_offset_t va; 628 pt_entry_t pte; 629}; 630 631void 632pmap_update_page(pmap_t pmap, vm_offset_t va, pt_entry_t pte) 633{ 634#ifdef SMP 635 struct pmap_update_page_arg arg; 636 637 arg.pmap = pmap; 638 arg.va = va; 639 arg.pte = pte; 640 641 smp_rendezvous(0, pmap_update_page_action, 0, (void *)&arg); 642} 643 644static void 645pmap_update_page_action(void *arg) 646{ 647 pmap_t pmap = ((struct pmap_update_page_arg *)arg)->pmap; 648 vm_offset_t va = ((struct pmap_update_page_arg *)arg)->va; 649 pt_entry_t pte = ((struct pmap_update_page_arg *)arg)->pte; 650 651#endif 652 if (is_kernel_pmap(pmap)) { 653 pmap_TLB_update_kernel(va, pte); 654 return; 655 } 656 if (pmap->pm_asid[PCPU_GET(cpuid)].gen != PCPU_GET(asid_generation)) 657 return; 658 else if (!(pmap->pm_active & PCPU_GET(cpumask))) { 659 pmap->pm_asid[PCPU_GET(cpuid)].gen = 0; 660 return; 661 } 662 va = pmap_va_asid(pmap, (va & ~PAGE_MASK)); 663 MachTLBUpdate(va, pte); 664} 665 666static void 667pmap_TLB_update_kernel(vm_offset_t va, pt_entry_t pte) 668{ 669 u_int32_t pid; 670 671 va &= ~PAGE_MASK; 672 673 MachTLBGetPID(pid); 674 va = va | (pid << VMTLB_PID_SHIFT); 675 676 MachTLBUpdate(va, pte); 677} 678 679/* 680 * Routine: pmap_extract 681 * Function: 682 * Extract the physical page address associated 683 * with the given map/virtual_address pair. 684 */ 685vm_paddr_t 686pmap_extract(pmap_t pmap, vm_offset_t va) 687{ 688 pt_entry_t *pte; 689 vm_offset_t retval = 0; 690 691 PMAP_LOCK(pmap); 692 pte = pmap_pte(pmap, va); 693 if (pte) { 694 retval = mips_tlbpfn_to_paddr(*pte) | (va & PAGE_MASK); 695 } 696 PMAP_UNLOCK(pmap); 697 return retval; 698} 699 700/* 701 * Routine: pmap_extract_and_hold 702 * Function: 703 * Atomically extract and hold the physical page 704 * with the given pmap and virtual address pair 705 * if that mapping permits the given protection. 706 */ 707vm_page_t 708pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot) 709{ 710 pt_entry_t pte; 711 vm_page_t m; 712 vm_paddr_t pa; 713 714 m = NULL; 715 pa = 0; 716 PMAP_LOCK(pmap); 717retry: 718 pte = *pmap_pte(pmap, va); 719 if (pte != 0 && pmap_pte_v(&pte) && 720 ((pte & PTE_RW) || (prot & VM_PROT_WRITE) == 0)) { 721 if (vm_page_pa_tryrelock(pmap, mips_tlbpfn_to_paddr(pte), &pa)) 722 goto retry; 723 724 m = PHYS_TO_VM_PAGE(mips_tlbpfn_to_paddr(pte)); 725 vm_page_hold(m); 726 } 727 PA_UNLOCK_COND(pa); 728 PMAP_UNLOCK(pmap); 729 return (m); 730} 731 732/*************************************************** 733 * Low level mapping routines..... 734 ***************************************************/ 735 736/* 737 * add a wired page to the kva 738 */ 739 /* PMAP_INLINE */ void 740pmap_kenter(vm_offset_t va, vm_paddr_t pa) 741{ 742 register pt_entry_t *pte; 743 pt_entry_t npte, opte; 744 745#ifdef PMAP_DEBUG 746 printf("pmap_kenter: va: 0x%08x -> pa: 0x%08x\n", va, pa); 747#endif 748 npte = mips_paddr_to_tlbpfn(pa) | PTE_RW | PTE_V | PTE_G | PTE_W; 749 750 if (is_cacheable_mem(pa)) 751 npte |= PTE_CACHE; 752 else 753 npte |= PTE_UNCACHED; 754 755 pte = pmap_pte(kernel_pmap, va); 756 opte = *pte; 757 *pte = npte; 758 759 pmap_update_page(kernel_pmap, va, npte); 760} 761 762/* 763 * remove a page from the kernel pagetables 764 */ 765 /* PMAP_INLINE */ void 766pmap_kremove(vm_offset_t va) 767{ 768 register pt_entry_t *pte; 769 770 /* 771 * Write back all caches from the page being destroyed 772 */ 773 mips_dcache_wbinv_range_index(va, PAGE_SIZE); 774 775 pte = pmap_pte(kernel_pmap, va); 776 *pte = PTE_G; 777 pmap_invalidate_page(kernel_pmap, va); 778} 779 780/* 781 * Used to map a range of physical addresses into kernel 782 * virtual address space. 783 * 784 * The value passed in '*virt' is a suggested virtual address for 785 * the mapping. Architectures which can support a direct-mapped 786 * physical to virtual region can return the appropriate address 787 * within that region, leaving '*virt' unchanged. Other 788 * architectures should map the pages starting at '*virt' and 789 * update '*virt' with the first usable address after the mapped 790 * region. 791 */ 792vm_offset_t 793pmap_map(vm_offset_t *virt, vm_offset_t start, vm_offset_t end, int prot) 794{ 795 vm_offset_t va, sva; 796 797 va = sva = *virt; 798 while (start < end) { 799 pmap_kenter(va, start); 800 va += PAGE_SIZE; 801 start += PAGE_SIZE; 802 } 803 *virt = va; 804 return (sva); 805} 806 807/* 808 * Add a list of wired pages to the kva 809 * this routine is only used for temporary 810 * kernel mappings that do not need to have 811 * page modification or references recorded. 812 * Note that old mappings are simply written 813 * over. The page *must* be wired. 814 */ 815void 816pmap_qenter(vm_offset_t va, vm_page_t *m, int count) 817{ 818 int i; 819 vm_offset_t origva = va; 820 821 for (i = 0; i < count; i++) { 822 pmap_flush_pvcache(m[i]); 823 pmap_kenter(va, VM_PAGE_TO_PHYS(m[i])); 824 va += PAGE_SIZE; 825 } 826 827 mips_dcache_wbinv_range_index(origva, PAGE_SIZE*count); 828} 829 830/* 831 * this routine jerks page mappings from the 832 * kernel -- it is meant only for temporary mappings. 833 */ 834void 835pmap_qremove(vm_offset_t va, int count) 836{ 837 /* 838 * No need to wb/inv caches here, 839 * pmap_kremove will do it for us 840 */ 841 842 while (count-- > 0) { 843 pmap_kremove(va); 844 va += PAGE_SIZE; 845 } 846} 847 848/*************************************************** 849 * Page table page management routines..... 850 ***************************************************/ 851 852/* Revision 1.507 853 * 854 * Simplify the reference counting of page table pages. Specifically, use 855 * the page table page's wired count rather than its hold count to contain 856 * the reference count. 857 */ 858 859/* 860 * This routine unholds page table pages, and if the hold count 861 * drops to zero, then it decrements the wire count. 862 */ 863static int 864_pmap_unwire_pte_hold(pmap_t pmap, vm_page_t m) 865{ 866 vm_offset_t pteva; 867 868 /* 869 * unmap the page table page 870 */ 871 pteva = (vm_offset_t)pmap->pm_segtab[m->pindex]; 872 if (pteva >= VM_MIN_KERNEL_ADDRESS) { 873 pmap_kremove(pteva); 874 kmem_free(kernel_map, pteva, PAGE_SIZE); 875 } else { 876 KASSERT(MIPS_IS_KSEG0_ADDR(pteva), 877 ("_pmap_unwire_pte_hold: 0x%0lx is not in kseg0", 878 (long)pteva)); 879 } 880 881 pmap->pm_segtab[m->pindex] = 0; 882 --pmap->pm_stats.resident_count; 883 884 if (pmap->pm_ptphint == m) 885 pmap->pm_ptphint = NULL; 886 887 /* 888 * If the page is finally unwired, simply free it. 889 */ 890 vm_page_free_zero(m); 891 atomic_subtract_int(&cnt.v_wire_count, 1); 892 return (1); 893} 894 895static PMAP_INLINE int 896pmap_unwire_pte_hold(pmap_t pmap, vm_page_t m) 897{ 898 --m->wire_count; 899 if (m->wire_count == 0) 900 return (_pmap_unwire_pte_hold(pmap, m)); 901 else 902 return (0); 903} 904 905/* 906 * After removing a page table entry, this routine is used to 907 * conditionally free the page, and manage the hold/wire counts. 908 */ 909static int 910pmap_unuse_pt(pmap_t pmap, vm_offset_t va, vm_page_t mpte) 911{ 912 unsigned ptepindex; 913 pd_entry_t pteva; 914 915 if (va >= VM_MAXUSER_ADDRESS) 916 return (0); 917 918 if (mpte == NULL) { 919 ptepindex = (va >> SEGSHIFT); 920 if (pmap->pm_ptphint && 921 (pmap->pm_ptphint->pindex == ptepindex)) { 922 mpte = pmap->pm_ptphint; 923 } else { 924 pteva = *pmap_pde(pmap, va); 925 mpte = PHYS_TO_VM_PAGE(vtophys(pteva)); 926 pmap->pm_ptphint = mpte; 927 } 928 } 929 return pmap_unwire_pte_hold(pmap, mpte); 930} 931 932void 933pmap_pinit0(pmap_t pmap) 934{ 935 int i; 936 937 PMAP_LOCK_INIT(pmap); 938 pmap->pm_segtab = kernel_segmap; 939 pmap->pm_active = 0; 940 pmap->pm_ptphint = NULL; 941 for (i = 0; i < MAXCPU; i++) { 942 pmap->pm_asid[i].asid = PMAP_ASID_RESERVED; 943 pmap->pm_asid[i].gen = 0; 944 } 945 PCPU_SET(curpmap, pmap); 946 TAILQ_INIT(&pmap->pm_pvlist); 947 bzero(&pmap->pm_stats, sizeof pmap->pm_stats); 948} 949 950/* 951 * Initialize a preallocated and zeroed pmap structure, 952 * such as one in a vmspace structure. 953 */ 954int 955pmap_pinit(pmap_t pmap) 956{ 957 vm_offset_t ptdva; 958 vm_paddr_t ptdpa; 959 vm_page_t ptdpg; 960 int i; 961 int req; 962 963 PMAP_LOCK_INIT(pmap); 964 965 req = VM_ALLOC_NOOBJ | VM_ALLOC_NORMAL | VM_ALLOC_WIRED | 966 VM_ALLOC_ZERO; 967 968 /* 969 * allocate the page directory page 970 */ 971 while ((ptdpg = vm_page_alloc(NULL, NUSERPGTBLS, req)) == NULL) 972 VM_WAIT; 973 974 ptdpg->valid = VM_PAGE_BITS_ALL; 975 976 ptdpa = VM_PAGE_TO_PHYS(ptdpg); 977 if (ptdpa < MIPS_KSEG0_LARGEST_PHYS) { 978 ptdva = MIPS_PHYS_TO_KSEG0(ptdpa); 979 } else { 980 ptdva = kmem_alloc_nofault(kernel_map, PAGE_SIZE); 981 if (ptdva == 0) 982 panic("pmap_pinit: unable to allocate kva"); 983 pmap_kenter(ptdva, ptdpa); 984 } 985 986 pmap->pm_segtab = (pd_entry_t *)ptdva; 987 if ((ptdpg->flags & PG_ZERO) == 0) 988 bzero(pmap->pm_segtab, PAGE_SIZE); 989 990 pmap->pm_active = 0; 991 pmap->pm_ptphint = NULL; 992 for (i = 0; i < MAXCPU; i++) { 993 pmap->pm_asid[i].asid = PMAP_ASID_RESERVED; 994 pmap->pm_asid[i].gen = 0; 995 } 996 TAILQ_INIT(&pmap->pm_pvlist); 997 bzero(&pmap->pm_stats, sizeof pmap->pm_stats); 998 999 return (1); 1000} 1001 1002/* 1003 * this routine is called if the page table page is not 1004 * mapped correctly. 1005 */ 1006static vm_page_t 1007_pmap_allocpte(pmap_t pmap, unsigned ptepindex, int flags) 1008{ 1009 vm_offset_t pteva, ptepa; 1010 vm_page_t m; 1011 int req; 1012 1013 KASSERT((flags & (M_NOWAIT | M_WAITOK)) == M_NOWAIT || 1014 (flags & (M_NOWAIT | M_WAITOK)) == M_WAITOK, 1015 ("_pmap_allocpte: flags is neither M_NOWAIT nor M_WAITOK")); 1016 1017 req = VM_ALLOC_WIRED | VM_ALLOC_ZERO | VM_ALLOC_NOOBJ; 1018 /* 1019 * Find or fabricate a new pagetable page 1020 */ 1021 if ((m = vm_page_alloc(NULL, ptepindex, req)) == NULL) { 1022 if (flags & M_WAITOK) { 1023 PMAP_UNLOCK(pmap); 1024 vm_page_unlock_queues(); 1025 VM_WAIT; 1026 vm_page_lock_queues(); 1027 PMAP_LOCK(pmap); 1028 } 1029 /* 1030 * Indicate the need to retry. While waiting, the page 1031 * table page may have been allocated. 1032 */ 1033 return (NULL); 1034 } 1035 if ((m->flags & PG_ZERO) == 0) 1036 pmap_zero_page(m); 1037 1038 KASSERT(m->queue == PQ_NONE, 1039 ("_pmap_allocpte: %p->queue != PQ_NONE", m)); 1040 1041 /* 1042 * Map the pagetable page into the process address space, if it 1043 * isn't already there. 1044 */ 1045 1046 pmap->pm_stats.resident_count++; 1047 1048 ptepa = VM_PAGE_TO_PHYS(m); 1049 if (ptepa < MIPS_KSEG0_LARGEST_PHYS) { 1050 pteva = MIPS_PHYS_TO_KSEG0(ptepa); 1051 } else { 1052 pteva = kmem_alloc_nofault(kernel_map, PAGE_SIZE); 1053 if (pteva == 0) 1054 panic("_pmap_allocpte: unable to allocate kva"); 1055 pmap_kenter(pteva, ptepa); 1056 } 1057 1058 pmap->pm_segtab[ptepindex] = (pd_entry_t)pteva; 1059 1060 /* 1061 * Set the page table hint 1062 */ 1063 pmap->pm_ptphint = m; 1064 1065 /* 1066 * Kernel page tables are allocated in pmap_bootstrap() or 1067 * pmap_growkernel(). 1068 */ 1069 if (is_kernel_pmap(pmap)) 1070 panic("_pmap_allocpte() called for kernel pmap\n"); 1071 1072 m->valid = VM_PAGE_BITS_ALL; 1073 vm_page_flag_clear(m, PG_ZERO); 1074 1075 return (m); 1076} 1077 1078static vm_page_t 1079pmap_allocpte(pmap_t pmap, vm_offset_t va, int flags) 1080{ 1081 unsigned ptepindex; 1082 vm_offset_t pteva; 1083 vm_page_t m; 1084 1085 KASSERT((flags & (M_NOWAIT | M_WAITOK)) == M_NOWAIT || 1086 (flags & (M_NOWAIT | M_WAITOK)) == M_WAITOK, 1087 ("pmap_allocpte: flags is neither M_NOWAIT nor M_WAITOK")); 1088 1089 /* 1090 * Calculate pagetable page index 1091 */ 1092 ptepindex = va >> SEGSHIFT; 1093retry: 1094 /* 1095 * Get the page directory entry 1096 */ 1097 pteva = (vm_offset_t)pmap->pm_segtab[ptepindex]; 1098 1099 /* 1100 * If the page table page is mapped, we just increment the hold 1101 * count, and activate it. 1102 */ 1103 if (pteva) { 1104 /* 1105 * In order to get the page table page, try the hint first. 1106 */ 1107 if (pmap->pm_ptphint && 1108 (pmap->pm_ptphint->pindex == ptepindex)) { 1109 m = pmap->pm_ptphint; 1110 } else { 1111 m = PHYS_TO_VM_PAGE(vtophys(pteva)); 1112 pmap->pm_ptphint = m; 1113 } 1114 m->wire_count++; 1115 } else { 1116 /* 1117 * Here if the pte page isn't mapped, or if it has been 1118 * deallocated. 1119 */ 1120 m = _pmap_allocpte(pmap, ptepindex, flags); 1121 if (m == NULL && (flags & M_WAITOK)) 1122 goto retry; 1123 } 1124 return m; 1125} 1126 1127 1128/*************************************************** 1129* Pmap allocation/deallocation routines. 1130 ***************************************************/ 1131/* 1132 * Revision 1.397 1133 * - Merged pmap_release and pmap_release_free_page. When pmap_release is 1134 * called only the page directory page(s) can be left in the pmap pte 1135 * object, since all page table pages will have been freed by 1136 * pmap_remove_pages and pmap_remove. In addition, there can only be one 1137 * reference to the pmap and the page directory is wired, so the page(s) 1138 * can never be busy. So all there is to do is clear the magic mappings 1139 * from the page directory and free the page(s). 1140 */ 1141 1142 1143/* 1144 * Release any resources held by the given physical map. 1145 * Called when a pmap initialized by pmap_pinit is being released. 1146 * Should only be called if the map contains no valid mappings. 1147 */ 1148void 1149pmap_release(pmap_t pmap) 1150{ 1151 vm_offset_t ptdva; 1152 vm_page_t ptdpg; 1153 1154 KASSERT(pmap->pm_stats.resident_count == 0, 1155 ("pmap_release: pmap resident count %ld != 0", 1156 pmap->pm_stats.resident_count)); 1157 1158 ptdva = (vm_offset_t)pmap->pm_segtab; 1159 ptdpg = PHYS_TO_VM_PAGE(vtophys(ptdva)); 1160 1161 if (ptdva >= VM_MIN_KERNEL_ADDRESS) { 1162 pmap_kremove(ptdva); 1163 kmem_free(kernel_map, ptdva, PAGE_SIZE); 1164 } else { 1165 KASSERT(MIPS_IS_KSEG0_ADDR(ptdva), 1166 ("pmap_release: 0x%0lx is not in kseg0", (long)ptdva)); 1167 } 1168 1169 ptdpg->wire_count--; 1170 atomic_subtract_int(&cnt.v_wire_count, 1); 1171 vm_page_free_zero(ptdpg); 1172 PMAP_LOCK_DESTROY(pmap); 1173} 1174 1175/* 1176 * grow the number of kernel page table entries, if needed 1177 */ 1178void 1179pmap_growkernel(vm_offset_t addr) 1180{ 1181 vm_offset_t ptppaddr; 1182 vm_page_t nkpg; 1183 pt_entry_t *pte; 1184 int i, req; 1185 1186 mtx_assert(&kernel_map->system_mtx, MA_OWNED); 1187 if (kernel_vm_end == 0) { 1188 kernel_vm_end = VM_MIN_KERNEL_ADDRESS; 1189 nkpt = 0; 1190 while (segtab_pde(kernel_segmap, kernel_vm_end)) { 1191 kernel_vm_end = (kernel_vm_end + PAGE_SIZE * NPTEPG) & 1192 ~(PAGE_SIZE * NPTEPG - 1); 1193 nkpt++; 1194 if (kernel_vm_end - 1 >= kernel_map->max_offset) { 1195 kernel_vm_end = kernel_map->max_offset; 1196 break; 1197 } 1198 } 1199 } 1200 addr = (addr + PAGE_SIZE * NPTEPG) & ~(PAGE_SIZE * NPTEPG - 1); 1201 if (addr - 1 >= kernel_map->max_offset) 1202 addr = kernel_map->max_offset; 1203 while (kernel_vm_end < addr) { 1204 if (segtab_pde(kernel_segmap, kernel_vm_end)) { 1205 kernel_vm_end = (kernel_vm_end + PAGE_SIZE * NPTEPG) & 1206 ~(PAGE_SIZE * NPTEPG - 1); 1207 if (kernel_vm_end - 1 >= kernel_map->max_offset) { 1208 kernel_vm_end = kernel_map->max_offset; 1209 break; 1210 } 1211 continue; 1212 } 1213 /* 1214 * This index is bogus, but out of the way 1215 */ 1216 req = VM_ALLOC_INTERRUPT | VM_ALLOC_WIRED | VM_ALLOC_NOOBJ; 1217 nkpg = vm_page_alloc(NULL, nkpt, req); 1218 if (!nkpg) 1219 panic("pmap_growkernel: no memory to grow kernel"); 1220 1221 nkpt++; 1222 1223 ptppaddr = VM_PAGE_TO_PHYS(nkpg); 1224 if (ptppaddr >= MIPS_KSEG0_LARGEST_PHYS) { 1225 /* 1226 * We need to do something here, but I am not sure 1227 * what. We can access anything in the 0 - 512Meg 1228 * region, but if we get a page to go in the kernel 1229 * segmap that is outside of of that we really need 1230 * to have another mapping beyond the temporary ones 1231 * I have. Not sure how to do this yet. FIXME FIXME. 1232 */ 1233 panic("Gak, can't handle a k-page table outside of lower 512Meg"); 1234 } 1235 pte = (pt_entry_t *)MIPS_PHYS_TO_KSEG0(ptppaddr); 1236 segtab_pde(kernel_segmap, kernel_vm_end) = (pd_entry_t)pte; 1237 1238 /* 1239 * The R[4-7]?00 stores only one copy of the Global bit in 1240 * the translation lookaside buffer for each 2 page entry. 1241 * Thus invalid entrys must have the Global bit set so when 1242 * Entry LO and Entry HI G bits are anded together they will 1243 * produce a global bit to store in the tlb. 1244 */ 1245 for (i = 0; i < NPTEPG; i++, pte++) 1246 *pte = PTE_G; 1247 1248 kernel_vm_end = (kernel_vm_end + PAGE_SIZE * NPTEPG) & 1249 ~(PAGE_SIZE * NPTEPG - 1); 1250 if (kernel_vm_end - 1 >= kernel_map->max_offset) { 1251 kernel_vm_end = kernel_map->max_offset; 1252 break; 1253 } 1254 } 1255} 1256 1257/*************************************************** 1258* page management routines. 1259 ***************************************************/ 1260 1261/* 1262 * free the pv_entry back to the free list 1263 */ 1264static PMAP_INLINE void 1265free_pv_entry(pv_entry_t pv) 1266{ 1267 1268 pv_entry_count--; 1269 uma_zfree(pvzone, pv); 1270} 1271 1272/* 1273 * get a new pv_entry, allocating a block from the system 1274 * when needed. 1275 * the memory allocation is performed bypassing the malloc code 1276 * because of the possibility of allocations at interrupt time. 1277 */ 1278static pv_entry_t 1279get_pv_entry(pmap_t locked_pmap) 1280{ 1281 static const struct timeval printinterval = { 60, 0 }; 1282 static struct timeval lastprint; 1283 struct vpgqueues *vpq; 1284 pt_entry_t *pte, oldpte; 1285 pmap_t pmap; 1286 pv_entry_t allocated_pv, next_pv, pv; 1287 vm_offset_t va; 1288 vm_page_t m; 1289 1290 PMAP_LOCK_ASSERT(locked_pmap, MA_OWNED); 1291 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1292 allocated_pv = uma_zalloc(pvzone, M_NOWAIT); 1293 if (allocated_pv != NULL) { 1294 pv_entry_count++; 1295 if (pv_entry_count > pv_entry_high_water) 1296 pagedaemon_wakeup(); 1297 else 1298 return (allocated_pv); 1299 } 1300 /* 1301 * Reclaim pv entries: At first, destroy mappings to inactive 1302 * pages. After that, if a pv entry is still needed, destroy 1303 * mappings to active pages. 1304 */ 1305 if (ratecheck(&lastprint, &printinterval)) 1306 printf("Approaching the limit on PV entries, " 1307 "increase the vm.pmap.shpgperproc tunable.\n"); 1308 vpq = &vm_page_queues[PQ_INACTIVE]; 1309retry: 1310 TAILQ_FOREACH(m, &vpq->pl, pageq) { 1311 if (m->hold_count || m->busy) 1312 continue; 1313 TAILQ_FOREACH_SAFE(pv, &m->md.pv_list, pv_list, next_pv) { 1314 va = pv->pv_va; 1315 pmap = pv->pv_pmap; 1316 /* Avoid deadlock and lock recursion. */ 1317 if (pmap > locked_pmap) 1318 PMAP_LOCK(pmap); 1319 else if (pmap != locked_pmap && !PMAP_TRYLOCK(pmap)) 1320 continue; 1321 pmap->pm_stats.resident_count--; 1322 pte = pmap_pte(pmap, va); 1323 KASSERT(pte != NULL, ("pte")); 1324 oldpte = loadandclear((u_int *)pte); 1325 if (is_kernel_pmap(pmap)) 1326 *pte = PTE_G; 1327 KASSERT((oldpte & PTE_W) == 0, 1328 ("wired pte for unwired page")); 1329 if (m->md.pv_flags & PV_TABLE_REF) 1330 vm_page_flag_set(m, PG_REFERENCED); 1331 if (oldpte & PTE_M) 1332 vm_page_dirty(m); 1333 pmap_invalidate_page(pmap, va); 1334 TAILQ_REMOVE(&pmap->pm_pvlist, pv, pv_plist); 1335 m->md.pv_list_count--; 1336 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list); 1337 if (TAILQ_EMPTY(&m->md.pv_list)) { 1338 vm_page_flag_clear(m, PG_WRITEABLE); 1339 m->md.pv_flags &= ~(PV_TABLE_REF | PV_TABLE_MOD); 1340 } 1341 pmap_unuse_pt(pmap, va, pv->pv_ptem); 1342 if (pmap != locked_pmap) 1343 PMAP_UNLOCK(pmap); 1344 if (allocated_pv == NULL) 1345 allocated_pv = pv; 1346 else 1347 free_pv_entry(pv); 1348 } 1349 } 1350 if (allocated_pv == NULL) { 1351 if (vpq == &vm_page_queues[PQ_INACTIVE]) { 1352 vpq = &vm_page_queues[PQ_ACTIVE]; 1353 goto retry; 1354 } 1355 panic("get_pv_entry: increase the vm.pmap.shpgperproc tunable"); 1356 } 1357 return (allocated_pv); 1358} 1359 1360/* 1361 * Revision 1.370 1362 * 1363 * Move pmap_collect() out of the machine-dependent code, rename it 1364 * to reflect its new location, and add page queue and flag locking. 1365 * 1366 * Notes: (1) alpha, i386, and ia64 had identical implementations 1367 * of pmap_collect() in terms of machine-independent interfaces; 1368 * (2) sparc64 doesn't require it; (3) powerpc had it as a TODO. 1369 * 1370 * MIPS implementation was identical to alpha [Junos 8.2] 1371 */ 1372 1373/* 1374 * If it is the first entry on the list, it is actually 1375 * in the header and we must copy the following entry up 1376 * to the header. Otherwise we must search the list for 1377 * the entry. In either case we free the now unused entry. 1378 */ 1379 1380static void 1381pmap_remove_entry(struct pmap *pmap, vm_page_t m, vm_offset_t va) 1382{ 1383 pv_entry_t pv; 1384 1385 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1386 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1387 if (m->md.pv_list_count < pmap->pm_stats.resident_count) { 1388 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 1389 if (pmap == pv->pv_pmap && va == pv->pv_va) 1390 break; 1391 } 1392 } else { 1393 TAILQ_FOREACH(pv, &pmap->pm_pvlist, pv_plist) { 1394 if (va == pv->pv_va) 1395 break; 1396 } 1397 } 1398 1399 KASSERT(pv != NULL, ("pmap_remove_entry: pv not found")); 1400 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list); 1401 m->md.pv_list_count--; 1402 if (TAILQ_FIRST(&m->md.pv_list) == NULL) 1403 vm_page_flag_clear(m, PG_WRITEABLE); 1404 1405 TAILQ_REMOVE(&pmap->pm_pvlist, pv, pv_plist); 1406 free_pv_entry(pv); 1407} 1408 1409/* 1410 * Create a pv entry for page at pa for 1411 * (pmap, va). 1412 */ 1413static void 1414pmap_insert_entry(pmap_t pmap, vm_offset_t va, vm_page_t mpte, vm_page_t m, 1415 boolean_t wired) 1416{ 1417 pv_entry_t pv; 1418 1419 pv = get_pv_entry(pmap); 1420 pv->pv_va = va; 1421 pv->pv_pmap = pmap; 1422 pv->pv_ptem = mpte; 1423 pv->pv_wired = wired; 1424 1425 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1426 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1427 TAILQ_INSERT_TAIL(&pmap->pm_pvlist, pv, pv_plist); 1428 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_list); 1429 m->md.pv_list_count++; 1430} 1431 1432/* 1433 * Conditionally create a pv entry. 1434 */ 1435static boolean_t 1436pmap_try_insert_pv_entry(pmap_t pmap, vm_page_t mpte, vm_offset_t va, 1437 vm_page_t m) 1438{ 1439 pv_entry_t pv; 1440 1441 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1442 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1443 if (pv_entry_count < pv_entry_high_water && 1444 (pv = uma_zalloc(pvzone, M_NOWAIT)) != NULL) { 1445 pv_entry_count++; 1446 pv->pv_va = va; 1447 pv->pv_pmap = pmap; 1448 pv->pv_ptem = mpte; 1449 pv->pv_wired = FALSE; 1450 TAILQ_INSERT_TAIL(&pmap->pm_pvlist, pv, pv_plist); 1451 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_list); 1452 m->md.pv_list_count++; 1453 return (TRUE); 1454 } else 1455 return (FALSE); 1456} 1457 1458/* 1459 * pmap_remove_pte: do the things to unmap a page in a process 1460 */ 1461static int 1462pmap_remove_pte(struct pmap *pmap, pt_entry_t *ptq, vm_offset_t va) 1463{ 1464 pt_entry_t oldpte; 1465 vm_page_t m; 1466 vm_offset_t pa; 1467 1468 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1469 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1470 1471 oldpte = loadandclear((u_int *)ptq); 1472 if (is_kernel_pmap(pmap)) 1473 *ptq = PTE_G; 1474 1475 if (oldpte & PTE_W) 1476 pmap->pm_stats.wired_count -= 1; 1477 1478 pmap->pm_stats.resident_count -= 1; 1479 pa = mips_tlbpfn_to_paddr(oldpte); 1480 1481 if (page_is_managed(pa)) { 1482 m = PHYS_TO_VM_PAGE(pa); 1483 if (oldpte & PTE_M) { 1484#if defined(PMAP_DIAGNOSTIC) 1485 if (pmap_nw_modified(oldpte)) { 1486 printf( 1487 "pmap_remove: modified page not writable: va: 0x%x, pte: 0x%x\n", 1488 va, oldpte); 1489 } 1490#endif 1491 vm_page_dirty(m); 1492 } 1493 if (m->md.pv_flags & PV_TABLE_REF) 1494 vm_page_flag_set(m, PG_REFERENCED); 1495 m->md.pv_flags &= ~(PV_TABLE_REF | PV_TABLE_MOD); 1496 1497 pmap_remove_entry(pmap, m, va); 1498 } 1499 return pmap_unuse_pt(pmap, va, NULL); 1500} 1501 1502/* 1503 * Remove a single page from a process address space 1504 */ 1505static void 1506pmap_remove_page(struct pmap *pmap, vm_offset_t va) 1507{ 1508 register pt_entry_t *ptq; 1509 1510 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1511 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1512 ptq = pmap_pte(pmap, va); 1513 1514 /* 1515 * if there is no pte for this address, just skip it!!! 1516 */ 1517 if (!ptq || !pmap_pte_v(ptq)) { 1518 return; 1519 } 1520 1521 /* 1522 * Write back all caches from the page being destroyed 1523 */ 1524 mips_dcache_wbinv_range_index(va, PAGE_SIZE); 1525 1526 /* 1527 * get a local va for mappings for this pmap. 1528 */ 1529 (void)pmap_remove_pte(pmap, ptq, va); 1530 pmap_invalidate_page(pmap, va); 1531 1532 return; 1533} 1534 1535/* 1536 * Remove the given range of addresses from the specified map. 1537 * 1538 * It is assumed that the start and end are properly 1539 * rounded to the page size. 1540 */ 1541void 1542pmap_remove(struct pmap *pmap, vm_offset_t sva, vm_offset_t eva) 1543{ 1544 vm_offset_t va, nva; 1545 1546 if (pmap == NULL) 1547 return; 1548 1549 if (pmap->pm_stats.resident_count == 0) 1550 return; 1551 1552 vm_page_lock_queues(); 1553 PMAP_LOCK(pmap); 1554 1555 /* 1556 * special handling of removing one page. a very common operation 1557 * and easy to short circuit some code. 1558 */ 1559 if ((sva + PAGE_SIZE) == eva) { 1560 pmap_remove_page(pmap, sva); 1561 goto out; 1562 } 1563 for (va = sva; va < eva; va = nva) { 1564 if (!*pmap_pde(pmap, va)) { 1565 nva = mips_segtrunc(va + MIPS_SEGSIZE); 1566 continue; 1567 } 1568 pmap_remove_page(pmap, va); 1569 nva = va + PAGE_SIZE; 1570 } 1571 1572out: 1573 vm_page_unlock_queues(); 1574 PMAP_UNLOCK(pmap); 1575} 1576 1577/* 1578 * Routine: pmap_remove_all 1579 * Function: 1580 * Removes this physical page from 1581 * all physical maps in which it resides. 1582 * Reflects back modify bits to the pager. 1583 * 1584 * Notes: 1585 * Original versions of this routine were very 1586 * inefficient because they iteratively called 1587 * pmap_remove (slow...) 1588 */ 1589 1590void 1591pmap_remove_all(vm_page_t m) 1592{ 1593 register pv_entry_t pv; 1594 register pt_entry_t *pte, tpte; 1595 1596 KASSERT((m->flags & PG_FICTITIOUS) == 0, 1597 ("pmap_remove_all: page %p is fictitious", m)); 1598 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1599 1600 if (m->md.pv_flags & PV_TABLE_REF) 1601 vm_page_flag_set(m, PG_REFERENCED); 1602 1603 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) { 1604 PMAP_LOCK(pv->pv_pmap); 1605 1606 /* 1607 * If it's last mapping writeback all caches from 1608 * the page being destroyed 1609 */ 1610 if (m->md.pv_list_count == 1) 1611 mips_dcache_wbinv_range_index(pv->pv_va, PAGE_SIZE); 1612 1613 pv->pv_pmap->pm_stats.resident_count--; 1614 1615 pte = pmap_pte(pv->pv_pmap, pv->pv_va); 1616 1617 tpte = loadandclear((u_int *)pte); 1618 if (is_kernel_pmap(pv->pv_pmap)) 1619 *pte = PTE_G; 1620 1621 if (tpte & PTE_W) 1622 pv->pv_pmap->pm_stats.wired_count--; 1623 1624 /* 1625 * Update the vm_page_t clean and reference bits. 1626 */ 1627 if (tpte & PTE_M) { 1628#if defined(PMAP_DIAGNOSTIC) 1629 if (pmap_nw_modified(tpte)) { 1630 printf( 1631 "pmap_remove_all: modified page not writable: va: 0x%x, pte: 0x%x\n", 1632 pv->pv_va, tpte); 1633 } 1634#endif 1635 vm_page_dirty(m); 1636 } 1637 pmap_invalidate_page(pv->pv_pmap, pv->pv_va); 1638 1639 TAILQ_REMOVE(&pv->pv_pmap->pm_pvlist, pv, pv_plist); 1640 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list); 1641 m->md.pv_list_count--; 1642 pmap_unuse_pt(pv->pv_pmap, pv->pv_va, pv->pv_ptem); 1643 PMAP_UNLOCK(pv->pv_pmap); 1644 free_pv_entry(pv); 1645 } 1646 1647 vm_page_flag_clear(m, PG_WRITEABLE); 1648 m->md.pv_flags &= ~(PV_TABLE_REF | PV_TABLE_MOD); 1649} 1650 1651/* 1652 * Set the physical protection on the 1653 * specified range of this map as requested. 1654 */ 1655void 1656pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot) 1657{ 1658 pt_entry_t *pte; 1659 1660 if (pmap == NULL) 1661 return; 1662 1663 if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 1664 pmap_remove(pmap, sva, eva); 1665 return; 1666 } 1667 if (prot & VM_PROT_WRITE) 1668 return; 1669 1670 vm_page_lock_queues(); 1671 PMAP_LOCK(pmap); 1672 while (sva < eva) { 1673 pt_entry_t pbits, obits; 1674 vm_page_t m; 1675 vm_offset_t pa; 1676 1677 /* 1678 * If segment table entry is empty, skip this segment. 1679 */ 1680 if (!*pmap_pde(pmap, sva)) { 1681 sva = mips_segtrunc(sva + MIPS_SEGSIZE); 1682 continue; 1683 } 1684 /* 1685 * If pte is invalid, skip this page 1686 */ 1687 pte = pmap_pte(pmap, sva); 1688 if (!pmap_pte_v(pte)) { 1689 sva += PAGE_SIZE; 1690 continue; 1691 } 1692retry: 1693 obits = pbits = *pte; 1694 pa = mips_tlbpfn_to_paddr(pbits); 1695 1696 if (page_is_managed(pa) && (pbits & PTE_M) != 0) { 1697 m = PHYS_TO_VM_PAGE(pa); 1698 vm_page_dirty(m); 1699 m->md.pv_flags &= ~PV_TABLE_MOD; 1700 } 1701 pbits = (pbits & ~PTE_M) | PTE_RO; 1702 1703 if (pbits != *pte) { 1704 if (!atomic_cmpset_int((u_int *)pte, obits, pbits)) 1705 goto retry; 1706 pmap_update_page(pmap, sva, pbits); 1707 } 1708 sva += PAGE_SIZE; 1709 } 1710 vm_page_unlock_queues(); 1711 PMAP_UNLOCK(pmap); 1712} 1713 1714/* 1715 * Insert the given physical page (p) at 1716 * the specified virtual address (v) in the 1717 * target physical map with the protection requested. 1718 * 1719 * If specified, the page will be wired down, meaning 1720 * that the related pte can not be reclaimed. 1721 * 1722 * NB: This is the only routine which MAY NOT lazy-evaluate 1723 * or lose information. That is, this routine must actually 1724 * insert this page into the given map NOW. 1725 */ 1726void 1727pmap_enter(pmap_t pmap, vm_offset_t va, vm_prot_t access, vm_page_t m, 1728 vm_prot_t prot, boolean_t wired) 1729{ 1730 vm_offset_t pa, opa; 1731 register pt_entry_t *pte; 1732 pt_entry_t origpte, newpte; 1733 vm_page_t mpte, om; 1734 int rw = 0; 1735 1736 if (pmap == NULL) 1737 return; 1738 1739 va &= ~PAGE_MASK; 1740#ifdef PMAP_DIAGNOSTIC 1741 if (va > VM_MAX_KERNEL_ADDRESS) 1742 panic("pmap_enter: toobig"); 1743#endif 1744 1745 mpte = NULL; 1746 1747 vm_page_lock_queues(); 1748 PMAP_LOCK(pmap); 1749 1750 /* 1751 * In the case that a page table page is not resident, we are 1752 * creating it here. 1753 */ 1754 if (va < VM_MAXUSER_ADDRESS) { 1755 mpte = pmap_allocpte(pmap, va, M_WAITOK); 1756 } 1757 pte = pmap_pte(pmap, va); 1758 1759 /* 1760 * Page Directory table entry not valid, we need a new PT page 1761 */ 1762 if (pte == NULL) { 1763 panic("pmap_enter: invalid page directory, pdir=%p, va=%p\n", 1764 (void *)pmap->pm_segtab, (void *)va); 1765 } 1766 pa = VM_PAGE_TO_PHYS(m); 1767 om = NULL; 1768 origpte = *pte; 1769 opa = mips_tlbpfn_to_paddr(origpte); 1770 1771 /* 1772 * Mapping has not changed, must be protection or wiring change. 1773 */ 1774 if ((origpte & PTE_V) && (opa == pa)) { 1775 /* 1776 * Wiring change, just update stats. We don't worry about 1777 * wiring PT pages as they remain resident as long as there 1778 * are valid mappings in them. Hence, if a user page is 1779 * wired, the PT page will be also. 1780 */ 1781 if (wired && ((origpte & PTE_W) == 0)) 1782 pmap->pm_stats.wired_count++; 1783 else if (!wired && (origpte & PTE_W)) 1784 pmap->pm_stats.wired_count--; 1785 1786#if defined(PMAP_DIAGNOSTIC) 1787 if (pmap_nw_modified(origpte)) { 1788 printf( 1789 "pmap_enter: modified page not writable: va: 0x%x, pte: 0x%x\n", 1790 va, origpte); 1791 } 1792#endif 1793 1794 /* 1795 * Remove extra pte reference 1796 */ 1797 if (mpte) 1798 mpte->wire_count--; 1799 1800 /* 1801 * We might be turning off write access to the page, so we 1802 * go ahead and sense modify status. 1803 */ 1804 if (page_is_managed(opa)) { 1805 om = m; 1806 } 1807 goto validate; 1808 } 1809 /* 1810 * Mapping has changed, invalidate old range and fall through to 1811 * handle validating new mapping. 1812 */ 1813 if (opa) { 1814 if (origpte & PTE_W) 1815 pmap->pm_stats.wired_count--; 1816 1817 if (page_is_managed(opa)) { 1818 om = PHYS_TO_VM_PAGE(opa); 1819 pmap_remove_entry(pmap, om, va); 1820 } 1821 if (mpte != NULL) { 1822 mpte->wire_count--; 1823 KASSERT(mpte->wire_count > 0, 1824 ("pmap_enter: missing reference to page table page," 1825 " va: %p", (void *)va)); 1826 } 1827 } else 1828 pmap->pm_stats.resident_count++; 1829 1830 /* 1831 * Enter on the PV list if part of our managed memory. Note that we 1832 * raise IPL while manipulating pv_table since pmap_enter can be 1833 * called at interrupt time. 1834 */ 1835 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0) { 1836 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva, 1837 ("pmap_enter: managed mapping within the clean submap")); 1838 pmap_insert_entry(pmap, va, mpte, m, wired); 1839 } 1840 /* 1841 * Increment counters 1842 */ 1843 if (wired) 1844 pmap->pm_stats.wired_count++; 1845 1846validate: 1847 if ((access & VM_PROT_WRITE) != 0) 1848 m->md.pv_flags |= PV_TABLE_MOD | PV_TABLE_REF; 1849 rw = init_pte_prot(va, m, prot); 1850 1851#ifdef PMAP_DEBUG 1852 printf("pmap_enter: va: 0x%08x -> pa: 0x%08x\n", va, pa); 1853#endif 1854 /* 1855 * Now validate mapping with desired protection/wiring. 1856 */ 1857 newpte = mips_paddr_to_tlbpfn(pa) | rw | PTE_V; 1858 1859 if (is_cacheable_mem(pa)) 1860 newpte |= PTE_CACHE; 1861 else 1862 newpte |= PTE_UNCACHED; 1863 1864 if (wired) 1865 newpte |= PTE_W; 1866 1867 if (is_kernel_pmap(pmap)) { 1868 newpte |= PTE_G; 1869 } 1870 1871 /* 1872 * if the mapping or permission bits are different, we need to 1873 * update the pte. 1874 */ 1875 if (origpte != newpte) { 1876 if (origpte & PTE_V) { 1877 *pte = newpte; 1878 if (page_is_managed(opa) && (opa != pa)) { 1879 if (om->md.pv_flags & PV_TABLE_REF) 1880 vm_page_flag_set(om, PG_REFERENCED); 1881 om->md.pv_flags &= 1882 ~(PV_TABLE_REF | PV_TABLE_MOD); 1883 } 1884 if (origpte & PTE_M) { 1885 KASSERT((origpte & PTE_RW), 1886 ("pmap_enter: modified page not writable:" 1887 " va: %p, pte: 0x%x", (void *)va, origpte)); 1888 if (page_is_managed(opa)) 1889 vm_page_dirty(om); 1890 } 1891 } else { 1892 *pte = newpte; 1893 } 1894 } 1895 pmap_update_page(pmap, va, newpte); 1896 1897 /* 1898 * Sync I & D caches for executable pages. Do this only if the the 1899 * target pmap belongs to the current process. Otherwise, an 1900 * unresolvable TLB miss may occur. 1901 */ 1902 if (!is_kernel_pmap(pmap) && (pmap == &curproc->p_vmspace->vm_pmap) && 1903 (prot & VM_PROT_EXECUTE)) { 1904 mips_icache_sync_range(va, PAGE_SIZE); 1905 mips_dcache_wbinv_range(va, PAGE_SIZE); 1906 } 1907 vm_page_unlock_queues(); 1908 PMAP_UNLOCK(pmap); 1909} 1910 1911/* 1912 * this code makes some *MAJOR* assumptions: 1913 * 1. Current pmap & pmap exists. 1914 * 2. Not wired. 1915 * 3. Read access. 1916 * 4. No page table pages. 1917 * but is *MUCH* faster than pmap_enter... 1918 */ 1919 1920void 1921pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot) 1922{ 1923 1924 PMAP_LOCK(pmap); 1925 (void)pmap_enter_quick_locked(pmap, va, m, prot, NULL); 1926 PMAP_UNLOCK(pmap); 1927} 1928 1929static vm_page_t 1930pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m, 1931 vm_prot_t prot, vm_page_t mpte) 1932{ 1933 pt_entry_t *pte; 1934 vm_offset_t pa; 1935 1936 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva || 1937 (m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0, 1938 ("pmap_enter_quick_locked: managed mapping within the clean submap")); 1939 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1940 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1941 1942 /* 1943 * In the case that a page table page is not resident, we are 1944 * creating it here. 1945 */ 1946 if (va < VM_MAXUSER_ADDRESS) { 1947 unsigned ptepindex; 1948 vm_offset_t pteva; 1949 1950 /* 1951 * Calculate pagetable page index 1952 */ 1953 ptepindex = va >> SEGSHIFT; 1954 if (mpte && (mpte->pindex == ptepindex)) { 1955 mpte->wire_count++; 1956 } else { 1957 /* 1958 * Get the page directory entry 1959 */ 1960 pteva = (vm_offset_t)pmap->pm_segtab[ptepindex]; 1961 1962 /* 1963 * If the page table page is mapped, we just 1964 * increment the hold count, and activate it. 1965 */ 1966 if (pteva) { 1967 if (pmap->pm_ptphint && 1968 (pmap->pm_ptphint->pindex == ptepindex)) { 1969 mpte = pmap->pm_ptphint; 1970 } else { 1971 mpte = PHYS_TO_VM_PAGE(vtophys(pteva)); 1972 pmap->pm_ptphint = mpte; 1973 } 1974 mpte->wire_count++; 1975 } else { 1976 mpte = _pmap_allocpte(pmap, ptepindex, 1977 M_NOWAIT); 1978 if (mpte == NULL) 1979 return (mpte); 1980 } 1981 } 1982 } else { 1983 mpte = NULL; 1984 } 1985 1986 pte = pmap_pte(pmap, va); 1987 if (pmap_pte_v(pte)) { 1988 if (mpte != NULL) { 1989 mpte->wire_count--; 1990 mpte = NULL; 1991 } 1992 return (mpte); 1993 } 1994 1995 /* 1996 * Enter on the PV list if part of our managed memory. 1997 */ 1998 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0 && 1999 !pmap_try_insert_pv_entry(pmap, mpte, va, m)) { 2000 if (mpte != NULL) { 2001 pmap_unwire_pte_hold(pmap, mpte); 2002 mpte = NULL; 2003 } 2004 return (mpte); 2005 } 2006 2007 /* 2008 * Increment counters 2009 */ 2010 pmap->pm_stats.resident_count++; 2011 2012 pa = VM_PAGE_TO_PHYS(m); 2013 2014 /* 2015 * Now validate mapping with RO protection 2016 */ 2017 *pte = mips_paddr_to_tlbpfn(pa) | PTE_V; 2018 2019 if (is_cacheable_mem(pa)) 2020 *pte |= PTE_CACHE; 2021 else 2022 *pte |= PTE_UNCACHED; 2023 2024 if (is_kernel_pmap(pmap)) 2025 *pte |= PTE_G; 2026 else { 2027 *pte |= PTE_RO; 2028 /* 2029 * Sync I & D caches. Do this only if the the target pmap 2030 * belongs to the current process. Otherwise, an 2031 * unresolvable TLB miss may occur. */ 2032 if (pmap == &curproc->p_vmspace->vm_pmap) { 2033 va &= ~PAGE_MASK; 2034 mips_icache_sync_range(va, PAGE_SIZE); 2035 mips_dcache_wbinv_range(va, PAGE_SIZE); 2036 } 2037 } 2038 return (mpte); 2039} 2040 2041/* 2042 * Make a temporary mapping for a physical address. This is only intended 2043 * to be used for panic dumps. 2044 */ 2045void * 2046pmap_kenter_temporary(vm_paddr_t pa, int i) 2047{ 2048 vm_offset_t va; 2049 register_t intr; 2050 if (i != 0) 2051 printf("%s: ERROR!!! More than one page of virtual address mapping not supported\n", 2052 __func__); 2053 2054 if (pa < MIPS_KSEG0_LARGEST_PHYS) { 2055 va = MIPS_PHYS_TO_KSEG0(pa); 2056 } else { 2057 int cpu; 2058 struct local_sysmaps *sysm; 2059 pt_entry_t *pte, npte; 2060 2061 /* If this is used other than for dumps, we may need to leave 2062 * interrupts disasbled on return. If crash dumps don't work when 2063 * we get to this point, we might want to consider this (leaving things 2064 * disabled as a starting point ;-) 2065 */ 2066 intr = intr_disable(); 2067 cpu = PCPU_GET(cpuid); 2068 sysm = &sysmap_lmem[cpu]; 2069 /* Since this is for the debugger, no locks or any other fun */ 2070 npte = mips_paddr_to_tlbpfn(pa) | PTE_RW | PTE_V | PTE_G | PTE_W | PTE_CACHE; 2071 pte = pmap_pte(kernel_pmap, sysm->base); 2072 *pte = npte; 2073 sysm->valid1 = 1; 2074 pmap_update_page(kernel_pmap, sysm->base, npte); 2075 va = sysm->base; 2076 intr_restore(intr); 2077 } 2078 return ((void *)va); 2079} 2080 2081void 2082pmap_kenter_temporary_free(vm_paddr_t pa) 2083{ 2084 int cpu; 2085 register_t intr; 2086 struct local_sysmaps *sysm; 2087 2088 if (pa < MIPS_KSEG0_LARGEST_PHYS) { 2089 /* nothing to do for this case */ 2090 return; 2091 } 2092 cpu = PCPU_GET(cpuid); 2093 sysm = &sysmap_lmem[cpu]; 2094 if (sysm->valid1) { 2095 pt_entry_t *pte; 2096 2097 intr = intr_disable(); 2098 pte = pmap_pte(kernel_pmap, sysm->base); 2099 *pte = PTE_G; 2100 pmap_invalidate_page(kernel_pmap, sysm->base); 2101 intr_restore(intr); 2102 sysm->valid1 = 0; 2103 } 2104} 2105 2106/* 2107 * Moved the code to Machine Independent 2108 * vm_map_pmap_enter() 2109 */ 2110 2111/* 2112 * Maps a sequence of resident pages belonging to the same object. 2113 * The sequence begins with the given page m_start. This page is 2114 * mapped at the given virtual address start. Each subsequent page is 2115 * mapped at a virtual address that is offset from start by the same 2116 * amount as the page is offset from m_start within the object. The 2117 * last page in the sequence is the page with the largest offset from 2118 * m_start that can be mapped at a virtual address less than the given 2119 * virtual address end. Not every virtual page between start and end 2120 * is mapped; only those for which a resident page exists with the 2121 * corresponding offset from m_start are mapped. 2122 */ 2123void 2124pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end, 2125 vm_page_t m_start, vm_prot_t prot) 2126{ 2127 vm_page_t m, mpte; 2128 vm_pindex_t diff, psize; 2129 2130 VM_OBJECT_LOCK_ASSERT(m_start->object, MA_OWNED); 2131 psize = atop(end - start); 2132 mpte = NULL; 2133 m = m_start; 2134 PMAP_LOCK(pmap); 2135 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 2136 mpte = pmap_enter_quick_locked(pmap, start + ptoa(diff), m, 2137 prot, mpte); 2138 m = TAILQ_NEXT(m, listq); 2139 } 2140 PMAP_UNLOCK(pmap); 2141} 2142 2143/* 2144 * pmap_object_init_pt preloads the ptes for a given object 2145 * into the specified pmap. This eliminates the blast of soft 2146 * faults on process startup and immediately after an mmap. 2147 */ 2148void 2149pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, 2150 vm_object_t object, vm_pindex_t pindex, vm_size_t size) 2151{ 2152 VM_OBJECT_LOCK_ASSERT(object, MA_OWNED); 2153 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG, 2154 ("pmap_object_init_pt: non-device object")); 2155} 2156 2157/* 2158 * Routine: pmap_change_wiring 2159 * Function: Change the wiring attribute for a map/virtual-address 2160 * pair. 2161 * In/out conditions: 2162 * The mapping must already exist in the pmap. 2163 */ 2164void 2165pmap_change_wiring(pmap_t pmap, vm_offset_t va, boolean_t wired) 2166{ 2167 register pt_entry_t *pte; 2168 2169 if (pmap == NULL) 2170 return; 2171 2172 PMAP_LOCK(pmap); 2173 pte = pmap_pte(pmap, va); 2174 2175 if (wired && !pmap_pte_w(pte)) 2176 pmap->pm_stats.wired_count++; 2177 else if (!wired && pmap_pte_w(pte)) 2178 pmap->pm_stats.wired_count--; 2179 2180 /* 2181 * Wiring is not a hardware characteristic so there is no need to 2182 * invalidate TLB. 2183 */ 2184 pmap_pte_set_w(pte, wired); 2185 PMAP_UNLOCK(pmap); 2186} 2187 2188/* 2189 * Copy the range specified by src_addr/len 2190 * from the source map to the range dst_addr/len 2191 * in the destination map. 2192 * 2193 * This routine is only advisory and need not do anything. 2194 */ 2195 2196void 2197pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, 2198 vm_size_t len, vm_offset_t src_addr) 2199{ 2200} 2201 2202/* 2203 * pmap_zero_page zeros the specified hardware page by mapping 2204 * the page into KVM and using bzero to clear its contents. 2205 */ 2206void 2207pmap_zero_page(vm_page_t m) 2208{ 2209 vm_offset_t va; 2210 vm_paddr_t phys = VM_PAGE_TO_PHYS(m); 2211 register_t intr; 2212 2213 if (phys < MIPS_KSEG0_LARGEST_PHYS) { 2214 va = MIPS_PHYS_TO_KSEG0(phys); 2215 2216 bzero((caddr_t)va, PAGE_SIZE); 2217 mips_dcache_wbinv_range(va, PAGE_SIZE); 2218 } else { 2219 PMAP_LMEM_MAP1(va, phys); 2220 2221 bzero((caddr_t)va, PAGE_SIZE); 2222 mips_dcache_wbinv_range(va, PAGE_SIZE); 2223 2224 PMAP_LMEM_UNMAP(); 2225 } 2226} 2227 2228/* 2229 * pmap_zero_page_area zeros the specified hardware page by mapping 2230 * the page into KVM and using bzero to clear its contents. 2231 * 2232 * off and size may not cover an area beyond a single hardware page. 2233 */ 2234void 2235pmap_zero_page_area(vm_page_t m, int off, int size) 2236{ 2237 vm_offset_t va; 2238 vm_paddr_t phys = VM_PAGE_TO_PHYS(m); 2239 register_t intr; 2240 2241 if (phys < MIPS_KSEG0_LARGEST_PHYS) { 2242 va = MIPS_PHYS_TO_KSEG0(phys); 2243 bzero((char *)(caddr_t)va + off, size); 2244 mips_dcache_wbinv_range(va + off, size); 2245 } else { 2246 PMAP_LMEM_MAP1(va, phys); 2247 2248 bzero((char *)va + off, size); 2249 mips_dcache_wbinv_range(va + off, size); 2250 2251 PMAP_LMEM_UNMAP(); 2252 } 2253} 2254 2255void 2256pmap_zero_page_idle(vm_page_t m) 2257{ 2258 vm_offset_t va; 2259 vm_paddr_t phys = VM_PAGE_TO_PHYS(m); 2260 register_t intr; 2261 2262 if (phys < MIPS_KSEG0_LARGEST_PHYS) { 2263 va = MIPS_PHYS_TO_KSEG0(phys); 2264 bzero((caddr_t)va, PAGE_SIZE); 2265 mips_dcache_wbinv_range(va, PAGE_SIZE); 2266 } else { 2267 PMAP_LMEM_MAP1(va, phys); 2268 2269 bzero((caddr_t)va, PAGE_SIZE); 2270 mips_dcache_wbinv_range(va, PAGE_SIZE); 2271 2272 PMAP_LMEM_UNMAP(); 2273 } 2274} 2275 2276/* 2277 * pmap_copy_page copies the specified (machine independent) 2278 * page by mapping the page into virtual memory and using 2279 * bcopy to copy the page, one machine dependent page at a 2280 * time. 2281 */ 2282void 2283pmap_copy_page(vm_page_t src, vm_page_t dst) 2284{ 2285 vm_offset_t va_src, va_dst; 2286 vm_paddr_t phy_src = VM_PAGE_TO_PHYS(src); 2287 vm_paddr_t phy_dst = VM_PAGE_TO_PHYS(dst); 2288 register_t intr; 2289 2290 if ((phy_src < MIPS_KSEG0_LARGEST_PHYS) && (phy_dst < MIPS_KSEG0_LARGEST_PHYS)) { 2291 /* easy case, all can be accessed via KSEG0 */ 2292 /* 2293 * Flush all caches for VA that are mapped to this page 2294 * to make sure that data in SDRAM is up to date 2295 */ 2296 pmap_flush_pvcache(src); 2297 mips_dcache_wbinv_range_index( 2298 MIPS_PHYS_TO_KSEG0(phy_dst), PAGE_SIZE); 2299 va_src = MIPS_PHYS_TO_KSEG0(phy_src); 2300 va_dst = MIPS_PHYS_TO_KSEG0(phy_dst); 2301 bcopy((caddr_t)va_src, (caddr_t)va_dst, PAGE_SIZE); 2302 mips_dcache_wbinv_range(va_dst, PAGE_SIZE); 2303 } else { 2304 PMAP_LMEM_MAP2(va_src, phy_src, va_dst, phy_dst); 2305 2306 bcopy((void *)va_src, (void *)va_dst, PAGE_SIZE); 2307 mips_dcache_wbinv_range(va_dst, PAGE_SIZE); 2308 2309 PMAP_LMEM_UNMAP(); 2310 } 2311} 2312 2313/* 2314 * Returns true if the pmap's pv is one of the first 2315 * 16 pvs linked to from this page. This count may 2316 * be changed upwards or downwards in the future; it 2317 * is only necessary that true be returned for a small 2318 * subset of pmaps for proper page aging. 2319 */ 2320boolean_t 2321pmap_page_exists_quick(pmap_t pmap, vm_page_t m) 2322{ 2323 pv_entry_t pv; 2324 int loops = 0; 2325 2326 if (m->flags & PG_FICTITIOUS) 2327 return FALSE; 2328 2329 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2330 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 2331 if (pv->pv_pmap == pmap) { 2332 return TRUE; 2333 } 2334 loops++; 2335 if (loops >= 16) 2336 break; 2337 } 2338 return (FALSE); 2339} 2340 2341/* 2342 * Remove all pages from specified address space 2343 * this aids process exit speeds. Also, this code 2344 * is special cased for current process only, but 2345 * can have the more generic (and slightly slower) 2346 * mode enabled. This is much faster than pmap_remove 2347 * in the case of running down an entire address space. 2348 */ 2349void 2350pmap_remove_pages(pmap_t pmap) 2351{ 2352 pt_entry_t *pte, tpte; 2353 pv_entry_t pv, npv; 2354 vm_page_t m; 2355 2356 if (pmap != vmspace_pmap(curthread->td_proc->p_vmspace)) { 2357 printf("warning: pmap_remove_pages called with non-current pmap\n"); 2358 return; 2359 } 2360 vm_page_lock_queues(); 2361 PMAP_LOCK(pmap); 2362 sched_pin(); 2363 //XXX need to be TAILQ_FOREACH_SAFE ? 2364 for (pv = TAILQ_FIRST(&pmap->pm_pvlist); pv; pv = npv) { 2365 2366 pte = pmap_pte(pv->pv_pmap, pv->pv_va); 2367 if (!pmap_pte_v(pte)) 2368 panic("pmap_remove_pages: page on pm_pvlist has no pte\n"); 2369 tpte = *pte; 2370 2371/* 2372 * We cannot remove wired pages from a process' mapping at this time 2373 */ 2374 if (tpte & PTE_W) { 2375 npv = TAILQ_NEXT(pv, pv_plist); 2376 continue; 2377 } 2378 *pte = is_kernel_pmap(pmap) ? PTE_G : 0; 2379 2380 m = PHYS_TO_VM_PAGE(mips_tlbpfn_to_paddr(tpte)); 2381 KASSERT(m != NULL, 2382 ("pmap_remove_pages: bad tpte %x", tpte)); 2383 2384 pv->pv_pmap->pm_stats.resident_count--; 2385 2386 /* 2387 * Update the vm_page_t clean and reference bits. 2388 */ 2389 if (tpte & PTE_M) { 2390 vm_page_dirty(m); 2391 } 2392 npv = TAILQ_NEXT(pv, pv_plist); 2393 TAILQ_REMOVE(&pv->pv_pmap->pm_pvlist, pv, pv_plist); 2394 2395 m->md.pv_list_count--; 2396 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list); 2397 if (TAILQ_FIRST(&m->md.pv_list) == NULL) { 2398 vm_page_flag_clear(m, PG_WRITEABLE); 2399 } 2400 pmap_unuse_pt(pv->pv_pmap, pv->pv_va, pv->pv_ptem); 2401 free_pv_entry(pv); 2402 } 2403 sched_unpin(); 2404 pmap_invalidate_all(pmap); 2405 PMAP_UNLOCK(pmap); 2406 vm_page_unlock_queues(); 2407} 2408 2409/* 2410 * pmap_testbit tests bits in pte's 2411 * note that the testbit/changebit routines are inline, 2412 * and a lot of things compile-time evaluate. 2413 */ 2414static boolean_t 2415pmap_testbit(vm_page_t m, int bit) 2416{ 2417 pv_entry_t pv; 2418 pt_entry_t *pte; 2419 boolean_t rv = FALSE; 2420 2421 if (m->flags & PG_FICTITIOUS) 2422 return rv; 2423 2424 if (TAILQ_FIRST(&m->md.pv_list) == NULL) 2425 return rv; 2426 2427 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2428 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 2429#if defined(PMAP_DIAGNOSTIC) 2430 if (!pv->pv_pmap) { 2431 printf("Null pmap (tb) at va: 0x%x\n", pv->pv_va); 2432 continue; 2433 } 2434#endif 2435 PMAP_LOCK(pv->pv_pmap); 2436 pte = pmap_pte(pv->pv_pmap, pv->pv_va); 2437 rv = (*pte & bit) != 0; 2438 PMAP_UNLOCK(pv->pv_pmap); 2439 if (rv) 2440 break; 2441 } 2442 return (rv); 2443} 2444 2445/* 2446 * this routine is used to modify bits in ptes 2447 */ 2448static __inline void 2449pmap_changebit(vm_page_t m, int bit, boolean_t setem) 2450{ 2451 register pv_entry_t pv; 2452 register pt_entry_t *pte; 2453 2454 if (m->flags & PG_FICTITIOUS) 2455 return; 2456 2457 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2458 /* 2459 * Loop over all current mappings setting/clearing as appropos If 2460 * setting RO do we need to clear the VAC? 2461 */ 2462 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 2463#if defined(PMAP_DIAGNOSTIC) 2464 if (!pv->pv_pmap) { 2465 printf("Null pmap (cb) at va: 0x%x\n", pv->pv_va); 2466 continue; 2467 } 2468#endif 2469 2470 PMAP_LOCK(pv->pv_pmap); 2471 pte = pmap_pte(pv->pv_pmap, pv->pv_va); 2472 2473 if (setem) { 2474 *(int *)pte |= bit; 2475 pmap_update_page(pv->pv_pmap, pv->pv_va, *pte); 2476 } else { 2477 vm_offset_t pbits = *(vm_offset_t *)pte; 2478 2479 if (pbits & bit) { 2480 if (bit == PTE_RW) { 2481 if (pbits & PTE_M) { 2482 vm_page_dirty(m); 2483 } 2484 *(int *)pte = (pbits & ~(PTE_M | PTE_RW)) | 2485 PTE_RO; 2486 } else { 2487 *(int *)pte = pbits & ~bit; 2488 } 2489 pmap_update_page(pv->pv_pmap, pv->pv_va, *pte); 2490 } 2491 } 2492 PMAP_UNLOCK(pv->pv_pmap); 2493 } 2494 if (!setem && bit == PTE_RW) 2495 vm_page_flag_clear(m, PG_WRITEABLE); 2496} 2497 2498/* 2499 * pmap_page_wired_mappings: 2500 * 2501 * Return the number of managed mappings to the given physical page 2502 * that are wired. 2503 */ 2504int 2505pmap_page_wired_mappings(vm_page_t m) 2506{ 2507 pv_entry_t pv; 2508 int count; 2509 2510 count = 0; 2511 if ((m->flags & PG_FICTITIOUS) != 0) 2512 return (count); 2513 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2514 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) 2515 if (pv->pv_wired) 2516 count++; 2517 return (count); 2518} 2519 2520/* 2521 * Clear the write and modified bits in each of the given page's mappings. 2522 */ 2523void 2524pmap_remove_write(vm_page_t m) 2525{ 2526 pv_entry_t pv, npv; 2527 vm_offset_t va; 2528 pt_entry_t *pte; 2529 2530 if ((m->flags & PG_WRITEABLE) == 0) 2531 return; 2532 2533 /* 2534 * Loop over all current mappings setting/clearing as appropos. 2535 */ 2536 for (pv = TAILQ_FIRST(&m->md.pv_list); pv; pv = npv) { 2537 npv = TAILQ_NEXT(pv, pv_plist); 2538 pte = pmap_pte(pv->pv_pmap, pv->pv_va); 2539 2540 if ((pte == NULL) || !mips_pg_v(*pte)) 2541 panic("page on pm_pvlist has no pte\n"); 2542 2543 va = pv->pv_va; 2544 pmap_protect(pv->pv_pmap, va, va + PAGE_SIZE, 2545 VM_PROT_READ | VM_PROT_EXECUTE); 2546 } 2547 vm_page_flag_clear(m, PG_WRITEABLE); 2548} 2549 2550/* 2551 * pmap_ts_referenced: 2552 * 2553 * Return the count of reference bits for a page, clearing all of them. 2554 */ 2555int 2556pmap_ts_referenced(vm_page_t m) 2557{ 2558 if (m->flags & PG_FICTITIOUS) 2559 return (0); 2560 2561 if (m->md.pv_flags & PV_TABLE_REF) { 2562 m->md.pv_flags &= ~PV_TABLE_REF; 2563 return 1; 2564 } 2565 return 0; 2566} 2567 2568/* 2569 * pmap_is_modified: 2570 * 2571 * Return whether or not the specified physical page was modified 2572 * in any physical maps. 2573 */ 2574boolean_t 2575pmap_is_modified(vm_page_t m) 2576{ 2577 if (m->flags & PG_FICTITIOUS) 2578 return FALSE; 2579 2580 if (m->md.pv_flags & PV_TABLE_MOD) 2581 return TRUE; 2582 else 2583 return pmap_testbit(m, PTE_M); 2584} 2585 2586/* N/C */ 2587 2588/* 2589 * pmap_is_prefaultable: 2590 * 2591 * Return whether or not the specified virtual address is elgible 2592 * for prefault. 2593 */ 2594boolean_t 2595pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr) 2596{ 2597 pt_entry_t *pte; 2598 boolean_t rv; 2599 2600 rv = FALSE; 2601 PMAP_LOCK(pmap); 2602 if (*pmap_pde(pmap, addr)) { 2603 pte = pmap_pte(pmap, addr); 2604 rv = (*pte == 0); 2605 } 2606 PMAP_UNLOCK(pmap); 2607 return (rv); 2608} 2609 2610/* 2611 * Clear the modify bits on the specified physical page. 2612 */ 2613void 2614pmap_clear_modify(vm_page_t m) 2615{ 2616 if (m->flags & PG_FICTITIOUS) 2617 return; 2618 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2619 if (m->md.pv_flags & PV_TABLE_MOD) { 2620 pmap_changebit(m, PTE_M, FALSE); 2621 m->md.pv_flags &= ~PV_TABLE_MOD; 2622 } 2623} 2624 2625/* 2626 * pmap_is_referenced: 2627 * 2628 * Return whether or not the specified physical page was referenced 2629 * in any physical maps. 2630 */ 2631boolean_t 2632pmap_is_referenced(vm_page_t m) 2633{ 2634 2635 return ((m->flags & PG_FICTITIOUS) == 0 && 2636 (m->md.pv_flags & PV_TABLE_REF) != 0); 2637} 2638 2639/* 2640 * pmap_clear_reference: 2641 * 2642 * Clear the reference bit on the specified physical page. 2643 */ 2644void 2645pmap_clear_reference(vm_page_t m) 2646{ 2647 if (m->flags & PG_FICTITIOUS) 2648 return; 2649 2650 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2651 if (m->md.pv_flags & PV_TABLE_REF) { 2652 m->md.pv_flags &= ~PV_TABLE_REF; 2653 } 2654} 2655 2656/* 2657 * Miscellaneous support routines follow 2658 */ 2659 2660/* 2661 * Map a set of physical memory pages into the kernel virtual 2662 * address space. Return a pointer to where it is mapped. This 2663 * routine is intended to be used for mapping device memory, 2664 * NOT real memory. 2665 */ 2666 2667/* 2668 * Map a set of physical memory pages into the kernel virtual 2669 * address space. Return a pointer to where it is mapped. This 2670 * routine is intended to be used for mapping device memory, 2671 * NOT real memory. 2672 */ 2673void * 2674pmap_mapdev(vm_offset_t pa, vm_size_t size) 2675{ 2676 vm_offset_t va, tmpva, offset; 2677 2678 /* 2679 * KSEG1 maps only first 512M of phys address space. For 2680 * pa > 0x20000000 we should make proper mapping * using pmap_kenter. 2681 */ 2682 if ((pa + size - 1) < MIPS_KSEG0_LARGEST_PHYS) 2683 return (void *)MIPS_PHYS_TO_KSEG1(pa); 2684 else { 2685 offset = pa & PAGE_MASK; 2686 size = roundup(size + offset, PAGE_SIZE); 2687 2688 va = kmem_alloc_nofault(kernel_map, size); 2689 if (!va) 2690 panic("pmap_mapdev: Couldn't alloc kernel virtual memory"); 2691 pa = trunc_page(pa); 2692 for (tmpva = va; size > 0;) { 2693 pmap_kenter(tmpva, pa); 2694 size -= PAGE_SIZE; 2695 tmpva += PAGE_SIZE; 2696 pa += PAGE_SIZE; 2697 } 2698 } 2699 2700 return ((void *)(va + offset)); 2701} 2702 2703void 2704pmap_unmapdev(vm_offset_t va, vm_size_t size) 2705{ 2706 vm_offset_t base, offset, tmpva; 2707 2708 /* If the address is within KSEG1 then there is nothing to do */ 2709 if (va >= MIPS_KSEG1_START && va <= MIPS_KSEG1_END) 2710 return; 2711 2712 base = trunc_page(va); 2713 offset = va & PAGE_MASK; 2714 size = roundup(size + offset, PAGE_SIZE); 2715 for (tmpva = base; tmpva < base + size; tmpva += PAGE_SIZE) 2716 pmap_kremove(tmpva); 2717 kmem_free(kernel_map, base, size); 2718} 2719 2720/* 2721 * perform the pmap work for mincore 2722 */ 2723int 2724pmap_mincore(pmap_t pmap, vm_offset_t addr) 2725{ 2726 2727 pt_entry_t *ptep, pte; 2728 vm_page_t m; 2729 int val = 0; 2730 2731 PMAP_LOCK(pmap); 2732 ptep = pmap_pte(pmap, addr); 2733 pte = (ptep != NULL) ? *ptep : 0; 2734 PMAP_UNLOCK(pmap); 2735 2736 if (mips_pg_v(pte)) { 2737 vm_offset_t pa; 2738 2739 val = MINCORE_INCORE; 2740 pa = mips_tlbpfn_to_paddr(pte); 2741 if (!page_is_managed(pa)) 2742 return val; 2743 2744 m = PHYS_TO_VM_PAGE(pa); 2745 2746 /* 2747 * Modified by us 2748 */ 2749 if (pte & PTE_M) 2750 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER; 2751 /* 2752 * Modified by someone 2753 */ 2754 else { 2755 vm_page_lock_queues(); 2756 if (m->dirty || pmap_is_modified(m)) 2757 val |= MINCORE_MODIFIED_OTHER; 2758 vm_page_unlock_queues(); 2759 } 2760 /* 2761 * Referenced by us or someone 2762 */ 2763 vm_page_lock_queues(); 2764 if ((m->flags & PG_REFERENCED) || pmap_is_referenced(m)) 2765 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER; 2766 vm_page_unlock_queues(); 2767 } 2768 return val; 2769} 2770 2771void 2772pmap_activate(struct thread *td) 2773{ 2774 pmap_t pmap, oldpmap; 2775 struct proc *p = td->td_proc; 2776 2777 critical_enter(); 2778 2779 pmap = vmspace_pmap(p->p_vmspace); 2780 oldpmap = PCPU_GET(curpmap); 2781 2782 if (oldpmap) 2783 atomic_clear_32(&oldpmap->pm_active, PCPU_GET(cpumask)); 2784 atomic_set_32(&pmap->pm_active, PCPU_GET(cpumask)); 2785 pmap_asid_alloc(pmap); 2786 if (td == curthread) { 2787 PCPU_SET(segbase, pmap->pm_segtab); 2788 MachSetPID(pmap->pm_asid[PCPU_GET(cpuid)].asid); 2789 } 2790 2791 PCPU_SET(curpmap, pmap); 2792 critical_exit(); 2793} 2794 2795void 2796pmap_sync_icache(pmap_t pm, vm_offset_t va, vm_size_t sz) 2797{ 2798} 2799 2800/* 2801 * Increase the starting virtual address of the given mapping if a 2802 * different alignment might result in more superpage mappings. 2803 */ 2804void 2805pmap_align_superpage(vm_object_t object, vm_ooffset_t offset, 2806 vm_offset_t *addr, vm_size_t size) 2807{ 2808 vm_offset_t superpage_offset; 2809 2810 if (size < NBSEG) 2811 return; 2812 if (object != NULL && (object->flags & OBJ_COLORED) != 0) 2813 offset += ptoa(object->pg_color); 2814 superpage_offset = offset & SEGOFSET; 2815 if (size - ((NBSEG - superpage_offset) & SEGOFSET) < NBSEG || 2816 (*addr & SEGOFSET) == superpage_offset) 2817 return; 2818 if ((*addr & SEGOFSET) < superpage_offset) 2819 *addr = (*addr & ~SEGOFSET) + superpage_offset; 2820 else 2821 *addr = ((*addr + SEGOFSET) & ~SEGOFSET) + superpage_offset; 2822} 2823 2824/* 2825 * Increase the starting virtual address of the given mapping so 2826 * that it is aligned to not be the second page in a TLB entry. 2827 * This routine assumes that the length is appropriately-sized so 2828 * that the allocation does not share a TLB entry at all if required. 2829 */ 2830void 2831pmap_align_tlb(vm_offset_t *addr) 2832{ 2833 if ((*addr & PAGE_SIZE) == 0) 2834 return; 2835 *addr += PAGE_SIZE; 2836 return; 2837} 2838 2839int pmap_pid_dump(int pid); 2840 2841int 2842pmap_pid_dump(int pid) 2843{ 2844 pmap_t pmap; 2845 struct proc *p; 2846 int npte = 0; 2847 int index; 2848 2849 sx_slock(&allproc_lock); 2850 LIST_FOREACH(p, &allproc, p_list) { 2851 if (p->p_pid != pid) 2852 continue; 2853 2854 if (p->p_vmspace) { 2855 int i, j; 2856 2857 printf("vmspace is %p\n", 2858 p->p_vmspace); 2859 index = 0; 2860 pmap = vmspace_pmap(p->p_vmspace); 2861 printf("pmap asid:%x generation:%x\n", 2862 pmap->pm_asid[0].asid, 2863 pmap->pm_asid[0].gen); 2864 for (i = 0; i < NUSERPGTBLS; i++) { 2865 pd_entry_t *pde; 2866 pt_entry_t *pte; 2867 unsigned base = i << SEGSHIFT; 2868 2869 pde = &pmap->pm_segtab[i]; 2870 if (pde && pmap_pde_v(pde)) { 2871 for (j = 0; j < 1024; j++) { 2872 vm_offset_t va = base + 2873 (j << PAGE_SHIFT); 2874 2875 pte = pmap_pte(pmap, va); 2876 if (pte && pmap_pte_v(pte)) { 2877 vm_offset_t pa; 2878 vm_page_t m; 2879 2880 pa = mips_tlbpfn_to_paddr(*pte); 2881 m = PHYS_TO_VM_PAGE(pa); 2882 printf("va: %p, pt: %p, h: %d, w: %d, f: 0x%x", 2883 (void *)va, 2884 (void *)pa, 2885 m->hold_count, 2886 m->wire_count, 2887 m->flags); 2888 npte++; 2889 index++; 2890 if (index >= 2) { 2891 index = 0; 2892 printf("\n"); 2893 } else { 2894 printf(" "); 2895 } 2896 } 2897 } 2898 } 2899 } 2900 } else { 2901 printf("Process pid:%d has no vm_space\n", pid); 2902 } 2903 break; 2904 } 2905 sx_sunlock(&allproc_lock); 2906 return npte; 2907} 2908 2909 2910#if defined(DEBUG) 2911 2912static void pads(pmap_t pm); 2913void pmap_pvdump(vm_offset_t pa); 2914 2915/* print address space of pmap*/ 2916static void 2917pads(pmap_t pm) 2918{ 2919 unsigned va, i, j; 2920 pt_entry_t *ptep; 2921 2922 if (pm == kernel_pmap) 2923 return; 2924 for (i = 0; i < NPTEPG; i++) 2925 if (pm->pm_segtab[i]) 2926 for (j = 0; j < NPTEPG; j++) { 2927 va = (i << SEGSHIFT) + (j << PAGE_SHIFT); 2928 if (pm == kernel_pmap && va < KERNBASE) 2929 continue; 2930 if (pm != kernel_pmap && 2931 va >= VM_MAXUSER_ADDRESS) 2932 continue; 2933 ptep = pmap_pte(pm, va); 2934 if (pmap_pte_v(ptep)) 2935 printf("%x:%x ", va, *(int *)ptep); 2936 } 2937 2938} 2939 2940void 2941pmap_pvdump(vm_offset_t pa) 2942{ 2943 register pv_entry_t pv; 2944 vm_page_t m; 2945 2946 printf("pa %x", pa); 2947 m = PHYS_TO_VM_PAGE(pa); 2948 for (pv = TAILQ_FIRST(&m->md.pv_list); pv; 2949 pv = TAILQ_NEXT(pv, pv_list)) { 2950 printf(" -> pmap %p, va %x", (void *)pv->pv_pmap, pv->pv_va); 2951 pads(pv->pv_pmap); 2952 } 2953 printf(" "); 2954} 2955 2956/* N/C */ 2957#endif 2958 2959 2960/* 2961 * Allocate TLB address space tag (called ASID or TLBPID) and return it. 2962 * It takes almost as much or more time to search the TLB for a 2963 * specific ASID and flush those entries as it does to flush the entire TLB. 2964 * Therefore, when we allocate a new ASID, we just take the next number. When 2965 * we run out of numbers, we flush the TLB, increment the generation count 2966 * and start over. ASID zero is reserved for kernel use. 2967 */ 2968static void 2969pmap_asid_alloc(pmap) 2970 pmap_t pmap; 2971{ 2972 if (pmap->pm_asid[PCPU_GET(cpuid)].asid != PMAP_ASID_RESERVED && 2973 pmap->pm_asid[PCPU_GET(cpuid)].gen == PCPU_GET(asid_generation)); 2974 else { 2975 if (PCPU_GET(next_asid) == pmap_max_asid) { 2976 MIPS_TBIAP(); 2977 PCPU_SET(asid_generation, 2978 (PCPU_GET(asid_generation) + 1) & ASIDGEN_MASK); 2979 if (PCPU_GET(asid_generation) == 0) { 2980 PCPU_SET(asid_generation, 1); 2981 } 2982 PCPU_SET(next_asid, 1); /* 0 means invalid */ 2983 } 2984 pmap->pm_asid[PCPU_GET(cpuid)].asid = PCPU_GET(next_asid); 2985 pmap->pm_asid[PCPU_GET(cpuid)].gen = PCPU_GET(asid_generation); 2986 PCPU_SET(next_asid, PCPU_GET(next_asid) + 1); 2987 } 2988} 2989 2990int 2991page_is_managed(vm_offset_t pa) 2992{ 2993 vm_offset_t pgnum = mips_btop(pa); 2994 2995 if (pgnum >= first_page) { 2996 vm_page_t m; 2997 2998 m = PHYS_TO_VM_PAGE(pa); 2999 if (m == NULL) 3000 return 0; 3001 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0) 3002 return 1; 3003 } 3004 return 0; 3005} 3006 3007static int 3008init_pte_prot(vm_offset_t va, vm_page_t m, vm_prot_t prot) 3009{ 3010 int rw = 0; 3011 3012 if (!(prot & VM_PROT_WRITE)) 3013 rw = PTE_ROPAGE; 3014 else { 3015 if (va >= VM_MIN_KERNEL_ADDRESS) { 3016 /* 3017 * Don't bother to trap on kernel writes, just 3018 * record page as dirty. 3019 */ 3020 rw = PTE_RWPAGE; 3021 vm_page_dirty(m); 3022 } else if ((m->md.pv_flags & PV_TABLE_MOD) || 3023 m->dirty == VM_PAGE_BITS_ALL) 3024 rw = PTE_RWPAGE; 3025 else 3026 rw = PTE_CWPAGE; 3027 vm_page_flag_set(m, PG_WRITEABLE); 3028 } 3029 return rw; 3030} 3031 3032/* 3033 * pmap_page_is_free: 3034 * 3035 * Called when a page is freed to allow pmap to clean up 3036 * any extra state associated with the page. In this case 3037 * clear modified/referenced bits. 3038 */ 3039void 3040pmap_page_is_free(vm_page_t m) 3041{ 3042 3043 m->md.pv_flags = 0; 3044} 3045 3046/* 3047 * pmap_set_modified: 3048 * 3049 * Sets the page modified and reference bits for the specified page. 3050 */ 3051void 3052pmap_set_modified(vm_offset_t pa) 3053{ 3054 3055 PHYS_TO_VM_PAGE(pa)->md.pv_flags |= (PV_TABLE_REF | PV_TABLE_MOD); 3056} 3057 3058/* 3059 * Routine: pmap_kextract 3060 * Function: 3061 * Extract the physical page address associated 3062 * virtual address. 3063 */ 3064 /* PMAP_INLINE */ vm_offset_t 3065pmap_kextract(vm_offset_t va) 3066{ 3067 vm_offset_t pa = 0; 3068 3069 if (va < MIPS_KSEG0_START) { 3070 /* user virtual address */ 3071 pt_entry_t *ptep; 3072 3073 if (curproc && curproc->p_vmspace) { 3074 ptep = pmap_pte(&curproc->p_vmspace->vm_pmap, va); 3075 if (ptep) 3076 pa = mips_tlbpfn_to_paddr(*ptep) | 3077 (va & PAGE_MASK); 3078 } 3079 } else if (va >= MIPS_KSEG0_START && 3080 va < MIPS_KSEG1_START) 3081 pa = MIPS_KSEG0_TO_PHYS(va); 3082 else if (va >= MIPS_KSEG1_START && 3083 va < MIPS_KSEG2_START) 3084 pa = MIPS_KSEG1_TO_PHYS(va); 3085 else if (va >= MIPS_KSEG2_START && va < VM_MAX_KERNEL_ADDRESS) { 3086 pt_entry_t *ptep; 3087 3088 /* Is the kernel pmap initialized? */ 3089 if (kernel_pmap->pm_active) { 3090 /* Its inside the virtual address range */ 3091 ptep = pmap_pte(kernel_pmap, va); 3092 if (ptep) 3093 pa = mips_tlbpfn_to_paddr(*ptep) | 3094 (va & PAGE_MASK); 3095 } 3096 } 3097 return pa; 3098} 3099 3100void 3101pmap_flush_pvcache(vm_page_t m) 3102{ 3103 pv_entry_t pv; 3104 3105 if (m != NULL) { 3106 for (pv = TAILQ_FIRST(&m->md.pv_list); pv; 3107 pv = TAILQ_NEXT(pv, pv_list)) { 3108 mips_dcache_wbinv_range_index(pv->pv_va, PAGE_SIZE); 3109 } 3110 } 3111} 3112 3113void 3114pmap_save_tlb(void) 3115{ 3116 int tlbno, cpu; 3117 3118 cpu = PCPU_GET(cpuid); 3119 3120 for (tlbno = 0; tlbno < num_tlbentries; ++tlbno) 3121 MachTLBRead(tlbno, &tlbstash[cpu][tlbno]); 3122} 3123 3124#ifdef DDB 3125#include <ddb/ddb.h> 3126 3127DB_SHOW_COMMAND(tlb, ddb_dump_tlb) 3128{ 3129 int cpu, tlbno; 3130 struct tlb *tlb; 3131 3132 if (have_addr) 3133 cpu = ((addr >> 4) % 16) * 10 + (addr % 16); 3134 else 3135 cpu = PCPU_GET(cpuid); 3136 3137 if (cpu < 0 || cpu >= mp_ncpus) { 3138 db_printf("Invalid CPU %d\n", cpu); 3139 return; 3140 } else 3141 db_printf("CPU %d:\n", cpu); 3142 3143 if (cpu == PCPU_GET(cpuid)) 3144 pmap_save_tlb(); 3145 3146 for (tlbno = 0; tlbno < num_tlbentries; ++tlbno) { 3147 tlb = &tlbstash[cpu][tlbno]; 3148 if (tlb->tlb_lo0 & PTE_V || tlb->tlb_lo1 & PTE_V) { 3149 printf("TLB %2d vad 0x%0lx ", 3150 tlbno, (long)(tlb->tlb_hi & 0xffffff00)); 3151 } else { 3152 printf("TLB*%2d vad 0x%0lx ", 3153 tlbno, (long)(tlb->tlb_hi & 0xffffff00)); 3154 } 3155 printf("0=0x%0lx ", pfn_to_vad((long)tlb->tlb_lo0)); 3156 printf("%c", tlb->tlb_lo0 & PTE_V ? 'V' : '-'); 3157 printf("%c", tlb->tlb_lo0 & PTE_M ? 'M' : '-'); 3158 printf("%c", tlb->tlb_lo0 & PTE_G ? 'G' : '-'); 3159 printf(" atr %x ", (tlb->tlb_lo0 >> 3) & 7); 3160 printf("1=0x%0lx ", pfn_to_vad((long)tlb->tlb_lo1)); 3161 printf("%c", tlb->tlb_lo1 & PTE_V ? 'V' : '-'); 3162 printf("%c", tlb->tlb_lo1 & PTE_M ? 'M' : '-'); 3163 printf("%c", tlb->tlb_lo1 & PTE_G ? 'G' : '-'); 3164 printf(" atr %x ", (tlb->tlb_lo1 >> 3) & 7); 3165 printf(" sz=%x pid=%x\n", tlb->tlb_mask, 3166 (tlb->tlb_hi & 0x000000ff)); 3167 } 3168} 3169#endif /* DDB */ 3170