pmap.c revision 188507
1/* 2 * Copyright (c) 1991 Regents of the University of California. 3 * All rights reserved. 4 * Copyright (c) 1994 John S. Dyson 5 * All rights reserved. 6 * Copyright (c) 1994 David Greenman 7 * All rights reserved. 8 * 9 * This code is derived from software contributed to Berkeley by 10 * the Systems Programming Group of the University of Utah Computer 11 * Science Department and William Jolitz of UUNET Technologies Inc. 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 1. Redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution. 21 * 4. Neither the name of the University nor the names of its contributors 22 * may be used to endorse or promote products derived from this software 23 * without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 28 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 31 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35 * SUCH DAMAGE. 36 * 37 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91 38 * from: src/sys/i386/i386/pmap.c,v 1.250.2.8 2000/11/21 00:09:14 ps 39 * JNPR: pmap.c,v 1.11.2.1 2007/08/16 11:51:06 girish 40 */ 41 42/* 43 * Manages physical address maps. 44 * 45 * In addition to hardware address maps, this 46 * module is called upon to provide software-use-only 47 * maps which may or may not be stored in the same 48 * form as hardware maps. These pseudo-maps are 49 * used to store intermediate results from copy 50 * operations to and from address spaces. 51 * 52 * Since the information managed by this module is 53 * also stored by the logical address mapping module, 54 * this module may throw away valid virtual-to-physical 55 * mappings at almost any time. However, invalidations 56 * of virtual-to-physical mappings must be done as 57 * requested. 58 * 59 * In order to cope with hardware architectures which 60 * make virtual-to-physical map invalidates expensive, 61 * this module may delay invalidate or reduced protection 62 * operations until such time as they are actually 63 * necessary. This module is given full information as 64 * to which processors are currently using which maps, 65 * and to when physical maps must be made correct. 66 */ 67 68#include <sys/cdefs.h> 69__FBSDID("$FreeBSD: head/sys/mips/mips/pmap.c 188507 2009-02-12 01:14:49Z imp $"); 70 71#include "opt_ddb.h" 72#include "opt_msgbuf.h" 73#include <sys/param.h> 74#include <sys/systm.h> 75#include <sys/proc.h> 76#include <sys/msgbuf.h> 77#include <sys/vmmeter.h> 78#include <sys/mman.h> 79 80#include <vm/vm.h> 81#include <vm/vm_param.h> 82#include <sys/lock.h> 83#include <sys/mutex.h> 84#include <vm/vm_kern.h> 85#include <vm/vm_page.h> 86#include <vm/vm_map.h> 87#include <vm/vm_object.h> 88#include <vm/vm_extern.h> 89#include <vm/vm_pageout.h> 90#include <vm/vm_pager.h> 91#include <vm/uma.h> 92#include <sys/pcpu.h> 93#include <sys/sched.h> 94#ifdef SMP 95#include <sys/smp.h> 96#endif 97 98#include <machine/cache.h> 99#include <machine/pltfm.h> 100#include <machine/md_var.h> 101 102#if defined(DIAGNOSTIC) 103#define PMAP_DIAGNOSTIC 104#endif 105 106#undef PMAP_DEBUG 107 108#ifndef PMAP_SHPGPERPROC 109#define PMAP_SHPGPERPROC 200 110#endif 111 112#if !defined(PMAP_DIAGNOSTIC) 113#define PMAP_INLINE __inline 114#else 115#define PMAP_INLINE 116#endif 117 118/* 119 * Get PDEs and PTEs for user/kernel address space 120 */ 121#define pmap_pde(m, v) (&((m)->pm_segtab[(vm_offset_t)(v) >> SEGSHIFT])) 122#define segtab_pde(m, v) (m[(vm_offset_t)(v) >> SEGSHIFT]) 123 124#define pmap_pte_w(pte) ((*(int *)pte & PTE_W) != 0) 125#define pmap_pde_v(pte) ((*(int *)pte) != 0) 126#define pmap_pte_m(pte) ((*(int *)pte & PTE_M) != 0) 127#define pmap_pte_v(pte) ((*(int *)pte & PTE_V) != 0) 128 129#define pmap_pte_set_w(pte, v) ((v)?(*(int *)pte |= PTE_W):(*(int *)pte &= ~PTE_W)) 130#define pmap_pte_set_prot(pte, v) ((*(int *)pte &= ~PG_PROT), (*(int *)pte |= (v))) 131 132#define MIPS_SEGSIZE (1L << SEGSHIFT) 133#define mips_segtrunc(va) ((va) & ~(MIPS_SEGSIZE-1)) 134#define pmap_TLB_invalidate_all() MIPS_TBIAP() 135#define pmap_va_asid(pmap, va) ((va) | ((pmap)->pm_asid[PCPU_GET(cpuid)].asid << VMTLB_PID_SHIFT)) 136#define is_kernel_pmap(x) ((x) == kernel_pmap) 137 138static struct pmap kernel_pmap_store; 139pmap_t kernel_pmap; 140pd_entry_t *kernel_segmap; 141 142vm_offset_t avail_start; /* PA of first available physical page */ 143vm_offset_t avail_end; /* PA of last available physical page */ 144vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */ 145vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */ 146 147static int nkpt; 148unsigned pmap_max_asid; /* max ASID supported by the system */ 149 150 151#define PMAP_ASID_RESERVED 0 152 153 154vm_offset_t kernel_vm_end; 155 156static void pmap_asid_alloc(pmap_t pmap); 157 158/* 159 * Data for the pv entry allocation mechanism 160 */ 161static uma_zone_t pvzone; 162static struct vm_object pvzone_obj; 163static int pv_entry_count = 0, pv_entry_max = 0, pv_entry_high_water = 0; 164int pmap_pagedaemon_waken = 0; 165 166struct fpage fpages_shared[FPAGES_SHARED]; 167 168struct sysmaps sysmaps_pcpu[MAXCPU]; 169 170static PMAP_INLINE void free_pv_entry(pv_entry_t pv); 171static pv_entry_t get_pv_entry(pmap_t locked_pmap); 172static __inline void pmap_changebit(vm_page_t m, int bit, boolean_t setem); 173 174static int pmap_remove_pte(struct pmap *pmap, pt_entry_t *ptq, vm_offset_t va); 175static void pmap_remove_page(struct pmap *pmap, vm_offset_t va); 176static void pmap_remove_entry(struct pmap *pmap, vm_page_t m, vm_offset_t va); 177static boolean_t pmap_testbit(vm_page_t m, int bit); 178static void 179pmap_insert_entry(pmap_t pmap, vm_offset_t va, vm_page_t mpte, 180 vm_page_t m, boolean_t wired); 181 182static vm_page_t pmap_allocpte(pmap_t pmap, vm_offset_t va, int flags); 183 184static vm_page_t _pmap_allocpte(pmap_t pmap, unsigned ptepindex, int flags); 185static int pmap_unuse_pt(pmap_t, vm_offset_t, vm_page_t); 186static int init_pte_prot(vm_offset_t va, vm_page_t m, vm_prot_t prot); 187static void pmap_TLB_invalidate_kernel(vm_offset_t); 188static void pmap_TLB_update_kernel(vm_offset_t, pt_entry_t); 189static void pmap_init_fpage(void); 190 191#ifdef SMP 192static void pmap_invalidate_page_action(void *arg); 193static void pmap_invalidate_all_action(void *arg); 194static void pmap_update_page_action(void *arg); 195 196#endif 197 198struct local_sysmaps { 199 struct mtx lock; 200 pt_entry_t CMAP1; 201 pt_entry_t CMAP2; 202 caddr_t CADDR1; 203 caddr_t CADDR2; 204 uint16_t valid1, valid2; 205}; 206 207/* This structure is for large memory 208 * above 512Meg. We can't (in 32 bit mode) 209 * just use the direct mapped MIPS_CACHED_TO_PHYS() 210 * macros since we can't see the memory and must 211 * map it in when we need to access it. In 64 212 * bit mode this goes away. 213 */ 214static struct local_sysmaps sysmap_lmem[MAXCPU]; 215caddr_t virtual_sys_start = (caddr_t)0; 216 217pd_entry_t 218pmap_segmap(pmap_t pmap, vm_offset_t va) 219{ 220 if (pmap->pm_segtab) 221 return (pmap->pm_segtab[((vm_offset_t)(va) >> SEGSHIFT)]); 222 else 223 return ((pd_entry_t)0); 224} 225 226/* 227 * Routine: pmap_pte 228 * Function: 229 * Extract the page table entry associated 230 * with the given map/virtual_address pair. 231 */ 232pt_entry_t * 233pmap_pte(pmap_t pmap, vm_offset_t va) 234{ 235 pt_entry_t *pdeaddr; 236 237 if (pmap) { 238 pdeaddr = (pt_entry_t *)pmap_segmap(pmap, va); 239 if (pdeaddr) { 240 return pdeaddr + vad_to_pte_offset(va); 241 } 242 } 243 return ((pt_entry_t *)0); 244} 245 246 247vm_offset_t 248pmap_steal_memory(vm_size_t size) 249{ 250 vm_size_t bank_size; 251 vm_offset_t pa, va; 252 253 size = round_page(size); 254 255 bank_size = phys_avail[1] - phys_avail[0]; 256 while (size > bank_size) { 257 int i; 258 259 for (i = 0; phys_avail[i + 2]; i += 2) { 260 phys_avail[i] = phys_avail[i + 2]; 261 phys_avail[i + 1] = phys_avail[i + 3]; 262 } 263 phys_avail[i] = 0; 264 phys_avail[i + 1] = 0; 265 if (!phys_avail[0]) 266 panic("pmap_steal_memory: out of memory"); 267 bank_size = phys_avail[1] - phys_avail[0]; 268 } 269 270 pa = phys_avail[0]; 271 phys_avail[0] += size; 272 if (pa >= MIPS_KSEG0_LARGEST_PHYS) { 273 panic("Out of memory below 512Meg?"); 274 } 275 va = MIPS_PHYS_TO_CACHED(pa); 276 bzero((caddr_t)va, size); 277 return va; 278} 279 280/* 281 * Bootstrap the system enough to run with virtual memory. This 282 * assumes that the phys_avail array has been initialized. 283 */ 284void 285pmap_bootstrap(void) 286{ 287 pt_entry_t *pgtab; 288 pt_entry_t *pte; 289 int i, j; 290 int memory_larger_than_512meg = 0; 291 292 /* Sort. */ 293again: 294 for (i = 0; phys_avail[i + 1] != 0; i += 2) { 295 if (phys_avail[i + 1] >= MIPS_KSEG0_LARGEST_PHYS) { 296 memory_larger_than_512meg++; 297 } 298 if (i < 2) 299 continue; 300 if (phys_avail[i - 2] > phys_avail[i]) { 301 vm_paddr_t ptemp[2]; 302 303 304 ptemp[0] = phys_avail[i + 0]; 305 ptemp[1] = phys_avail[i + 1]; 306 307 phys_avail[i + 0] = phys_avail[i - 2]; 308 phys_avail[i + 1] = phys_avail[i - 1]; 309 310 phys_avail[i - 2] = ptemp[0]; 311 phys_avail[i - 1] = ptemp[1]; 312 goto again; 313 } 314 } 315 316 if (bootverbose) { 317 printf("Physical memory chunk(s):\n"); 318 for (i = 0; phys_avail[i + 1] != 0; i += 2) { 319 vm_paddr_t size; 320 321 size = phys_avail[i + 1] - phys_avail[i]; 322 printf("%#08jx - %#08jx, %ju bytes (%ju pages)\n", 323 (uintmax_t) phys_avail[i], 324 (uintmax_t) phys_avail[i + 1] - 1, 325 (uintmax_t) size, (uintmax_t) size / PAGE_SIZE); 326 } 327 } 328 /* 329 * Steal the message buffer from the beginning of memory. 330 */ 331 msgbufp = (struct msgbuf *)pmap_steal_memory(MSGBUF_SIZE); 332 msgbufinit(msgbufp, MSGBUF_SIZE); 333 334 /* 335 * Steal thread0 kstack. 336 */ 337 kstack0 = pmap_steal_memory(KSTACK_PAGES << PAGE_SHIFT); 338 339 340 virtual_avail = VM_MIN_KERNEL_ADDRESS + VM_KERNEL_ALLOC_OFFSET; 341 virtual_end = VM_MAX_KERNEL_ADDRESS; 342 343 /* 344 * Steal some virtual space that will not be in kernel_segmap. This 345 * va memory space will be used to map in kernel pages that are 346 * outside the 512Meg region. Note that we only do this steal when 347 * we do have memory in this region, that way for systems with 348 * smaller memory we don't "steal" any va ranges :-) 349 */ 350 if (memory_larger_than_512meg) { 351 for (i = 0; i < MAXCPU; i++) { 352 sysmap_lmem[i].CMAP1 = PTE_G; 353 sysmap_lmem[i].CMAP2 = PTE_G; 354 sysmap_lmem[i].CADDR1 = (caddr_t)virtual_avail; 355 virtual_avail += PAGE_SIZE; 356 sysmap_lmem[i].CADDR2 = (caddr_t)virtual_avail; 357 virtual_avail += PAGE_SIZE; 358 sysmap_lmem[i].valid1 = sysmap_lmem[i].valid2 = 0; 359 PMAP_LGMEM_LOCK_INIT(&sysmap_lmem[i]); 360 } 361 } 362 virtual_sys_start = (caddr_t)virtual_avail; 363 /* 364 * Allocate segment table for the kernel 365 */ 366 kernel_segmap = (pd_entry_t *)pmap_steal_memory(PAGE_SIZE); 367 368 /* 369 * Allocate second level page tables for the kernel 370 */ 371 nkpt = NKPT; 372 if (memory_larger_than_512meg) { 373 /* 374 * If we have a large memory system we CANNOT afford to hit 375 * pmap_growkernel() and allocate memory. Since we MAY end 376 * up with a page that is NOT mappable. For that reason we 377 * up front grab more. Normall NKPT is 120 (YMMV see pmap.h) 378 * this gives us 480meg of kernel virtual addresses at the 379 * cost of 120 pages (each page gets us 4 Meg). Since the 380 * kernel starts at virtual_avail, we can use this to 381 * calculate how many entris are left from there to the end 382 * of the segmap, we want to allocate all of it, which would 383 * be somewhere above 0xC0000000 - 0xFFFFFFFF which results 384 * in about 256 entries or so instead of the 120. 385 */ 386 nkpt = (PAGE_SIZE / sizeof(pd_entry_t)) - (virtual_avail >> SEGSHIFT); 387 } 388 pgtab = (pt_entry_t *)pmap_steal_memory(PAGE_SIZE * nkpt); 389 390 /* 391 * The R[4-7]?00 stores only one copy of the Global bit in the 392 * translation lookaside buffer for each 2 page entry. Thus invalid 393 * entrys must have the Global bit set so when Entry LO and Entry HI 394 * G bits are anded together they will produce a global bit to store 395 * in the tlb. 396 */ 397 for (i = 0, pte = pgtab; i < (nkpt * NPTEPG); i++, pte++) 398 *pte = PTE_G; 399 400 printf("Va=0x%x Ve=%x\n", virtual_avail, virtual_end); 401 /* 402 * The segment table contains the KVA of the pages in the second 403 * level page table. 404 */ 405 printf("init kernel_segmap va >> = %d nkpt:%d\n", 406 (virtual_avail >> SEGSHIFT), 407 nkpt); 408 for (i = 0, j = (virtual_avail >> SEGSHIFT); i < nkpt; i++, j++) 409 kernel_segmap[j] = (pd_entry_t)(pgtab + (i * NPTEPG)); 410 411 avail_start = phys_avail[0]; 412 for (i = 0; phys_avail[i + 2]; i += 2); 413 avail_end = phys_avail[i + 1]; 414 415 /* 416 * The kernel's pmap is statically allocated so we don't have to use 417 * pmap_create, which is unlikely to work correctly at this part of 418 * the boot sequence (XXX and which no longer exists). 419 */ 420 kernel_pmap = &kernel_pmap_store; 421 422 PMAP_LOCK_INIT(kernel_pmap); 423 kernel_pmap->pm_segtab = kernel_segmap; 424 kernel_pmap->pm_active = ~0; 425 TAILQ_INIT(&kernel_pmap->pm_pvlist); 426 printf("avail_start:0x%x avail_end:0x%x\n", 427 avail_start, avail_end); 428 429 kernel_pmap->pm_asid[PCPU_GET(cpuid)].asid = PMAP_ASID_RESERVED; 430 kernel_pmap->pm_asid[PCPU_GET(cpuid)].gen = 0; 431 pmap_max_asid = VMNUM_PIDS; 432 MachSetPID(0); 433} 434 435/* 436 * Initialize a vm_page's machine-dependent fields. 437 */ 438void 439pmap_page_init(vm_page_t m) 440{ 441 442 TAILQ_INIT(&m->md.pv_list); 443 m->md.pv_list_count = 0; 444 m->md.pv_flags = 0; 445} 446 447/* 448 * Initialize the pmap module. 449 * Called by vm_init, to initialize any structures that the pmap 450 * system needs to map virtual memory. 451 * pmap_init has been enhanced to support in a fairly consistant 452 * way, discontiguous physical memory. 453 */ 454void 455pmap_init(void) 456{ 457 458 if (need_wired_tlb_page_pool) 459 pmap_init_fpage(); 460 /* 461 * Initialize the address space (zone) for the pv entries. Set a 462 * high water mark so that the system can recover from excessive 463 * numbers of pv entries. 464 */ 465 pvzone = uma_zcreate("PV ENTRY", sizeof(struct pv_entry), NULL, NULL, 466 NULL, NULL, UMA_ALIGN_PTR, UMA_ZONE_VM | UMA_ZONE_NOFREE); 467 pv_entry_max = PMAP_SHPGPERPROC * maxproc + cnt.v_page_count; 468 pv_entry_high_water = 9 * (pv_entry_max / 10); 469 uma_zone_set_obj(pvzone, &pvzone_obj, pv_entry_max); 470} 471 472/*************************************************** 473 * Low level helper routines..... 474 ***************************************************/ 475 476#if defined(PMAP_DIAGNOSTIC) 477 478/* 479 * This code checks for non-writeable/modified pages. 480 * This should be an invalid condition. 481 */ 482static int 483pmap_nw_modified(pt_entry_t pte) 484{ 485 if ((pte & (PTE_M | PTE_RO)) == (PTE_M | PTE_RO)) 486 return (1); 487 else 488 return (0); 489} 490 491#endif 492 493static void 494pmap_invalidate_all(pmap_t pmap) 495{ 496#ifdef SMP 497 smp_rendezvous(0, pmap_invalidate_all_action, 0, (void *)pmap); 498} 499 500static void 501pmap_invalidate_all_action(void *arg) 502{ 503 pmap_t pmap = (pmap_t)arg; 504 505#endif 506 507 if (pmap->pm_active & PCPU_GET(cpumask)) { 508 pmap_TLB_invalidate_all(); 509 } else 510 pmap->pm_asid[PCPU_GET(cpuid)].gen = 0; 511} 512 513struct pmap_invalidate_page_arg { 514 pmap_t pmap; 515 vm_offset_t va; 516}; 517 518static __inline void 519pmap_invalidate_page(pmap_t pmap, vm_offset_t va) 520{ 521#ifdef SMP 522 struct pmap_invalidate_page_arg arg; 523 524 arg.pmap = pmap; 525 arg.va = va; 526 527 smp_rendezvous(0, pmap_invalidate_page_action, 0, (void *)&arg); 528} 529 530static void 531pmap_invalidate_page_action(void *arg) 532{ 533 pmap_t pmap = ((struct pmap_invalidate_page_arg *)arg)->pmap; 534 vm_offset_t va = ((struct pmap_invalidate_page_arg *)arg)->va; 535 536#endif 537 538 if (is_kernel_pmap(pmap)) { 539 pmap_TLB_invalidate_kernel(va); 540 return; 541 } 542 if (pmap->pm_asid[PCPU_GET(cpuid)].gen != PCPU_GET(asid_generation)) 543 return; 544 else if (!(pmap->pm_active & PCPU_GET(cpumask))) { 545 pmap->pm_asid[PCPU_GET(cpuid)].gen = 0; 546 return; 547 } 548 va = pmap_va_asid(pmap, (va & ~PGOFSET)); 549 mips_TBIS(va); 550} 551 552static void 553pmap_TLB_invalidate_kernel(vm_offset_t va) 554{ 555 u_int32_t pid; 556 557 MachTLBGetPID(pid); 558 va = va | (pid << VMTLB_PID_SHIFT); 559 mips_TBIS(va); 560} 561 562struct pmap_update_page_arg { 563 pmap_t pmap; 564 vm_offset_t va; 565 pt_entry_t pte; 566}; 567 568void 569pmap_update_page(pmap_t pmap, vm_offset_t va, pt_entry_t pte) 570{ 571#ifdef SMP 572 struct pmap_update_page_arg arg; 573 574 arg.pmap = pmap; 575 arg.va = va; 576 arg.pte = pte; 577 578 smp_rendezvous(0, pmap_update_page_action, 0, (void *)&arg); 579} 580 581static void 582pmap_update_page_action(void *arg) 583{ 584 pmap_t pmap = ((struct pmap_update_page_arg *)arg)->pmap; 585 vm_offset_t va = ((struct pmap_update_page_arg *)arg)->va; 586 pt_entry_t pte = ((struct pmap_update_page_arg *)arg)->pte; 587 588#endif 589 if (is_kernel_pmap(pmap)) { 590 pmap_TLB_update_kernel(va, pte); 591 return; 592 } 593 if (pmap->pm_asid[PCPU_GET(cpuid)].gen != PCPU_GET(asid_generation)) 594 return; 595 else if (!(pmap->pm_active & PCPU_GET(cpumask))) { 596 pmap->pm_asid[PCPU_GET(cpuid)].gen = 0; 597 return; 598 } 599 va = pmap_va_asid(pmap, va); 600 MachTLBUpdate(va, pte); 601} 602 603static void 604pmap_TLB_update_kernel(vm_offset_t va, pt_entry_t pte) 605{ 606 u_int32_t pid; 607 608 MachTLBGetPID(pid); 609 va = va | (pid << VMTLB_PID_SHIFT); 610 611 MachTLBUpdate(va, pte); 612} 613 614/* 615 * Routine: pmap_extract 616 * Function: 617 * Extract the physical page address associated 618 * with the given map/virtual_address pair. 619 */ 620vm_paddr_t 621pmap_extract(pmap_t pmap, vm_offset_t va) 622{ 623 pt_entry_t *pte; 624 vm_offset_t retval = 0; 625 626 PMAP_LOCK(pmap); 627 pte = pmap_pte(pmap, va); 628 if (pte) { 629 retval = mips_tlbpfn_to_paddr(*pte) | (va & PAGE_MASK); 630 } 631 PMAP_UNLOCK(pmap); 632 return retval; 633} 634 635/* 636 * Routine: pmap_extract_and_hold 637 * Function: 638 * Atomically extract and hold the physical page 639 * with the given pmap and virtual address pair 640 * if that mapping permits the given protection. 641 */ 642vm_page_t 643pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot) 644{ 645 pt_entry_t pte; 646 vm_page_t m; 647 648 m = NULL; 649 vm_page_lock_queues(); 650 PMAP_LOCK(pmap); 651 652 pte = *pmap_pte(pmap, va); 653 if (pte != 0 && pmap_pte_v(&pte) && 654 ((pte & PTE_RW) || (prot & VM_PROT_WRITE) == 0)) { 655 m = PHYS_TO_VM_PAGE(mips_tlbpfn_to_paddr(pte)); 656 vm_page_hold(m); 657 } 658 vm_page_unlock_queues(); 659 PMAP_UNLOCK(pmap); 660 return (m); 661} 662 663/*************************************************** 664 * Low level mapping routines..... 665 ***************************************************/ 666 667/* 668 * add a wired page to the kva 669 */ 670 /* PMAP_INLINE */ void 671pmap_kenter(vm_offset_t va, vm_paddr_t pa) 672{ 673 register pt_entry_t *pte; 674 pt_entry_t npte, opte; 675 676#ifdef PMAP_DEBUG 677 printf("pmap_kenter: va: 0x%08x -> pa: 0x%08x\n", va, pa); 678#endif 679 npte = mips_paddr_to_tlbpfn(pa) | PTE_RW | PTE_V | PTE_G | PTE_W; 680 681 if (is_cacheable_mem(pa)) 682 npte |= PTE_CACHE; 683 else 684 npte |= PTE_UNCACHED; 685 686 pte = pmap_pte(kernel_pmap, va); 687 opte = *pte; 688 *pte = npte; 689 690 pmap_update_page(kernel_pmap, va, npte); 691} 692 693/* 694 * remove a page from the kernel pagetables 695 */ 696 /* PMAP_INLINE */ void 697pmap_kremove(vm_offset_t va) 698{ 699 register pt_entry_t *pte; 700 701 pte = pmap_pte(kernel_pmap, va); 702 *pte = PTE_G; 703 pmap_invalidate_page(kernel_pmap, va); 704} 705 706/* 707 * Used to map a range of physical addresses into kernel 708 * virtual address space. 709 * 710 * The value passed in '*virt' is a suggested virtual address for 711 * the mapping. Architectures which can support a direct-mapped 712 * physical to virtual region can return the appropriate address 713 * within that region, leaving '*virt' unchanged. Other 714 * architectures should map the pages starting at '*virt' and 715 * update '*virt' with the first usable address after the mapped 716 * region. 717 */ 718vm_offset_t 719pmap_map(vm_offset_t *virt, vm_offset_t start, vm_offset_t end, int prot) 720{ 721 vm_offset_t va, sva; 722 723 va = sva = *virt; 724 while (start < end) { 725 pmap_kenter(va, start); 726 va += PAGE_SIZE; 727 start += PAGE_SIZE; 728 } 729 *virt = va; 730 return (sva); 731} 732 733/* 734 * Add a list of wired pages to the kva 735 * this routine is only used for temporary 736 * kernel mappings that do not need to have 737 * page modification or references recorded. 738 * Note that old mappings are simply written 739 * over. The page *must* be wired. 740 */ 741void 742pmap_qenter(vm_offset_t va, vm_page_t *m, int count) 743{ 744 int i; 745 746 for (i = 0; i < count; i++) { 747 pmap_kenter(va, VM_PAGE_TO_PHYS(m[i])); 748 va += PAGE_SIZE; 749 } 750} 751 752/* 753 * this routine jerks page mappings from the 754 * kernel -- it is meant only for temporary mappings. 755 */ 756void 757pmap_qremove(vm_offset_t va, int count) 758{ 759 while (count-- > 0) { 760 pmap_kremove(va); 761 va += PAGE_SIZE; 762 } 763} 764 765/*************************************************** 766 * Page table page management routines..... 767 ***************************************************/ 768 769/* 770 * floating pages (FPAGES) management routines 771 * 772 * FPAGES are the reserved virtual memory areas which can be 773 * mapped to any physical memory. This gets used typically 774 * in the following functions: 775 * 776 * pmap_zero_page 777 * pmap_copy_page 778 */ 779 780/* 781 * Create the floating pages, aka FPAGES! 782 */ 783static void 784pmap_init_fpage() 785{ 786 vm_offset_t kva; 787 int i, j; 788 struct sysmaps *sysmaps; 789 790 /* 791 * We allocate a total of (FPAGES*MAXCPU + FPAGES_SHARED + 1) pages 792 * at first. FPAGES & FPAGES_SHARED should be EVEN Then we'll adjust 793 * 'kva' to be even-page aligned so that the fpage area can be wired 794 * in the TLB with a single TLB entry. 795 */ 796 kva = kmem_alloc_nofault(kernel_map, 797 (FPAGES * MAXCPU + 1 + FPAGES_SHARED) * PAGE_SIZE); 798 if ((void *)kva == NULL) 799 panic("pmap_init_fpage: fpage allocation failed"); 800 801 /* 802 * Make up start at an even page number so we can wire down the 803 * fpage area in the tlb with a single tlb entry. 804 */ 805 if ((((vm_offset_t)kva) >> PGSHIFT) & 1) { 806 /* 807 * 'kva' is not even-page aligned. Adjust it and free the 808 * first page which is unused. 809 */ 810 kmem_free(kernel_map, (vm_offset_t)kva, NBPG); 811 kva = ((vm_offset_t)kva) + NBPG; 812 } else { 813 /* 814 * 'kva' is even page aligned. We don't need the last page, 815 * free it. 816 */ 817 kmem_free(kernel_map, ((vm_offset_t)kva) + FSPACE, NBPG); 818 } 819 820 for (i = 0; i < MAXCPU; i++) { 821 sysmaps = &sysmaps_pcpu[i]; 822 mtx_init(&sysmaps->lock, "SYSMAPS", NULL, MTX_DEF); 823 824 /* Assign FPAGES pages to the CPU */ 825 for (j = 0; j < FPAGES; j++) 826 sysmaps->fp[j].kva = kva + (j) * PAGE_SIZE; 827 kva = ((vm_offset_t)kva) + (FPAGES * PAGE_SIZE); 828 } 829 830 /* 831 * An additional 2 pages are needed, one for pmap_zero_page_idle() 832 * and one for coredump. These pages are shared by all cpu's 833 */ 834 fpages_shared[PMAP_FPAGE3].kva = kva; 835 fpages_shared[PMAP_FPAGE_KENTER_TEMP].kva = kva + PAGE_SIZE; 836} 837 838/* 839 * Map the page to the fpage virtual address as specified thru' fpage id 840 */ 841vm_offset_t 842pmap_map_fpage(vm_paddr_t pa, struct fpage *fp, boolean_t check_unmaped) 843{ 844 vm_offset_t kva; 845 register pt_entry_t *pte; 846 pt_entry_t npte; 847 848 KASSERT(curthread->td_pinned > 0, ("curthread not pinned")); 849 /* 850 * Check if the fpage is free 851 */ 852 if (fp->state) { 853 if (check_unmaped == TRUE) 854 pmap_unmap_fpage(pa, fp); 855 else 856 panic("pmap_map_fpage: fpage is busy"); 857 } 858 fp->state = TRUE; 859 kva = fp->kva; 860 861 npte = mips_paddr_to_tlbpfn(pa) | PTE_RW | PTE_V | PTE_G | PTE_W | PTE_CACHE; 862 pte = pmap_pte(kernel_pmap, kva); 863 *pte = npte; 864 865 pmap_TLB_update_kernel(kva, npte); 866 867 return (kva); 868} 869 870/* 871 * Unmap the page from the fpage virtual address as specified thru' fpage id 872 */ 873void 874pmap_unmap_fpage(vm_paddr_t pa, struct fpage *fp) 875{ 876 vm_offset_t kva; 877 register pt_entry_t *pte; 878 879 KASSERT(curthread->td_pinned > 0, ("curthread not pinned")); 880 /* 881 * Check if the fpage is busy 882 */ 883 if (!(fp->state)) { 884 panic("pmap_unmap_fpage: fpage is free"); 885 } 886 kva = fp->kva; 887 888 pte = pmap_pte(kernel_pmap, kva); 889 *pte = PTE_G; 890 pmap_TLB_invalidate_kernel(kva); 891 892 fp->state = FALSE; 893 894 /* 895 * Should there be any flush operation at the end? 896 */ 897} 898 899/* Revision 1.507 900 * 901 * Simplify the reference counting of page table pages. Specifically, use 902 * the page table page's wired count rather than its hold count to contain 903 * the reference count. 904 */ 905 906/* 907 * This routine unholds page table pages, and if the hold count 908 * drops to zero, then it decrements the wire count. 909 */ 910static int 911_pmap_unwire_pte_hold(pmap_t pmap, vm_page_t m) 912{ 913 914 /* 915 * unmap the page table page 916 */ 917 pmap->pm_segtab[m->pindex] = 0; 918 --pmap->pm_stats.resident_count; 919 920 if (pmap->pm_ptphint == m) 921 pmap->pm_ptphint = NULL; 922 923 /* 924 * If the page is finally unwired, simply free it. 925 */ 926 vm_page_free_zero(m); 927 atomic_subtract_int(&cnt.v_wire_count, 1); 928 return (1); 929} 930 931static PMAP_INLINE int 932pmap_unwire_pte_hold(pmap_t pmap, vm_page_t m) 933{ 934 --m->wire_count; 935 if (m->wire_count == 0) 936 return (_pmap_unwire_pte_hold(pmap, m)); 937 else 938 return (0); 939} 940 941/* 942 * After removing a page table entry, this routine is used to 943 * conditionally free the page, and manage the hold/wire counts. 944 */ 945static int 946pmap_unuse_pt(pmap_t pmap, vm_offset_t va, vm_page_t mpte) 947{ 948 unsigned ptepindex; 949 pd_entry_t pteva; 950 951 if (va >= VM_MAXUSER_ADDRESS) 952 return (0); 953 954 if (mpte == NULL) { 955 ptepindex = (va >> SEGSHIFT); 956 if (pmap->pm_ptphint && 957 (pmap->pm_ptphint->pindex == ptepindex)) { 958 mpte = pmap->pm_ptphint; 959 } else { 960 pteva = *pmap_pde(pmap, va); 961 mpte = PHYS_TO_VM_PAGE(MIPS_CACHED_TO_PHYS(pteva)); 962 pmap->pm_ptphint = mpte; 963 } 964 } 965 return pmap_unwire_pte_hold(pmap, mpte); 966} 967 968void 969pmap_pinit0(pmap_t pmap) 970{ 971 int i; 972 973 PMAP_LOCK_INIT(pmap); 974 pmap->pm_segtab = kernel_segmap; 975 pmap->pm_active = 0; 976 pmap->pm_ptphint = NULL; 977 for (i = 0; i < MAXCPU; i++) { 978 pmap->pm_asid[i].asid = PMAP_ASID_RESERVED; 979 pmap->pm_asid[i].gen = 0; 980 } 981 PCPU_SET(curpmap, pmap); 982 TAILQ_INIT(&pmap->pm_pvlist); 983 bzero(&pmap->pm_stats, sizeof pmap->pm_stats); 984} 985 986/* 987 * Initialize a preallocated and zeroed pmap structure, 988 * such as one in a vmspace structure. 989 */ 990int 991pmap_pinit(pmap_t pmap) 992{ 993 vm_page_t ptdpg; 994 int i; 995 int req; 996 997 PMAP_LOCK_INIT(pmap); 998 999 req = VM_ALLOC_NOOBJ | VM_ALLOC_NORMAL | VM_ALLOC_WIRED | 1000 VM_ALLOC_ZERO; 1001 1002#ifdef VM_ALLOC_WIRED_TLB_PG_POOL 1003 if (need_wired_tlb_page_pool) 1004 req |= VM_ALLOC_WIRED_TLB_PG_POOL; 1005#endif 1006 /* 1007 * allocate the page directory page 1008 */ 1009 ptdpg = vm_page_alloc(NULL, NUSERPGTBLS, req); 1010 1011#if 0 1012 /* I think we can just delete these, now that PG_BUSY is gone */ 1013 vm_page_lock_queues(); 1014 vm_page_flag_clear(ptdpg, PTE_BUSY); /* not usually mapped */ 1015#endif 1016 ptdpg->valid = VM_PAGE_BITS_ALL; 1017 1018#if 0 1019 vm_page_unlock_queues(); 1020#endif 1021 1022 pmap->pm_segtab = (pd_entry_t *) 1023 MIPS_PHYS_TO_CACHED(VM_PAGE_TO_PHYS(ptdpg)); 1024 if ((ptdpg->flags & PG_ZERO) == 0) 1025 bzero(pmap->pm_segtab, PAGE_SIZE); 1026 1027 pmap->pm_active = 0; 1028 pmap->pm_ptphint = NULL; 1029 for (i = 0; i < MAXCPU; i++) { 1030 pmap->pm_asid[i].asid = PMAP_ASID_RESERVED; 1031 pmap->pm_asid[i].gen = 0; 1032 } 1033 TAILQ_INIT(&pmap->pm_pvlist); 1034 bzero(&pmap->pm_stats, sizeof pmap->pm_stats); 1035 1036 return (1); 1037} 1038 1039/* 1040 * this routine is called if the page table page is not 1041 * mapped correctly. 1042 */ 1043static vm_page_t 1044_pmap_allocpte(pmap_t pmap, unsigned ptepindex, int flags) 1045{ 1046 vm_offset_t pteva, ptepa; 1047 vm_page_t m; 1048 int req; 1049 1050 KASSERT((flags & (M_NOWAIT | M_WAITOK)) == M_NOWAIT || 1051 (flags & (M_NOWAIT | M_WAITOK)) == M_WAITOK, 1052 ("_pmap_allocpte: flags is neither M_NOWAIT nor M_WAITOK")); 1053 1054 req = VM_ALLOC_WIRED | VM_ALLOC_ZERO | VM_ALLOC_NOOBJ; 1055#ifdef VM_ALLOC_WIRED_TLB_PG_POOL 1056 if (need_wired_tlb_page_pool) 1057 req |= VM_ALLOC_WIRED_TLB_PG_POOL; 1058#endif 1059 /* 1060 * Find or fabricate a new pagetable page 1061 */ 1062 if ((m = vm_page_alloc(NULL, ptepindex, req)) == NULL) { 1063 if (flags & M_WAITOK) { 1064 PMAP_UNLOCK(pmap); 1065 vm_page_unlock_queues(); 1066 VM_WAIT; 1067 vm_page_lock_queues(); 1068 PMAP_LOCK(pmap); 1069 } 1070 /* 1071 * Indicate the need to retry. While waiting, the page 1072 * table page may have been allocated. 1073 */ 1074 return (NULL); 1075 } 1076 if ((m->flags & PG_ZERO) == 0) 1077 pmap_zero_page(m); 1078 1079 KASSERT(m->queue == PQ_NONE, 1080 ("_pmap_allocpte: %p->queue != PQ_NONE", m)); 1081 1082 /* 1083 * Map the pagetable page into the process address space, if it 1084 * isn't already there. 1085 */ 1086 1087 pmap->pm_stats.resident_count++; 1088 1089 ptepa = VM_PAGE_TO_PHYS(m); 1090 pteva = MIPS_PHYS_TO_CACHED(ptepa); 1091 pmap->pm_segtab[ptepindex] = (pd_entry_t)pteva; 1092 1093 /* 1094 * Set the page table hint 1095 */ 1096 pmap->pm_ptphint = m; 1097 1098 /* 1099 * Kernel page tables are allocated in pmap_bootstrap() or 1100 * pmap_growkernel(). 1101 */ 1102 if (is_kernel_pmap(pmap)) 1103 panic("_pmap_allocpte() called for kernel pmap\n"); 1104 1105 m->valid = VM_PAGE_BITS_ALL; 1106 vm_page_flag_clear(m, PG_ZERO); 1107 1108 return (m); 1109} 1110 1111static vm_page_t 1112pmap_allocpte(pmap_t pmap, vm_offset_t va, int flags) 1113{ 1114 unsigned ptepindex; 1115 vm_offset_t pteva; 1116 vm_page_t m; 1117 1118 KASSERT((flags & (M_NOWAIT | M_WAITOK)) == M_NOWAIT || 1119 (flags & (M_NOWAIT | M_WAITOK)) == M_WAITOK, 1120 ("pmap_allocpte: flags is neither M_NOWAIT nor M_WAITOK")); 1121 1122 /* 1123 * Calculate pagetable page index 1124 */ 1125 ptepindex = va >> SEGSHIFT; 1126retry: 1127 /* 1128 * Get the page directory entry 1129 */ 1130 pteva = (vm_offset_t)pmap->pm_segtab[ptepindex]; 1131 1132 /* 1133 * If the page table page is mapped, we just increment the hold 1134 * count, and activate it. 1135 */ 1136 if (pteva) { 1137 /* 1138 * In order to get the page table page, try the hint first. 1139 */ 1140 if (pmap->pm_ptphint && 1141 (pmap->pm_ptphint->pindex == ptepindex)) { 1142 m = pmap->pm_ptphint; 1143 } else { 1144 m = PHYS_TO_VM_PAGE(MIPS_CACHED_TO_PHYS(pteva)); 1145 pmap->pm_ptphint = m; 1146 } 1147 m->wire_count++; 1148 } else { 1149 /* 1150 * Here if the pte page isn't mapped, or if it has been 1151 * deallocated. 1152 */ 1153 m = _pmap_allocpte(pmap, ptepindex, flags); 1154 if (m == NULL && (flags & M_WAITOK)) 1155 goto retry; 1156 } 1157 return m; 1158} 1159 1160 1161/*************************************************** 1162* Pmap allocation/deallocation routines. 1163 ***************************************************/ 1164/* 1165 * Revision 1.397 1166 * - Merged pmap_release and pmap_release_free_page. When pmap_release is 1167 * called only the page directory page(s) can be left in the pmap pte 1168 * object, since all page table pages will have been freed by 1169 * pmap_remove_pages and pmap_remove. In addition, there can only be one 1170 * reference to the pmap and the page directory is wired, so the page(s) 1171 * can never be busy. So all there is to do is clear the magic mappings 1172 * from the page directory and free the page(s). 1173 */ 1174 1175 1176/* 1177 * Release any resources held by the given physical map. 1178 * Called when a pmap initialized by pmap_pinit is being released. 1179 * Should only be called if the map contains no valid mappings. 1180 */ 1181void 1182pmap_release(pmap_t pmap) 1183{ 1184 vm_page_t ptdpg; 1185 1186 KASSERT(pmap->pm_stats.resident_count == 0, 1187 ("pmap_release: pmap resident count %ld != 0", 1188 pmap->pm_stats.resident_count)); 1189 1190 ptdpg = PHYS_TO_VM_PAGE(MIPS_CACHED_TO_PHYS(pmap->pm_segtab)); 1191 1192 vm_page_lock_queues(); 1193 ptdpg->wire_count--; 1194 atomic_subtract_int(&cnt.v_wire_count, 1); 1195 vm_page_free_zero(ptdpg); 1196 vm_page_unlock_queues(); 1197} 1198 1199/* 1200 * grow the number of kernel page table entries, if needed 1201 */ 1202void 1203pmap_growkernel(vm_offset_t addr) 1204{ 1205 vm_offset_t ptppaddr; 1206 vm_page_t nkpg; 1207 pt_entry_t *pte; 1208 int i, req; 1209 1210 mtx_assert(&kernel_map->system_mtx, MA_OWNED); 1211 if (kernel_vm_end == 0) { 1212 kernel_vm_end = VM_MIN_KERNEL_ADDRESS + VM_KERNEL_ALLOC_OFFSET; 1213 nkpt = 0; 1214 while (segtab_pde(kernel_segmap, kernel_vm_end)) { 1215 kernel_vm_end = (kernel_vm_end + PAGE_SIZE * NPTEPG) & 1216 ~(PAGE_SIZE * NPTEPG - 1); 1217 nkpt++; 1218 if (kernel_vm_end - 1 >= kernel_map->max_offset) { 1219 kernel_vm_end = kernel_map->max_offset; 1220 break; 1221 } 1222 } 1223 } 1224 addr = (addr + PAGE_SIZE * NPTEPG) & ~(PAGE_SIZE * NPTEPG - 1); 1225 if (addr - 1 >= kernel_map->max_offset) 1226 addr = kernel_map->max_offset; 1227 while (kernel_vm_end < addr) { 1228 if (segtab_pde(kernel_segmap, kernel_vm_end)) { 1229 kernel_vm_end = (kernel_vm_end + PAGE_SIZE * NPTEPG) & 1230 ~(PAGE_SIZE * NPTEPG - 1); 1231 if (kernel_vm_end - 1 >= kernel_map->max_offset) { 1232 kernel_vm_end = kernel_map->max_offset; 1233 break; 1234 } 1235 continue; 1236 } 1237 /* 1238 * This index is bogus, but out of the way 1239 */ 1240 req = VM_ALLOC_INTERRUPT | VM_ALLOC_WIRED | VM_ALLOC_NOOBJ; 1241#ifdef VM_ALLOC_WIRED_TLB_PG_POOL 1242 if (need_wired_tlb_page_pool) 1243 req |= VM_ALLOC_WIRED_TLB_PG_POOL; 1244#endif 1245 nkpg = vm_page_alloc(NULL, nkpt, req); 1246 if (!nkpg) 1247 panic("pmap_growkernel: no memory to grow kernel"); 1248 1249 nkpt++; 1250 1251 ptppaddr = VM_PAGE_TO_PHYS(nkpg); 1252 if (ptppaddr >= MIPS_KSEG0_LARGEST_PHYS) { 1253 /* 1254 * We need to do something here, but I am not sure 1255 * what. We can access anything in the 0 - 512Meg 1256 * region, but if we get a page to go in the kernel 1257 * segmap that is outside of of that we really need 1258 * to have another mapping beyond the temporary ones 1259 * I have. Not sure how to do this yet. FIXME FIXME. 1260 */ 1261 panic("Gak, can't handle a k-page table outside of lower 512Meg"); 1262 } 1263 pte = (pt_entry_t *)MIPS_PHYS_TO_CACHED(ptppaddr); 1264 segtab_pde(kernel_segmap, kernel_vm_end) = (pd_entry_t)pte; 1265 1266 /* 1267 * The R[4-7]?00 stores only one copy of the Global bit in 1268 * the translation lookaside buffer for each 2 page entry. 1269 * Thus invalid entrys must have the Global bit set so when 1270 * Entry LO and Entry HI G bits are anded together they will 1271 * produce a global bit to store in the tlb. 1272 */ 1273 for (i = 0; i < NPTEPG; i++, pte++) 1274 *pte = PTE_G; 1275 1276 kernel_vm_end = (kernel_vm_end + PAGE_SIZE * NPTEPG) & 1277 ~(PAGE_SIZE * NPTEPG - 1); 1278 if (kernel_vm_end - 1 >= kernel_map->max_offset) { 1279 kernel_vm_end = kernel_map->max_offset; 1280 break; 1281 } 1282 } 1283} 1284 1285/*************************************************** 1286* page management routines. 1287 ***************************************************/ 1288 1289/* 1290 * free the pv_entry back to the free list 1291 */ 1292static PMAP_INLINE void 1293free_pv_entry(pv_entry_t pv) 1294{ 1295 1296 pv_entry_count--; 1297 uma_zfree(pvzone, pv); 1298} 1299 1300/* 1301 * get a new pv_entry, allocating a block from the system 1302 * when needed. 1303 * the memory allocation is performed bypassing the malloc code 1304 * because of the possibility of allocations at interrupt time. 1305 */ 1306static pv_entry_t 1307get_pv_entry(pmap_t locked_pmap) 1308{ 1309 static const struct timeval printinterval = { 60, 0 }; 1310 static struct timeval lastprint; 1311 struct vpgqueues *vpq; 1312 pt_entry_t *pte, oldpte; 1313 pmap_t pmap; 1314 pv_entry_t allocated_pv, next_pv, pv; 1315 vm_offset_t va; 1316 vm_page_t m; 1317 1318 PMAP_LOCK_ASSERT(locked_pmap, MA_OWNED); 1319 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1320 allocated_pv = uma_zalloc(pvzone, M_NOWAIT); 1321 if (allocated_pv != NULL) { 1322 pv_entry_count++; 1323 if (pv_entry_count > pv_entry_high_water) 1324 pagedaemon_wakeup(); 1325 else 1326 return (allocated_pv); 1327 } 1328 /* 1329 * Reclaim pv entries: At first, destroy mappings to inactive 1330 * pages. After that, if a pv entry is still needed, destroy 1331 * mappings to active pages. 1332 */ 1333 if (ratecheck(&lastprint, &printinterval)) 1334 printf("Approaching the limit on PV entries, " 1335 "increase the vm.pmap.shpgperproc tunable.\n"); 1336 vpq = &vm_page_queues[PQ_INACTIVE]; 1337retry: 1338 TAILQ_FOREACH(m, &vpq->pl, pageq) { 1339 if (m->hold_count || m->busy) 1340 continue; 1341 TAILQ_FOREACH_SAFE(pv, &m->md.pv_list, pv_list, next_pv) { 1342 va = pv->pv_va; 1343 pmap = pv->pv_pmap; 1344 /* Avoid deadlock and lock recursion. */ 1345 if (pmap > locked_pmap) 1346 PMAP_LOCK(pmap); 1347 else if (pmap != locked_pmap && !PMAP_TRYLOCK(pmap)) 1348 continue; 1349 pmap->pm_stats.resident_count--; 1350 pte = pmap_pte(pmap, va); 1351 KASSERT(pte != NULL, ("pte")); 1352 oldpte = loadandclear((u_int *)pte); 1353 if (is_kernel_pmap(pmap)) 1354 *pte = PTE_G; 1355 KASSERT((oldpte & PTE_W) == 0, 1356 ("wired pte for unwired page")); 1357 if (m->md.pv_flags & PV_TABLE_REF) 1358 vm_page_flag_set(m, PG_REFERENCED); 1359 if (oldpte & PTE_M) 1360 vm_page_dirty(m); 1361 pmap_invalidate_page(pmap, va); 1362 TAILQ_REMOVE(&pmap->pm_pvlist, pv, pv_plist); 1363 m->md.pv_list_count--; 1364 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list); 1365 if (TAILQ_EMPTY(&m->md.pv_list)) { 1366 vm_page_flag_clear(m, PG_WRITEABLE); 1367 m->md.pv_flags &= ~(PV_TABLE_REF | PV_TABLE_MOD); 1368 } 1369 pmap_unuse_pt(pmap, va, pv->pv_ptem); 1370 if (pmap != locked_pmap) 1371 PMAP_UNLOCK(pmap); 1372 if (allocated_pv == NULL) 1373 allocated_pv = pv; 1374 else 1375 free_pv_entry(pv); 1376 } 1377 } 1378 if (allocated_pv == NULL) { 1379 if (vpq == &vm_page_queues[PQ_INACTIVE]) { 1380 vpq = &vm_page_queues[PQ_ACTIVE]; 1381 goto retry; 1382 } 1383 panic("get_pv_entry: increase the vm.pmap.shpgperproc tunable"); 1384 } 1385 return (allocated_pv); 1386} 1387 1388/* 1389 * Revision 1.370 1390 * 1391 * Move pmap_collect() out of the machine-dependent code, rename it 1392 * to reflect its new location, and add page queue and flag locking. 1393 * 1394 * Notes: (1) alpha, i386, and ia64 had identical implementations 1395 * of pmap_collect() in terms of machine-independent interfaces; 1396 * (2) sparc64 doesn't require it; (3) powerpc had it as a TODO. 1397 * 1398 * MIPS implementation was identical to alpha [Junos 8.2] 1399 */ 1400 1401/* 1402 * If it is the first entry on the list, it is actually 1403 * in the header and we must copy the following entry up 1404 * to the header. Otherwise we must search the list for 1405 * the entry. In either case we free the now unused entry. 1406 */ 1407 1408static void 1409pmap_remove_entry(struct pmap *pmap, vm_page_t m, vm_offset_t va) 1410{ 1411 pv_entry_t pv; 1412 1413 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1414 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1415 if (m->md.pv_list_count < pmap->pm_stats.resident_count) { 1416 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 1417 if (pmap == pv->pv_pmap && va == pv->pv_va) 1418 break; 1419 } 1420 } else { 1421 TAILQ_FOREACH(pv, &pmap->pm_pvlist, pv_plist) { 1422 if (va == pv->pv_va) 1423 break; 1424 } 1425 } 1426 1427 KASSERT(pv != NULL, ("pmap_remove_entry: pv not found")); 1428 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list); 1429 m->md.pv_list_count--; 1430 if (TAILQ_FIRST(&m->md.pv_list) == NULL) 1431 vm_page_flag_clear(m, PG_WRITEABLE); 1432 1433 TAILQ_REMOVE(&pmap->pm_pvlist, pv, pv_plist); 1434 free_pv_entry(pv); 1435} 1436 1437/* 1438 * Create a pv entry for page at pa for 1439 * (pmap, va). 1440 */ 1441static void 1442pmap_insert_entry(pmap_t pmap, vm_offset_t va, vm_page_t mpte, vm_page_t m, 1443 boolean_t wired) 1444{ 1445 1446 pv_entry_t pv; 1447 1448 pv = get_pv_entry(pmap); 1449 pv->pv_va = va; 1450 pv->pv_pmap = pmap; 1451 pv->pv_ptem = mpte; 1452 pv->pv_wired = wired; 1453 1454 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1455 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1456 TAILQ_INSERT_TAIL(&pmap->pm_pvlist, pv, pv_plist); 1457 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_list); 1458 m->md.pv_list_count++; 1459 1460} 1461 1462/* 1463 * pmap_remove_pte: do the things to unmap a page in a process 1464 */ 1465static int 1466pmap_remove_pte(struct pmap *pmap, pt_entry_t *ptq, vm_offset_t va) 1467{ 1468 pt_entry_t oldpte; 1469 vm_page_t m; 1470 vm_offset_t pa; 1471 1472 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1473 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1474 1475 oldpte = loadandclear((u_int *)ptq); 1476 if (is_kernel_pmap(pmap)) 1477 *ptq = PTE_G; 1478 1479 if (oldpte & PTE_W) 1480 pmap->pm_stats.wired_count -= 1; 1481 1482 pmap->pm_stats.resident_count -= 1; 1483 pa = mips_tlbpfn_to_paddr(oldpte); 1484 1485 if (page_is_managed(pa)) { 1486 m = PHYS_TO_VM_PAGE(pa); 1487 if (oldpte & PTE_M) { 1488#if defined(PMAP_DIAGNOSTIC) 1489 if (pmap_nw_modified(oldpte)) { 1490 printf( 1491 "pmap_remove: modified page not writable: va: 0x%x, pte: 0x%x\n", 1492 va, oldpte); 1493 } 1494#endif 1495 vm_page_dirty(m); 1496 } 1497 if (m->md.pv_flags & PV_TABLE_REF) 1498 vm_page_flag_set(m, PG_REFERENCED); 1499 m->md.pv_flags &= ~(PV_TABLE_REF | PV_TABLE_MOD); 1500 1501 pmap_remove_entry(pmap, m, va); 1502 } 1503 return pmap_unuse_pt(pmap, va, NULL); 1504 1505} 1506 1507/* 1508 * Remove a single page from a process address space 1509 */ 1510static void 1511pmap_remove_page(struct pmap *pmap, vm_offset_t va) 1512{ 1513 register pt_entry_t *ptq; 1514 1515 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1516 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1517 ptq = pmap_pte(pmap, va); 1518 1519 /* 1520 * if there is no pte for this address, just skip it!!! 1521 */ 1522 if (!ptq || !pmap_pte_v(ptq)) { 1523 return; 1524 } 1525 /* 1526 * get a local va for mappings for this pmap. 1527 */ 1528 (void)pmap_remove_pte(pmap, ptq, va); 1529 pmap_invalidate_page(pmap, va); 1530 1531 return; 1532} 1533 1534/* 1535 * Remove the given range of addresses from the specified map. 1536 * 1537 * It is assumed that the start and end are properly 1538 * rounded to the page size. 1539 */ 1540void 1541pmap_remove(struct pmap *pmap, vm_offset_t sva, vm_offset_t eva) 1542{ 1543 vm_offset_t va, nva; 1544 1545 if (pmap == NULL) 1546 return; 1547 1548 if (pmap->pm_stats.resident_count == 0) 1549 return; 1550 1551 vm_page_lock_queues(); 1552 PMAP_LOCK(pmap); 1553 1554 /* 1555 * special handling of removing one page. a very common operation 1556 * and easy to short circuit some code. 1557 */ 1558 if ((sva + PAGE_SIZE) == eva) { 1559 pmap_remove_page(pmap, sva); 1560 goto out; 1561 } 1562 for (va = sva; va < eva; va = nva) { 1563 if (!*pmap_pde(pmap, va)) { 1564 nva = mips_segtrunc(va + MIPS_SEGSIZE); 1565 continue; 1566 } 1567 pmap_remove_page(pmap, va); 1568 nva = va + PAGE_SIZE; 1569 } 1570 1571out: 1572 vm_page_unlock_queues(); 1573 PMAP_UNLOCK(pmap); 1574} 1575 1576/* 1577 * Routine: pmap_remove_all 1578 * Function: 1579 * Removes this physical page from 1580 * all physical maps in which it resides. 1581 * Reflects back modify bits to the pager. 1582 * 1583 * Notes: 1584 * Original versions of this routine were very 1585 * inefficient because they iteratively called 1586 * pmap_remove (slow...) 1587 */ 1588 1589void 1590pmap_remove_all(vm_page_t m) 1591{ 1592 register pv_entry_t pv; 1593 register pt_entry_t *pte, tpte; 1594 1595#if defined(PMAP_DEBUG) 1596 /* 1597 * XXX This makes pmap_remove_all() illegal for non-managed pages! 1598 */ 1599 if (m->flags & PG_FICTITIOUS) { 1600 panic("pmap_page_protect: illegal for unmanaged page, va: 0x%x", VM_PAGE_TO_PHYS(m)); 1601 } 1602#endif 1603 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1604 1605 if (m->md.pv_flags & PV_TABLE_REF) 1606 vm_page_flag_set(m, PG_REFERENCED); 1607 1608 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) { 1609 PMAP_LOCK(pv->pv_pmap); 1610 pv->pv_pmap->pm_stats.resident_count--; 1611 1612 pte = pmap_pte(pv->pv_pmap, pv->pv_va); 1613 1614 tpte = loadandclear((u_int *)pte); 1615 if (is_kernel_pmap(pv->pv_pmap)) 1616 *pte = PTE_G; 1617 1618 if (tpte & PTE_W) 1619 pv->pv_pmap->pm_stats.wired_count--; 1620 1621 /* 1622 * Update the vm_page_t clean and reference bits. 1623 */ 1624 if (tpte & PTE_M) { 1625#if defined(PMAP_DIAGNOSTIC) 1626 if (pmap_nw_modified(tpte)) { 1627 printf( 1628 "pmap_remove_all: modified page not writable: va: 0x%x, pte: 0x%x\n", 1629 pv->pv_va, tpte); 1630 } 1631#endif 1632 vm_page_dirty(m); 1633 } 1634 pmap_invalidate_page(pv->pv_pmap, pv->pv_va); 1635 1636 TAILQ_REMOVE(&pv->pv_pmap->pm_pvlist, pv, pv_plist); 1637 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list); 1638 m->md.pv_list_count--; 1639 pmap_unuse_pt(pv->pv_pmap, pv->pv_va, pv->pv_ptem); 1640 PMAP_UNLOCK(pv->pv_pmap); 1641 free_pv_entry(pv); 1642 } 1643 1644 vm_page_flag_clear(m, PG_WRITEABLE); 1645 m->md.pv_flags &= ~(PV_TABLE_REF | PV_TABLE_MOD); 1646} 1647 1648/* 1649 * Set the physical protection on the 1650 * specified range of this map as requested. 1651 */ 1652void 1653pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot) 1654{ 1655 pt_entry_t *pte; 1656 1657 if (pmap == NULL) 1658 return; 1659 1660 if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 1661 pmap_remove(pmap, sva, eva); 1662 return; 1663 } 1664 if (prot & VM_PROT_WRITE) 1665 return; 1666 1667 vm_page_lock_queues(); 1668 PMAP_LOCK(pmap); 1669 while (sva < eva) { 1670 pt_entry_t pbits, obits; 1671 vm_page_t m; 1672 vm_offset_t pa; 1673 1674 /* 1675 * If segment table entry is empty, skip this segment. 1676 */ 1677 if (!*pmap_pde(pmap, sva)) { 1678 sva = mips_segtrunc(sva + MIPS_SEGSIZE); 1679 continue; 1680 } 1681 /* 1682 * If pte is invalid, skip this page 1683 */ 1684 pte = pmap_pte(pmap, sva); 1685 if (!pmap_pte_v(pte)) { 1686 sva += PAGE_SIZE; 1687 continue; 1688 } 1689retry: 1690 obits = pbits = *pte; 1691 pa = mips_tlbpfn_to_paddr(pbits); 1692 1693 if (page_is_managed(pa)) { 1694 m = PHYS_TO_VM_PAGE(pa); 1695 if (m->md.pv_flags & PV_TABLE_REF) { 1696 vm_page_flag_set(m, PG_REFERENCED); 1697 m->md.pv_flags &= ~PV_TABLE_REF; 1698 } 1699 if (pbits & PTE_M) { 1700 vm_page_dirty(m); 1701 m->md.pv_flags &= ~PV_TABLE_MOD; 1702 } 1703 } 1704 pbits = (pbits & ~PTE_M) | PTE_RO; 1705 1706 if (pbits != *pte) { 1707 if (!atomic_cmpset_int((u_int *)pte, obits, pbits)) 1708 goto retry; 1709 pmap_update_page(pmap, sva, pbits); 1710 } 1711 sva += PAGE_SIZE; 1712 } 1713 vm_page_unlock_queues(); 1714 PMAP_UNLOCK(pmap); 1715} 1716 1717/* 1718 * Insert the given physical page (p) at 1719 * the specified virtual address (v) in the 1720 * target physical map with the protection requested. 1721 * 1722 * If specified, the page will be wired down, meaning 1723 * that the related pte can not be reclaimed. 1724 * 1725 * NB: This is the only routine which MAY NOT lazy-evaluate 1726 * or lose information. That is, this routine must actually 1727 * insert this page into the given map NOW. 1728 */ 1729void 1730pmap_enter(pmap_t pmap, vm_offset_t va, vm_prot_t fault_type, vm_page_t m, vm_prot_t prot, 1731 boolean_t wired) 1732{ 1733 vm_offset_t pa, opa; 1734 register pt_entry_t *pte; 1735 pt_entry_t origpte, newpte; 1736 vm_page_t mpte, om; 1737 int rw = 0; 1738 1739 if (pmap == NULL) 1740 return; 1741 1742 va &= ~PAGE_MASK; 1743#ifdef PMAP_DIAGNOSTIC 1744 if (va > VM_MAX_KERNEL_ADDRESS) 1745 panic("pmap_enter: toobig"); 1746#endif 1747 1748 mpte = NULL; 1749 1750 vm_page_lock_queues(); 1751 PMAP_LOCK(pmap); 1752 1753 /* 1754 * In the case that a page table page is not resident, we are 1755 * creating it here. 1756 */ 1757 if (va < VM_MAXUSER_ADDRESS) { 1758 mpte = pmap_allocpte(pmap, va, M_WAITOK); 1759 } 1760 pte = pmap_pte(pmap, va); 1761 1762 /* 1763 * Page Directory table entry not valid, we need a new PT page 1764 */ 1765 if (pte == NULL) { 1766 panic("pmap_enter: invalid page directory, pdir=%p, va=0x%x\n", 1767 (void *)pmap->pm_segtab, va); 1768 } 1769 pa = VM_PAGE_TO_PHYS(m); 1770 om = NULL; 1771 origpte = *pte; 1772 opa = mips_tlbpfn_to_paddr(origpte); 1773 1774 /* 1775 * Mapping has not changed, must be protection or wiring change. 1776 */ 1777 if ((origpte & PTE_V) && (opa == pa)) { 1778 /* 1779 * Wiring change, just update stats. We don't worry about 1780 * wiring PT pages as they remain resident as long as there 1781 * are valid mappings in them. Hence, if a user page is 1782 * wired, the PT page will be also. 1783 */ 1784 if (wired && ((origpte & PTE_W) == 0)) 1785 pmap->pm_stats.wired_count++; 1786 else if (!wired && (origpte & PTE_W)) 1787 pmap->pm_stats.wired_count--; 1788 1789#if defined(PMAP_DIAGNOSTIC) 1790 if (pmap_nw_modified(origpte)) { 1791 printf( 1792 "pmap_enter: modified page not writable: va: 0x%x, pte: 0x%x\n", 1793 va, origpte); 1794 } 1795#endif 1796 1797 /* 1798 * Remove extra pte reference 1799 */ 1800 if (mpte) 1801 mpte->wire_count--; 1802 1803 /* 1804 * We might be turning off write access to the page, so we 1805 * go ahead and sense modify status. 1806 */ 1807 if (page_is_managed(opa)) { 1808 om = m; 1809 } 1810 goto validate; 1811 } 1812 /* 1813 * Mapping has changed, invalidate old range and fall through to 1814 * handle validating new mapping. 1815 */ 1816 if (opa) { 1817 if (origpte & PTE_W) 1818 pmap->pm_stats.wired_count--; 1819 1820 if (page_is_managed(opa)) { 1821 om = PHYS_TO_VM_PAGE(opa); 1822 pmap_remove_entry(pmap, om, va); 1823 } 1824 if (mpte != NULL) { 1825 mpte->wire_count--; 1826 KASSERT(mpte->wire_count > 0, 1827 ("pmap_enter: missing reference to page table page," 1828 " va: 0x%x", va)); 1829 } 1830 } else 1831 pmap->pm_stats.resident_count++; 1832 1833 /* 1834 * Enter on the PV list if part of our managed memory. Note that we 1835 * raise IPL while manipulating pv_table since pmap_enter can be 1836 * called at interrupt time. 1837 */ 1838 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0) { 1839 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva, 1840 ("pmap_enter: managed mapping within the clean submap")); 1841 pmap_insert_entry(pmap, va, mpte, m, wired); 1842 } 1843 /* 1844 * Increment counters 1845 */ 1846 if (wired) 1847 pmap->pm_stats.wired_count++; 1848 1849validate: 1850 rw = init_pte_prot(va, m, prot); 1851 1852#ifdef PMAP_DEBUG 1853 printf("pmap_enter: va: 0x%08x -> pa: 0x%08x\n", va, pa); 1854#endif 1855 /* 1856 * Now validate mapping with desired protection/wiring. 1857 */ 1858 newpte = mips_paddr_to_tlbpfn(pa) | rw | PTE_V; 1859 1860 if (is_cacheable_mem(pa)) 1861 newpte |= PTE_CACHE; 1862 else 1863 newpte |= PTE_UNCACHED; 1864 1865 if (wired) 1866 newpte |= PTE_W; 1867 1868 if (is_kernel_pmap(pmap)) { 1869 newpte |= PTE_G; 1870 } 1871 1872 /* 1873 * if the mapping or permission bits are different, we need to 1874 * update the pte. 1875 */ 1876 if (origpte != newpte) { 1877 if (origpte & PTE_V) { 1878 *pte = newpte; 1879 if (page_is_managed(opa) && (opa != pa)) { 1880 if (om->md.pv_flags & PV_TABLE_REF) 1881 vm_page_flag_set(om, PG_REFERENCED); 1882 om->md.pv_flags &= 1883 ~(PV_TABLE_REF | PV_TABLE_MOD); 1884 } 1885 if (origpte & PTE_M) { 1886 KASSERT((origpte & PTE_RW), 1887 ("pmap_enter: modified page not writable:" 1888 " va: 0x%x, pte: 0x%lx", va, origpte)); 1889 if (page_is_managed(opa)) 1890 vm_page_dirty(om); 1891 } 1892 } else { 1893 *pte = newpte; 1894 } 1895 } 1896 pmap_update_page(pmap, va, newpte); 1897 1898 /* 1899 * Sync I & D caches for executable pages. Do this only if the the 1900 * target pmap belongs to the current process. Otherwise, an 1901 * unresolvable TLB miss may occur. 1902 */ 1903 if (!is_kernel_pmap(pmap) && (pmap == &curproc->p_vmspace->vm_pmap) && 1904 (prot & VM_PROT_EXECUTE)) { 1905 mips_icache_sync_range(va, NBPG); 1906 mips_dcache_wbinv_range(va, NBPG); 1907 } 1908 vm_page_unlock_queues(); 1909 PMAP_UNLOCK(pmap); 1910} 1911 1912/* 1913 * this code makes some *MAJOR* assumptions: 1914 * 1. Current pmap & pmap exists. 1915 * 2. Not wired. 1916 * 3. Read access. 1917 * 4. No page table pages. 1918 * but is *MUCH* faster than pmap_enter... 1919 */ 1920 1921 1922void 1923pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot) 1924{ 1925 pt_entry_t *pte; 1926 vm_offset_t pa; 1927 vm_page_t mpte = NULL; 1928 1929 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva || 1930 (m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0, 1931 ("pmap_enter_quick: managed mapping within the clean submap")); 1932 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1933 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED); 1934 PMAP_LOCK(pmap); 1935 /* 1936 * In the case that a page table page is not resident, we are 1937 * creating it here. 1938 */ 1939 if (va < VM_MAXUSER_ADDRESS) { 1940 unsigned ptepindex; 1941 vm_offset_t pteva; 1942 1943 /* 1944 * Calculate pagetable page index 1945 */ 1946 ptepindex = va >> SEGSHIFT; 1947 if (mpte && (mpte->pindex == ptepindex)) { 1948 mpte->wire_count++; 1949 } else { 1950 retry: 1951 /* 1952 * Get the page directory entry 1953 */ 1954 pteva = (vm_offset_t)pmap->pm_segtab[ptepindex]; 1955 1956 /* 1957 * If the page table page is mapped, we just 1958 * increment the hold count, and activate it. 1959 */ 1960 if (pteva) { 1961 if (pmap->pm_ptphint && 1962 (pmap->pm_ptphint->pindex == ptepindex)) { 1963 mpte = pmap->pm_ptphint; 1964 } else { 1965 mpte = PHYS_TO_VM_PAGE(MIPS_CACHED_TO_PHYS(pteva)); 1966 pmap->pm_ptphint = mpte; 1967 } 1968 mpte->wire_count++; 1969 } else { 1970 mpte = _pmap_allocpte(pmap, ptepindex, M_NOWAIT); 1971 if (mpte == NULL) { 1972 PMAP_UNLOCK(pmap); 1973 vm_page_busy(m); 1974 vm_page_unlock_queues(); 1975 VM_OBJECT_UNLOCK(m->object); 1976 VM_WAIT; 1977 VM_OBJECT_LOCK(m->object); 1978 vm_page_lock_queues(); 1979 vm_page_wakeup(m); 1980 PMAP_LOCK(pmap); 1981 goto retry; 1982 } 1983 } 1984 } 1985 } else { 1986 mpte = NULL; 1987 } 1988 1989 pte = pmap_pte(pmap, va); 1990 if (pmap_pte_v(pte)) { 1991 if (mpte) 1992 pmap_unwire_pte_hold(pmap, mpte); 1993 PMAP_UNLOCK(pmap); 1994 return; 1995 } 1996 /* 1997 * Enter on the PV list if part of our managed memory. Note that we 1998 * raise IPL while manipulating pv_table since pmap_enter can be 1999 * called at interrupt time. 2000 */ 2001 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0) 2002 pmap_insert_entry(pmap, va, mpte, m, FALSE); 2003 2004 /* 2005 * Increment counters 2006 */ 2007 pmap->pm_stats.resident_count++; 2008 2009 pa = VM_PAGE_TO_PHYS(m); 2010 2011 /* 2012 * Now validate mapping with RO protection 2013 */ 2014 *pte = mips_paddr_to_tlbpfn(pa) | PTE_V; 2015 2016 if (is_cacheable_mem(pa)) 2017 *pte |= PTE_CACHE; 2018 else 2019 *pte |= PTE_UNCACHED; 2020 2021 if (is_kernel_pmap(pmap)) 2022 *pte |= PTE_G; 2023 else { 2024 *pte |= PTE_RO; 2025 /* 2026 * Sync I & D caches. Do this only if the the target pmap 2027 * belongs to the current process. Otherwise, an 2028 * unresolvable TLB miss may occur. */ 2029 if (pmap == &curproc->p_vmspace->vm_pmap) { 2030 va &= ~PAGE_MASK; 2031 mips_icache_sync_range(va, NBPG); 2032 mips_dcache_wbinv_range(va, NBPG); 2033 } 2034 } 2035 2036 PMAP_UNLOCK(pmap); 2037 return; 2038} 2039 2040/* 2041 * Make a temporary mapping for a physical address. This is only intended 2042 * to be used for panic dumps. 2043 */ 2044void * 2045pmap_kenter_temporary(vm_paddr_t pa, int i) 2046{ 2047 vm_offset_t va; 2048 2049 if (i != 0) 2050 printf("%s: ERROR!!! More than one page of virtual address mapping not supported\n", 2051 __func__); 2052 2053#ifdef VM_ALLOC_WIRED_TLB_PG_POOL 2054 if (need_wired_tlb_page_pool) { 2055 va = pmap_map_fpage(pa, &fpages_shared[PMAP_FPAGE_KENTER_TEMP], 2056 TRUE); 2057 } else 2058#endif 2059 if (pa < MIPS_KSEG0_LARGEST_PHYS) { 2060 va = MIPS_PHYS_TO_CACHED(pa); 2061 } else { 2062 int cpu; 2063 struct local_sysmaps *sysm; 2064 2065 cpu = PCPU_GET(cpuid); 2066 sysm = &sysmap_lmem[cpu]; 2067 /* Since this is for the debugger, no locks or any other fun */ 2068 sysm->CMAP1 = mips_paddr_to_tlbpfn(pa) | PTE_RW | PTE_V | PTE_G | PTE_W | PTE_CACHE; 2069 pmap_TLB_update_kernel((vm_offset_t)sysm->CADDR1, sysm->CMAP1); 2070 sysm->valid1 = 1; 2071 va = (vm_offset_t)sysm->CADDR1; 2072 } 2073 return ((void *)va); 2074} 2075 2076void 2077pmap_kenter_temporary_free(vm_paddr_t pa) 2078{ 2079 int cpu; 2080 struct local_sysmaps *sysm; 2081 2082 if (pa < MIPS_KSEG0_LARGEST_PHYS) { 2083 /* nothing to do for this case */ 2084 return; 2085 } 2086 cpu = PCPU_GET(cpuid); 2087 sysm = &sysmap_lmem[cpu]; 2088 if (sysm->valid1) { 2089 pmap_TLB_invalidate_kernel((vm_offset_t)sysm->CADDR1); 2090 sysm->CMAP1 = 0; 2091 sysm->valid1 = 0; 2092 } 2093} 2094 2095/* 2096 * Moved the code to Machine Independent 2097 * vm_map_pmap_enter() 2098 */ 2099 2100/* 2101 * Maps a sequence of resident pages belonging to the same object. 2102 * The sequence begins with the given page m_start. This page is 2103 * mapped at the given virtual address start. Each subsequent page is 2104 * mapped at a virtual address that is offset from start by the same 2105 * amount as the page is offset from m_start within the object. The 2106 * last page in the sequence is the page with the largest offset from 2107 * m_start that can be mapped at a virtual address less than the given 2108 * virtual address end. Not every virtual page between start and end 2109 * is mapped; only those for which a resident page exists with the 2110 * corresponding offset from m_start are mapped. 2111 */ 2112void 2113pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end, 2114 vm_page_t m_start, vm_prot_t prot) 2115{ 2116 vm_page_t m; 2117 vm_pindex_t diff, psize; 2118 2119 psize = atop(end - start); 2120 m = m_start; 2121 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 2122 /* FIX ME FIX ME - prot is passed in both the 2123 * the normal spot m, prot but also as the fault_type 2124 * which we don't use. If we ever use it in pmap_enter 2125 * we will have to fix this. 2126 */ 2127 pmap_enter(pmap, start + ptoa(diff), prot, m, prot & 2128 (VM_PROT_READ | VM_PROT_EXECUTE), FALSE); 2129 m = TAILQ_NEXT(m, listq); 2130 } 2131} 2132 2133/* 2134 * pmap_object_init_pt preloads the ptes for a given object 2135 * into the specified pmap. This eliminates the blast of soft 2136 * faults on process startup and immediately after an mmap. 2137 */ 2138void 2139pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, 2140 vm_object_t object, vm_pindex_t pindex, vm_size_t size) 2141{ 2142 VM_OBJECT_LOCK_ASSERT(object, MA_OWNED); 2143 KASSERT(object->type == OBJT_DEVICE, 2144 ("pmap_object_init_pt: non-device object")); 2145} 2146 2147/* 2148 * Routine: pmap_change_wiring 2149 * Function: Change the wiring attribute for a map/virtual-address 2150 * pair. 2151 * In/out conditions: 2152 * The mapping must already exist in the pmap. 2153 */ 2154void 2155pmap_change_wiring(pmap_t pmap, vm_offset_t va, boolean_t wired) 2156{ 2157 register pt_entry_t *pte; 2158 2159 if (pmap == NULL) 2160 return; 2161 2162 PMAP_LOCK(pmap); 2163 pte = pmap_pte(pmap, va); 2164 2165 if (wired && !pmap_pte_w(pte)) 2166 pmap->pm_stats.wired_count++; 2167 else if (!wired && pmap_pte_w(pte)) 2168 pmap->pm_stats.wired_count--; 2169 2170 /* 2171 * Wiring is not a hardware characteristic so there is no need to 2172 * invalidate TLB. 2173 */ 2174 pmap_pte_set_w(pte, wired); 2175 PMAP_UNLOCK(pmap); 2176} 2177 2178/* 2179 * Copy the range specified by src_addr/len 2180 * from the source map to the range dst_addr/len 2181 * in the destination map. 2182 * 2183 * This routine is only advisory and need not do anything. 2184 */ 2185 2186void 2187pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, 2188 vm_size_t len, vm_offset_t src_addr) 2189{ 2190} 2191 2192/* 2193 * pmap_zero_page zeros the specified hardware page by mapping 2194 * the page into KVM and using bzero to clear its contents. 2195 */ 2196void 2197pmap_zero_page(vm_page_t m) 2198{ 2199 vm_offset_t va; 2200 vm_paddr_t phys = VM_PAGE_TO_PHYS(m); 2201 2202#ifdef VM_ALLOC_WIRED_TLB_PG_POOL 2203 if (need_wired_tlb_page_pool) { 2204 struct fpage *fp1; 2205 struct sysmaps *sysmaps; 2206 2207 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)]; 2208 mtx_lock(&sysmaps->lock); 2209 sched_pin(); 2210 2211 fp1 = &sysmaps->fp[PMAP_FPAGE1]; 2212 va = pmap_map_fpage(phys, fp1, FALSE); 2213 bzero((caddr_t)va, PAGE_SIZE); 2214 pmap_unmap_fpage(phys, fp1); 2215 sched_unpin(); 2216 mtx_unlock(&sysmaps->lock); 2217 /* 2218 * Should you do cache flush? 2219 */ 2220 } else 2221#endif 2222 if (phys < MIPS_KSEG0_LARGEST_PHYS) { 2223 2224 va = MIPS_PHYS_TO_UNCACHED(phys); 2225 2226 bzero((caddr_t)va, PAGE_SIZE); 2227 mips_dcache_wbinv_range(va, PAGE_SIZE); 2228 } else { 2229 int cpu; 2230 struct local_sysmaps *sysm; 2231 2232 cpu = PCPU_GET(cpuid); 2233 sysm = &sysmap_lmem[cpu]; 2234 PMAP_LGMEM_LOCK(sysm); 2235 sched_pin(); 2236 sysm->CMAP1 = mips_paddr_to_tlbpfn(phys) | PTE_RW | PTE_V | PTE_G | PTE_W | PTE_CACHE; 2237 pmap_TLB_update_kernel((vm_offset_t)sysm->CADDR1, sysm->CMAP1); 2238 sysm->valid1 = 1; 2239 bzero(sysm->CADDR1, PAGE_SIZE); 2240 pmap_TLB_invalidate_kernel((vm_offset_t)sysm->CADDR1); 2241 sysm->CMAP1 = 0; 2242 sysm->valid1 = 0; 2243 sched_unpin(); 2244 PMAP_LGMEM_UNLOCK(sysm); 2245 } 2246 2247} 2248 2249/* 2250 * pmap_zero_page_area zeros the specified hardware page by mapping 2251 * the page into KVM and using bzero to clear its contents. 2252 * 2253 * off and size may not cover an area beyond a single hardware page. 2254 */ 2255void 2256pmap_zero_page_area(vm_page_t m, int off, int size) 2257{ 2258 vm_offset_t va; 2259 vm_paddr_t phys = VM_PAGE_TO_PHYS(m); 2260 2261#ifdef VM_ALLOC_WIRED_TLB_PG_POOL 2262 if (need_wired_tlb_page_pool) { 2263 struct fpage *fp1; 2264 struct sysmaps *sysmaps; 2265 2266 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)]; 2267 mtx_lock(&sysmaps->lock); 2268 sched_pin(); 2269 2270 fp1 = &sysmaps->fp[PMAP_FPAGE1]; 2271 va = pmap_map_fpage(phys, fp1, FALSE); 2272 bzero((caddr_t)va + off, size); 2273 pmap_unmap_fpage(phys, fp1); 2274 2275 sched_unpin(); 2276 mtx_unlock(&sysmaps->lock); 2277 } else 2278#endif 2279 if (phys < MIPS_KSEG0_LARGEST_PHYS) { 2280 va = MIPS_PHYS_TO_UNCACHED(phys); 2281 bzero((char *)(caddr_t)va + off, size); 2282 mips_dcache_wbinv_range(va + off, size); 2283 } else { 2284 int cpu; 2285 struct local_sysmaps *sysm; 2286 2287 cpu = PCPU_GET(cpuid); 2288 sysm = &sysmap_lmem[cpu]; 2289 PMAP_LGMEM_LOCK(sysm); 2290 sched_pin(); 2291 sysm->CMAP1 = mips_paddr_to_tlbpfn(phys) | PTE_RW | PTE_V | PTE_G | PTE_W | PTE_CACHE; 2292 pmap_TLB_update_kernel((vm_offset_t)sysm->CADDR1, sysm->CMAP1); 2293 sysm->valid1 = 1; 2294 bzero((char *)sysm->CADDR1 + off, size); 2295 pmap_TLB_invalidate_kernel((vm_offset_t)sysm->CADDR1); 2296 sysm->CMAP1 = 0; 2297 sysm->valid1 = 0; 2298 sched_unpin(); 2299 PMAP_LGMEM_UNLOCK(sysm); 2300 } 2301} 2302 2303void 2304pmap_zero_page_idle(vm_page_t m) 2305{ 2306 vm_offset_t va; 2307 vm_paddr_t phys = VM_PAGE_TO_PHYS(m); 2308 2309#ifdef VM_ALLOC_WIRED_TLB_PG_POOL 2310 if (need_wired_tlb_page_pool) { 2311 sched_pin(); 2312 va = pmap_map_fpage(phys, &fpages_shared[PMAP_FPAGE3], FALSE); 2313 bzero((caddr_t)va, PAGE_SIZE); 2314 pmap_unmap_fpage(phys, &fpages_shared[PMAP_FPAGE3]); 2315 sched_unpin(); 2316 } else 2317#endif 2318 if (phys < MIPS_KSEG0_LARGEST_PHYS) { 2319 va = MIPS_PHYS_TO_UNCACHED(phys); 2320 bzero((caddr_t)va, PAGE_SIZE); 2321 mips_dcache_wbinv_range(va, PAGE_SIZE); 2322 } else { 2323 int cpu; 2324 struct local_sysmaps *sysm; 2325 2326 cpu = PCPU_GET(cpuid); 2327 sysm = &sysmap_lmem[cpu]; 2328 PMAP_LGMEM_LOCK(sysm); 2329 sched_pin(); 2330 sysm->CMAP1 = mips_paddr_to_tlbpfn(phys) | PTE_RW | PTE_V | PTE_G | PTE_W | PTE_CACHE; 2331 pmap_TLB_update_kernel((vm_offset_t)sysm->CADDR1, sysm->CMAP1); 2332 sysm->valid1 = 1; 2333 bzero(sysm->CADDR1, PAGE_SIZE); 2334 pmap_TLB_invalidate_kernel((vm_offset_t)sysm->CADDR1); 2335 sysm->CMAP1 = 0; 2336 sysm->valid1 = 0; 2337 sched_unpin(); 2338 PMAP_LGMEM_UNLOCK(sysm); 2339 } 2340 2341} 2342 2343/* 2344 * pmap_copy_page copies the specified (machine independent) 2345 * page by mapping the page into virtual memory and using 2346 * bcopy to copy the page, one machine dependent page at a 2347 * time. 2348 */ 2349void 2350pmap_copy_page(vm_page_t src, vm_page_t dst) 2351{ 2352 vm_offset_t va_src, va_dst; 2353 vm_paddr_t phy_src = VM_PAGE_TO_PHYS(src); 2354 vm_paddr_t phy_dst = VM_PAGE_TO_PHYS(dst); 2355 2356 2357#ifdef VM_ALLOC_WIRED_TLB_PG_POOL 2358 if (need_wired_tlb_page_pool) { 2359 struct fpage *fp1, *fp2; 2360 struct sysmaps *sysmaps; 2361 2362 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)]; 2363 mtx_lock(&sysmaps->lock); 2364 sched_pin(); 2365 2366 fp1 = &sysmaps->fp[PMAP_FPAGE1]; 2367 fp2 = &sysmaps->fp[PMAP_FPAGE2]; 2368 2369 va_src = pmap_map_fpage(phy_src, fp1, FALSE); 2370 va_dst = pmap_map_fpage(phy_dst, fp2, FALSE); 2371 2372 bcopy((caddr_t)va_src, (caddr_t)va_dst, PAGE_SIZE); 2373 2374 pmap_unmap_fpage(phy_src, fp1); 2375 pmap_unmap_fpage(phy_dst, fp2); 2376 sched_unpin(); 2377 mtx_unlock(&sysmaps->lock); 2378 2379 /* 2380 * Should you flush the cache? 2381 */ 2382 } else 2383#endif 2384 { 2385 if ((phy_src < MIPS_KSEG0_LARGEST_PHYS) && (phy_dst < MIPS_KSEG0_LARGEST_PHYS)) { 2386 /* easy case, all can be accessed via KSEG0 */ 2387 va_src = MIPS_PHYS_TO_CACHED(phy_src); 2388 va_dst = MIPS_PHYS_TO_CACHED(phy_dst); 2389 bcopy((caddr_t)va_src, (caddr_t)va_dst, PAGE_SIZE); 2390 } else { 2391 int cpu; 2392 struct local_sysmaps *sysm; 2393 2394 cpu = PCPU_GET(cpuid); 2395 sysm = &sysmap_lmem[cpu]; 2396 PMAP_LGMEM_LOCK(sysm); 2397 sched_pin(); 2398 if (phy_src < MIPS_KSEG0_LARGEST_PHYS) { 2399 /* one side needs mapping - dest */ 2400 va_src = MIPS_PHYS_TO_CACHED(phy_src); 2401 sysm->CMAP2 = mips_paddr_to_tlbpfn(phy_dst) | PTE_RW | PTE_V | PTE_G | PTE_W | PTE_CACHE; 2402 pmap_TLB_update_kernel((vm_offset_t)sysm->CADDR2, sysm->CMAP2); 2403 sysm->valid2 = 2; 2404 va_dst = (vm_offset_t)sysm->CADDR2; 2405 } else if (phy_dst < MIPS_KSEG0_LARGEST_PHYS) { 2406 /* one side needs mapping - src */ 2407 va_dst = MIPS_PHYS_TO_CACHED(phy_dst); 2408 sysm->CMAP1 = mips_paddr_to_tlbpfn(phy_src) | PTE_RW | PTE_V | PTE_G | PTE_W | PTE_CACHE; 2409 pmap_TLB_update_kernel((vm_offset_t)sysm->CADDR1, sysm->CMAP1); 2410 va_src = (vm_offset_t)sysm->CADDR1; 2411 sysm->valid1 = 1; 2412 } else { 2413 /* all need mapping */ 2414 sysm->CMAP1 = mips_paddr_to_tlbpfn(phy_src) | PTE_RW | PTE_V | PTE_G | PTE_W | PTE_CACHE; 2415 sysm->CMAP2 = mips_paddr_to_tlbpfn(phy_dst) | PTE_RW | PTE_V | PTE_G | PTE_W | PTE_CACHE; 2416 pmap_TLB_update_kernel((vm_offset_t)sysm->CADDR1, sysm->CMAP1); 2417 pmap_TLB_update_kernel((vm_offset_t)sysm->CADDR2, sysm->CMAP2); 2418 sysm->valid1 = sysm->valid2 = 1; 2419 va_src = (vm_offset_t)sysm->CADDR1; 2420 va_dst = (vm_offset_t)sysm->CADDR2; 2421 } 2422 bcopy((void *)va_src, (void *)va_dst, PAGE_SIZE); 2423 if (sysm->valid1) { 2424 pmap_TLB_invalidate_kernel((vm_offset_t)sysm->CADDR1); 2425 sysm->CMAP1 = 0; 2426 sysm->valid1 = 0; 2427 } 2428 if (sysm->valid2) { 2429 pmap_TLB_invalidate_kernel((vm_offset_t)sysm->CADDR2); 2430 sysm->CMAP2 = 0; 2431 sysm->valid2 = 0; 2432 } 2433 sched_unpin(); 2434 PMAP_LGMEM_UNLOCK(sysm); 2435 } 2436 } 2437} 2438 2439/* 2440 * Returns true if the pmap's pv is one of the first 2441 * 16 pvs linked to from this page. This count may 2442 * be changed upwards or downwards in the future; it 2443 * is only necessary that true be returned for a small 2444 * subset of pmaps for proper page aging. 2445 */ 2446boolean_t 2447pmap_page_exists_quick(pmap_t pmap, vm_page_t m) 2448{ 2449 pv_entry_t pv; 2450 int loops = 0; 2451 2452 if (m->flags & PG_FICTITIOUS) 2453 return FALSE; 2454 2455 vm_page_lock_queues(); 2456 PMAP_LOCK(pmap); 2457 2458 /* 2459 * Not found, check current mappings returning immediately if found. 2460 */ 2461 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 2462 if (pv->pv_pmap == pmap) { 2463 PMAP_UNLOCK(pmap); 2464 vm_page_unlock_queues(); 2465 return TRUE; 2466 } 2467 loops++; 2468 if (loops >= 16) 2469 break; 2470 } 2471 PMAP_UNLOCK(pmap); 2472 vm_page_unlock_queues(); 2473 return (FALSE); 2474} 2475 2476#define PMAP_REMOVE_PAGES_CURPROC_ONLY 2477/* 2478 * Remove all pages from specified address space 2479 * this aids process exit speeds. Also, this code 2480 * is special cased for current process only, but 2481 * can have the more generic (and slightly slower) 2482 * mode enabled. This is much faster than pmap_remove 2483 * in the case of running down an entire address space. 2484 */ 2485void 2486pmap_remove_pages(pmap_t pmap) 2487{ 2488 pt_entry_t *pte, tpte; 2489 pv_entry_t pv, npv; 2490 vm_page_t m; 2491 2492#ifdef PMAP_REMOVE_PAGES_CURPROC_ONLY 2493 if (pmap != vmspace_pmap(curthread->td_proc->p_vmspace)) { 2494 printf("warning: pmap_remove_pages called with non-current pmap\n"); 2495 return; 2496 } 2497#endif 2498 2499 vm_page_lock_queues(); 2500 PMAP_LOCK(pmap); 2501 sched_pin(); 2502 //XXX need to be TAILQ_FOREACH_SAFE ? 2503 for (pv = TAILQ_FIRST(&pmap->pm_pvlist); 2504 pv; 2505 pv = npv) { 2506 2507 pte = pmap_pte(pv->pv_pmap, pv->pv_va); 2508 if (!pmap_pte_v(pte)) 2509 panic("pmap_remove_pages: page on pm_pvlist has no pte\n"); 2510 tpte = *pte; 2511 2512/* 2513 * We cannot remove wired pages from a process' mapping at this time 2514 */ 2515 if (tpte & PTE_W) { 2516 npv = TAILQ_NEXT(pv, pv_plist); 2517 continue; 2518 } 2519 *pte = is_kernel_pmap(pmap) ? PTE_G : 0; 2520 2521 m = PHYS_TO_VM_PAGE(mips_tlbpfn_to_paddr(tpte)); 2522 2523 KASSERT(m < &vm_page_array[vm_page_array_size], 2524 ("pmap_remove_pages: bad tpte %lx", tpte)); 2525 2526 pv->pv_pmap->pm_stats.resident_count--; 2527 2528 /* 2529 * Update the vm_page_t clean and reference bits. 2530 */ 2531 if (tpte & PTE_M) { 2532 vm_page_dirty(m); 2533 } 2534 npv = TAILQ_NEXT(pv, pv_plist); 2535 TAILQ_REMOVE(&pv->pv_pmap->pm_pvlist, pv, pv_plist); 2536 2537 m->md.pv_list_count--; 2538 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list); 2539 if (TAILQ_FIRST(&m->md.pv_list) == NULL) { 2540 vm_page_flag_clear(m, PG_WRITEABLE); 2541 } 2542 pmap_unuse_pt(pv->pv_pmap, pv->pv_va, pv->pv_ptem); 2543 free_pv_entry(pv); 2544 } 2545 sched_unpin(); 2546 pmap_invalidate_all(pmap); 2547 PMAP_UNLOCK(pmap); 2548 vm_page_unlock_queues(); 2549} 2550 2551/* 2552 * pmap_testbit tests bits in pte's 2553 * note that the testbit/changebit routines are inline, 2554 * and a lot of things compile-time evaluate. 2555 */ 2556static boolean_t 2557pmap_testbit(vm_page_t m, int bit) 2558{ 2559 pv_entry_t pv; 2560 pt_entry_t *pte; 2561 boolean_t rv = FALSE; 2562 2563 if (m->flags & PG_FICTITIOUS) 2564 return rv; 2565 2566 if (TAILQ_FIRST(&m->md.pv_list) == NULL) 2567 return rv; 2568 2569 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2570 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 2571#if defined(PMAP_DIAGNOSTIC) 2572 if (!pv->pv_pmap) { 2573 printf("Null pmap (tb) at va: 0x%x\n", pv->pv_va); 2574 continue; 2575 } 2576#endif 2577 PMAP_LOCK(pv->pv_pmap); 2578 pte = pmap_pte(pv->pv_pmap, pv->pv_va); 2579 rv = (*pte & bit) != 0; 2580 PMAP_UNLOCK(pv->pv_pmap); 2581 if (rv) 2582 break; 2583 } 2584 return (rv); 2585} 2586 2587/* 2588 * this routine is used to modify bits in ptes 2589 */ 2590static __inline void 2591pmap_changebit(vm_page_t m, int bit, boolean_t setem) 2592{ 2593 register pv_entry_t pv; 2594 register pt_entry_t *pte; 2595 2596 if (m->flags & PG_FICTITIOUS) 2597 return; 2598 2599 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2600 /* 2601 * Loop over all current mappings setting/clearing as appropos If 2602 * setting RO do we need to clear the VAC? 2603 */ 2604 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 2605#if defined(PMAP_DIAGNOSTIC) 2606 if (!pv->pv_pmap) { 2607 printf("Null pmap (cb) at va: 0x%x\n", pv->pv_va); 2608 continue; 2609 } 2610#endif 2611 2612 PMAP_LOCK(pv->pv_pmap); 2613 pte = pmap_pte(pv->pv_pmap, pv->pv_va); 2614 2615 if (setem) { 2616 *(int *)pte |= bit; 2617 pmap_update_page(pv->pv_pmap, pv->pv_va, *pte); 2618 } else { 2619 vm_offset_t pbits = *(vm_offset_t *)pte; 2620 2621 if (pbits & bit) { 2622 if (bit == PTE_RW) { 2623 if (pbits & PTE_M) { 2624 vm_page_dirty(m); 2625 } 2626 *(int *)pte = (pbits & ~(PTE_M | PTE_RW)) | 2627 PTE_RO; 2628 } else { 2629 *(int *)pte = pbits & ~bit; 2630 } 2631 pmap_update_page(pv->pv_pmap, pv->pv_va, *pte); 2632 } 2633 } 2634 PMAP_UNLOCK(pv->pv_pmap); 2635 } 2636 if (!setem && bit == PTE_RW) 2637 vm_page_flag_clear(m, PG_WRITEABLE); 2638} 2639 2640/* 2641 * pmap_page_wired_mappings: 2642 * 2643 * Return the number of managed mappings to the given physical page 2644 * that are wired. 2645 */ 2646int 2647pmap_page_wired_mappings(vm_page_t m) 2648{ 2649 pv_entry_t pv; 2650 int count; 2651 2652 count = 0; 2653 if ((m->flags & PG_FICTITIOUS) != 0) 2654 return (count); 2655 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2656 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) 2657 if (pv->pv_wired) 2658 count++; 2659 return (count); 2660} 2661 2662/* 2663 * Clear the write and modified bits in each of the given page's mappings. 2664 */ 2665void 2666pmap_remove_write(vm_page_t m) 2667{ 2668 pv_entry_t pv, npv; 2669 vm_offset_t va; 2670 pt_entry_t *pte; 2671 2672 if ((m->flags & PG_WRITEABLE) == 0) 2673 return; 2674 2675 /* 2676 * Loop over all current mappings setting/clearing as appropos. 2677 */ 2678 for (pv = TAILQ_FIRST(&m->md.pv_list); pv; pv = npv) { 2679 npv = TAILQ_NEXT(pv, pv_plist); 2680 pte = pmap_pte(pv->pv_pmap, pv->pv_va); 2681 2682 if ((pte == NULL) || !mips_pg_v(*pte)) 2683 panic("page on pm_pvlist has no pte\n"); 2684 2685 va = pv->pv_va; 2686 pmap_protect(pv->pv_pmap, va, va + PAGE_SIZE, 2687 VM_PROT_READ | VM_PROT_EXECUTE); 2688 } 2689 vm_page_flag_clear(m, PG_WRITEABLE); 2690} 2691 2692/* 2693 * pmap_ts_referenced: 2694 * 2695 * Return the count of reference bits for a page, clearing all of them. 2696 */ 2697int 2698pmap_ts_referenced(vm_page_t m) 2699{ 2700 if (m->flags & PG_FICTITIOUS) 2701 return (0); 2702 2703 if (m->md.pv_flags & PV_TABLE_REF) { 2704 m->md.pv_flags &= ~PV_TABLE_REF; 2705 return 1; 2706 } 2707 return 0; 2708} 2709 2710/* 2711 * pmap_is_modified: 2712 * 2713 * Return whether or not the specified physical page was modified 2714 * in any physical maps. 2715 */ 2716boolean_t 2717pmap_is_modified(vm_page_t m) 2718{ 2719 if (m->flags & PG_FICTITIOUS) 2720 return FALSE; 2721 2722 if (m->md.pv_flags & PV_TABLE_MOD) 2723 return TRUE; 2724 else 2725 return pmap_testbit(m, PTE_M); 2726} 2727 2728/* N/C */ 2729 2730/* 2731 * pmap_is_prefaultable: 2732 * 2733 * Return whether or not the specified virtual address is elgible 2734 * for prefault. 2735 */ 2736boolean_t 2737pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr) 2738{ 2739 pt_entry_t *pte; 2740 boolean_t rv; 2741 2742 rv = FALSE; 2743 PMAP_LOCK(pmap); 2744 if (*pmap_pde(pmap, addr)) { 2745 pte = pmap_pte(pmap, addr); 2746 rv = (*pte == 0); 2747 } 2748 PMAP_UNLOCK(pmap); 2749 return (rv); 2750} 2751 2752/* 2753 * Clear the modify bits on the specified physical page. 2754 */ 2755void 2756pmap_clear_modify(vm_page_t m) 2757{ 2758 if (m->flags & PG_FICTITIOUS) 2759 return; 2760 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2761 if (m->md.pv_flags & PV_TABLE_MOD) { 2762 pmap_changebit(m, PTE_M, FALSE); 2763 m->md.pv_flags &= ~PV_TABLE_MOD; 2764 } 2765} 2766 2767/* 2768 * pmap_clear_reference: 2769 * 2770 * Clear the reference bit on the specified physical page. 2771 */ 2772void 2773pmap_clear_reference(vm_page_t m) 2774{ 2775 if (m->flags & PG_FICTITIOUS) 2776 return; 2777 2778 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2779 if (m->md.pv_flags & PV_TABLE_REF) { 2780 m->md.pv_flags &= ~PV_TABLE_REF; 2781 } 2782} 2783 2784/* 2785 * Miscellaneous support routines follow 2786 */ 2787 2788/* 2789 * Map a set of physical memory pages into the kernel virtual 2790 * address space. Return a pointer to where it is mapped. This 2791 * routine is intended to be used for mapping device memory, 2792 * NOT real memory. 2793 */ 2794 2795/* 2796 * Map a set of physical memory pages into the kernel virtual 2797 * address space. Return a pointer to where it is mapped. This 2798 * routine is intended to be used for mapping device memory, 2799 * NOT real memory. 2800 */ 2801void * 2802pmap_mapdev(vm_offset_t pa, vm_size_t size) 2803{ 2804 vm_offset_t va, tmpva, offset; 2805 2806 /* 2807 * KSEG1 maps only first 512M of phys address space. For 2808 * pa > 0x20000000 we should make proper mapping * using pmap_kenter. 2809 */ 2810 if (pa + size < MIPS_KSEG0_LARGEST_PHYS) 2811 return (void *)MIPS_PHYS_TO_KSEG1(pa); 2812 else { 2813 offset = pa & PAGE_MASK; 2814 size = roundup(size, PAGE_SIZE); 2815 2816 va = kmem_alloc_nofault(kernel_map, size); 2817 if (!va) 2818 panic("pmap_mapdev: Couldn't alloc kernel virtual memory"); 2819 for (tmpva = va; size > 0;) { 2820 pmap_kenter(tmpva, pa); 2821 size -= PAGE_SIZE; 2822 tmpva += PAGE_SIZE; 2823 pa += PAGE_SIZE; 2824 } 2825 } 2826 2827 return ((void *)(va + offset)); 2828} 2829 2830void 2831pmap_unmapdev(vm_offset_t va, vm_size_t size) 2832{ 2833} 2834 2835/* 2836 * perform the pmap work for mincore 2837 */ 2838int 2839pmap_mincore(pmap_t pmap, vm_offset_t addr) 2840{ 2841 2842 pt_entry_t *ptep, pte; 2843 vm_page_t m; 2844 int val = 0; 2845 2846 PMAP_LOCK(pmap); 2847 ptep = pmap_pte(pmap, addr); 2848 pte = (ptep != NULL) ? *ptep : 0; 2849 PMAP_UNLOCK(pmap); 2850 2851 if (mips_pg_v(pte)) { 2852 vm_offset_t pa; 2853 2854 val = MINCORE_INCORE; 2855 pa = mips_tlbpfn_to_paddr(pte); 2856 if (!page_is_managed(pa)) 2857 return val; 2858 2859 m = PHYS_TO_VM_PAGE(pa); 2860 2861 /* 2862 * Modified by us 2863 */ 2864 if (pte & PTE_M) 2865 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER; 2866 /* 2867 * Modified by someone 2868 */ 2869 else { 2870 vm_page_lock_queues(); 2871 if (m->dirty || pmap_is_modified(m)) 2872 val |= MINCORE_MODIFIED_OTHER; 2873 vm_page_unlock_queues(); 2874 } 2875 /* 2876 * Referenced by us or someone 2877 */ 2878 vm_page_lock_queues(); 2879 if ((m->flags & PG_REFERENCED) || pmap_ts_referenced(m)) { 2880 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER; 2881 vm_page_flag_set(m, PG_REFERENCED); 2882 } 2883 vm_page_unlock_queues(); 2884 } 2885 return val; 2886} 2887 2888void 2889pmap_activate(struct thread *td) 2890{ 2891 pmap_t pmap, oldpmap; 2892 struct proc *p = td->td_proc; 2893 2894 critical_enter(); 2895 2896 pmap = vmspace_pmap(p->p_vmspace); 2897 oldpmap = PCPU_GET(curpmap); 2898 2899 if (oldpmap) 2900 atomic_clear_32(&oldpmap->pm_active, PCPU_GET(cpumask)); 2901 atomic_set_32(&pmap->pm_active, PCPU_GET(cpumask)); 2902 pmap_asid_alloc(pmap); 2903 if (td == curthread) { 2904 PCPU_SET(segbase, pmap->pm_segtab); 2905 MachSetPID(pmap->pm_asid[PCPU_GET(cpuid)].asid); 2906 } 2907 PCPU_SET(curpmap, pmap); 2908 critical_exit(); 2909} 2910 2911/* 2912 * Increase the starting virtual address of the given mapping if a 2913 * different alignment might result in more superpage mappings. 2914 */ 2915void 2916pmap_align_superpage(vm_object_t object, vm_ooffset_t offset, 2917 vm_offset_t *addr, vm_size_t size) 2918{ 2919 vm_offset_t superpage_offset; 2920 2921 if (size < NBSEG) 2922 return; 2923 if (object != NULL && (object->flags & OBJ_COLORED) != 0) 2924 offset += ptoa(object->pg_color); 2925 superpage_offset = offset & SEGOFSET; 2926 if (size - ((NBSEG - superpage_offset) & SEGOFSET) < NBSEG || 2927 (*addr & SEGOFSET) == superpage_offset) 2928 return; 2929 if ((*addr & SEGOFSET) < superpage_offset) 2930 *addr = (*addr & ~SEGOFSET) + superpage_offset; 2931 else 2932 *addr = ((*addr + SEGOFSET) & ~SEGOFSET) + superpage_offset; 2933} 2934 2935int pmap_pid_dump(int pid); 2936 2937int 2938pmap_pid_dump(int pid) 2939{ 2940 pmap_t pmap; 2941 struct proc *p; 2942 int npte = 0; 2943 int index; 2944 2945 sx_slock(&allproc_lock); 2946 LIST_FOREACH(p, &allproc, p_list) { 2947 if (p->p_pid != pid) 2948 continue; 2949 2950 if (p->p_vmspace) { 2951 int i, j; 2952 2953 printf("vmspace is %p\n", 2954 p->p_vmspace); 2955 index = 0; 2956 pmap = vmspace_pmap(p->p_vmspace); 2957 printf("pmap asid:%x generation:%x\n", 2958 pmap->pm_asid[0].asid, 2959 pmap->pm_asid[0].gen); 2960 for (i = 0; i < NUSERPGTBLS; i++) { 2961 pd_entry_t *pde; 2962 pt_entry_t *pte; 2963 unsigned base = i << SEGSHIFT; 2964 2965 pde = &pmap->pm_segtab[i]; 2966 if (pde && pmap_pde_v(pde)) { 2967 for (j = 0; j < 1024; j++) { 2968 unsigned va = base + 2969 (j << PAGE_SHIFT); 2970 2971 pte = pmap_pte(pmap, va); 2972 if (pte && pmap_pte_v(pte)) { 2973 vm_offset_t pa; 2974 vm_page_t m; 2975 2976 pa = mips_tlbpfn_to_paddr(*pte); 2977 m = PHYS_TO_VM_PAGE(pa); 2978 printf("va: 0x%x, pt: 0x%x, h: %d, w: %d, f: 0x%x", 2979 va, pa, 2980 m->hold_count, 2981 m->wire_count, 2982 m->flags); 2983 npte++; 2984 index++; 2985 if (index >= 2) { 2986 index = 0; 2987 printf("\n"); 2988 } else { 2989 printf(" "); 2990 } 2991 } 2992 } 2993 } 2994 } 2995 } else { 2996 printf("Process pid:%d has no vm_space\n", pid); 2997 } 2998 break; 2999 } 3000 sx_sunlock(&allproc_lock); 3001 return npte; 3002} 3003 3004 3005#if defined(DEBUG) 3006 3007static void pads(pmap_t pm); 3008void pmap_pvdump(vm_offset_t pa); 3009 3010/* print address space of pmap*/ 3011static void 3012pads(pmap_t pm) 3013{ 3014 unsigned va, i, j; 3015 pt_entry_t *ptep; 3016 3017 if (pm == kernel_pmap) 3018 return; 3019 for (i = 0; i < NPTEPG; i++) 3020 if (pm->pm_segtab[i]) 3021 for (j = 0; j < NPTEPG; j++) { 3022 va = (i << SEGSHIFT) + (j << PAGE_SHIFT); 3023 if (pm == kernel_pmap && va < KERNBASE) 3024 continue; 3025 if (pm != kernel_pmap && 3026 va >= VM_MAXUSER_ADDRESS) 3027 continue; 3028 ptep = pmap_pte(pm, va); 3029 if (pmap_pte_v(ptep)) 3030 printf("%x:%x ", va, *(int *)ptep); 3031 } 3032 3033} 3034 3035void 3036pmap_pvdump(vm_offset_t pa) 3037{ 3038 register pv_entry_t pv; 3039 vm_page_t m; 3040 3041 printf("pa %x", pa); 3042 m = PHYS_TO_VM_PAGE(pa); 3043 for (pv = TAILQ_FIRST(&m->md.pv_list); pv; 3044 pv = TAILQ_NEXT(pv, pv_list)) { 3045 printf(" -> pmap %p, va %x", (void *)pv->pv_pmap, pv->pv_va); 3046 pads(pv->pv_pmap); 3047 } 3048 printf(" "); 3049} 3050 3051/* N/C */ 3052#endif 3053 3054 3055/* 3056 * Allocate TLB address space tag (called ASID or TLBPID) and return it. 3057 * It takes almost as much or more time to search the TLB for a 3058 * specific ASID and flush those entries as it does to flush the entire TLB. 3059 * Therefore, when we allocate a new ASID, we just take the next number. When 3060 * we run out of numbers, we flush the TLB, increment the generation count 3061 * and start over. ASID zero is reserved for kernel use. 3062 */ 3063static void 3064pmap_asid_alloc(pmap) 3065 pmap_t pmap; 3066{ 3067 if (pmap->pm_asid[PCPU_GET(cpuid)].asid != PMAP_ASID_RESERVED && 3068 pmap->pm_asid[PCPU_GET(cpuid)].gen == PCPU_GET(asid_generation)); 3069 else { 3070 if (PCPU_GET(next_asid) == pmap_max_asid) { 3071 MIPS_TBIAP(); 3072 PCPU_SET(asid_generation, 3073 (PCPU_GET(asid_generation) + 1) & ASIDGEN_MASK); 3074 if (PCPU_GET(asid_generation) == 0) { 3075 PCPU_SET(asid_generation, 1); 3076 } 3077 PCPU_SET(next_asid, 1); /* 0 means invalid */ 3078 } 3079 pmap->pm_asid[PCPU_GET(cpuid)].asid = PCPU_GET(next_asid); 3080 pmap->pm_asid[PCPU_GET(cpuid)].gen = PCPU_GET(asid_generation); 3081 PCPU_SET(next_asid, PCPU_GET(next_asid) + 1); 3082 } 3083 3084#ifdef DEBUG 3085 if (pmapdebug & (PDB_FOLLOW | PDB_TLBPID)) { 3086 if (curproc) 3087 printf("pmap_asid_alloc: curproc %d '%s' ", 3088 curproc->p_pid, curproc->p_comm); 3089 else 3090 printf("pmap_asid_alloc: curproc <none> "); 3091 printf("segtab %p asid %d\n", pmap->pm_segtab, 3092 pmap->pm_asid[PCPU_GET(cpuid)].asid); 3093 } 3094#endif 3095} 3096 3097int 3098page_is_managed(vm_offset_t pa) 3099{ 3100 vm_offset_t pgnum = mips_btop(pa); 3101 3102 if (pgnum >= first_page && (pgnum < (first_page + vm_page_array_size))) { 3103 vm_page_t m; 3104 3105 m = PHYS_TO_VM_PAGE(pa); 3106 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0) 3107 return 1; 3108 } 3109 return 0; 3110} 3111 3112static int 3113init_pte_prot(vm_offset_t va, vm_page_t m, vm_prot_t prot) 3114{ 3115 int rw = 0; 3116 3117 if (!(prot & VM_PROT_WRITE)) 3118 rw = PTE_ROPAGE; 3119 else { 3120 if (va >= VM_MIN_KERNEL_ADDRESS) { 3121 /* 3122 * Don't bother to trap on kernel writes, just 3123 * record page as dirty. 3124 */ 3125 rw = PTE_RWPAGE; 3126 vm_page_dirty(m); 3127 } else if ((m->md.pv_flags & PV_TABLE_MOD) || m->dirty) 3128 rw = PTE_RWPAGE; 3129 else 3130 rw = PTE_CWPAGE; 3131 } 3132 return rw; 3133} 3134 3135/* 3136 * pmap_page_is_free: 3137 * 3138 * Called when a page is freed to allow pmap to clean up 3139 * any extra state associated with the page. In this case 3140 * clear modified/referenced bits. 3141 */ 3142void 3143pmap_page_is_free(vm_page_t m) 3144{ 3145 3146 m->md.pv_flags = 0; 3147} 3148 3149/* 3150 * pmap_set_modified: 3151 * 3152 * Sets the page modified and reference bits for the specified page. 3153 */ 3154void 3155pmap_set_modified(vm_offset_t pa) 3156{ 3157 3158 PHYS_TO_VM_PAGE(pa)->md.pv_flags |= (PV_TABLE_REF | PV_TABLE_MOD); 3159} 3160 3161#include <machine/db_machdep.h> 3162 3163/* 3164 * Dump the translation buffer (TLB) in readable form. 3165 */ 3166 3167void 3168db_dump_tlb(int first, int last) 3169{ 3170 struct tlb tlb; 3171 int tlbno; 3172 3173 tlbno = first; 3174 3175 while (tlbno <= last) { 3176 MachTLBRead(tlbno, &tlb); 3177 if (tlb.tlb_lo0 & PTE_V || tlb.tlb_lo1 & PTE_V) { 3178 printf("TLB %2d vad 0x%08x ", tlbno, (tlb.tlb_hi & 0xffffff00)); 3179 } else { 3180 printf("TLB*%2d vad 0x%08x ", tlbno, (tlb.tlb_hi & 0xffffff00)); 3181 } 3182 printf("0=0x%08x ", pfn_to_vad(tlb.tlb_lo0)); 3183 printf("%c", tlb.tlb_lo0 & PTE_M ? 'M' : ' '); 3184 printf("%c", tlb.tlb_lo0 & PTE_G ? 'G' : ' '); 3185 printf(" atr %x ", (tlb.tlb_lo0 >> 3) & 7); 3186 printf("1=0x%08x ", pfn_to_vad(tlb.tlb_lo1)); 3187 printf("%c", tlb.tlb_lo1 & PTE_M ? 'M' : ' '); 3188 printf("%c", tlb.tlb_lo1 & PTE_G ? 'G' : ' '); 3189 printf(" atr %x ", (tlb.tlb_lo1 >> 3) & 7); 3190 printf(" sz=%x pid=%x\n", tlb.tlb_mask, 3191 (tlb.tlb_hi & 0x000000ff) 3192 ); 3193 tlbno++; 3194 } 3195} 3196 3197#ifdef DDB 3198#include <sys/kernel.h> 3199#include <ddb/ddb.h> 3200 3201DB_SHOW_COMMAND(tlb, ddb_dump_tlb) 3202{ 3203 db_dump_tlb(0, num_tlbentries - 1); 3204} 3205 3206#endif 3207 3208/* 3209 * Routine: pmap_kextract 3210 * Function: 3211 * Extract the physical page address associated 3212 * virtual address. 3213 */ 3214 /* PMAP_INLINE */ vm_offset_t 3215pmap_kextract(vm_offset_t va) 3216{ 3217 vm_offset_t pa = 0; 3218 3219 if (va < MIPS_CACHED_MEMORY_ADDR) { 3220 /* user virtual address */ 3221 pt_entry_t *ptep; 3222 3223 if (curproc && curproc->p_vmspace) { 3224 ptep = pmap_pte(&curproc->p_vmspace->vm_pmap, va); 3225 if (ptep) 3226 pa = mips_tlbpfn_to_paddr(*ptep) | 3227 (va & PAGE_MASK); 3228 } 3229 } else if (va >= MIPS_CACHED_MEMORY_ADDR && 3230 va < MIPS_UNCACHED_MEMORY_ADDR) 3231 pa = MIPS_CACHED_TO_PHYS(va); 3232 else if (va >= MIPS_UNCACHED_MEMORY_ADDR && 3233 va < MIPS_KSEG2_START) 3234 pa = MIPS_UNCACHED_TO_PHYS(va); 3235#ifdef VM_ALLOC_WIRED_TLB_PG_POOL 3236 else if (need_wired_tlb_page_pool && ((va >= VM_MIN_KERNEL_ADDRESS) && 3237 (va < (VM_MIN_KERNEL_ADDRESS + VM_KERNEL_ALLOC_OFFSET)))) 3238 pa = MIPS_CACHED_TO_PHYS(va); 3239#endif 3240 else if (va >= MIPS_KSEG2_START && va < VM_MAX_KERNEL_ADDRESS) { 3241 pt_entry_t *ptep; 3242 3243 if (kernel_pmap) { 3244 if (va >= (vm_offset_t)virtual_sys_start) { 3245 /* Its inside the virtual address range */ 3246 ptep = pmap_pte(kernel_pmap, va); 3247 if (ptep) 3248 pa = mips_tlbpfn_to_paddr(*ptep) | 3249 (va & PAGE_MASK); 3250 } else { 3251 int i; 3252 3253 /* 3254 * its inside the special mapping area, I 3255 * don't think this should happen, but if it 3256 * does I want it toa all work right :-) 3257 * Note if it does happen, we assume the 3258 * caller has the lock? FIXME, this needs to 3259 * be checked FIXEM - RRS. 3260 */ 3261 for (i = 0; i < MAXCPU; i++) { 3262 if ((sysmap_lmem[i].valid1) && ((vm_offset_t)sysmap_lmem[i].CADDR1 == va)) { 3263 pa = mips_tlbpfn_to_paddr(sysmap_lmem[i].CMAP1); 3264 break; 3265 } 3266 if ((sysmap_lmem[i].valid2) && ((vm_offset_t)sysmap_lmem[i].CADDR2 == va)) { 3267 pa = mips_tlbpfn_to_paddr(sysmap_lmem[i].CMAP2); 3268 break; 3269 } 3270 } 3271 } 3272 } 3273 } 3274 return pa; 3275} 3276