machdep.c revision 211280
1 /* $OpenBSD: machdep.c,v 1.33 1998/09/15 10:58:54 pefo Exp $ */ 2/* tracked to 1.38 */ 3/* 4 * Copyright (c) 1988 University of Utah. 5 * Copyright (c) 1992, 1993 6 * The Regents of the University of California. All rights reserved. 7 * 8 * This code is derived from software contributed to Berkeley by 9 * the Systems Programming Group of the University of Utah Computer 10 * Science Department, The Mach Operating System project at 11 * Carnegie-Mellon University and Ralph Campbell. 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 1. Redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution. 21 * 4. Neither the name of the University nor the names of its contributors 22 * may be used to endorse or promote products derived from this software 23 * without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 28 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 31 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35 * SUCH DAMAGE. 36 * 37 * from: @(#)machdep.c 8.3 (Berkeley) 1/12/94 38 * Id: machdep.c,v 1.33 1998/09/15 10:58:54 pefo Exp 39 * JNPR: machdep.c,v 1.11.2.3 2007/08/29 12:24:49 40 */ 41 42#include <sys/cdefs.h> 43__FBSDID("$FreeBSD: head/sys/mips/mips/machdep.c 211280 2010-08-13 12:56:00Z jchandra $"); 44 45#include "opt_cputype.h" 46#include "opt_ddb.h" 47#include "opt_md.h" 48#include "opt_msgbuf.h" 49 50#include <sys/param.h> 51#include <sys/proc.h> 52#include <sys/systm.h> 53#include <sys/buf.h> 54#include <sys/bus.h> 55#include <sys/conf.h> 56#include <sys/cpu.h> 57#include <sys/kernel.h> 58#include <sys/linker.h> 59#include <sys/malloc.h> 60#include <sys/mbuf.h> 61#include <sys/msgbuf.h> 62#include <sys/reboot.h> 63#include <sys/sched.h> 64#include <sys/sysctl.h> 65#include <sys/sysproto.h> 66#include <sys/vmmeter.h> 67 68#include <vm/vm.h> 69#include <vm/vm_kern.h> 70#include <vm/vm_object.h> 71#include <vm/vm_page.h> 72#include <vm/pmap.h> 73#include <vm/vm_map.h> 74#include <vm/vm_pager.h> 75#include <vm/vm_extern.h> 76#include <sys/socket.h> 77 78#include <sys/user.h> 79#include <sys/interrupt.h> 80#include <sys/cons.h> 81#include <sys/syslog.h> 82#include <machine/asm.h> 83#include <machine/bootinfo.h> 84#include <machine/cache.h> 85#include <machine/clock.h> 86#include <machine/cpu.h> 87#include <machine/cpuregs.h> 88#include <machine/elf.h> 89#include <machine/hwfunc.h> 90#include <machine/intr_machdep.h> 91#include <machine/md_var.h> 92#include <machine/tlb.h> 93#ifdef DDB 94#include <sys/kdb.h> 95#include <ddb/ddb.h> 96#endif 97 98#include <sys/random.h> 99#include <net/if.h> 100 101#define BOOTINFO_DEBUG 0 102 103char machine[] = "mips"; 104SYSCTL_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD, machine, 0, "Machine class"); 105 106static char cpu_model[30]; 107SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD, cpu_model, 0, "Machine model"); 108 109int cold = 1; 110long realmem = 0; 111long Maxmem = 0; 112int cpu_clock = MIPS_DEFAULT_HZ; 113SYSCTL_INT(_hw, OID_AUTO, clockrate, CTLFLAG_RD, 114 &cpu_clock, 0, "CPU instruction clock rate"); 115int clocks_running = 0; 116 117vm_offset_t kstack0; 118 119/* 120 * Each entry in the pcpu_space[] array is laid out in the following manner: 121 * struct pcpu for cpu 'n' pcpu_space[n] 122 * boot stack for cpu 'n' pcpu_space[n] + PAGE_SIZE * 2 - CALLFRAME_SIZ 123 * 124 * Note that the boot stack grows downwards and we assume that we never 125 * use enough stack space to trample over the 'struct pcpu' that is at 126 * the beginning of the array. 127 * 128 * The array is aligned on a (PAGE_SIZE * 2) boundary so that the 'struct pcpu' 129 * is always in the even page frame of the wired TLB entry on SMP kernels. 130 * 131 * The array is in the .data section so that the stack does not get zeroed out 132 * when the .bss section is zeroed. 133 */ 134char pcpu_space[MAXCPU][PAGE_SIZE * 2] \ 135 __aligned(PAGE_SIZE * 2) __section(".data"); 136 137struct pcpu *pcpup = (struct pcpu *)pcpu_space; 138 139vm_offset_t phys_avail[PHYS_AVAIL_ENTRIES + 2]; 140vm_offset_t physmem_desc[PHYS_AVAIL_ENTRIES + 2]; 141 142#ifdef UNIMPLEMENTED 143struct platform platform; 144#endif 145 146static void cpu_startup(void *); 147SYSINIT(cpu, SI_SUB_CPU, SI_ORDER_FIRST, cpu_startup, NULL); 148 149struct kva_md_info kmi; 150 151int cpucfg; /* Value of processor config register */ 152int num_tlbentries = 64; /* Size of the CPU tlb */ 153int cputype; 154 155extern char MipsException[], MipsExceptionEnd[]; 156 157/* TLB miss handler address and end */ 158extern char MipsTLBMiss[], MipsTLBMissEnd[]; 159 160/* Cache error handler */ 161extern char MipsCache[], MipsCacheEnd[]; 162 163extern char edata[], end[]; 164#ifdef DDB 165extern vm_offset_t ksym_start, ksym_end; 166#endif 167 168u_int32_t bootdev; 169struct bootinfo bootinfo; 170/* 171 * First kseg0 address available for use. By default it's equal to &end. 172 * But in some cases there might be additional data placed right after 173 * _end by loader or ELF trampoline. 174 */ 175vm_offset_t kernel_kseg0_end = (vm_offset_t)&end; 176 177static void 178cpu_startup(void *dummy) 179{ 180 181 if (boothowto & RB_VERBOSE) 182 bootverbose++; 183 184 printf("real memory = %lu (%luK bytes)\n", ptoa(realmem), 185 ptoa(realmem) / 1024); 186 187 /* 188 * Display any holes after the first chunk of extended memory. 189 */ 190 if (bootverbose) { 191 int indx; 192 193 printf("Physical memory chunk(s):\n"); 194 for (indx = 0; phys_avail[indx + 1] != 0; indx += 2) { 195 uintptr_t size1 = phys_avail[indx + 1] - phys_avail[indx]; 196 197 printf("0x%08llx - 0x%08llx, %llu bytes (%llu pages)\n", 198 (unsigned long long)phys_avail[indx], 199 (unsigned long long)phys_avail[indx + 1] - 1, 200 (unsigned long long)size1, 201 (unsigned long long)size1 / PAGE_SIZE); 202 } 203 } 204 205 vm_ksubmap_init(&kmi); 206 207 printf("avail memory = %lu (%luMB)\n", ptoa(cnt.v_free_count), 208 ptoa(cnt.v_free_count) / 1048576); 209 cpu_init_interrupts(); 210 211 /* 212 * Set up buffers, so they can be used to read disk labels. 213 */ 214 bufinit(); 215 vm_pager_bufferinit(); 216} 217 218/* 219 * Shutdown the CPU as much as possible 220 */ 221void 222cpu_reset(void) 223{ 224 225 platform_reset(); 226} 227 228/* 229 * Flush the D-cache for non-DMA I/O so that the I-cache can 230 * be made coherent later. 231 */ 232void 233cpu_flush_dcache(void *ptr, size_t len) 234{ 235 /* TBD */ 236} 237 238/* Get current clock frequency for the given cpu id. */ 239int 240cpu_est_clockrate(int cpu_id, uint64_t *rate) 241{ 242 243 return (ENXIO); 244} 245 246/* 247 * Shutdown the CPU as much as possible 248 */ 249void 250cpu_halt(void) 251{ 252 for (;;) 253 ; 254} 255 256SYSCTL_STRUCT(_machdep, OID_AUTO, bootinfo, CTLFLAG_RD, &bootinfo, 257 bootinfo, "Bootinfo struct: kernel filename, BIOS harddisk geometry, etc"); 258 259/* 260 * Initialize per cpu data structures, include curthread. 261 */ 262void 263mips_pcpu0_init() 264{ 265 /* Initialize pcpu info of cpu-zero */ 266 pcpu_init(PCPU_ADDR(0), 0, sizeof(struct pcpu)); 267 PCPU_SET(curthread, &thread0); 268} 269 270/* 271 * Initialize mips and configure to run kernel 272 */ 273void 274mips_proc0_init(void) 275{ 276#ifdef SMP 277 if (platform_processor_id() != 0) 278 panic("BSP must be processor number 0"); 279#endif 280 proc_linkup0(&proc0, &thread0); 281 282 KASSERT((kstack0 & PAGE_MASK) == 0, 283 ("kstack0 is not aligned on a page boundary: 0x%0lx", 284 (long)kstack0)); 285 thread0.td_kstack = kstack0; 286 thread0.td_kstack_pages = KSTACK_PAGES; 287 /* 288 * Do not use cpu_thread_alloc to initialize these fields 289 * thread0 is the only thread that has kstack located in KSEG0 290 * while cpu_thread_alloc handles kstack allocated in KSEG2. 291 */ 292 thread0.td_pcb = (struct pcb *)(thread0.td_kstack + 293 thread0.td_kstack_pages * PAGE_SIZE) - 1; 294 thread0.td_frame = &thread0.td_pcb->pcb_regs; 295 296 /* Steal memory for the dynamic per-cpu area. */ 297 dpcpu_init((void *)pmap_steal_memory(DPCPU_SIZE), 0); 298 299 PCPU_SET(curpcb, thread0.td_pcb); 300 /* 301 * There is no need to initialize md_upte array for thread0 as it's 302 * located in .bss section and should be explicitly zeroed during 303 * kernel initialization. 304 */ 305} 306 307void 308cpu_initclocks(void) 309{ 310 311 platform_initclocks(); 312 cpu_initclocks_bsp(); 313} 314 315struct msgbuf *msgbufp=0; 316 317/* 318 * Initialize the hardware exception vectors, and the jump table used to 319 * call locore cache and TLB management functions, based on the kind 320 * of CPU the kernel is running on. 321 */ 322void 323mips_vector_init(void) 324{ 325 /* 326 * Copy down exception vector code. 327 */ 328 if (MipsTLBMissEnd - MipsTLBMiss > 0x80) 329 panic("startup: UTLB code too large"); 330 331 if (MipsCacheEnd - MipsCache > 0x80) 332 panic("startup: Cache error code too large"); 333 334 bcopy(MipsTLBMiss, (void *)MIPS_UTLB_MISS_EXC_VEC, 335 MipsTLBMissEnd - MipsTLBMiss); 336 337#if defined(CPU_CNMIPS) || defined(CPU_RMI) 338/* Fake, but sufficient, for the 32-bit with 64-bit hardware addresses */ 339 bcopy(MipsTLBMiss, (void *)MIPS3_XTLB_MISS_EXC_VEC, 340 MipsTLBMissEnd - MipsTLBMiss); 341#endif 342 343 bcopy(MipsException, (void *)MIPS3_GEN_EXC_VEC, 344 MipsExceptionEnd - MipsException); 345 346 bcopy(MipsCache, (void *)MIPS3_CACHE_ERR_EXC_VEC, 347 MipsCacheEnd - MipsCache); 348 349 /* 350 * Clear out the I and D caches. 351 */ 352 mips_icache_sync_all(); 353 mips_dcache_wbinv_all(); 354 355 /* 356 * Mask all interrupts. Each interrupt will be enabled 357 * when handler is installed for it 358 */ 359 set_intr_mask(MIPS_SR_INT_MASK); 360 361 /* Clear BEV in SR so we start handling our own exceptions */ 362 mips_wr_status(mips_rd_status() & ~MIPS_SR_BEV); 363} 364 365/* 366 * Fix kernel_kseg0_end address in case trampoline placed debug sympols 367 * data there 368 */ 369void 370mips_postboot_fixup(void) 371{ 372#ifdef DDB 373 Elf_Size *trampoline_data = (Elf_Size*)kernel_kseg0_end; 374 Elf_Size symtabsize = 0; 375 376 if (trampoline_data[0] == SYMTAB_MAGIC) { 377 symtabsize = trampoline_data[1]; 378 kernel_kseg0_end += 2 * sizeof(Elf_Size); 379 /* start of .symtab */ 380 ksym_start = kernel_kseg0_end; 381 kernel_kseg0_end += symtabsize; 382 /* end of .strtab */ 383 ksym_end = kernel_kseg0_end; 384 } 385#endif 386} 387 388/* 389 * Many SoCs have a means to reset the core itself. Others do not, or 390 * the method is unknown to us. For those cases, we jump to the mips 391 * reset vector and hope for the best. This works well in practice. 392 */ 393void 394mips_generic_reset() 395{ 396 ((void(*)(void))(intptr_t)MIPS_VEC_RESET)(); 397} 398 399#ifdef SMP 400void 401mips_pcpu_tlb_init(struct pcpu *pcpu) 402{ 403 vm_paddr_t pa; 404 pt_entry_t pte; 405 406 /* 407 * Map the pcpu structure at the virtual address 'pcpup'. 408 * We use a wired tlb index to do this one-time mapping. 409 */ 410 pa = vtophys(pcpu); 411 pte = PTE_D | PTE_V | PTE_G | PTE_C_CACHE; 412 tlb_insert_wired(PCPU_TLB_ENTRY, (vm_offset_t)pcpup, 413 TLBLO_PA_TO_PFN(pa) | pte, 414 TLBLO_PA_TO_PFN(pa + PAGE_SIZE) | pte); 415} 416#endif 417 418/* 419 * Initialise a struct pcpu. 420 */ 421void 422cpu_pcpu_init(struct pcpu *pcpu, int cpuid, size_t size) 423{ 424 425 pcpu->pc_next_asid = 1; 426 pcpu->pc_asid_generation = 1; 427#ifdef SMP 428 if ((vm_offset_t)pcpup >= VM_MIN_KERNEL_ADDRESS) 429 mips_pcpu_tlb_init(pcpu); 430#endif 431} 432 433int 434fill_dbregs(struct thread *td, struct dbreg *dbregs) 435{ 436 437 /* No debug registers on mips */ 438 return (ENOSYS); 439} 440 441int 442set_dbregs(struct thread *td, struct dbreg *dbregs) 443{ 444 445 /* No debug registers on mips */ 446 return (ENOSYS); 447} 448 449void 450spinlock_enter(void) 451{ 452 struct thread *td; 453 454 td = curthread; 455 if (td->td_md.md_spinlock_count == 0) 456 td->td_md.md_saved_intr = intr_disable(); 457 td->td_md.md_spinlock_count++; 458 critical_enter(); 459} 460 461void 462spinlock_exit(void) 463{ 464 struct thread *td; 465 466 td = curthread; 467 critical_exit(); 468 td->td_md.md_spinlock_count--; 469 if (td->td_md.md_spinlock_count == 0) 470 intr_restore(td->td_md.md_saved_intr); 471} 472 473/* 474 * call platform specific code to halt (until next interrupt) for the idle loop 475 */ 476void 477cpu_idle(int busy) 478{ 479 if (mips_rd_status() & MIPS_SR_INT_IE) 480 __asm __volatile ("wait"); 481 else 482 panic("ints disabled in idleproc!"); 483} 484 485void 486dumpsys(struct dumperinfo *di __unused) 487{ 488 489 printf("Kernel dumps not implemented on this architecture\n"); 490} 491 492int 493cpu_idle_wakeup(int cpu) 494{ 495 496 return (0); 497} 498 499int 500is_physical_memory(vm_offset_t addr) 501{ 502 int i; 503 504 for (i = 0; physmem_desc[i + 1] != 0; i += 2) { 505 if (addr >= physmem_desc[i] && addr < physmem_desc[i + 1]) 506 return (1); 507 } 508 509 return (0); 510} 511