locore.S revision 202864
1/* $OpenBSD: locore.S,v 1.18 1998/09/15 10:58:53 pefo Exp $ */ 2/*- 3 * Copyright (c) 1992, 1993 4 * The Regents of the University of California. All rights reserved. 5 * 6 * This code is derived from software contributed to Berkeley by 7 * Digital Equipment Corporation and Ralph Campbell. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 4. Neither the name of the University nor the names of its contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 25 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 31 * SUCH DAMAGE. 32 * 33 * Copyright (C) 1989 Digital Equipment Corporation. 34 * Permission to use, copy, modify, and distribute this software and 35 * its documentation for any purpose and without fee is hereby granted, 36 * provided that the above copyright notice appears in all copies. 37 * Digital Equipment Corporation makes no representations about the 38 * suitability of this software for any purpose. It is provided "as is" 39 * without express or implied warranty. 40 * 41 * from: Header: /sprite/src/kernel/mach/ds3100.md/RCS/loMem.s, 42 * v 1.1 89/07/11 17:55:04 nelson Exp SPRITE (DECWRL) 43 * from: Header: /sprite/src/kernel/mach/ds3100.md/RCS/machAsm.s, 44 * v 9.2 90/01/29 18:00:39 shirriff Exp SPRITE (DECWRL) 45 * from: Header: /sprite/src/kernel/vm/ds3100.md/vmPmaxAsm.s, 46 * v 1.1 89/07/10 14:27:41 nelson Exp SPRITE (DECWRL) 47 * 48 * from: @(#)locore.s 8.5 (Berkeley) 1/4/94 49 * JNPR: locore.S,v 1.6.2.1 2007/08/29 12:24:49 girish 50 * $FreeBSD: head/sys/mips/mips/locore.S 202864 2010-01-23 03:19:13Z neel $ 51 */ 52 53/* 54 * FREEBSD_DEVELOPERS_FIXME 55 * The start routine below was written for a multi-core CPU 56 * with each core being hyperthreaded. This serves as an example 57 * for a complex CPU architecture. For a different CPU complex 58 * please make necessary changes to read CPU-ID etc. 59 * A clean solution would be to have a different locore file for 60 * each CPU type. 61 */ 62 63/* 64 * Contains code that is the first executed at boot time plus 65 * assembly language support routines. 66 */ 67 68#include <machine/asm.h> 69#include <machine/cpu.h> 70#include <machine/cpuregs.h> 71#include <machine/regnum.h> 72 73#include "assym.s" 74 75 .data 76#ifdef YAMON 77GLOBAL(fenvp) 78 .space 4 # Assumes mips32? Is that OK? 79#endif 80GLOBAL(stackspace) 81 .space NBPG /* Smaller than it should be since it's temp. */ 82 .align 8 83GLOBAL(topstack) 84 85 86 .set noreorder 87 88 .text 89 90GLOBAL(btext) 91ASM_ENTRY(_start) 92VECTOR(_locore, unknown) 93 /* UNSAFE TO USE a0..a3, since some bootloaders pass that to us */ 94 mtc0 zero, COP_0_CAUSE_REG # Clear soft interrupts 95 96#if defined(TARGET_OCTEON) 97 /* 98 * t1: Bits to set explicitly: 99 * Enable FPU 100 */ 101 102 /* Set these bits */ 103 li t1, (MIPS_SR_COP_2_BIT | MIPS_SR_COP_0_BIT | MIPS_SR_PX | MIPS_SR_KX | MIPS_SR_UX | MIPS_SR_SX | MIPS_SR_BEV) 104 105 /* Reset these bits */ 106 li t0, ~(MIPS_SR_DE | MIPS_SR_SOFT_RESET | MIPS_SR_ERL | MIPS_SR_EXL | MIPS_SR_INT_IE) 107#else 108 /* 109 * t0: Bits to preserve if set: 110 * Soft reset 111 * Boot exception vectors (firmware-provided) 112 */ 113 li t0, (MIPS_SR_BEV | MIPS_SR_SOFT_RESET) 114 /* 115 * t1: Bits to set explicitly: 116 * Enable FPU 117 */ 118 li t1, MIPS_SR_COP_1_BIT 119#endif 120 /* 121 * Read coprocessor 0 status register, clear bits not 122 * preserved (namely, clearing interrupt bits), and set 123 * bits we want to explicitly set. 124 */ 125 mfc0 t2, COP_0_STATUS_REG 126 and t2, t0 127 or t2, t1 128 mtc0 t2, COP_0_STATUS_REG 129 COP0_SYNC 130 /* Make sure KSEG0 is cached */ 131 li t0, CFG_K0_CACHED 132 mtc0 t0, MIPS_COP_0_CONFIG 133 COP0_SYNC 134 135 /* Read and store the PrID FPU ID for CPU identification, if any. */ 136 mfc0 t2, COP_0_STATUS_REG 137 mfc0 t0, MIPS_COP_0_PRID 138#ifdef CPU_HAVEFPU 139 and t2, MIPS_SR_COP_1_BIT 140 beqz t2, 1f 141 move t1, zero 142 cfc1 t1, MIPS_FPU_ID 1431: 144#else 145 /* 146 * This platform has no FPU, and attempting to detect one 147 * using the official method causes an exception. 148 */ 149 move t1, zero 150#endif 151 sw t0, _C_LABEL(cpu_id) 152 sw t1, _C_LABEL(fpu_id) 153 154/* 155 * Initialize stack and call machine startup. 156 */ 157 PTR_LA sp, _C_LABEL(topstack) - START_FRAME 158 PTR_LA gp, _C_LABEL(_gp) 159 sw zero, START_FRAME - 4(sp) # Zero out old ra for debugger 160 161 /*xxximp 162 * now that we pass a0...a3 to the platform_init routine, do we need 163 * to stash this stuff here? 164 */ 165#ifdef YAMON 166 /* Save YAMON boot environment pointer */ 167 sw a2, _C_LABEL(fenvp) 168#endif 169 170 /* 171 * The following needs to be done differently for each platform and 172 * there needs to be a good way to plug this in. 173 */ 174#if defined(SMP) && defined(CPU_XLR) 175/* 176 * Block all the slave CPUs 177 */ 178 /* XXX a0, a1, a2 shouldn't be used here */ 179 /* 180 * Read the cpu id from the cp0 config register 181 * cpuid[9:4], thrid[3: 0] 182 */ 183 mfc0 a0, COP_0_CONFIG, 7 184 srl a1, a0, 4 185 andi a1, a1, 0x3f 186 andi a0, a0, 0xf 187 188 /* calculate linear cpuid */ 189 sll t0, a1, 2 190 addu a2, t0, a0 191/* Initially, disable all hardware threads on each core except thread0 */ 192 li t1, VCPU_ID_0 193 li t2, XLR_THREAD_ENABLE_IND 194 mtcr t1, t2 195#endif 196 197 198#if defined(TARGET_OCTEON) /* Maybe this is mips32/64 generic? */ 199 .set push 200 .set mips32r2 201 rdhwr t0, $0 202 .set pop 203#else 204 move t0, zero 205#endif 206 207 /* Stage the secondary cpu start until later */ 208 bne t0, zero, start_secondary 209 nop 210 211#ifdef SMP 212 PTR_LA t0, _C_LABEL(__pcpu) 213 SET_CPU_PCPU(t0) 214 /* If not master cpu, jump... */ 215/*XXX this assumes the above #if 0'd code runs */ 216 bne a2, zero, start_secondary 217 nop 218#endif 219 220 /* Call the platform-specific startup code. */ 221 jal _C_LABEL(platform_start) 222 sw zero, START_FRAME - 8(sp) # Zero out old fp for debugger 223 224 PTR_LA sp, _C_LABEL(thread0) 225 lw a0, TD_PCB(sp) 226 li t0, ~7 227 and a0, a0, t0 228 subu sp, a0, START_FRAME 229 230 jal _C_LABEL(mi_startup) # mi_startup(frame) 231 sw zero, START_FRAME - 8(sp) # Zero out old fp for debugger 232 233 PANIC("Startup failed!") 234 235#ifdef SMP 236start_secondary: 237 move a0, a1 2382: 239 addiu t0, PCPU_SIZE 240 subu a1, 1 241 bne a1, zero, 2b 242 nop 243 SET_CPU_PCPU(t0) 244smp_wait: 245 lw sp, PC_BOOT_STACK(t0) 246 beqz sp, smp_wait 247 nop 248 jal _C_LABEL(smp_init_secondary) 249 nop 250#else 251start_secondary: 252 b start_secondary 253 nop 254#endif 255 256VECTOR_END(_locore) 257