locore.S revision 206721
1219820Sjeff/*	$OpenBSD: locore.S,v 1.18 1998/09/15 10:58:53 pefo Exp $	*/
2219820Sjeff/*-
3219820Sjeff * Copyright (c) 1992, 1993
4219820Sjeff *	The Regents of the University of California.  All rights reserved.
5270710Shselasky *
6219820Sjeff * This code is derived from software contributed to Berkeley by
7219820Sjeff * Digital Equipment Corporation and Ralph Campbell.
8219820Sjeff *
9219820Sjeff * Redistribution and use in source and binary forms, with or without
10219820Sjeff * modification, are permitted provided that the following conditions
11219820Sjeff * are met:
12219820Sjeff * 1. Redistributions of source code must retain the above copyright
13219820Sjeff *    notice, this list of conditions and the following disclaimer.
14219820Sjeff * 2. Redistributions in binary form must reproduce the above copyright
15219820Sjeff *    notice, this list of conditions and the following disclaimer in the
16219820Sjeff *    documentation and/or other materials provided with the distribution.
17219820Sjeff * 4. Neither the name of the University nor the names of its contributors
18219820Sjeff *    may be used to endorse or promote products derived from this software
19219820Sjeff *    without specific prior written permission.
20219820Sjeff *
21219820Sjeff * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
22219820Sjeff * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23219820Sjeff * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24219820Sjeff * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
25219820Sjeff * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
26219820Sjeff * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
27219820Sjeff * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
28289644Shselasky * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
29289644Shselasky * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30219820Sjeff * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31219820Sjeff * SUCH DAMAGE.
32219820Sjeff *
33219820Sjeff * Copyright (C) 1989 Digital Equipment Corporation.
34219820Sjeff * Permission to use, copy, modify, and distribute this software and
35219820Sjeff * its documentation for any purpose and without fee is hereby granted,
36219820Sjeff * provided that the above copyright notice appears in all copies.
37219820Sjeff * Digital Equipment Corporation makes no representations about the
38219820Sjeff * suitability of this software for any purpose.  It is provided "as is"
39219820Sjeff * without express or implied warranty.
40219820Sjeff *
41219820Sjeff * from: Header: /sprite/src/kernel/mach/ds3100.md/RCS/loMem.s,
42219820Sjeff *	v 1.1 89/07/11 17:55:04 nelson Exp  SPRITE (DECWRL)
43219820Sjeff * from: Header: /sprite/src/kernel/mach/ds3100.md/RCS/machAsm.s,
44219820Sjeff *	v 9.2 90/01/29 18:00:39 shirriff Exp  SPRITE (DECWRL)
45219820Sjeff * from: Header: /sprite/src/kernel/vm/ds3100.md/vmPmaxAsm.s,
46219820Sjeff *	v 1.1 89/07/10 14:27:41 nelson Exp  SPRITE (DECWRL)
47219820Sjeff *
48219820Sjeff *	from: @(#)locore.s	8.5 (Berkeley) 1/4/94
49219820Sjeff *	JNPR: locore.S,v 1.6.2.1 2007/08/29 12:24:49 girish
50219820Sjeff * $FreeBSD: head/sys/mips/mips/locore.S 206721 2010-04-17 03:08:13Z jmallett $
51219820Sjeff */
52219820Sjeff
53219820Sjeff/*
54219820Sjeff * FREEBSD_DEVELOPERS_FIXME
55219820Sjeff * The start routine below was written for a multi-core CPU
56219820Sjeff * with each core being hyperthreaded. This serves as an example
57219820Sjeff * for a complex CPU architecture. For a different CPU complex
58219820Sjeff * please make necessary changes to read CPU-ID etc.
59219820Sjeff * A clean solution would be to have a different locore file for
60219820Sjeff * each CPU type.
61219820Sjeff */
62219820Sjeff
63219820Sjeff/*
64219820Sjeff *	Contains code that is the first executed at boot time plus
65219820Sjeff *	assembly language support routines.
66219820Sjeff */
67219820Sjeff
68219820Sjeff#include <machine/asm.h>
69219820Sjeff#include <machine/cpu.h>
70219820Sjeff#include <machine/cpuregs.h>
71219820Sjeff#include <machine/regnum.h>
72219820Sjeff
73219820Sjeff#include "assym.s"
74219820Sjeff
75219820Sjeff	.data
76219820Sjeff#ifdef YAMON
77219820SjeffGLOBAL(fenvp)
78219820Sjeff	.space 4			# Assumes mips32?  Is that OK?
79219820Sjeff#endif
80219820Sjeff
81219820Sjeff	.set noreorder
82219820Sjeff
83219820Sjeff	.text
84219820Sjeff
85219820SjeffGLOBAL(btext)
86219820SjeffASM_ENTRY(_start)
87219820SjeffVECTOR(_locore, unknown)
88219820Sjeff	/* UNSAFE TO USE a0..a3, since some bootloaders pass that to us */
89219820Sjeff	mtc0	zero, COP_0_CAUSE_REG	# Clear soft interrupts
90219820Sjeff
91289571Shselasky#if defined(TARGET_OCTEON)
92219820Sjeff	/*
93219820Sjeff	 * t1: Bits to set explicitly:
94219820Sjeff	 *	Enable FPU
95219820Sjeff	 */
96219820Sjeff
97219820Sjeff	/* Set these bits */
98219820Sjeff        li	t1, (MIPS_SR_COP_2_BIT | MIPS_SR_COP_0_BIT | MIPS_SR_PX | MIPS_SR_KX | MIPS_SR_UX | MIPS_SR_SX | MIPS_SR_BEV)
99219820Sjeff
100331756Semaste	/* Reset these bits */
101219820Sjeff        li	t0, ~(MIPS_SR_DE | MIPS_SR_SOFT_RESET | MIPS_SR_ERL | MIPS_SR_EXL | MIPS_SR_INT_IE)
102219820Sjeff#elif defined (CPU_XLR)
103219820Sjeff	/* Set these bits */
104219820Sjeff        li	t1, (MIPS_SR_COP_2_BIT | MIPS_SR_COP_0_BIT | MIPS_SR_KX)
105219820Sjeff
106219820Sjeff	/* Reset these bits */
107219820Sjeff        li	t0, ~(MIPS_SR_BEV | MIPS_SR_SOFT_RESET | MIPS_SR_INT_IE)
108219820Sjeff#else
109219820Sjeff	/*
110219820Sjeff	 * t0: Bits to preserve if set:
111219820Sjeff	 * 	Soft reset
112219820Sjeff	 *	Boot exception vectors (firmware-provided)
113219820Sjeff	 */
114219820Sjeff	li	t0, (MIPS_SR_BEV | MIPS_SR_SOFT_RESET)
115219820Sjeff	/*
116219820Sjeff	 * t1: Bits to set explicitly:
117219820Sjeff	 *	Enable FPU
118298829Spfg	 */
119219820Sjeff	li	t1, MIPS_SR_COP_1_BIT
120219820Sjeff#endif
121219820Sjeff	/*
122345907Shselasky	 * Read coprocessor 0 status register, clear bits not
123345907Shselasky	 * preserved (namely, clearing interrupt bits), and set
124345907Shselasky	 * bits we want to explicitly set.
125345907Shselasky	 */
126345907Shselasky	mfc0	t2, COP_0_STATUS_REG
127345907Shselasky	and	t2, t0
128345907Shselasky	or	t2, t1
129345907Shselasky	mtc0	t2, COP_0_STATUS_REG
130345907Shselasky	COP0_SYNC
131345907Shselasky
132345907Shselasky	/* Make sure KSEG0 is cached */
133219820Sjeff	li	t0, CFG_K0_CACHED
134219820Sjeff	mtc0	t0, MIPS_COP_0_CONFIG
135219820Sjeff	COP0_SYNC
136219820Sjeff
137219820Sjeff	/* Read and store the PrID FPU ID for CPU identification, if any. */
138219820Sjeff	mfc0	t2, COP_0_STATUS_REG
139219820Sjeff	mfc0	t0, MIPS_COP_0_PRID
140219820Sjeff#ifdef CPU_HAVEFPU
141325936Shselasky	and	t2, MIPS_SR_COP_1_BIT
142219820Sjeff	beqz	t2, 1f
143328653Shselasky	move	t1, zero
144328653Shselasky	cfc1	t1, MIPS_FPU_ID
145219820Sjeff1:
146328653Shselasky#else
147219820Sjeff	/*
148254025Sjeff	 * This platform has no FPU, and attempting to detect one
149219820Sjeff	 * using the official method causes an exception.
150219820Sjeff	 */
151219820Sjeff	move	t1, zero
152219820Sjeff#endif
153219820Sjeff	sw	t0, _C_LABEL(cpu_id)
154219820Sjeff	sw	t1, _C_LABEL(fpu_id)
155219820Sjeff
156277396Shselasky	/*xxximp
157277396Shselasky	 * now that we pass a0...a3 to the platform_init routine, do we need
158277396Shselasky	 * to stash this stuff here?
159277396Shselasky	 */
160277396Shselasky#ifdef YAMON
161277396Shselasky	/* Save YAMON boot environment pointer */
162277396Shselasky	sw	a2, _C_LABEL(fenvp)
163277396Shselasky#endif
164331756Semaste
165219820Sjeff#if defined(TARGET_OCTEON) && defined(SMP)
166219820Sjeff	.set push
167219820Sjeff	.set mips32r2
168219820Sjeff	rdhwr	t2, $0
169219820Sjeff	beqz	t2, 1f
170254025Sjeff	nop
171219820Sjeff	j	octeon_ap_wait
172219820Sjeff	nop
173219820Sjeff	.set pop
174219820Sjeff1:
175219820Sjeff#endif
176219820Sjeff
177219820Sjeff	/*
178219820Sjeff	 * Initialize stack and call machine startup.
179219820Sjeff	 */
180219820Sjeff	PTR_LA	sp, _C_LABEL(pcpu_space)
181219820Sjeff	addiu	sp, (NBPG * 2) - CALLFRAME_SIZ
182219820Sjeff
183219820Sjeff	sw	zero, CALLFRAME_SIZ - 4(sp)	# Zero out old ra for debugger
184219820Sjeff	sw	zero, CALLFRAME_SIZ - 8(sp)	# Zero out old fp for debugger
185219820Sjeff
186219820Sjeff	PTR_LA	gp, _C_LABEL(_gp)
187219820Sjeff
188345920Shselasky	/* Call the platform-specific startup code. */
189345920Shselasky	jal	_C_LABEL(platform_start)
190345920Shselasky	nop
191345920Shselasky
192345920Shselasky	PTR_LA	sp, _C_LABEL(thread0)
193345920Shselasky	PTR_L	a0, TD_PCB(sp)
194345920Shselasky	REG_LI	t0, ~7
195345920Shselasky	and	a0, a0, t0
196219820Sjeff	PTR_SUBU	sp, a0, CALLFRAME_SIZ
197219820Sjeff
198219820Sjeff	jal	_C_LABEL(mi_startup)		# mi_startup(frame)
199219820Sjeff	sw	zero, CALLFRAME_SIZ - 8(sp)	# Zero out old fp for debugger
200219820Sjeff
201219820Sjeff	PANIC("Startup failed!")
202331756Semaste
203219820SjeffVECTOR_END(_locore)
204219820Sjeff