mtk_soc.h revision 297666
1297666Ssgalabov/*- 2297666Ssgalabov * Copyright (c) 2016 Stanislav Galabov. 3297666Ssgalabov * All rights reserved. 4297666Ssgalabov * 5297666Ssgalabov * Redistribution and use in source and binary forms, with or without 6297666Ssgalabov * modification, are permitted provided that the following conditions 7297666Ssgalabov * are met: 8297666Ssgalabov * 1. Redistributions of source code must retain the above copyright 9297666Ssgalabov * notice unmodified, this list of conditions, and the following 10297666Ssgalabov * disclaimer. 11297666Ssgalabov * 2. Redistributions in binary form must reproduce the above copyright 12297666Ssgalabov * notice, this list of conditions and the following disclaimer in the 13297666Ssgalabov * documentation and/or other materials provided with the distribution. 14297666Ssgalabov * 15297666Ssgalabov * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16297666Ssgalabov * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17297666Ssgalabov * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18297666Ssgalabov * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19297666Ssgalabov * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20297666Ssgalabov * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21297666Ssgalabov * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22297666Ssgalabov * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23297666Ssgalabov * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24297666Ssgalabov * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25297666Ssgalabov * SUCH DAMAGE. 26297666Ssgalabov * 27297666Ssgalabov * $FreeBSD: head/sys/mips/mediatek/mtk_soc.h 297666 2016-04-07 11:02:49Z sgalabov $ 28297666Ssgalabov */ 29297666Ssgalabov 30297666Ssgalabov#ifndef _MTK_SOC_H_ 31297666Ssgalabov#define _MTK_SOC_H_ 32297666Ssgalabov 33297666Ssgalabovenum mtk_soc_id { 34297666Ssgalabov MTK_SOC_UNKNOWN, 35297666Ssgalabov MTK_SOC_RT3050, 36297666Ssgalabov MTK_SOC_RT3052, 37297666Ssgalabov MTK_SOC_RT3350, 38297666Ssgalabov MTK_SOC_RT3352, 39297666Ssgalabov MTK_SOC_RT3662, 40297666Ssgalabov MTK_SOC_RT3883, 41297666Ssgalabov MTK_SOC_RT5350, 42297666Ssgalabov MTK_SOC_MT7620A, 43297666Ssgalabov MTK_SOC_MT7620N, 44297666Ssgalabov MTK_SOC_MT7621, 45297666Ssgalabov MTK_SOC_MT7628, 46297666Ssgalabov MTK_SOC_MT7688, 47297666Ssgalabov MTK_SOC_MAX 48297666Ssgalabov}; 49297666Ssgalabov 50297666Ssgalabov#define RT305X_CPU_CLKSEL_OFF 18 51297666Ssgalabov#define RT305X_CPU_CLKSEL_MSK 0x1 52297666Ssgalabov#define RT3352_CPU_CLKSEL_OFF 8 53297666Ssgalabov#define RT3352_CPU_CLKSEL_MSK 0x1 54297666Ssgalabov#define RT3883_CPU_CLKSEL_OFF 8 55297666Ssgalabov#define RT3883_CPU_CLKSEL_MSK 0x3 56297666Ssgalabov#define RT5350_CPU_CLKSEL_OFF1 8 57297666Ssgalabov#define RT5350_CPU_CLKSEL_OFF2 10 58297666Ssgalabov#define RT5350_CPU_CLKSEL_MSK 0x1 59297666Ssgalabov#define MT7628_CPU_CLKSEL_OFF 6 60297666Ssgalabov#define MT7628_CPU_CLKSEL_MSK 0x1 61297666Ssgalabov 62297666Ssgalabov#define MT7620_CPU_CLK_AUX0 (1u<<24) 63297666Ssgalabov#define MT7620_CPLL_SW_CFG (1u<<31) 64297666Ssgalabov#define MT7620_PLL_MULT_RATIO_OFF 16 65297666Ssgalabov#define MT7620_PLL_MULT_RATIO_MSK 0x7 66297666Ssgalabov#define MT7620_PLL_MULT_RATIO_BASE 24 67297666Ssgalabov#define MT7620_PLL_DIV_RATIO_OFF 10 68297666Ssgalabov#define MT7620_PLL_DIV_RATIO_MSK 0x3 69297666Ssgalabov#define MT7620_PLL_DIV_RATIO_BASE 2 70297666Ssgalabov#define MT7620_PLL_DIV_RATIO_MAX 8 71297666Ssgalabov#define MT7620_XTAL_40 40 72297666Ssgalabov 73297666Ssgalabov#define MT7621_USES_MEMDIV (1u<<30) 74297666Ssgalabov#define MT7621_MEMDIV_OFF 4 75297666Ssgalabov#define MT7621_MEMDIV_MSK 0x7f 76297666Ssgalabov#define MT7621_MEMDIV_BASE 1 77297666Ssgalabov#define MT7621_CLKSEL_OFF 6 78297666Ssgalabov#define MT7621_CLKSEL_MSK 0x7 79297666Ssgalabov#define MT7621_CLKSEL_25MHZ_VAL 6 80297666Ssgalabov#define MT7621_CLKSEL_20MHZ_VAL 3 81297666Ssgalabov#define MT7621_CLKSEL_20MHZ 20 82297666Ssgalabov#define MT7621_CLKSEL_25MHZ 25 83297666Ssgalabov#define MT7621_CLK_STS_DIV_OFF 8 84297666Ssgalabov#define MT7621_CLK_STS_MSK 0x1f 85297666Ssgalabov#define MT7621_CLK_STS_BASE 500 86297666Ssgalabov 87297666Ssgalabov#define MTK_MT7621_CLKDIV_REG 0x5648 88297666Ssgalabov#define MTK_MT7621_CLKDIV_OFF 4 89297666Ssgalabov#define MTK_MT7621_CLKDIV_MSK 0x7f 90297666Ssgalabov 91297666Ssgalabov#define MTK_MHZ(x) ((x) * 1000 * 1000) 92297666Ssgalabov 93297666Ssgalabov#define MTK_CPU_CLK_UNKNOWN 0 94297666Ssgalabov#define MTK_CPU_CLK_250MHZ 250000000 95297666Ssgalabov#define MTK_CPU_CLK_300MHZ 300000000 96297666Ssgalabov#define MTK_CPU_CLK_320MHZ 320000000 97297666Ssgalabov#define MTK_CPU_CLK_360MHZ 360000000 98297666Ssgalabov#define MTK_CPU_CLK_384MHZ 384000000 99297666Ssgalabov#define MTK_CPU_CLK_400MHZ 400000000 100297666Ssgalabov#define MTK_CPU_CLK_480MHZ 480000000 101297666Ssgalabov#define MTK_CPU_CLK_500MHZ 500000000 102297666Ssgalabov#define MTK_CPU_CLK_575MHZ 575000000 103297666Ssgalabov#define MTK_CPU_CLK_580MHZ 580000000 104297666Ssgalabov#define MTK_CPU_CLK_600MHZ 600000000 105297666Ssgalabov#define MTK_CPU_CLK_880MHZ 880000000 106297666Ssgalabov 107297666Ssgalabov#define MTK_UART_CLK_40MHZ 40000000 108297666Ssgalabov#define MTK_UART_CLK_50MHZ 50000000 109297666Ssgalabov 110297666Ssgalabov#define MTK_UARTDIV_2 2 111297666Ssgalabov#define MTK_UARTDIV_3 3 112297666Ssgalabov 113297666Ssgalabov#define MTK_DEFAULT_BASE 0x10000000 114297666Ssgalabov#define MTK_MT7621_BASE 0x1e000000 115297666Ssgalabov#define MTK_DEFAULT_SIZE 0x6000 116297666Ssgalabov 117297666Ssgalabovextern void mtk_soc_try_early_detect(void); 118297666Ssgalabovextern uint32_t mtk_soc_get_uartclk(void); 119297666Ssgalabovextern uint32_t mtk_soc_get_cpuclk(void); 120297666Ssgalabovextern uint32_t mtk_soc_get_timerclk(void); 121297666Ssgalabovextern uint32_t mtk_soc_get_socid(void); 122297666Ssgalabov 123297666Ssgalabovextern int mtk_soc_reset_device(device_t); 124297666Ssgalabovextern int mtk_soc_stop_clock(device_t); 125297666Ssgalabovextern int mtk_soc_start_clock(device_t); 126297666Ssgalabovextern int mtk_soc_assert_reset(device_t); 127297666Ssgalabovextern int mtk_soc_deassert_reset(device_t); 128297666Ssgalabovextern void mtk_soc_reset(void); 129297666Ssgalabov 130297666Ssgalabov#endif /* _MTK_SOC_H_ */ 131