mtk_pcie.h revision 297717
1/*- 2 * Copyright (c) 2016 Stanislav Galabov. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD: head/sys/mips/mediatek/mtk_pcie.h 297717 2016-04-08 15:26:49Z sgalabov $ 27 */ 28#ifndef __MTK_PCIE_H__ 29#define __MTK_PCIE_H__ 30 31#define PCI_MIN_IO_ALLOC 4 32#define PCI_MIN_MEM_ALLOC 16 33#define BITS_PER_UINT32 (NBBY * sizeof(uint32_t)) 34 35#define MTK_PCI_NIRQS 3 36#define MTK_PCI_BASESLOT 0 37 38struct mtk_pci_softc { 39 device_t sc_dev; 40 41 struct resource * pci_res[MTK_PCI_NIRQS + 1]; 42 void * pci_intrhand[MTK_PCI_NIRQS]; 43 44 int sc_busno; 45 int sc_cur_secbus; 46 47 struct rman sc_mem_rman; 48 struct rman sc_io_rman; 49 struct rman sc_irq_rman; 50 51 uint32_t sc_num_irq; 52 uint32_t sc_irq_start; 53 uint32_t sc_irq_end; 54 55 bus_addr_t sc_mem_base; 56 bus_addr_t sc_mem_size; 57 uint32_t sc_mem_map[(256*1024*1024) / 58 (PCI_MIN_MEM_ALLOC * BITS_PER_UINT32)]; 59 60 bus_addr_t sc_io_base; 61 bus_addr_t sc_io_size; 62 uint32_t sc_io_map[(16*1024*1024) / 63 (PCI_MIN_IO_ALLOC * BITS_PER_UINT32)]; 64 65 struct intr_event *sc_eventstab[MTK_PCI_NIRQS]; 66 67 uint32_t pcie_link_status; 68 uint32_t num_slots; 69 uint32_t socid; 70 uint32_t addr_mask; 71}; 72 73#define MTK_PCI_PCICFG 0x0000 74#define MTK_PCI_RESET (1<<1) 75#define MTK_PCI_PCIINT 0x0008 76#define MTK_PCI_PCIENA 0x000C 77#define MTK_PCI_CFGADDR 0x0020 78#define MTK_PCI_CFGDATA 0x0024 79#define MTK_PCI_MEMBASE 0x0028 80#define MTK_PCI_IOBASE 0x002C 81#define MTK_PCI_ARBCTL 0x0080 82#define MTK_PCI_PHY0_CFG 0x0090 83 84#define MTK_PCI_PCIE0_BAR0SETUP 0x2010 85#define MTK_PCI_PCIE0_BAR1SETUP 0x2014 86#define MTK_PCI_PCIE0_IMBASEBAR0 0x2018 87#define MTK_PCI_PCIE0_ID 0x2030 88#define MTK_PCI_PCIE0_CLASS 0x2034 89#define MTK_PCI_PCIE0_SUBID 0x2038 90#define MTK_PCI_PCIE0_STATUS 0x2050 91#define MTK_PCI_PCIE0_DLECR 0x2060 92#define MTK_PCI_PCIE0_ECRC 0x2064 93 94#define MTK_PCIE_BAR0SETUP(_s) (MTK_PCI_PCIE0_BAR0SETUP + (_s)*0x1000) 95#define MTK_PCIE_BAR1SETUP(_s) (MTK_PCI_PCIE0_BAR1SETUP + (_s)*0x1000) 96#define MTK_PCIE_IMBASEBAR0(_s) (MTK_PCI_PCIE0_IMBASEBAR0 + (_s)*0x1000) 97#define MTK_PCIE_ID(_s) (MTK_PCI_PCIE0_ID + (_s)*0x1000) 98#define MTK_PCIE_CLASS(_s) (MTK_PCI_PCIE0_CLASS + (_s)*0x1000) 99#define MTK_PCIE_SUBID(_s) (MTK_PCI_PCIE0_SUBID + (_s)*0x1000) 100#define MTK_PCIE_STATUS(_s) (MTK_PCI_PCIE0_STATUS + (_s)*0x1000) 101 102#define MTK_PCIE0_IRQ 20 103#define MTK_PCIE1_IRQ 21 104#define MTK_PCIE2_IRQ 22 105 106#define MTK_PCI_INTR_PIN 2 107 108/* Chip specific defines */ 109#define MT7620_MAX_RETRIES 10 110#define MT7620_PCIE_PHY_CFG 0x90 111#define PHY_BUSY (1<<31) 112#define PHY_MODE_WRITE (1<<23) 113#define PHY_ADDR_OFFSET 8 114#define MT7620_PPLL_CFG0 0x98 115#define PPLL_SW_SET (1<<31) 116#define MT7620_PPLL_CFG1 0x9c 117#define PPLL_PD (1<<26) 118#define PPLL_LOCKED (1<<23) 119#define MT7620_PPLL_DRV 0xa0 120#define PDRV_SW_SET (1<<31) 121#define LC_CKDRVPD (1<<19) 122#define LC_CKDRVOHZ (1<<18) 123#define LC_CKDRVHZ (1<<17) 124#define MT7620_PERST_GPIO_MODE (3<<16) 125#define MT7620_PERST (0<<16) 126#define MT7620_GPIO (2<<16) 127#define MT7620_PKG_BGA (1<<16) 128 129#define MT7628_PERST_GPIO_MODE (1<<16) 130#define MT7628_PERST (0<<16) 131 132#define MT7621_PERST_GPIO_MODE (3<<10) 133#define MT7621_PERST_GPIO (1<<10) 134#define MT7621_UARTL3_GPIO_MODE (3<<3) 135#define MT7621_UARTL3_GPIO (1<<3) 136#define MT7621_PCIE0_RST (1<<19) 137#define MT7621_PCIE1_RST (1<<8) 138#define MT7621_PCIE2_RST (1<<7) 139#define MT7621_PCIE_RST (MT7621_PCIE0_RST | MT7621_PCIE1_RST | \ 140 MT7621_PCIE2_RST) 141 142#define RT3883_PCI_RST (1<<24) 143#define RT3883_PCI_CLK (1<<19) 144#define RT3883_PCI_HOST_MODE (1<<7) 145#define RT3883_PCIE_RC_MODE (1<<8) 146/* End of chip specific defines */ 147 148#define MT_WRITE32(sc, off, val) \ 149 bus_write_4((sc)->pci_res[0], (off), (val)) 150#define MT_WRITE16(sc, off, val) \ 151 bus_write_2((sc)->pci_res[0], (off), (val)) 152#define MT_WRITE8(sc, off, val) \ 153 bus_write_1((sc)->pci_res[0], (off), (val)) 154#define MT_READ32(sc, off) \ 155 bus_read_4((sc)->pci_res[0], (off)) 156#define MT_READ16(sc, off) \ 157 bus_read_2((sc)->pci_res[0], (off)) 158#define MT_READ8(sc, off) \ 159 bus_read_1((sc)->pci_res[0], (off)) 160 161#define MT_CLR_SET32(sc, off, clr, set) \ 162 MT_WRITE32((sc), (off), ((MT_READ32((sc), (off)) & ~(clr)) | (off))) 163 164#endif /* __MTK_PCIE_H__ */ 165