mtk_pcie.c revision 297850
1/*- 2 * Copyright (c) 2016 Stanislav Galabov. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 */ 25#include <sys/cdefs.h> 26__FBSDID("$FreeBSD: head/sys/mips/mediatek/mtk_pcie.c 297850 2016-04-12 07:21:22Z sgalabov $"); 27 28#include <sys/param.h> 29#include <sys/systm.h> 30 31#include <sys/bus.h> 32#include <sys/interrupt.h> 33#include <sys/malloc.h> 34#include <sys/kernel.h> 35#include <sys/module.h> 36#include <sys/rman.h> 37#include <sys/lock.h> 38#include <sys/mutex.h> 39#include <sys/endian.h> 40 41#include <vm/vm.h> 42#include <vm/pmap.h> 43#include <vm/vm_extern.h> 44 45#include <machine/bus.h> 46#include <machine/cpu.h> 47#include <machine/intr.h> 48#include <machine/pmap.h> 49 50#include <dev/pci/pcivar.h> 51#include <dev/pci/pcireg.h> 52 53#include <dev/pci/pcib_private.h> 54 55#include <dev/fdt/fdt_common.h> 56#include <dev/fdt/fdt_clock.h> 57#include <dev/ofw/openfirm.h> 58#include <dev/ofw/ofw_bus.h> 59#include <dev/ofw/ofw_bus_subr.h> 60 61#include <mips/mediatek/mtk_pcie.h> 62#include <mips/mediatek/mtk_soc.h> 63#include <mips/mediatek/mtk_sysctl.h> 64#include <mips/mediatek/fdt_reset.h> 65 66#include "ofw_bus_if.h" 67#include "pcib_if.h" 68#include "pic_if.h" 69 70/* 71 * Note: We only support PCIe at the moment. 72 * Most SoCs in the Ralink/Mediatek family that we target actually don't 73 * support PCI anyway, with the notable exceptions being RT3662/RT3883, which 74 * support both PCI and PCIe. If there exists a board based on one of them 75 * which is of interest in the future it shouldn't be too hard to enable PCI 76 * support for it. 77 */ 78 79/* Chip specific function declarations */ 80static int mtk_pcie_phy_init(device_t); 81static int mtk_pcie_phy_start(device_t); 82static int mtk_pcie_phy_stop(device_t); 83static int mtk_pcie_phy_mt7621_init(device_t); 84static int mtk_pcie_phy_mt7628_init(device_t); 85static int mtk_pcie_phy_mt7620_init(device_t); 86static int mtk_pcie_phy_rt3883_init(device_t); 87static void mtk_pcie_phy_setup_slots(device_t); 88 89/* Generic declarations */ 90struct mtx mtk_pci_mtx; 91MTX_SYSINIT(mtk_pci_mtx, &mtk_pci_mtx, "MTK PCIe mutex", MTX_SPIN); 92 93static int mtk_pci_intr(void *); 94 95static struct mtk_pci_softc *mt_sc = NULL; 96 97struct mtk_pci_range { 98 u_long base; 99 u_long len; 100}; 101 102#define FDT_RANGES_CELLS (3 * 2) 103 104static void 105mtk_pci_range_dump(struct mtk_pci_range *range) 106{ 107#ifdef DEBUG 108 printf("\n"); 109 printf(" base = 0x%08lx\n", range->base); 110 printf(" len = 0x%08lx\n", range->len); 111#endif 112} 113 114static int 115mtk_pci_ranges_decode(phandle_t node, struct mtk_pci_range *io_space, 116 struct mtk_pci_range *mem_space) 117{ 118 struct mtk_pci_range *pci_space; 119 pcell_t ranges[FDT_RANGES_CELLS]; 120 pcell_t *rangesptr; 121 pcell_t cell0, cell1, cell2; 122 int tuples, i, rv, len; 123 124 /* 125 * Retrieve 'ranges' property. 126 */ 127 if (!OF_hasprop(node, "ranges")) { 128 printf("%s: %d\n", __FUNCTION__, 1); 129 return (EINVAL); 130 } 131 132 len = OF_getproplen(node, "ranges"); 133 if (len > sizeof(ranges)) { 134 printf("%s: %d\n", __FUNCTION__, 2); 135 return (ENOMEM); 136 } 137 138 if (OF_getprop(node, "ranges", ranges, sizeof(ranges)) <= 0) { 139 printf("%s: %d\n", __FUNCTION__, 3); 140 return (EINVAL); 141 } 142 143 tuples = len / (sizeof(pcell_t) * 3); 144 145 /* 146 * Initialize the ranges so that we don't have to worry about 147 * having them all defined in the FDT. In particular, it is 148 * perfectly fine not to want I/O space on PCI busses. 149 */ 150 bzero(io_space, sizeof(*io_space)); 151 bzero(mem_space, sizeof(*mem_space)); 152 153 rangesptr = &ranges[0]; 154 for (i = 0; i < tuples; i++) { 155 cell0 = fdt_data_get((void *)rangesptr, 1); 156 rangesptr++; 157 cell1 = fdt_data_get((void *)rangesptr, 1); 158 rangesptr++; 159 cell2 = fdt_data_get((void *)rangesptr, 1); 160 rangesptr++; 161 162 if (cell0 == 2) { 163 pci_space = mem_space; 164 } else if (cell0 == 1) { 165 pci_space = io_space; 166 } else { 167 rv = ERANGE; 168 printf("%s: %d\n", __FUNCTION__, 4); 169 goto out; 170 } 171 172 pci_space->base = cell1; 173 pci_space->len = cell2; 174 } 175 176 rv = 0; 177out: 178 return (rv); 179} 180 181static int 182mtk_pci_ranges(phandle_t node, struct mtk_pci_range *io_space, 183 struct mtk_pci_range *mem_space) 184{ 185 int err; 186 187 if ((err = mtk_pci_ranges_decode(node, io_space, mem_space)) != 0) { 188 return (err); 189 } 190 191 mtk_pci_range_dump(io_space); 192 mtk_pci_range_dump(mem_space); 193 194 return (0); 195} 196 197static struct ofw_compat_data compat_data[] = { 198 { "ralink,rt3662-pcie", MTK_SOC_RT3883 }, 199 { "ralink,rt3883-pcie", MTK_SOC_RT3883 }, 200 { "ralink,mt7620a-pcie", MTK_SOC_MT7620A }, 201 { "ralink,mt7621-pcie", MTK_SOC_MT7621 }, 202 { "ralink,mt7628-pcie", MTK_SOC_MT7628 }, 203 { "ralink,mt7688-pcie", MTK_SOC_MT7628 }, 204 { NULL, MTK_SOC_UNKNOWN } 205}; 206 207static int 208mtk_pci_probe(device_t dev) 209{ 210 struct mtk_pci_softc *sc = device_get_softc(dev); 211 212 if (!ofw_bus_status_okay(dev)) 213 return (ENXIO); 214 215 sc->socid = ofw_bus_search_compatible(dev, compat_data)->ocd_data; 216 if (sc->socid == MTK_SOC_UNKNOWN) 217 return (ENXIO); 218 219 device_set_desc(dev, "MTK PCIe Controller"); 220 221 return (0); 222} 223 224static int 225mtk_pci_attach(device_t dev) 226{ 227 struct mtk_pci_softc *sc = device_get_softc(dev); 228 struct mtk_pci_range io_space, mem_space; 229 phandle_t node; 230 intptr_t xref; 231 int i, rid; 232 233 sc->sc_dev = dev; 234 mt_sc = sc; 235 sc->addr_mask = 0xffffffff; 236 237 /* Request our memory */ 238 rid = 0; 239 sc->pci_res[0] = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 240 RF_ACTIVE); 241 if (sc->pci_res[0] == NULL) { 242 device_printf(dev, "could not allocate memory resource\n"); 243 return (ENXIO); 244 } 245 246 /* See how many interrupts we need */ 247 if (sc->socid == MTK_SOC_MT7621) 248 sc->sc_num_irq = 3; 249 else { 250 sc->sc_num_irq = 1; 251 sc->pci_res[2] = sc->pci_res[3] = NULL; 252 sc->pci_intrhand[1] = sc->pci_intrhand[2] = NULL; 253 } 254 255 /* Request our interrupts */ 256 for (i = 1; i <= sc->sc_num_irq ; i++) { 257 rid = i - 1; 258 sc->pci_res[i] = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 259 RF_ACTIVE); 260 if (sc->pci_res[i] == NULL) { 261 device_printf(dev, "could not allocate interrupt " 262 "resource %d\n", rid); 263 goto cleanup_res; 264 } 265 } 266 267 /* Parse our PCI 'ranges' property */ 268 node = ofw_bus_get_node(dev); 269 xref = OF_xref_from_node(node); 270 if (mtk_pci_ranges(node, &io_space, &mem_space)) { 271 device_printf(dev, "could not retrieve 'ranges' data\n"); 272 goto cleanup_res; 273 } 274 275 /* Memory, I/O and IRQ resource limits */ 276 sc->sc_io_base = io_space.base; 277 sc->sc_io_size = io_space.len; 278 sc->sc_mem_base = mem_space.base; 279 sc->sc_mem_size = mem_space.len; 280 sc->sc_irq_start = MTK_PCIE0_IRQ; 281 sc->sc_irq_end = MTK_PCIE2_IRQ; 282 283 /* Init resource managers for memory, I/O and IRQ */ 284 sc->sc_mem_rman.rm_type = RMAN_ARRAY; 285 sc->sc_mem_rman.rm_descr = "mtk pcie memory window"; 286 if (rman_init(&sc->sc_mem_rman) != 0 || 287 rman_manage_region(&sc->sc_mem_rman, sc->sc_mem_base, 288 sc->sc_mem_base + sc->sc_mem_size - 1) != 0) { 289 device_printf(dev, "failed to setup memory rman\n"); 290 goto cleanup_res; 291 } 292 293 sc->sc_io_rman.rm_type = RMAN_ARRAY; 294 sc->sc_io_rman.rm_descr = "mtk pcie io window"; 295 if (rman_init(&sc->sc_io_rman) != 0 || 296 rman_manage_region(&sc->sc_io_rman, sc->sc_io_base, 297 sc->sc_io_base + sc->sc_io_size - 1) != 0) { 298 device_printf(dev, "failed to setup io rman\n"); 299 goto cleanup_res; 300 } 301 302 sc->sc_irq_rman.rm_type = RMAN_ARRAY; 303 sc->sc_irq_rman.rm_descr = "mtk pcie irqs"; 304 if (rman_init(&sc->sc_irq_rman) != 0 || 305 rman_manage_region(&sc->sc_irq_rman, sc->sc_irq_start, 306 sc->sc_irq_end) != 0) { 307 device_printf(dev, "failed to setup irq rman\n"); 308 goto cleanup_res; 309 } 310 311 /* Do SoC-specific PCIe initialization */ 312 if (mtk_pcie_phy_init(dev)) { 313 device_printf(dev, "pcie phy init failed\n"); 314 goto cleanup_rman; 315 } 316 317 /* Register ourselves as an interrupt controller */ 318 if (intr_pic_register(dev, xref) != 0) { 319 device_printf(dev, "could not register PIC\n"); 320 goto cleanup_rman; 321 } 322 323 /* Set up our interrupt handler */ 324 for (i = 1; i <= sc->sc_num_irq; i++) { 325 sc->pci_intrhand[i - 1] = NULL; 326 if (bus_setup_intr(dev, sc->pci_res[i], INTR_TYPE_MISC, 327 mtk_pci_intr, NULL, sc, &sc->pci_intrhand[i - 1])) { 328 device_printf(dev, "could not setup intr handler %d\n", 329 i); 330 goto cleanup; 331 } 332 } 333 334 /* Attach our PCI child so bus enumeration can start */ 335 if (device_add_child(dev, "pci", -1) == NULL) { 336 device_printf(dev, "could not attach pci bus\n"); 337 goto cleanup; 338 } 339 340 /* And finally, attach ourselves to the bus */ 341 if (bus_generic_attach(dev)) { 342 device_printf(dev, "could not attach to bus\n"); 343 goto cleanup; 344 } 345 346 return (0); 347 348cleanup: 349#ifdef notyet 350 intr_pic_unregister(dev, xref); 351#endif 352 for (i = 1; i <= sc->sc_num_irq; i++) { 353 if (sc->pci_intrhand[i - 1] != NULL) 354 bus_teardown_intr(dev, sc->pci_res[i], 355 sc->pci_intrhand[i - 1]); 356 } 357cleanup_rman: 358 mtk_pcie_phy_stop(dev); 359 rman_fini(&sc->sc_irq_rman); 360 rman_fini(&sc->sc_io_rman); 361 rman_fini(&sc->sc_mem_rman); 362cleanup_res: 363 mt_sc = NULL; 364 if (sc->pci_res[0] != NULL) 365 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->pci_res[0]); 366 if (sc->pci_res[1] != NULL) 367 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->pci_res[1]); 368 if (sc->pci_res[2] != NULL) 369 bus_release_resource(dev, SYS_RES_IRQ, 1, sc->pci_res[2]); 370 if (sc->pci_res[3] != NULL) 371 bus_release_resource(dev, SYS_RES_IRQ, 2, sc->pci_res[3]); 372 return (ENXIO); 373} 374 375static int 376mtk_pci_read_ivar(device_t dev, device_t child, int which, 377 uintptr_t *result) 378{ 379 struct mtk_pci_softc *sc = device_get_softc(dev); 380 381 switch (which) { 382 case PCIB_IVAR_DOMAIN: 383 *result = device_get_unit(dev); 384 return (0); 385 case PCIB_IVAR_BUS: 386 *result = sc->sc_busno; 387 return (0); 388 } 389 390 return (ENOENT); 391} 392 393static int 394mtk_pci_write_ivar(device_t dev, device_t child, int which, 395 uintptr_t result) 396{ 397 struct mtk_pci_softc *sc = device_get_softc(dev); 398 399 switch (which) { 400 case PCIB_IVAR_BUS: 401 sc->sc_busno = result; 402 return (0); 403 } 404 405 return (ENOENT); 406} 407 408static struct resource * 409mtk_pci_alloc_resource(device_t bus, device_t child, int type, int *rid, 410 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) 411{ 412 struct mtk_pci_softc *sc = device_get_softc(bus); 413 struct resource *rv; 414 struct rman *rm; 415 416 switch (type) { 417 case PCI_RES_BUS: 418 return pci_domain_alloc_bus(0, child, rid, start, end, count, 419 flags); 420 case SYS_RES_IRQ: 421 rm = &sc->sc_irq_rman; 422 break; 423 case SYS_RES_IOPORT: 424 rm = &sc->sc_io_rman; 425 break; 426 case SYS_RES_MEMORY: 427 rm = &sc->sc_mem_rman; 428 break; 429 default: 430 return (NULL); 431 } 432 433 rv = rman_reserve_resource(rm, start, end, count, flags, child); 434 435 if (rv == NULL) 436 return (NULL); 437 438 rman_set_rid(rv, *rid); 439 440 if ((flags & RF_ACTIVE) && type != SYS_RES_IRQ) { 441 if (bus_activate_resource(child, type, *rid, rv)) { 442 rman_release_resource(rv); 443 return (NULL); 444 } 445 } 446 447 return (rv); 448} 449 450static int 451mtk_pci_release_resource(device_t bus, device_t child, int type, int rid, 452 struct resource *res) 453{ 454 455 if (type == PCI_RES_BUS) 456 return (pci_domain_release_bus(0, child, rid, res)); 457 458 return (bus_generic_release_resource(bus, child, type, rid, res)); 459} 460 461static int 462mtk_pci_adjust_resource(device_t bus, device_t child, int type, 463 struct resource *res, rman_res_t start, rman_res_t end) 464{ 465 struct mtk_pci_softc *sc = device_get_softc(bus); 466 struct rman *rm; 467 468 switch (type) { 469 case PCI_RES_BUS: 470 return pci_domain_adjust_bus(0, child, res, start, end); 471 case SYS_RES_IRQ: 472 rm = &sc->sc_irq_rman; 473 break; 474 case SYS_RES_IOPORT: 475 rm = &sc->sc_io_rman; 476 break; 477 case SYS_RES_MEMORY: 478 rm = &sc->sc_mem_rman; 479 break; 480 default: 481 rm = NULL; 482 break; 483 } 484 485 if (rm != NULL) 486 return (rman_adjust_resource(res, start, end)); 487 488 return (bus_generic_adjust_resource(bus, child, type, res, start, end)); 489} 490 491static inline int 492mtk_idx_to_irq(int idx) 493{ 494 495 return ((idx == 0) ? MTK_PCIE0_IRQ : 496 (idx == 1) ? MTK_PCIE1_IRQ : 497 (idx == 2) ? MTK_PCIE2_IRQ : -1); 498} 499 500static inline int 501mtk_irq_to_idx(int irq) 502{ 503 504 return ((irq == MTK_PCIE0_IRQ) ? 0 : 505 (irq == MTK_PCIE1_IRQ) ? 1 : 506 (irq == MTK_PCIE2_IRQ) ? 2 : -1); 507} 508 509static void 510mtk_pci_mask_irq(void *source) 511{ 512 MT_WRITE32(mt_sc, MTK_PCI_PCIENA, 513 MT_READ32(mt_sc, MTK_PCI_PCIENA) & ~(1<<((int)source))); 514} 515 516static void 517mtk_pci_unmask_irq(void *source) 518{ 519 520 MT_WRITE32(mt_sc, MTK_PCI_PCIENA, 521 MT_READ32(mt_sc, MTK_PCI_PCIENA) | (1<<((int)source))); 522} 523 524static int 525mtk_pci_setup_intr(device_t bus, device_t child, struct resource *ires, 526 int flags, driver_filter_t *filt, driver_intr_t *handler, 527 void *arg, void **cookiep) 528{ 529 struct mtk_pci_softc *sc = device_get_softc(bus); 530 struct intr_event *event; 531 int irq, error, irqidx; 532 533 irq = rman_get_start(ires); 534 535 if (irq < sc->sc_irq_start || irq > sc->sc_irq_end) 536 return (EINVAL); 537 538 irqidx = irq - sc->sc_irq_start; 539 540 event = sc->sc_eventstab[irqidx]; 541 if (event == NULL) { 542 error = intr_event_create(&event, (void *)irq, 0, irq, 543 mtk_pci_mask_irq, mtk_pci_unmask_irq, NULL, NULL, 544 "pci intr%d:", irq); 545 546 if (error == 0) { 547 sc->sc_eventstab[irqidx] = event; 548 } 549 else { 550 return (error); 551 } 552 } 553 554 intr_event_add_handler(event, device_get_nameunit(child), filt, 555 handler, arg, intr_priority(flags), flags, cookiep); 556 557 mtk_pci_unmask_irq((void*)irq); 558 559 return (0); 560} 561 562static int 563mtk_pci_teardown_intr(device_t dev, device_t child, struct resource *ires, 564 void *cookie) 565{ 566 struct mtk_pci_softc *sc = device_get_softc(dev); 567 int irq, result, irqidx; 568 569 irq = rman_get_start(ires); 570 if (irq < sc->sc_irq_start || irq > sc->sc_irq_end) 571 return (EINVAL); 572 573 irqidx = irq - sc->sc_irq_start; 574 if (sc->sc_eventstab[irqidx] == NULL) 575 panic("Trying to teardown unoccupied IRQ"); 576 577 mtk_pci_mask_irq((void*)irq); 578 579 result = intr_event_remove_handler(cookie); 580 if (!result) 581 sc->sc_eventstab[irqidx] = NULL; 582 583 584 return (result); 585} 586 587static inline uint32_t 588mtk_pci_make_addr(int bus, int slot, int func, int reg) 589{ 590 uint32_t addr; 591 592 addr = ((((reg & 0xf00) >> 8) << 24) | (bus << 16) | (slot << 11) | 593 (func << 8) | (reg & 0xfc) | (1 << 31)); 594 595 return (addr); 596} 597 598static int 599mtk_pci_maxslots(device_t dev) 600{ 601 602 return (PCI_SLOTMAX); 603} 604 605static inline int 606mtk_pci_slot_has_link(device_t dev, int slot) 607{ 608 struct mtk_pci_softc *sc = device_get_softc(dev); 609 610 return !!(sc->pcie_link_status & (1<<slot)); 611} 612 613static uint32_t 614mtk_pci_read_config(device_t dev, u_int bus, u_int slot, u_int func, 615 u_int reg, int bytes) 616{ 617 struct mtk_pci_softc *sc = device_get_softc(dev); 618 uint32_t addr = 0, data = 0; 619 620 /* Return ~0U if slot has no link */ 621 if (bus == 0 && mtk_pci_slot_has_link(dev, slot) == 0) { 622 return (~0U); 623 } 624 625 mtx_lock_spin(&mtk_pci_mtx); 626 addr = mtk_pci_make_addr(bus, slot, func, (reg & ~3)) & sc->addr_mask; 627 MT_WRITE32(sc, MTK_PCI_CFGADDR, addr); 628 switch (bytes % 4) { 629 case 0: 630 data = MT_READ32(sc, MTK_PCI_CFGDATA); 631 break; 632 case 1: 633 data = MT_READ8(sc, MTK_PCI_CFGDATA + (reg & 0x3)); 634 break; 635 case 2: 636 data = MT_READ16(sc, MTK_PCI_CFGDATA + (reg & 0x3)); 637 break; 638 default: 639 panic("%s(): Wrong number of bytes (%d) requested!\n", 640 __FUNCTION__, bytes % 4); 641 } 642 mtx_unlock_spin(&mtk_pci_mtx); 643 644 return (data); 645} 646 647static void 648mtk_pci_write_config(device_t dev, u_int bus, u_int slot, u_int func, 649 u_int reg, uint32_t val, int bytes) 650{ 651 struct mtk_pci_softc *sc = device_get_softc(dev); 652 uint32_t addr = 0, data = val; 653 654 /* Do not write if slot has no link */ 655 if (bus == 0 && mtk_pci_slot_has_link(dev, slot) == 0) 656 return; 657 658 mtx_lock_spin(&mtk_pci_mtx); 659 addr = mtk_pci_make_addr(bus, slot, func, (reg & ~3)) & sc->addr_mask; 660 MT_WRITE32(sc, MTK_PCI_CFGADDR, addr); 661 switch (bytes % 4) { 662 case 0: 663 MT_WRITE32(sc, MTK_PCI_CFGDATA, data); 664 break; 665 case 1: 666 MT_WRITE8(sc, MTK_PCI_CFGDATA + (reg & 0x3), data); 667 break; 668 case 2: 669 MT_WRITE16(sc, MTK_PCI_CFGDATA + (reg & 0x3), data); 670 break; 671 default: 672 panic("%s(): Wrong number of bytes (%d) requested!\n", 673 __FUNCTION__, bytes % 4); 674 } 675 mtx_unlock_spin(&mtk_pci_mtx); 676} 677 678static int 679mtk_pci_route_interrupt(device_t pcib, device_t device, int pin) 680{ 681 int bus, sl, dev; 682 683 bus = pci_get_bus(device); 684 sl = pci_get_slot(device); 685 dev = pci_get_device(device); 686 687 if (bus != 0) 688 panic("Unexpected bus number %d\n", bus); 689 690 /* PCIe only */ 691 switch (sl) { 692 case 0: return MTK_PCIE0_IRQ; 693 case 1: return MTK_PCIE0_IRQ + 1; 694 case 2: return MTK_PCIE0_IRQ + 2; 695 default: return (-1); 696 } 697 698 return (-1); 699} 700 701static device_method_t mtk_pci_methods[] = { 702 /* Device interface */ 703 DEVMETHOD(device_probe, mtk_pci_probe), 704 DEVMETHOD(device_attach, mtk_pci_attach), 705 DEVMETHOD(device_shutdown, bus_generic_shutdown), 706 DEVMETHOD(device_suspend, bus_generic_suspend), 707 DEVMETHOD(device_resume, bus_generic_resume), 708 709 /* Bus interface */ 710 DEVMETHOD(bus_read_ivar, mtk_pci_read_ivar), 711 DEVMETHOD(bus_write_ivar, mtk_pci_write_ivar), 712 DEVMETHOD(bus_alloc_resource, mtk_pci_alloc_resource), 713 DEVMETHOD(bus_release_resource, mtk_pci_release_resource), 714 DEVMETHOD(bus_adjust_resource, mtk_pci_adjust_resource), 715 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 716 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 717 DEVMETHOD(bus_setup_intr, mtk_pci_setup_intr), 718 DEVMETHOD(bus_teardown_intr, mtk_pci_teardown_intr), 719 720 /* pcib interface */ 721 DEVMETHOD(pcib_maxslots, mtk_pci_maxslots), 722 DEVMETHOD(pcib_read_config, mtk_pci_read_config), 723 DEVMETHOD(pcib_write_config, mtk_pci_write_config), 724 DEVMETHOD(pcib_route_interrupt, mtk_pci_route_interrupt), 725 726 /* OFW bus interface */ 727 DEVMETHOD(ofw_bus_get_compat, ofw_bus_gen_get_compat), 728 DEVMETHOD(ofw_bus_get_model, ofw_bus_gen_get_model), 729 DEVMETHOD(ofw_bus_get_name, ofw_bus_gen_get_name), 730 DEVMETHOD(ofw_bus_get_node, ofw_bus_gen_get_node), 731 DEVMETHOD(ofw_bus_get_type, ofw_bus_gen_get_type), 732 733 DEVMETHOD_END 734}; 735 736static driver_t mtk_pci_driver = { 737 "pcib", 738 mtk_pci_methods, 739 sizeof(struct mtk_pci_softc), 740}; 741 742static devclass_t mtk_pci_devclass; 743 744DRIVER_MODULE(mtk_pci, simplebus, mtk_pci_driver, mtk_pci_devclass, 0, 0); 745 746/* Our interrupt handler */ 747static int 748mtk_pci_intr(void *arg) 749{ 750 struct mtk_pci_softc *sc = arg; 751 struct intr_event *event; 752 uint32_t reg, irq, irqidx; 753 754 reg = MT_READ32(sc, MTK_PCI_PCIINT); 755 756 for (irq = sc->sc_irq_start; irq <= sc->sc_irq_end; irq++) { 757 if (reg & (1u<<irq)) { 758 irqidx = irq - sc->sc_irq_start; 759 event = sc->sc_eventstab[irqidx]; 760 if (!event || TAILQ_EMPTY(&event->ie_handlers)) { 761 if (irq != 0) 762 printf("Stray PCI IRQ %d\n", irq); 763 continue; 764 } 765 766 intr_event_handle(event, NULL); 767 } 768 } 769 770 return (FILTER_HANDLED); 771} 772 773/* PCIe SoC-specific initialization */ 774static int 775mtk_pcie_phy_init(device_t dev) 776{ 777 struct mtk_pci_softc *sc; 778 779 /* Get our softc */ 780 sc = device_get_softc(dev); 781 782 /* We don't know how many slots we have yet */ 783 sc->num_slots = 0; 784 785 /* Handle SoC specific PCIe init */ 786 switch (sc->socid) { 787 case MTK_SOC_MT7628: /* Fallthrough */ 788 case MTK_SOC_MT7688: 789 if (mtk_pcie_phy_mt7628_init(dev)) 790 return (ENXIO); 791 break; 792 case MTK_SOC_MT7621: 793 if (mtk_pcie_phy_mt7621_init(dev)) 794 return (ENXIO); 795 break; 796 case MTK_SOC_MT7620A: 797 if (mtk_pcie_phy_mt7620_init(dev)) 798 return (ENXIO); 799 break; 800 case MTK_SOC_RT3662: /* Fallthrough */ 801 case MTK_SOC_RT3883: 802 if (mtk_pcie_phy_rt3883_init(dev)) 803 return (ENXIO); 804 break; 805 default: 806 device_printf(dev, "unsupported device %x\n", sc->socid); 807 return (ENXIO); 808 } 809 810 /* 811 * If we were successful so far go and set up the PCIe slots, so we 812 * may allocate mem/io/irq resources and enumerate busses later. 813 */ 814 mtk_pcie_phy_setup_slots(dev); 815 816 return (0); 817} 818 819static int 820mtk_pcie_phy_start(device_t dev) 821{ 822 struct mtk_pci_softc *sc = device_get_softc(dev); 823 824 if (sc->socid == MTK_SOC_MT7621 && 825 (mtk_sysctl_get(SYSCTL_REVID) & SYSCTL_REVID_MASK) != 826 SYSCTL_MT7621_REV_E) { 827 if (fdt_reset_assert_all(dev)) 828 return (ENXIO); 829 } else { 830 if (fdt_reset_deassert_all(dev)) 831 return (ENXIO); 832 } 833 834 if (fdt_clock_enable_all(dev)) 835 return (ENXIO); 836 837 return (0); 838} 839 840static int 841mtk_pcie_phy_stop(device_t dev) 842{ 843 struct mtk_pci_softc *sc = device_get_softc(dev); 844 845 if (sc->socid == MTK_SOC_MT7621 && 846 (mtk_sysctl_get(SYSCTL_REVID) & SYSCTL_REVID_MASK) != 847 SYSCTL_MT7621_REV_E) { 848 if (fdt_reset_deassert_all(dev)) 849 return (ENXIO); 850 } else { 851 if (fdt_reset_assert_all(dev)) 852 return (ENXIO); 853 } 854 855 if (fdt_clock_disable_all(dev)) 856 return (ENXIO); 857 858 return (0); 859} 860 861#define mtk_pcie_phy_set(_sc, _reg, _s, _n, _v) \ 862 MT_WRITE32((_sc), (_reg), ((MT_READ32((_sc), (_reg)) & \ 863 (~(((1ull << (_n)) - 1) << (_s)))) | ((_v) << (_s)))) 864 865static void 866mtk_pcie_phy_mt7621_bypass_pipe_rst(struct mtk_pci_softc *sc, uint32_t off) 867{ 868 869 mtk_pcie_phy_set(sc, off + 0x002c, 12, 1, 1); 870 mtk_pcie_phy_set(sc, off + 0x002c, 4, 1, 1); 871 mtk_pcie_phy_set(sc, off + 0x012c, 12, 1, 1); 872 mtk_pcie_phy_set(sc, off + 0x012c, 4, 1, 1); 873 mtk_pcie_phy_set(sc, off + 0x102c, 12, 1, 1); 874 mtk_pcie_phy_set(sc, off + 0x102c, 4, 1, 1); 875} 876 877static void 878mtk_pcie_phy_mt7621_setup_ssc(struct mtk_pci_softc *sc, uint32_t off) 879{ 880 uint32_t xtal_sel; 881 882 xtal_sel = mtk_sysctl_get(SYSCTL_SYSCFG) >> 6; 883 xtal_sel &= 0x7; 884 885 mtk_pcie_phy_set(sc, off + 0x400, 8, 1, 1); 886 mtk_pcie_phy_set(sc, off + 0x400, 9, 2, 0); 887 mtk_pcie_phy_set(sc, off + 0x000, 4, 1, 1); 888 mtk_pcie_phy_set(sc, off + 0x100, 4, 1, 1); 889 mtk_pcie_phy_set(sc, off + 0x000, 5, 1, 0); 890 mtk_pcie_phy_set(sc, off + 0x100, 5, 1, 0); 891 892 if (xtal_sel <= 5 && xtal_sel >= 3) { 893 mtk_pcie_phy_set(sc, off + 0x490, 6, 2, 1); 894 mtk_pcie_phy_set(sc, off + 0x4a8, 0, 12, 0x1a); 895 mtk_pcie_phy_set(sc, off + 0x4a8, 16, 12, 0x1a); 896 } else { 897 mtk_pcie_phy_set(sc, off + 0x490, 6, 2, 0); 898 if (xtal_sel >= 6) { 899 mtk_pcie_phy_set(sc, off + 0x4bc, 4, 2, 0x01); 900 mtk_pcie_phy_set(sc, off + 0x49c, 0, 31, 0x18000000); 901 mtk_pcie_phy_set(sc, off + 0x4a4, 0, 16, 0x18d); 902 mtk_pcie_phy_set(sc, off + 0x4a8, 0, 12, 0x4a); 903 mtk_pcie_phy_set(sc, off + 0x4a8, 16, 12, 0x4a); 904 mtk_pcie_phy_set(sc, off + 0x4a8, 0, 12, 0x11); 905 mtk_pcie_phy_set(sc, off + 0x4a8, 16, 12, 0x11); 906 } else { 907 mtk_pcie_phy_set(sc, off + 0x4a8, 0, 12, 0x1a); 908 mtk_pcie_phy_set(sc, off + 0x4a8, 16, 12, 0x1a); 909 } 910 } 911 912 mtk_pcie_phy_set(sc, off + 0x4a0, 5, 1, 1); 913 mtk_pcie_phy_set(sc, off + 0x490, 22, 2, 2); 914 mtk_pcie_phy_set(sc, off + 0x490, 18, 4, 6); 915 mtk_pcie_phy_set(sc, off + 0x490, 12, 4, 2); 916 mtk_pcie_phy_set(sc, off + 0x490, 8, 4, 1); 917 mtk_pcie_phy_set(sc, off + 0x4ac, 16, 3, 0); 918 mtk_pcie_phy_set(sc, off + 0x490, 1, 3, 2); 919 920 if (xtal_sel <= 5 && xtal_sel >= 3) { 921 mtk_pcie_phy_set(sc, off + 0x414, 6, 2, 1); 922 mtk_pcie_phy_set(sc, off + 0x414, 5, 1, 1); 923 } 924 925 mtk_pcie_phy_set(sc, off + 0x414, 28, 2, 1); 926 mtk_pcie_phy_set(sc, off + 0x040, 17, 4, 7); 927 mtk_pcie_phy_set(sc, off + 0x040, 16, 1, 1); 928 mtk_pcie_phy_set(sc, off + 0x140, 17, 4, 7); 929 mtk_pcie_phy_set(sc, off + 0x140, 16, 1, 1); 930 931 mtk_pcie_phy_set(sc, off + 0x000, 5, 1, 1); 932 mtk_pcie_phy_set(sc, off + 0x100, 5, 1, 1); 933 mtk_pcie_phy_set(sc, off + 0x000, 4, 1, 0); 934 mtk_pcie_phy_set(sc, off + 0x100, 4, 1, 0); 935} 936 937/* XXX: ugly, we need to fix this at some point */ 938#define MT7621_GPIO_CTRL0 *((volatile uint32_t *)0xbe000600) 939#define MT7621_GPIO_DATA0 *((volatile uint32_t *)0xbe000620) 940 941#define mtk_gpio_clr_set(_reg, _clr, _set) \ 942 do { \ 943 (_reg) = ((_reg) & (_clr)) | (_set); \ 944 } while (0) 945 946static int 947mtk_pcie_phy_mt7621_init(device_t dev) 948{ 949 struct mtk_pci_softc *sc = device_get_softc(dev); 950 951 /* First off, stop the PHY */ 952 if (mtk_pcie_phy_stop(dev)) 953 return (ENXIO); 954 955 /* PCIe resets are GPIO pins */ 956 mtk_sysctl_clr_set(SYSCTL_GPIOMODE, MT7621_PERST_GPIO_MODE | 957 MT7621_UARTL3_GPIO_MODE, MT7621_PERST_GPIO | MT7621_UARTL3_GPIO); 958 959 /* Set GPIO pins as outputs */ 960 mtk_gpio_clr_set(MT7621_GPIO_CTRL0, 0, MT7621_PCIE_RST); 961 962 /* Assert resets to PCIe devices */ 963 mtk_gpio_clr_set(MT7621_GPIO_DATA0, MT7621_PCIE_RST, 0); 964 965 /* Give everything a chance to sink in */ 966 DELAY(100000); 967 968 /* Now start the PHY again */ 969 if (mtk_pcie_phy_start(dev)) 970 return (ENXIO); 971 972 /* Wait for things to settle */ 973 DELAY(100000); 974 975 /* Only apply below to REV-E hardware */ 976 if ((mtk_sysctl_get(SYSCTL_REVID) & SYSCTL_REVID_MASK) == 977 SYSCTL_MT7621_REV_E) 978 mtk_pcie_phy_mt7621_bypass_pipe_rst(sc, 0x9000); 979 980 /* Setup PCIe ports 0 and 1 */ 981 mtk_pcie_phy_mt7621_setup_ssc(sc, 0x9000); 982 /* Setup PCIe port 2 */ 983 mtk_pcie_phy_mt7621_setup_ssc(sc, 0xa000); 984 985 /* Deassert resets to PCIe devices */ 986 mtk_gpio_clr_set(MT7621_GPIO_DATA0, 0, MT7621_PCIE_RST); 987 988 /* Set number of slots supported */ 989 sc->num_slots = 3; 990 991 /* Give it a chance to sink in */ 992 DELAY(100000); 993 994 return (0); 995} 996 997static void 998mtk_pcie_phy_mt7628_setup(struct mtk_pci_softc *sc, uint32_t off) 999{ 1000 uint32_t xtal_sel; 1001 1002 xtal_sel = mtk_sysctl_get(SYSCTL_SYSCFG) >> 6; 1003 xtal_sel &= 0x1; 1004 1005 mtk_pcie_phy_set(sc, off + 0x400, 8, 1, 1); 1006 mtk_pcie_phy_set(sc, off + 0x400, 9, 2, 0); 1007 mtk_pcie_phy_set(sc, off + 0x000, 4, 1, 1); 1008 mtk_pcie_phy_set(sc, off + 0x000, 5, 1, 0); 1009 mtk_pcie_phy_set(sc, off + 0x4ac, 16, 3, 3); 1010 1011 if (xtal_sel == 1) { 1012 mtk_pcie_phy_set(sc, off + 0x4bc, 24, 8, 0x7d); 1013 mtk_pcie_phy_set(sc, off + 0x490, 12, 4, 0x08); 1014 mtk_pcie_phy_set(sc, off + 0x490, 6, 2, 0x01); 1015 mtk_pcie_phy_set(sc, off + 0x4c0, 0, 32, 0x1f400000); 1016 mtk_pcie_phy_set(sc, off + 0x4a4, 0, 16, 0x013d); 1017 mtk_pcie_phy_set(sc, off + 0x4a8, 16, 16, 0x74); 1018 mtk_pcie_phy_set(sc, off + 0x4a8, 0, 16, 0x74); 1019 } else { 1020 mtk_pcie_phy_set(sc, off + 0x4bc, 24, 8, 0x64); 1021 mtk_pcie_phy_set(sc, off + 0x490, 12, 4, 0x0a); 1022 mtk_pcie_phy_set(sc, off + 0x490, 6, 2, 0x00); 1023 mtk_pcie_phy_set(sc, off + 0x4c0, 0, 32, 0x19000000); 1024 mtk_pcie_phy_set(sc, off + 0x4a4, 0, 16, 0x018d); 1025 mtk_pcie_phy_set(sc, off + 0x4a8, 16, 16, 0x4a); 1026 mtk_pcie_phy_set(sc, off + 0x4a8, 0, 16, 0x4a); 1027 } 1028 1029 mtk_pcie_phy_set(sc, off + 0x498, 0, 8, 5); 1030 mtk_pcie_phy_set(sc, off + 0x000, 5, 1, 1); 1031 mtk_pcie_phy_set(sc, off + 0x000, 4, 1, 0); 1032} 1033 1034static int 1035mtk_pcie_phy_mt7628_init(device_t dev) 1036{ 1037 struct mtk_pci_softc *sc = device_get_softc(dev); 1038 1039 /* Set PCIe reset to normal mode */ 1040 mtk_sysctl_clr_set(SYSCTL_GPIOMODE, MT7628_PERST_GPIO_MODE, 1041 MT7628_PERST); 1042 1043 /* Start the PHY */ 1044 if (mtk_pcie_phy_start(dev)) 1045 return (ENXIO); 1046 1047 /* Give it a chance to sink in */ 1048 DELAY(100000); 1049 1050 /* Setup the PHY */ 1051 mtk_pcie_phy_mt7628_setup(sc, 0x9000); 1052 1053 /* Deassert PCIe device reset */ 1054 MT_CLR_SET32(sc, MTK_PCI_PCICFG, MTK_PCI_RESET, 0); 1055 1056 /* Set number of slots supported */ 1057 sc->num_slots = 1; 1058 1059 return (0); 1060} 1061 1062static int 1063mtk_pcie_phy_mt7620_wait_busy(struct mtk_pci_softc *sc) 1064{ 1065 uint32_t reg_value, retry; 1066 1067 reg_value = retry = 0; 1068 1069 while (retry++ < MT7620_MAX_RETRIES) { 1070 reg_value = MT_READ32(sc, MT7620_PCIE_PHY_CFG); 1071 if (reg_value & PHY_BUSY) 1072 DELAY(100000); 1073 else 1074 break; 1075 } 1076 1077 if (retry >= MT7620_MAX_RETRIES) 1078 return (ENXIO); 1079 1080 return (0); 1081} 1082 1083static int 1084mtk_pcie_phy_mt7620_set(struct mtk_pci_softc *sc, uint32_t reg, 1085 uint32_t val) 1086{ 1087 uint32_t reg_val; 1088 1089 if (mtk_pcie_phy_mt7620_wait_busy(sc)) 1090 return (ENXIO); 1091 1092 reg_val = PHY_MODE_WRITE | ((reg & 0xff) << PHY_ADDR_OFFSET) | 1093 (val & 0xff); 1094 MT_WRITE32(sc, MT7620_PCIE_PHY_CFG, reg_val); 1095 DELAY(1000); 1096 1097 if (mtk_pcie_phy_mt7620_wait_busy(sc)) 1098 return (ENXIO); 1099 1100 return (0); 1101} 1102 1103static int 1104mtk_pcie_phy_mt7620_init(device_t dev) 1105{ 1106 struct mtk_pci_softc *sc = device_get_softc(dev); 1107 1108 /* 1109 * The below sets the PCIe PHY to bypass the PCIe DLL and enables 1110 * "elastic buffer control", whatever that may be... 1111 */ 1112 if (mtk_pcie_phy_mt7620_set(sc, 0x00, 0x80) || 1113 mtk_pcie_phy_mt7620_set(sc, 0x01, 0x04) || 1114 mtk_pcie_phy_mt7620_set(sc, 0x68, 0x84)) 1115 return (ENXIO); 1116 1117 /* Stop PCIe */ 1118 if (mtk_pcie_phy_stop(dev)) 1119 return (ENXIO); 1120 1121 /* Restore PPLL to a sane state before going on */ 1122 mtk_sysctl_clr_set(MT7620_PPLL_DRV, LC_CKDRVPD, PDRV_SW_SET); 1123 1124 /* No PCIe on the MT7620N */ 1125 if (!(mtk_sysctl_get(SYSCTL_REVID) & MT7620_PKG_BGA)) { 1126 device_printf(dev, "PCIe disabled for MT7620N\n"); 1127 mtk_sysctl_clr_set(MT7620_PPLL_CFG0, 0, PPLL_SW_SET); 1128 mtk_sysctl_clr_set(MT7620_PPLL_CFG1, 0, PPLL_PD); 1129 return (ENXIO); 1130 } 1131 1132 /* PCIe device reset pin is in normal mode */ 1133 mtk_sysctl_clr_set(SYSCTL_GPIOMODE, MT7620_PERST_GPIO_MODE, 1134 MT7620_PERST); 1135 1136 /* Enable PCIe now */ 1137 if (mtk_pcie_phy_start(dev)) 1138 return (ENXIO); 1139 1140 /* Give it a chance to sink in */ 1141 DELAY(100000); 1142 1143 /* If PLL is not locked - bail */ 1144 if (!(mtk_sysctl_get(MT7620_PPLL_CFG1) & PPLL_LOCKED)) { 1145 device_printf(dev, "no PPLL not lock\n"); 1146 mtk_pcie_phy_stop(dev); 1147 return (ENXIO); 1148 } 1149 1150 /* Configure PCIe PLL */ 1151 mtk_sysctl_clr_set(MT7620_PPLL_DRV, LC_CKDRVOHZ | LC_CKDRVHZ, 1152 LC_CKDRVPD | PDRV_SW_SET); 1153 1154 /* and give it a chance to settle */ 1155 DELAY(100000); 1156 1157 /* Deassert PCIe device reset */ 1158 MT_CLR_SET32(sc, MTK_PCI_PCICFG, MTK_PCI_RESET, 0); 1159 1160 /* MT7620 supports one PCIe slot */ 1161 sc->num_slots = 1; 1162 1163 return (0); 1164} 1165 1166static int 1167mtk_pcie_phy_rt3883_init(device_t dev) 1168{ 1169 struct mtk_pci_softc *sc = device_get_softc(dev); 1170 1171 /* Enable PCI host mode and PCIe RC mode */ 1172 mtk_sysctl_clr_set(SYSCTL_SYSCFG1, 0, RT3883_PCI_HOST_MODE | 1173 RT3883_PCIE_RC_MODE); 1174 1175 /* Enable PCIe PHY */ 1176 if (mtk_pcie_phy_start(dev)) 1177 return (ENXIO); 1178 1179 /* Disable PCI, we only support PCIe for now */ 1180 mtk_sysctl_clr_set(SYSCTL_RSTCTRL, 0, RT3883_PCI_RST); 1181 mtk_sysctl_clr_set(SYSCTL_CLKCFG1, RT3883_PCI_CLK, 0); 1182 1183 /* Give things a chance to sink in */ 1184 DELAY(500000); 1185 1186 /* Set PCIe port number to 0 and lift PCIe reset */ 1187 MT_WRITE32(sc, MTK_PCI_PCICFG, 0); 1188 1189 /* Configure PCI Arbiter */ 1190 MT_WRITE32(sc, MTK_PCI_ARBCTL, 0x79); 1191 1192 /* We have a single PCIe slot */ 1193 sc->num_slots = 1; 1194 1195 return (0); 1196} 1197 1198static void 1199mtk_pcie_phy_setup_slots(device_t dev) 1200{ 1201 struct mtk_pci_softc *sc = device_get_softc(dev); 1202 uint32_t bar0_val, val; 1203 int i; 1204 1205 /* Disable all PCIe interrupts */ 1206 MT_WRITE32(sc, MTK_PCI_PCIENA, 0); 1207 1208 /* Default bar0_val is 64M, enabled */ 1209 bar0_val = 0x03FF0001; 1210 1211 /* But we override it to 2G, enabled for some SoCs */ 1212 if (sc->socid == MTK_SOC_MT7620A || sc->socid == MTK_SOC_MT7628 || 1213 sc->socid == MTK_SOC_MT7688 || sc->socid == MTK_SOC_MT7621) 1214 bar0_val = 0x7FFF0001; 1215 1216 /* We still don't know which slots have linked up */ 1217 sc->pcie_link_status = 0; 1218 1219 /* XXX: I am not sure if this delay is really necessary */ 1220 DELAY(500000); 1221 1222 /* 1223 * See which slots have links and mark them. 1224 * Set up all slots' BARs and make them look like PCIe bridges. 1225 */ 1226 for (i = 0; i < sc->num_slots; i++) { 1227 /* If slot has link - mark it */ 1228 if (MT_READ32(sc, MTK_PCIE_STATUS(i)) & 1) 1229 sc->pcie_link_status |= (1<<i); 1230 else 1231 continue; 1232 1233 /* Generic slot configuration follows */ 1234 1235 /* We enable BAR0 */ 1236 MT_WRITE32(sc, MTK_PCIE_BAR0SETUP(i), bar0_val); 1237 /* and disable BAR1 */ 1238 MT_WRITE32(sc, MTK_PCIE_BAR1SETUP(i), 0); 1239 /* Internal memory base has no offset */ 1240 MT_WRITE32(sc, MTK_PCIE_IMBASEBAR0(i), 0); 1241 /* We're a PCIe bridge */ 1242 MT_WRITE32(sc, MTK_PCIE_CLASS(i), 0x06040001); 1243 1244 val = mtk_pci_read_config(dev, 0, i, 0, 0x4, 4); 1245 mtk_pci_write_config(dev, 0, i, 0, 0x4, val | 0x4, 4); 1246 val = mtk_pci_read_config(dev, 0, i, 0, 0x70c, 4); 1247 val &= ~(0xff << 8); 1248 val |= (0x50 << 8); 1249 mtk_pci_write_config(dev, 0, i, 0, 0x70c, val, 4); 1250 1251 mtk_pci_write_config(dev, 0, i, 0, PCIR_IOBASEL_1, 0xff, 1); 1252 mtk_pci_write_config(dev, 0, i, 0, PCIR_IOBASEH_1, 0xffff, 2); 1253 mtk_pci_write_config(dev, 0, i, 0, PCIR_IOLIMITL_1, 0, 1); 1254 mtk_pci_write_config(dev, 0, i, 0, PCIR_IOLIMITH_1, 0, 2); 1255 mtk_pci_write_config(dev, 0, i, 0, PCIR_MEMBASE_1, 0xffff, 2); 1256 mtk_pci_write_config(dev, 0, i, 0, PCIR_MEMLIMIT_1, 0, 2); 1257 mtk_pci_write_config(dev, 0, i, 0, PCIR_PMBASEL_1, 0xffff, 2); 1258 mtk_pci_write_config(dev, 0, i, 0, PCIR_PMBASEH_1, 0xffffffff, 1259 4); 1260 mtk_pci_write_config(dev, 0, i, 0, PCIR_PMLIMITL_1, 0, 2); 1261 mtk_pci_write_config(dev, 0, i, 0, PCIR_PMLIMITH_1, 0, 4); 1262 } 1263} 1264