gt_pci.c revision 224072
1/* $NetBSD: gt_pci.c,v 1.4 2003/07/15 00:24:54 lukem Exp $ */ 2 3/*- 4 * Copyright (c) 2001, 2002 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38/* 39 * PCI configuration support for gt I/O Processor chip. 40 */ 41 42#include <sys/cdefs.h> 43__FBSDID("$FreeBSD: head/sys/mips/malta/gt_pci.c 224072 2011-07-16 00:30:23Z adrian $"); 44 45#include <sys/param.h> 46#include <sys/systm.h> 47 48#include <sys/bus.h> 49#include <sys/interrupt.h> 50#include <sys/malloc.h> 51#include <sys/kernel.h> 52#include <sys/module.h> 53#include <sys/rman.h> 54 55#include <vm/vm.h> 56#include <vm/pmap.h> 57#include <vm/vm_extern.h> 58 59#include <machine/bus.h> 60#include <machine/cpu.h> 61#include <machine/pmap.h> 62 63#include <mips/malta/maltareg.h> 64 65#include <mips/malta/gtreg.h> 66#include <mips/malta/gtvar.h> 67 68#include <isa/isareg.h> 69#include <dev/ic/i8259.h> 70 71#include <dev/pci/pcireg.h> 72#include <dev/pci/pcivar.h> 73 74#include <dev/pci/pcib_private.h> 75#include "pcib_if.h" 76 77 78#define ICU_LEN 16 /* number of ISA IRQs */ 79 80/* 81 * XXX: These defines are from NetBSD's <dev/ic/i8259reg.h>. Respective file 82 * from FreeBSD src tree <dev/ic/i8259.h> lacks some definitions. 83 */ 84#define PIC_OCW1 1 85#define PIC_OCW2 0 86#define PIC_OCW3 0 87 88#define OCW2_SELECT 0 89#define OCW2_ILS(x) ((x) << 0) /* interrupt level select */ 90 91#define OCW3_POLL_IRQ(x) ((x) & 0x7f) 92#define OCW3_POLL_PENDING (1U << 7) 93 94struct gt_pci_softc; 95 96struct gt_pci_intr_cookie { 97 int irq; 98 struct gt_pci_softc *sc; 99}; 100 101struct gt_pci_softc { 102 device_t sc_dev; 103 bus_space_tag_t sc_st; 104 bus_space_handle_t sc_ioh_icu1; 105 bus_space_handle_t sc_ioh_icu2; 106 bus_space_handle_t sc_ioh_elcr; 107 108 int sc_busno; 109 struct rman sc_mem_rman; 110 struct rman sc_io_rman; 111 struct rman sc_irq_rman; 112 unsigned long sc_mem; 113 bus_space_handle_t sc_io; 114 115 struct resource *sc_irq; 116 struct intr_event *sc_eventstab[ICU_LEN]; 117 struct gt_pci_intr_cookie sc_intr_cookies[ICU_LEN]; 118 uint16_t sc_imask; 119 uint16_t sc_elcr; 120 121 uint16_t sc_reserved; 122 123 void *sc_ih; 124}; 125 126static void gt_pci_set_icus(struct gt_pci_softc *); 127static int gt_pci_intr(void *v); 128static int gt_pci_probe(device_t); 129static int gt_pci_attach(device_t); 130static int gt_pci_activate_resource(device_t, device_t, int, int, 131 struct resource *); 132static int gt_pci_setup_intr(device_t, device_t, struct resource *, 133 int, driver_filter_t *, driver_intr_t *, void *, void **); 134static int gt_pci_teardown_intr(device_t, device_t, struct resource *, void*); 135static int gt_pci_maxslots(device_t ); 136static int gt_pci_conf_setup(struct gt_pci_softc *, int, int, int, int, 137 uint32_t *); 138static uint32_t gt_pci_read_config(device_t, u_int, u_int, u_int, u_int, int); 139static void gt_pci_write_config(device_t, u_int, u_int, u_int, u_int, 140 uint32_t, int); 141static int gt_pci_route_interrupt(device_t pcib, device_t dev, int pin); 142static struct resource * gt_pci_alloc_resource(device_t, device_t, int, 143 int *, u_long, u_long, u_long, u_int); 144 145static void 146gt_pci_mask_irq(void *source) 147{ 148 struct gt_pci_intr_cookie *cookie = source; 149 struct gt_pci_softc *sc = cookie->sc; 150 int irq = cookie->irq; 151 152 sc->sc_imask |= (1 << irq); 153 sc->sc_elcr |= (1 << irq); 154 155 gt_pci_set_icus(sc); 156} 157 158static void 159gt_pci_unmask_irq(void *source) 160{ 161 struct gt_pci_intr_cookie *cookie = source; 162 struct gt_pci_softc *sc = cookie->sc; 163 int irq = cookie->irq; 164 165 /* Enable it, set trigger mode. */ 166 sc->sc_imask &= ~(1 << irq); 167 sc->sc_elcr &= ~(1 << irq); 168 169 gt_pci_set_icus(sc); 170} 171 172static void 173gt_pci_set_icus(struct gt_pci_softc *sc) 174{ 175 /* Enable the cascade IRQ (2) if 8-15 is enabled. */ 176 if ((sc->sc_imask & 0xff00) != 0xff00) 177 sc->sc_imask &= ~(1U << 2); 178 else 179 sc->sc_imask |= (1U << 2); 180 181 bus_space_write_1(sc->sc_st, sc->sc_ioh_icu1, PIC_OCW1, 182 sc->sc_imask & 0xff); 183 bus_space_write_1(sc->sc_st, sc->sc_ioh_icu2, PIC_OCW1, 184 (sc->sc_imask >> 8) & 0xff); 185 186 bus_space_write_1(sc->sc_st, sc->sc_ioh_elcr, 0, 187 sc->sc_elcr & 0xff); 188 bus_space_write_1(sc->sc_st, sc->sc_ioh_elcr, 1, 189 (sc->sc_elcr >> 8) & 0xff); 190} 191 192static int 193gt_pci_intr(void *v) 194{ 195 struct gt_pci_softc *sc = v; 196 struct intr_event *event; 197 int irq; 198 199 for (;;) { 200 bus_space_write_1(sc->sc_st, sc->sc_ioh_icu1, PIC_OCW3, 201 OCW3_SEL | OCW3_P); 202 irq = bus_space_read_1(sc->sc_st, sc->sc_ioh_icu1, PIC_OCW3); 203 if ((irq & OCW3_POLL_PENDING) == 0) 204 { 205 return FILTER_HANDLED; 206 } 207 208 irq = OCW3_POLL_IRQ(irq); 209 210 if (irq == 2) { 211 bus_space_write_1(sc->sc_st, sc->sc_ioh_icu2, 212 PIC_OCW3, OCW3_SEL | OCW3_P); 213 irq = bus_space_read_1(sc->sc_st, sc->sc_ioh_icu2, 214 PIC_OCW3); 215 if (irq & OCW3_POLL_PENDING) 216 irq = OCW3_POLL_IRQ(irq) + 8; 217 else 218 irq = 2; 219 } 220 221 event = sc->sc_eventstab[irq]; 222 223 if (!event || TAILQ_EMPTY(&event->ie_handlers)) 224 continue; 225 226 /* TODO: frame instead of NULL? */ 227 intr_event_handle(event, NULL); 228 /* XXX: Log stray IRQs */ 229 230 /* Send a specific EOI to the 8259. */ 231 if (irq > 7) { 232 bus_space_write_1(sc->sc_st, sc->sc_ioh_icu2, 233 PIC_OCW2, OCW2_SELECT | OCW2_EOI | OCW2_SL | 234 OCW2_ILS(irq & 7)); 235 irq = 2; 236 } 237 238 bus_space_write_1(sc->sc_st, sc->sc_ioh_icu1, PIC_OCW2, 239 OCW2_SELECT | OCW2_EOI | OCW2_SL | OCW2_ILS(irq)); 240 } 241 242 return FILTER_HANDLED; 243} 244 245static int 246gt_pci_probe(device_t dev) 247{ 248 device_set_desc(dev, "GT64120 PCI bridge"); 249 return (0); 250} 251 252static int 253gt_pci_attach(device_t dev) 254{ 255 256 uint32_t busno; 257 struct gt_pci_softc *sc = device_get_softc(dev); 258 int rid; 259 260 busno = 0; 261 sc->sc_dev = dev; 262 sc->sc_busno = busno; 263 sc->sc_st = mips_bus_space_generic; 264 265 /* Use KSEG1 to access IO ports for it is uncached */ 266 sc->sc_io = MIPS_PHYS_TO_KSEG1(MALTA_PCI0_IO_BASE); 267 sc->sc_io_rman.rm_type = RMAN_ARRAY; 268 sc->sc_io_rman.rm_descr = "GT64120 PCI I/O Ports"; 269 if (rman_init(&sc->sc_io_rman) != 0 || 270 rman_manage_region(&sc->sc_io_rman, 0, 0xffff) != 0) { 271 panic("gt_pci_attach: failed to set up I/O rman"); 272 } 273 274 /* Use KSEG1 to access PCI memory for it is uncached */ 275 sc->sc_mem = MIPS_PHYS_TO_KSEG1(MALTA_PCIMEM1_BASE); 276 sc->sc_mem_rman.rm_type = RMAN_ARRAY; 277 sc->sc_mem_rman.rm_descr = "GT64120 PCI Memory"; 278 if (rman_init(&sc->sc_mem_rman) != 0 || 279 rman_manage_region(&sc->sc_mem_rman, 280 sc->sc_mem, sc->sc_mem + MALTA_PCIMEM1_SIZE) != 0) { 281 panic("gt_pci_attach: failed to set up memory rman"); 282 } 283 sc->sc_irq_rman.rm_type = RMAN_ARRAY; 284 sc->sc_irq_rman.rm_descr = "GT64120 PCI IRQs"; 285 if (rman_init(&sc->sc_irq_rman) != 0 || 286 rman_manage_region(&sc->sc_irq_rman, 1, 31) != 0) 287 panic("gt_pci_attach: failed to set up IRQ rman"); 288 289 /* 290 * Map the PIC/ELCR registers. 291 */ 292#if 0 293 if (bus_space_map(sc->sc_st, 0x4d0, 2, 0, &sc->sc_ioh_elcr) != 0) 294 device_printf(dev, "unable to map ELCR registers\n"); 295 if (bus_space_map(sc->sc_st, IO_ICU1, 2, 0, &sc->sc_ioh_icu1) != 0) 296 device_printf(dev, "unable to map ICU1 registers\n"); 297 if (bus_space_map(sc->sc_st, IO_ICU2, 2, 0, &sc->sc_ioh_icu2) != 0) 298 device_printf(dev, "unable to map ICU2 registers\n"); 299#else 300 sc->sc_ioh_elcr = sc->sc_io + 0x4d0; 301 sc->sc_ioh_icu1 = sc->sc_io + IO_ICU1; 302 sc->sc_ioh_icu2 = sc->sc_io + IO_ICU2; 303#endif 304 305 306 /* All interrupts default to "masked off". */ 307 sc->sc_imask = 0xffff; 308 309 /* All interrupts default to edge-triggered. */ 310 sc->sc_elcr = 0; 311 312 /* 313 * Initialize the 8259s. 314 */ 315 /* reset, program device, 4 bytes */ 316 bus_space_write_1(sc->sc_st, sc->sc_ioh_icu1, 0, 317 ICW1_RESET | ICW1_IC4); 318 /* 319 * XXX: values from NetBSD's <dev/ic/i8259reg.h> 320 */ 321 bus_space_write_1(sc->sc_st, sc->sc_ioh_icu1, 1, 322 0/*XXX*/); 323 bus_space_write_1(sc->sc_st, sc->sc_ioh_icu1, 1, 324 1 << 2); 325 bus_space_write_1(sc->sc_st, sc->sc_ioh_icu1, 1, 326 ICW4_8086); 327 328 /* mask all interrupts */ 329 bus_space_write_1(sc->sc_st, sc->sc_ioh_icu1, 1, 330 sc->sc_imask & 0xff); 331 332 /* enable special mask mode */ 333 bus_space_write_1(sc->sc_st, sc->sc_ioh_icu1, 0, 334 OCW3_SEL | OCW3_ESMM | OCW3_SMM); 335 336 /* read IRR by default */ 337 bus_space_write_1(sc->sc_st, sc->sc_ioh_icu1, 0, 338 OCW3_SEL | OCW3_RR); 339 340 /* reset, program device, 4 bytes */ 341 bus_space_write_1(sc->sc_st, sc->sc_ioh_icu2, 0, 342 ICW1_RESET | ICW1_IC4); 343 bus_space_write_1(sc->sc_st, sc->sc_ioh_icu2, 1, 344 0/*XXX*/); 345 bus_space_write_1(sc->sc_st, sc->sc_ioh_icu2, 1, 346 1 << 2); 347 bus_space_write_1(sc->sc_st, sc->sc_ioh_icu2, 1, 348 ICW4_8086); 349 350 /* mask all interrupts */ 351 bus_space_write_1(sc->sc_st, sc->sc_ioh_icu2, 1, 352 sc->sc_imask & 0xff); 353 354 /* enable special mask mode */ 355 bus_space_write_1(sc->sc_st, sc->sc_ioh_icu2, 0, 356 OCW3_SEL | OCW3_ESMM | OCW3_SMM); 357 358 /* read IRR by default */ 359 bus_space_write_1(sc->sc_st, sc->sc_ioh_icu2, 0, 360 OCW3_SEL | OCW3_RR); 361 362 /* 363 * Default all interrupts to edge-triggered. 364 */ 365 bus_space_write_1(sc->sc_st, sc->sc_ioh_elcr, 0, 366 sc->sc_elcr & 0xff); 367 bus_space_write_1(sc->sc_st, sc->sc_ioh_elcr, 1, 368 (sc->sc_elcr >> 8) & 0xff); 369 370 /* 371 * Some ISA interrupts are reserved for devices that 372 * we know are hard-wired to certain IRQs. 373 */ 374 sc->sc_reserved = 375 (1U << 0) | /* timer */ 376 (1U << 1) | /* keyboard controller (keyboard) */ 377 (1U << 2) | /* PIC cascade */ 378 (1U << 3) | /* COM 2 */ 379 (1U << 4) | /* COM 1 */ 380 (1U << 6) | /* floppy */ 381 (1U << 7) | /* centronics */ 382 (1U << 8) | /* RTC */ 383 (1U << 9) | /* I2C */ 384 (1U << 12) | /* keyboard controller (mouse) */ 385 (1U << 14) | /* IDE primary */ 386 (1U << 15); /* IDE secondary */ 387 388 /* Hook up our interrupt handler. */ 389 if ((sc->sc_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 390 MALTA_SOUTHBRIDGE_INTR, MALTA_SOUTHBRIDGE_INTR, 1, 391 RF_SHAREABLE | RF_ACTIVE)) == NULL) { 392 device_printf(dev, "unable to allocate IRQ resource\n"); 393 return ENXIO; 394 } 395 396 if ((bus_setup_intr(dev, sc->sc_irq, INTR_TYPE_MISC, 397 gt_pci_intr, NULL, sc, &sc->sc_ih))) { 398 device_printf(dev, 399 "WARNING: unable to register interrupt handler\n"); 400 return ENXIO; 401 } 402 403 /* Initialize memory and i/o rmans. */ 404 device_add_child(dev, "pci", busno); 405 return (bus_generic_attach(dev)); 406} 407 408static int 409gt_pci_maxslots(device_t dev) 410{ 411 return (PCI_SLOTMAX); 412} 413 414static int 415gt_pci_conf_setup(struct gt_pci_softc *sc, int bus, int slot, int func, 416 int reg, uint32_t *addr) 417{ 418 *addr = (bus << 16) | (slot << 11) | (func << 8) | reg; 419 420 return (0); 421} 422 423static uint32_t 424gt_pci_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg, 425 int bytes) 426{ 427 struct gt_pci_softc *sc = device_get_softc(dev); 428 uint32_t data; 429 uint32_t addr; 430 uint32_t shift, mask; 431 432 if (gt_pci_conf_setup(sc, bus, slot, func, reg & ~3, &addr)) 433 return (uint32_t)(-1); 434 435 /* Clear cause register bits. */ 436 GT_REGVAL(GT_INTR_CAUSE) = 0; 437 438 GT_REGVAL(GT_PCI0_CFG_ADDR) = (1 << 31) | addr; 439 data = GT_REGVAL(GT_PCI0_CFG_DATA); 440 441 /* Check for master abort. */ 442 if (GT_REGVAL(GT_INTR_CAUSE) & (GTIC_MASABORT0 | GTIC_TARABORT0)) 443 data = (uint32_t) -1; 444 445 /* 446 * XXX: We assume that words readed from GT chip are BE. 447 * Should we set the mode explicitly during chip 448 * Initialization? 449 */ 450 switch(reg % 4) 451 { 452 case 3: 453 shift = 24; 454 break; 455 case 2: 456 shift = 16; 457 break; 458 case 1: 459 shift = 8; 460 break; 461 default: 462 shift = 0; 463 break; 464 } 465 466 switch(bytes) 467 { 468 case 1: 469 mask = 0xff; 470 data = (data >> shift) & mask; 471 break; 472 case 2: 473 mask = 0xffff; 474 if(reg % 4 == 0) 475 data = data & mask; 476 else 477 data = (data >> 16) & mask; 478 break; 479 case 4: 480 break; 481 default: 482 panic("gt_pci_readconfig: wrong bytes count"); 483 break; 484 } 485#if 0 486 printf("PCICONF_READ(%02x:%02x.%02x[%04x] -> %02x(%d)\n", 487 bus, slot, func, reg, data, bytes); 488#endif 489 490 return (data); 491} 492 493static void 494gt_pci_write_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg, 495 uint32_t data, int bytes) 496{ 497 struct gt_pci_softc *sc = device_get_softc(dev); 498 uint32_t addr; 499 uint32_t reg_data; 500 uint32_t shift, mask; 501 502 if(bytes != 4) 503 { 504 reg_data = gt_pci_read_config(dev, bus, slot, func, reg, 4); 505 506 /* 507 * XXX: We assume that words readed from GT chip are BE. 508 * Should we set the mode explicitly during chip 509 * Initialization? 510 */ 511 shift = 8 * (reg & 3); 512 513 switch(bytes) 514 { 515 case 1: 516 mask = 0xff; 517 data = (reg_data & ~ (mask << shift)) | (data << shift); 518 break; 519 case 2: 520 mask = 0xffff; 521 if(reg % 4 == 0) 522 data = (reg_data & ~mask) | data; 523 else 524 data = (reg_data & ~ (mask << shift)) | 525 (data << shift); 526 break; 527 case 4: 528 break; 529 default: 530 panic("gt_pci_readconfig: wrong bytes count"); 531 break; 532 } 533 } 534 535 if (gt_pci_conf_setup(sc, bus, slot, func, reg & ~3, &addr)) 536 return; 537 538 /* The galileo has problems accessing device 31. */ 539 if (bus == 0 && slot == 31) 540 return; 541 542 /* XXX: no support for bus > 0 yet */ 543 if (bus > 0) 544 return; 545 546 /* Clear cause register bits. */ 547 GT_REGVAL(GT_INTR_CAUSE) = 0; 548 549 GT_REGVAL(GT_PCI0_CFG_ADDR) = (1 << 31) | addr; 550 GT_REGVAL(GT_PCI0_CFG_DATA) = data; 551} 552 553static int 554gt_pci_route_interrupt(device_t pcib, device_t dev, int pin) 555{ 556 int bus; 557 int device; 558 int func; 559 /* struct gt_pci_softc *sc = device_get_softc(pcib); */ 560 bus = pci_get_bus(dev); 561 device = pci_get_slot(dev); 562 func = pci_get_function(dev); 563 /* 564 * XXXMIPS: We need routing logic. This is just a stub . 565 */ 566 switch (device) { 567 case 9: /* 568 * PIIX4 IDE adapter. HW IRQ0 569 */ 570 return 0; 571 default: 572 printf("No mapping for %d/%d/%d/%d\n", bus, device, func, pin); 573 574 } 575 return (0); 576 577} 578 579static int 580gt_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 581{ 582 struct gt_pci_softc *sc = device_get_softc(dev); 583 switch (which) { 584 case PCIB_IVAR_DOMAIN: 585 *result = 0; 586 return (0); 587 case PCIB_IVAR_BUS: 588 *result = sc->sc_busno; 589 return (0); 590 591 } 592 return (ENOENT); 593} 594 595static int 596gt_write_ivar(device_t dev, device_t child, int which, uintptr_t result) 597{ 598 struct gt_pci_softc * sc = device_get_softc(dev); 599 600 switch (which) { 601 case PCIB_IVAR_BUS: 602 sc->sc_busno = result; 603 return (0); 604 } 605 return (ENOENT); 606} 607 608static struct resource * 609gt_pci_alloc_resource(device_t bus, device_t child, int type, int *rid, 610 u_long start, u_long end, u_long count, u_int flags) 611{ 612 struct gt_pci_softc *sc = device_get_softc(bus); 613 struct resource *rv = NULL; 614 struct rman *rm; 615 bus_space_tag_t bt = 0; 616 bus_space_handle_t bh = 0; 617 618 switch (type) { 619 case SYS_RES_IRQ: 620 rm = &sc->sc_irq_rman; 621 break; 622 case SYS_RES_MEMORY: 623 rm = &sc->sc_mem_rman; 624 bt = sc->sc_st; 625 bh = sc->sc_mem; 626 break; 627 case SYS_RES_IOPORT: 628 rm = &sc->sc_io_rman; 629 bt = sc->sc_st; 630 bh = sc->sc_io; 631 break; 632 default: 633 return (NULL); 634 } 635 636 rv = rman_reserve_resource(rm, start, end, count, flags, child); 637 if (rv == NULL) 638 return (NULL); 639 rman_set_rid(rv, *rid); 640 if (type != SYS_RES_IRQ) { 641 bh += (rman_get_start(rv)); 642 643 rman_set_bustag(rv, bt); 644 rman_set_bushandle(rv, bh); 645 if (flags & RF_ACTIVE) { 646 if (bus_activate_resource(child, type, *rid, rv)) { 647 rman_release_resource(rv); 648 return (NULL); 649 } 650 } 651 } 652 return (rv); 653} 654 655static int 656gt_pci_activate_resource(device_t bus, device_t child, int type, int rid, 657 struct resource *r) 658{ 659 bus_space_handle_t p; 660 int error; 661 662 if ((type == SYS_RES_MEMORY) || (type == SYS_RES_IOPORT)) { 663 error = bus_space_map(rman_get_bustag(r), 664 rman_get_bushandle(r), rman_get_size(r), 0, &p); 665 if (error) 666 return (error); 667 rman_set_bushandle(r, p); 668 } 669 return (rman_activate_resource(r)); 670} 671 672static int 673gt_pci_setup_intr(device_t dev, device_t child, struct resource *ires, 674 int flags, driver_filter_t *filt, driver_intr_t *handler, 675 void *arg, void **cookiep) 676{ 677 struct gt_pci_softc *sc = device_get_softc(dev); 678 struct intr_event *event; 679 int irq, error; 680 681 irq = rman_get_start(ires); 682 if (irq >= ICU_LEN || irq == 2) 683 panic("%s: bad irq or type", __func__); 684 685 event = sc->sc_eventstab[irq]; 686 sc->sc_intr_cookies[irq].irq = irq; 687 sc->sc_intr_cookies[irq].sc = sc; 688 if (event == NULL) { 689 error = intr_event_create(&event, 690 (void *)&sc->sc_intr_cookies[irq], 0, irq, 691 gt_pci_mask_irq, gt_pci_unmask_irq, 692 NULL, NULL, "gt_pci intr%d:", irq); 693 if (error) 694 return 0; 695 sc->sc_eventstab[irq] = event; 696 } 697 698 intr_event_add_handler(event, device_get_nameunit(child), filt, 699 handler, arg, intr_priority(flags), flags, cookiep); 700 701 gt_pci_unmask_irq((void *)&sc->sc_intr_cookies[irq]); 702 return 0; 703} 704 705static int 706gt_pci_teardown_intr(device_t dev, device_t child, struct resource *res, 707 void *cookie) 708{ 709 struct gt_pci_softc *sc = device_get_softc(dev); 710 int irq; 711 712 irq = rman_get_start(res); 713 gt_pci_mask_irq((void *)&sc->sc_intr_cookies[irq]); 714 715 return (intr_event_remove_handler(cookie)); 716} 717 718static device_method_t gt_pci_methods[] = { 719 /* Device interface */ 720 DEVMETHOD(device_probe, gt_pci_probe), 721 DEVMETHOD(device_attach, gt_pci_attach), 722 DEVMETHOD(device_shutdown, bus_generic_shutdown), 723 DEVMETHOD(device_suspend, bus_generic_suspend), 724 DEVMETHOD(device_resume, bus_generic_resume), 725 726 /* Bus interface */ 727 DEVMETHOD(bus_print_child, bus_generic_print_child), 728 DEVMETHOD(bus_read_ivar, gt_read_ivar), 729 DEVMETHOD(bus_write_ivar, gt_write_ivar), 730 DEVMETHOD(bus_alloc_resource, gt_pci_alloc_resource), 731 DEVMETHOD(bus_release_resource, bus_generic_release_resource), 732 DEVMETHOD(bus_activate_resource, gt_pci_activate_resource), 733 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 734 DEVMETHOD(bus_setup_intr, gt_pci_setup_intr), 735 DEVMETHOD(bus_teardown_intr, gt_pci_teardown_intr), 736 737 /* pcib interface */ 738 DEVMETHOD(pcib_maxslots, gt_pci_maxslots), 739 DEVMETHOD(pcib_read_config, gt_pci_read_config), 740 DEVMETHOD(pcib_write_config, gt_pci_write_config), 741 DEVMETHOD(pcib_route_interrupt, gt_pci_route_interrupt), 742 743 {0, 0} 744}; 745 746static driver_t gt_pci_driver = { 747 "pcib", 748 gt_pci_methods, 749 sizeof(struct gt_pci_softc), 750}; 751 752static devclass_t gt_pci_devclass; 753 754DRIVER_MODULE(gt_pci, gt, gt_pci_driver, gt_pci_devclass, 0, 0); 755